STA016A13TR - STMicroelectronics

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STA016A

July 2004

This is preliminary information on a new product now in development. Details are subject to change without notice.

1FEATURES

■SINGLE CHIP MPEG LAYER 3 DECODER

SUPPORTING:

– All features specified for Layer III in ISO/IEC

11172-3 (MP EG 1 Aud io)

– All features specified for Layer III in ISO/IEC

13818-3.2 (MPEG 2 Audio)

– Lower sampling frequencies syntax exten-

sion, (not specified by ISO) called MPEG 2.5

■DECODES LAYER III STEREO CHANNELS,

DUAL CHANNEL, SINGLE CHANNEL (MONO)

■SUPPORTING ALL THE MPEG 1 & 2

SAMPLING FREQUENCIES AND THE

EXTENS ION TO MPEG 2.5:48 , 44.1,32,

24,22.05, 16, 12,11. 025, 8 KHz

■ACCEPTS MPEG 2.5 LAYE R III

ELEMENTARY COMPRESSED BITSTREAM

WITH DATA RATE FROM 8 Kbit/s UP TO 320

Kbit/s

■BYPASS MODE FOR EXT ER N AL AUXIL IARY

AUDIO SOURCE

■EMBEDDED ISO9660 LAYER FOR FILE-

SYSTEM DECODING (JOLIET)

■EMBEDDED CD-ROM DECODER BLOCKS

INCLUDING ECC/EDC CAPABILITY

■FLEXIBLE I2S INPUT I NTE RFACE FO R EAS Y

CONNECTION WITH MOST CD-SERVO

DEVICES

■EMBEDDED BROWSING COMMAND

INTERPRETER FOR EASY FILE-SYSTEM

BROWSING

■CUE-SHEET CAPAB ILITY UP TO 100

ENTRIES

■BROWSER COMMAND INTERPRETER (BCI)

– Parent Dir

– Enter Dir

– Previous Entry

– Nex t En try

– Get Record Infos

■EASY PROGRAMMABLE GPSO INTERFACE

(MONO/STEREO) FOR ENCODED DATA UP

TO 5Mbit/s

■DIGITAL VO LUM E

■BASS & TR EBLE CONTROL

■SERIAL BITSTREAM INPUT INTERFACE

■EASY PROGRAMMABLE ADC INPUT

INTERFACE

■SERI AL PCM O UTPUT I N TERFACE ( I2S AND

OTHER FORMATS)

■PLL FOR INTERNAL CLOCK AND FOR

OUTPUT PCM CLOCK GENERATION

■CRC CHECK AND SYNCHRO NISATION

ERROR DETECTIO N WITH SOFTWARE

INDICATORS

■I2C CONTROL BUS

■LOW POWER 2.4V CMOS TECHNOLOGY

WIT H 3.3V TOL ER AN T AND CAPABL E I/O

■FAST FORWARD A ND PAUSE CAPA BILI TIE S

■ADDITIONAL FEA TUR ES AVAILABL E VIA

SOFTWARE

– MM C and SD card: read and format ia SPI

– MMC an SD cards: write

– Sample Rate Converter for MPEG streams:

from general input frequence to internal

44.1kHz

– Generic fea tures

– Faster browsing, feed forward and rewind ca-

pabilities

– long file name suppo rt

1.1 APPLICATIONS

■AUDIO CD PLAYERS

■MULTIME D IA PL AYER S

■CD-ROM PLAYERS

■CAR RADIO PLAYERS

PRODUCT PREVIEW

MPEG 2.5 LAYER III AUDIO DECODER

SUPPORTING CD-ROM CAPABILITY

REV. 1

STA016AASTA016AA

Figure 1. Package

able 1. Order Codes

Part Number Package

STA016A TQFP64

TQFP64

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2DESCRIPTION

The STA016A i s a single chi p MPEG 1, 2 and 2. 5 Layer III audi o decoder with embedded CDROM decoding

capability . It c an b e ea si ly connected to m ost existing CDDSP devices via a software configurable serial link. A

tipical application block diagram is show in Figure 1. The audio sources, for instance could be an external flash

memory.

A useful bypass mode allow using this device also as an audio processor for volume an d tone controls.

Figure 2. Typical CD-Player app lication

Table 2. ABSOLUTE MAXIMUM RATINGS

(*) guarantee by design

Table 3. TH E R MAL DATA

Symbol Parameter Value Unit

VDD Digital Power Supply at 2.5V (nominal) -0.5 to 3.3 V

VCC Digital Power Supply at 3.3V (nominal) -0.5 to 4 V

PLL-VCC Analog Supply Voltage at 2.5V (nominal) -0.5 to 3.3 V

VIH/VIL Voltage on input pins (3.3V pads) -0.5 to VCC +0.5 V

Tstg Storage Temperature -40 to +150 °C

Top Operative ambient temp -40 to +85(*) °C

TjOperating Junction Temperature -40 to 125 °C

Symbol Parameter Value Unit

Rth j-amb Thermal resistance Junction to Ambient 85 °C/W

I2C

SDI

GPSO

I2 S O UT

CDDSP I/F L

STA016

CDDSP

Mechanic

MCU

D/A

FL ASH ME M O RY

for

M P3 f ile s

encoded messages

(optional)

TUNER M O DULE

AUX. A UDIO

SOURCE

CD M ODULE

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STA016A

3OVERVIEW

The device can decode/process data coming from thre e possible sources, as show ed in Figure 2:

■CDDSP seri al li nk: using this input interface, besides MP3 encoded data CD, it's possible to playback

also standard Audio CD using the available volume and ton e equalizer features of the device and

allowing the use of only one D/A converter with no external analog switch.

■SDI input interface: through this i nput interface it's possible t o decode any MP3 bitstream coming, for

instance, from an external flash memory .

■I2S input interface: this interface can be used to process an ext ernal audio source (tuner, for i nstance)

through the DSP based volume and tone controls:this BYPASS mode can avoid the use of additional

D/A converters or postprocessing units.

3.1 MP3 decoder engine

The MP 3 decoder engine is able to decode any Layer III compliant bitstream: MP EG1, MPEG2 and MPEG2.5

streams are supported.

Decoded audio data goes thr ough a software volume control and a two- band equalizer blocks before feeding

the output I

S interface. This results in no need for an external audio processor.

Table 4. MPEG Sampl ing Rates (KHz)

Figu re 3. Blo ck Diagram

The basic functions of the device can be fully operated via the I

C bus. Besides that the GPS O interface can be

used to move huge amount of data this fast and flexible interface can achie ve transfer rates up to 5 Mb it/s.

The embedded DSP fir mware implements all the layers required to decode a standard data CD, as shown in

the Figure 4:

MPEG 1 MPEG 2 MPEG 2.5

48 24 12

44.1 22.05 11.025

32 16 8

CDDSP

I/F

SECTOR

BUFFER

SYNC

DETECT.

MMDSP

CORE

- ISO9660 + JOLIET

- BCI

- MP3

DESCRAM.

INPUT SELECTOR

CDROM DECODER (C3)

ECC/EDC

CD_BCK

CD_SDI

D_LRCK

I2S IN

I/F

BCKI

SDI

LRCKI

STB

RQST

I2C

I/F I2C

REG BANK PLL

OSCK XTI XTO

OSC

PCM OUTPUT

BUFFER I2S OUT

I/F

GPSO

I/F

SCL

SDA GPSO_RE

GPSO_SD

GPSO_CK

LRCKO

SDO

BCKO

SDI

I/F

BS_BCK

BS_SDI

BS_LRCK

DREQ

D04AU1565

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Figure 4. Layers performed by embedded DSP firmware

The whole C DROM and file-system decod ing task is performed by embedded firmware. The application MCU,

basically, must ma nage CDDSP device according to STA016A requests. Three basic com m and flows exist:

■MCU -> STA016A: commands used to handle decoder operation and t o ask f or specific information like

filename, filelength, sector raw data, etc . Thi s f low will use I2C (GPSO f or special operations) in terf ace.

■STA016A -> MCU: this channel is used to retrieve inquired information and to inform MCU that a

CDDSP specific operation must be perf ormed (like pick-up repositioning). This flow is based on I2C link

plus an additional interrupt signal in order to a void time consum ing polling techniques .

■MCU -> CDDSP: the CDDSP management is fully up to the application MCU. This architecture allows

maximum flexibility and easy migration from existing CDPlayers to MP3 CDPlayers.

Figure 5. PIN CONNECTION

FRAMES to SECTOR TRANSLATOR

SYNC DETECTOR

DESCRAMBLER

EDC/ECC (C3)

IS O 9 660 F ile System D eco d in g

(with Joliet support)

Browsing Command Interface

28 29 30 31 32

59 58 57 56 54

55 53 52 51 50 49

VSS_1

VDD_1

DREQ

CD_BCK

D_LRCK

CD_SDI

VSS_2

VDD_2

BS_SDI

BS_LRCK

BS_BCK

SDO

VCC_1

VSS_3

CLKOUT

ODATA1

ODATA0

ODATA2

VDD_3

VSS_4

ODATA3

ODATA4

RQST

VCC_3

VSS_8

GPSO_RE

GPSO_SD

GPSO_CK

VDD_5

VSS_7

IODATA15

IODATA14

IODATA13

VSS_6

VCC_2

PLL_GND

PLL_VCC

FILT1

FILT0

IODATA1

IODATA8

IODATA9

D00AU1227

22 23 24 25 26

STB

VSS_9

VDD_6

SCL

SDA

XTI

XTO

OSCK

LRCKO

BCKO

17 18 19 20 21

VSS_5

VDD_4

IODATA6

IODATA5

IODATA7

TESTEN

RESET

SDI

LRCK1

BCKI

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STA016A

Table 5.

PIN DESCRIPTION

PIN Pin Name Type Description Sourde/Dest

CDDSP interface

1 CD_LRCK I DSP Interface left/right Clock From DSP

3 CD_SDI I DSP interface serial data From DSP

2 CD_BCK I DSP interface bit clock From DSP

SDI interface

9 BS_SDI I Bitstream interface serial data From MCU

7 BS_LRCK I Bitstream interface left/right Clock From MCU

8 BS_BCK I Bitstream interface clock From MCU

4 DREQ O Bitstream data request To MCU

PCM IN interface

13 BCKI I ADC bit clock From ADC

14 SDI I ADC serial data From ADC

12 LRCKI I ADC left/right Clock From ADC

PCM OUT interface

20 LRCKO O DAC Interface left/right Clock To DAC

22 SDO O DAC serial data To DAC

21 BCKO O DAC bit clock To DAC

19 OSCK O DAC oversampling clock To DAC/ADC

GPSO interface

55 GPSO_CK I GPSO bit clock From MCU

54 GPSO_SDO O GPSO serial data To MCU

56 GPSO_REQ O GPSO request signal To MCU

GPIO interface

26 IODATA0 I/O GPIODATA0

27 IODATA1 I/O GPIODATA1

28 IODATA2 I/O GPIODATA2

31 IODATA3 I/O GPIODATA3

32 IODATA4 I/O GPIODATA4

33 IODATA5 I/O GPIODATA5

34 IODATA6 I/O GPIODATA6

35 IODATA7 I/O GPIODATA7

44 IODATA8 I/O GPIODATA8

45 IODATA9 I/O GPIODATA9

46 IODATA10 I/O GPIODATA10

47 IODATA11 I/O GPIODATA11

48 IODATA12 I/O GPIODATA12

49 IODATA13 I/O GPIODATA13

50 IODATA14 I/O GPIODATA14

51 IODATA15 I/O GPIODATA15

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HANDSHAKE SIGNALS

60 STB I Strobe signal From MCU

59 RQST O I2C data signal To MCU

I2C LINK

63 SCL I I2C clock signal From MCU

64 SDA I/O I2C data signal To MCU

MISCELLANEOUS

17 XTI I Oscillator input

18 XTO O Oscillator output

25 CLKOUT O Buffered output clock

15 -RESET I Reset

16 -TESTEN I Reserved for test purpose

40 FILT0 I PLL external f ilter

38 FILT1 PLL external filter

POWER SUPPLY

39 PLL_VCC Digital supply (2.5V Power Supply)

41 PLL_GND Ground

5 VDD_1 Digital supply (2.5V Power Supply)

10 VDD_2 Digital supply (2.5V Power Supply)

29 VDD_3 Digital supply (2.5V Power Supply)

36 VDD_4 Digital supply (2.5V Power Supply)

53 VDD_5 Digital supply (2.5V Power Supply)

62 VDD_6 Digital supply (2.5V Power Supply)

23 VCC_1 Digital supply (3.3V Power Supply)

42 VCC_2 Digital supply (3.3V Power Supply)

58 VCC_3 Digital supply (3.3V Power Supply)

6 VSS_1 Ground

11 VSS_2 Ground

24 VSS_3 Ground

30 VSS_4 Ground

37 VSS_5 Ground

43 VSS_6 Ground

52 VSS_7 Ground

57 VSS_8 Ground

61 VSS_9 Ground

Table 5.

PIN DESCRIPTION

(continued)

PIN Pin Name Type Description Sourde/Dest

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STA016A

4 ELE CTRICAL CHARA CTERI STCS

amb

= 25°C; R

= 50

Ω

unless otherwise specified)

Table 6. DC OPERATING CONDITIONS

Table 7. GENERAL INTERFACE ELECTRICAL CHARACTERISTICS

Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress

on the pin.

Not e 2: Human Body Model.

Table 8. DC ELECTRICAL CHA RACTERISTICS

Note1: Takes into account 200mV voltage drop in both supply lines.

Note 2: X is the sou rce/ sink cu rrent under wors t ca se cond i tions and is reflec ted in the name of the I /O ce l l acc ording to the dri ve capability.

Table 9.

Note 1: Min. condi tion: VDD = 2.7V, 125° C M i n proc ess Max . condi tion: VDD = 3.6V, -20°C Max.

Ta ble 10. POWER DISSIPATION

Symbol Parameter Value Unit

VDD Power Supply Voltage 2.5 ± 0.25 V

VCC Power Supply Voltage 3.3 ± 0.3 V

PLL_VCC Power Supply Voltage 2.5 ± 0.25 V

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

IIL Low Level Input

CurrentWithout pull-up device Vi = 0V -10 10 µA1

IIH High Level Input

CurrentWithout pull-up device Vi = VDD -10 10 µA1

Vesd Electrostatic Protection Leakage < 1µA2000 V2

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

VIL Low Level Input Voltage

0.2*V

VIH High Level Input Voltage

0.8*V

Vol Low Level Output Voltage Iol = Xma 0.4V V 1, 2

Voh High Level Output Voltage

0.85*V

V1, 2

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

Ipu Pull-up current Vi = 0V; pin numbers 7, 24

and 26 -25 -66 -125 µA1

Rpu Equivalent Pull-up Resistance 50 kΩ

Symbol Parameter Test Condition Min. Typ. Max. Unit Note

Power Dissipa tion@ V

= 2.4V

Sampling_freq ≤24 kHz t.b.d. mW

Sampling_freq ≤32 kHz t.b.d. mW

Sampling_freq ≤48 kHz t.b.d. mW

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5 HOST REGISTERS

The following table gives a description of STA016A register list.

The STA016A device includes 256 I

C registers. In this document, only the user-oriented registers are de-

scribed. The undocumented registers are reserved or unused. These registers must never be accessed (in

Read or in Write mode). The Read-Only registers must never be written

We can split the data flux in different time periods (see following diagram) meanw hile host registers can be read

or written :

■DWT : During Whole Time (at any time during process).

■DEC : During External Confi g (period between RUN=2 and RUN=1).

■DBO : During Boot (period between RUN=0 and RUN=2).

■ABO : After BOot (period after RUN=1).

■AEC : After External Config (period after RUN=2).

■EDF : Every Decoded Frame (each time a frame has been decoded ).

■EDB : Every Decoded Block (each time a block has been decoded).

Figure 6.

R RUN==0

SOFT_RESET = 1

CK_CMD = 0

RUN==2 RUN==1 block1

frame1 block2

frame1 block1

frame2 tim

DWT

ABO

DECDBO

AEC

EDB EDB

EDF EDB

D01AU1260

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STA016A

Table 11. REGISTER MAP BY FUNCTION

VERSION 0x00 0 VERSION RO DWT

0x01 1 IDENT RO DWT

0xD3 211 SOFT_VERSION RO DWT

PLL_AUDIO_CONFIGURATION 0xDC 220 PLL_AUDIO_PEL_192 RW DEC

0xDD 221 PLL_AUDIO_PEH_192 RW DEC

0xDE 222 PLL_AUDIO_NDIV_192 RW DEC

0xDF 223 PLL_AUDIO_XDIV_192 RW DEC

0xE0 224 PLL_AUDIO_MDIV_192 RW DEC

0xE1 225 PLL_AUDIO_PEL_176 RW DEC

0xE2 226 PLL_AUDIO_PEH_176 RW DEC

0xE3 227 PLL_AUDIO_NDIV_176 RW DEC

0xE4 228 PLL_AUDIO_XDIV_176 RW DEC

0xE5 229 PLL_AUDIO_MDIV_176 RW DEC

PLL_SYSTEM_CONFIGURATION 0xE6 230 PLL_SYSTEM_PEL_50 RW DEC

0xE7 231 PLL_SYSTEM_PEH_50 RW DEC

0xE8 232 PLL_SYSTEM_NDIV_50 RW DEC

0xE9 233 PLL_SYSTEM_XDIV_50 RW DEC

0xEA 234 PLL_SYSTEM_MDIV_50 RW DEC

0xEB 235 PLL_SYSTEM_PEL_42_5 RW DEC

0xEC 236 PLL_SYSTEM_PEH_42_5 RW DEC

0xED 237 PLL_SYSTEM_NDIV_42_5 RW DEC

0xEE 238 PLL_SYSTEM_XDIV_42_5 RW DEC

0xEF 239 PLL_SYSTEM_MDIV_42_5 RW DEC

I2Sout_CONFIGURATION 0x66 102 OUTPUT_CONF RW DEC

0x67 103 PCM_DIV RW DEC

0x68 104 PCM_CONF RW DEC

0x69 105 PCM_CROSS RW DEC

GPSO_CONFIGURATION 0x66 102 OUTPUT_CONF RW DEC

0x6A 106 GPSO_CONF RW DEC

I2Sin_CONFIGURATION 0x5A 90 INPUT_CONF RW DEC

0x5B 91 I_AUDIO_CONFIG_1 RW DEC

0x5C 92 I_AUDIO_CONFIG_2 RW DEC

0x5D 93 I_AUDIO_CONFIG_3 RW DEC

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CDBSA_CONFIGURATION 0x5A 90 INPUT_CONF RW DEC

0x5B 91 I_AUDIO_CONFIG_1 RW DEC

0x5C 92 I_AUDIO_CONFIG_2 RW DEC

0x5D 93 I_AUDIO_CONFIG_3 RW DEC

0x5E 94 I_AUDIO_CONFIG_4 RW DEC

0x5F 95 I_AUDIO_CONFIG_5 RW DEC

0x60 96 I_AUDIO_CONFIG_6 RW DEC

0x61 97 I_AUDIO_CONFIG_7 RW DEC

0x62 98 I_AUDIO_CONFIG_8 RW DEC

0x63 99 I_AUDIO_CONFIG_9 RW DEC

0x64 100 I_AUDIO_CONFIG_10 RW DEC

0x65 101 I_AUDIO_CONFIG_11 RW DEC

BSB_CONFIGURATION 0x59 89 POL_REQ RW DEC

0x5A 90 INPUT_CONF RW DEC

0x5B 91 I_AUDIO_CONFIG_1 RW DEC

CD_CONFIGURATION 0x40 64 BASIC_COMMAND WO AEC

0x41 65 FAST_FUNCTION_VAL RW ABO

0x42 66 REQUIRED_TRACK RW ABO

0x43 67 REQUIRED_DIR RW ABO

0x44 68 PLAY_MODE RW ABO

0x46 70 TYPE _CD_EXT_REQ RO AEC

0x47 71 MINUTE_REQ RO AEC

0x48 72 SECOND_REQ RO AEC

0x49 73 SECTOR_REQ RO AEC

0x4A 74 MINUTE_SPENT RO AEC

0x4B 75 SECOND_SPENT RO AEC

0x4C 76 SCANNING_TIME RW ABO

0x4D 77 PLAY_LIST_INDEX RW ABO

0x4E 78 PLAY_LIST_VALUE RW ABO

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STA016A

0x86 134 CD_SONG_INFO_C1 RO AEC

0x87 135 CD_SONG_INFO_C2 RO AEC

0x88 136 CD_SONG_INFO_C3 RO AEC

0x89 137 CD_SONG_INFO_C4 RO AEC

0x8A 138 CD_SONG_INFO_C5 RO AEC

0x8B 139 CD_SONG_INFO_C6 RO AEC

0x8C 140 CD_SONG_INFO_C7 RO AEC

0x8D 141 CD_SONG_INFO_C8 RO AEC

0x8E 142 CD_SONG_INFO_C9 RO AEC

0x8F 143 CD_SONG_INFO_C10 RO AEC

0x90 144 CD_SONG_INFO_C11 RO AEC

0x91 145 CD_SONG_INFO_C12 RO AEC

0x92 146 CD_SONG_INFO_C13 RO AEC

0x93 147 CD_SONG_INFO_C14 RO AEC

0x94 148 CD_SONG_INFO_C15 RO AEC

0x95 149 CD_SONG_INFO_C16 RO AEC

0x96 150 CD_SONG_INFO_C17 RO AEC

0x97 151 CD_SONG_INFO_C18 RO AEC

0x98 152 CD_SONG_INFO_C19 RO AEC

0x99 153 CD_SONG_INFO_C20 RO AEC

0x9A 154 CD_SONG_INFO_C21 RO AEC

0x9B 155 CD_SONG_INFO_C22 RO AEC

0x9C 156 CD_SONG_INFO_C23 RO AEC

0x9D 157 CD_SONG_INFO_C24 RO AEC

0x9E 158 CD_SONG_INFO_C25 RO AEC

0x9F 159 CD_SONG_INFO_C26 RO AEC

0xA0 160 CD_SONG_INFO_C27 RO AEC

0xA1 161 CD_SONG_INFO_C28 RO AEC

0xA2 162 CD_SONG_INFO_C29 RO AEC

0xA3 163 CD_SONG_INFO_C30 RO AEC

0xA4 164 CD_SONG_INFO_C31 RO AEC

0xA5 165 CD_SONG_INFO_C32 RO AEC

0xA6 166 CD_SONG_TYPE_INFO RO AEC

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0xA7 167 NB_OF_CUR_TRACK RO AEC

0xA8 168 NB_OF_CUR_DIR RO AEC

0xA9 169 CD_CUR_STATUS RO AEC

0xAA 170 CD_TRACK_FORMAT RO AEC

0xAB 171 CD_NB_OF_SUB_DIR RO AEC

0xAC 172 CD_NB_OF_SUB_FILE RO AEC

0xAD 173 DIRECTORY_LEVEL RO AEC

0xAE 174 DIR_IDENTIFIER_B1 RO AEC

0xAF 175 DIR_IDENTIFIER_B2 RO AEC

0xB0 176 DIR_IDENTIFIER_B3 RO AEC

0xB1 177 DIR_IDENTIFIER_B4 RO AEC

0xB2 178 VOL_IDENTIFIER_B1 RO AEC

0xB3 179 VOL_IDENTIFIER_B2 RO AEC

0xB4 180 VOL_IDENTIFIER_B3 RO AEC

0xB5 181 VOL_IDENTIFIER_B4 RO AEC

0xB6 182 EXTRACT_BYTE_IDX_B1 RW ABO

0xB7 183 EXTRACT_BYTE_IDX_B2 RW ABO

0xB8 184 EXTRACT_BYTE_IDX_B3 RW ABO

0xB9 185 EXTRACT_BYTE_IDX_B4 RW ABO

0xBA 186 EXTRACT_ADR_MODE RW ABO

0xBC 188 CONFIG_MODULE RW DEC

COMMAND 0x10 16 SOFT_RESET WO DWT

0x3A 58 CK_CMD WO DBO

0x55 85 DEC_SEL RW DEC

0x56 86 RUN RW DEC

0x52 82 CRC_IGNORE RW ABO

0x53 83 MUTE RW ABO

0x57 87 SKIP RW ABO

0x58 88 PAUSE RW ABO

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STATUS 0xCC 204 STATUS_MODE RO EDF

0xCD 205 STATUS_CHAN_NB RO EDF

0xCE 206 STATUS_SF RO EDF

0x6F 111 STATUS_FE RO EDF

0xD4 212 HEADER_1 RO EDF

0xD5 213 HEADER_2 RO EDF

0xD6 214 HEADER_3 RO EDF

0xD7 215 HEADER_4 RO EDF

0xD8 216 HEADER_5 RO EDF

0xD9 217 HEADER_6 RO EDF

BYPASSA_CONFIGURATION 0x70 112 CHAN_NB RW DEC

0x71 113 SAMPLING_FREQ RW DEC

0xCB 203 PCMCLK_INPUT RW DEC

MP3_CONFIGURATION 0x52 82 CRC_IGNORE RW ABO

0x6B 107 ERR_DEC_LEVEL RO EDB

0x6C 108 ERR_DEC_NB_1 RO EDB

0x6D 109 ERR_DEC_NB_2 RO EDB

RESERVED 0x70 112 RESERVED

0x71 113 RESERVED

0x72 114 RESERVED

0x73 115 RESERVED

0x74 116 RESERVED

MIX_CONFIGURATION 0x75 117 MIX_MODE RW ABO

0x76 118 MIX_DLA RW ABO

0x77 119 MIX_DLB RW ABO

0x78 120 MIX_DRA RW ABO

0x79 121 MIX_DRB RW ABO

TONE_CONFIGURATION 0x7A 122 TONE_ON RW ABO

0x7B 123 TONE_FCUTH RW ABO

0x7C 124 TONE_FCUTL RW ABO

0x7D 125 TONE_GAINH RW ABO

0x7E 126 TONE_GAINL RW ABO

0x7F 127 TONE_GAIN_ATTEN RW ABO

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6 REGISTER DESCRIPTION

6.1 VERSION registers description

6.1.1 VERSI ON :

Address : 0x00 (0)

Type : RO - DWT

Software Reset : 0x10

H ar d wa r e Reset : 0x10

De scription :

The VERS ION registe r is Read-only and it is used to

identify the IC on the application board.

6.1.2 IDENT :

Address : 0x01 (1)

Type : RO - DWT

So ftware Re se t : 0 xAC

H ar d wa r e Reset : 0xAC

De scription :

IDENT is a read-only register and it is used to identify

the IC on an application board. IDENT always has the

value 0xAC.

6.1.3 SOFT_ VERSION :

Address : 0xD3 (211)

Type : RO - DWT

So ftware Re se t : X

De scription :

The SOFT _VERSION regi s ter i s Read-only and i t is

used to identify the software runn ing on the IC.

6.2 PLL_AUDIO_CONFIGURATION registers

description

6.2.1 PL L_AUDIO_P E L_ 192 :

Address : 0xDC (220)

Type : RW - DEC

So ftware Re se t : 5 8

De scription :

This regi ster must c ontai n a PEL val ue t hat enables

the audio PLL to generate a frequency of ofact*192

kHz for the PCM CK .See table 1, 2 & 3.

ofact is the oversampling factor needed by the DAC

(ofac==246 or ofac==384).

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.2 PLL_AUDIO_PEH_192 :

Address : 0xDD (221)

Type : RW - DEC

So ftware Re se t : 1 8 7

De scription :

This register must contain a PEH value that enables

the audio PLL to generate a frequency of ofact*192

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

– ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.3 PLL_AUDIO_NDIV_192 :

Address : 0xDE (222)

Type : RW - DEC

So ftware Re se t : 0

b7 b6 b5 b4 b3 b2 b1 b0

10101100

b7 b6 b5 b4 b3 b2 b1 b0

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STA016A

De scription :

This register must contain a NDIV value that enables

the audio PLL to generate a frequency of ofact*192

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.4 PLL_AUDIO_XDI V_192 :

Address : 0xDF (223)

Type : RW - DEC

So ftware Re se t : 3

De scription :

This register mus t con tain a XDIV value that enables

the audio PLL to generate a frequency of ofact*192

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.5 PLL_AUDIO_MD IV _192 :

Address : 0xE0 (224)

Type : RW - DEC

So ftware Re se t : 1 2

De scription :

This register must contain a MDIV value that enables

the audio PLL to generate a frequency of ofact*192

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.6 PL L_AUDIO_P E L_ 176 :

Address : 0xE1 (225)

Type : RW - DEC

So ftware Re se t : 5 4

De scription :

This regi ster must c ontai n a PEL val ue t hat enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

– fact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.7 PLL_AUDIO_PEH_176 :

Address : 0xE2 (226)

Type : RW - DEC

So ftware Re se t : 1 1 8

De scription :

This register must contain a PEH value that enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.8 PLL_AUDIO_NDIV_176 :

Address : 0xE3 (227)

Type : RW - DEC

So ftware Re se t : 0

De scription :

This register must contain a NDIV value that enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

b7 b6 b5 b4 b3 b2 b1 b0

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6.2.9 PLL_AUDIO_XDI V_176 :

Address : 0xE4 (228)

Type : RW - DEC

So ftware Re se t : 2

De scription :

This register mus t con tain a XDIV value that enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCM CK .See table 1, 2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.2.10 P L L_AUDIO_M DI V _176 :

Address : 0xE5 (229)

Type : RW - DEC

So ftware Re se t : 8

De scription :

This register must contain a MDIV value that enables

the audio PLL to generate a frequency of ofact*176

kHz for the PCM CK .See table 1,2 & 3.

D e fa ult value at so ft r e se t assume :

–ofact == 256

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3 PLL_SYSTEM_CONFIGURATION

re gisters desc rip tion

6.3.1 P L L_SY STE M_ PEL _50 :

Address : 0xE6 (230)

Type : RW - DEC

So ftware Re se t : 0

De scription :

This regi ster must c ontai n a PEL val ue t hat enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.2 PLL_SYSTEM_PEH_50 :

Address : 0xE7 (231)

Type : RW - DEC

So ftware Re se t : 0

De scription :

This register must contain a PEH value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.3 PL L_SY STE M_ NDIV_50 :

Address : 0xE8 (232)

Type : RW - DEC

So ftware Re se t : 0

De scription :

This register must contain a NDIV value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.4 P L L_SY STE M_ XDIV_50 :

Address : 0xE9 (233)

Type : RW - DEC

So ftware Re se t : 1

b7 b6 b5 b4 b3 b2 b1 b0

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STA016A

De scription :

This register mus t con tain a XDIV value that enables

the system PLL to gener ate a frequency of 50 MHZ

for the SYSCK. See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.5 P L L_SY STE M_ MDIV_50 :

Address : 0xEA (234)

Type : RW - DEC

So ftware Re se t : 1 3

De scription :

This register must contain a MDIV value that enables

the system PLL to generate a frequency of 50 MHz

for the SYSCK. See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.6 PLL_SYSTEM_PEL_42_5

Address : 0xE6 (230)

Type : RW - DEC

So ftware Re se t : 1 2 6

De scription :

This regi ster must c ontai n a PEL val ue t hat enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.7 PLL_SYSTEM_PEH_42_5 :

Address : 0xE7 (231)

Type : RW - DEC

So ftware Re se t : 2 2 3

De scription :

This register must contain a PEH value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.8

6.3.9 PLL_SYSTEM_NDIV_42_5 :

Address : 0xE8 (232)

Type : RW - DEC

So ftware Re se t : 0

De scription :

This register must contain a NDIV value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.10 PLL_SYSTEM_XDIV_42_5 :

Address : 0xE9 (233)

Type : RW - DEC

So ftware Re se t : 1

De scription :

This register mus t con tain a XDIV value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.3.11 PLL_S YST EM_ MDI V_42_5 :

Address : 0xEA (234)

b7 b6 b5 b4 b3 b2 b1 b0

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Type : RW - DEC

So ftware Re se t : 1 0

De scription :

This register must contain a MDIV value that enables

the system PLL to generate a frequency of 42.5 MHz

for the SYSCK.See table 4.

D e fa ult value at so ft r e se t assume :

– external crysta l provide a CRYCK runn ing at

14.31818 MHz

6.4 I

Sout_CONFIGURATION registers

description

6.4.1 OUTPUT_CONF :

Address : 0x66 (102)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If set to 1 enable the configurability of the PCM-

BLOCK Output thanks to following registers, else dis-

able this configurability and take embedded default

configuration for PCM-BLOCK registers.

Note that this embedded def ault configuration can be

retrieved by user thanks to following setting :

– PCM_DI V = 3;

–PCM_CONF = 0;

– PCM_CROSS = 0;

6.4.2 PCM _DIV :

Address : 0x67 (103)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If OUTPUT_CO NF == 1, configure the divider to gen-

erate the bit clock of the I2Sout interface, called

BCK0, from PC MCK. acco rding the following relation

: BCKO = PCMCK / 2 * (P CM _ DIV+1)

6.4.3 P CM _CON F :

Address : 0x68 (104)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If OUTPUT_CONF == 1, configur e the I 2Sout inter-

face according following table

Table 12. .

6.4.4 PCM_CROSS :

Address : 0x69 (105)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If OUTPUT_CONF == 1, CR[1:0] is used to configure

b7 b6 b5 b4 b3 b2 b1 b0

0 0 DV5DV4DV3DV2DV1DV0

b7 b6 b5 b4 b3 b2 b1 b0

0 CO6 CO5 CO4 CO3 CO2 CO1 CO0

Bit

fields Comment

CO[1:0] 0 : 16 bits mode (16 slots transmitted).

1 : 18 bits mode (18 slots transmitted).

2 : 20 bits mode (20 slots transmitted).

3 : 24 bits mode (24 slots transmitted).

CO2 Polarity of BCKO :

0 : data are sent on the falling edge & stable

on the rising).

1 : (data are sent on the rising edge & stable

on the falling).

CO3 0 : I2S format is selected

1 : other format is selected

CO4 Polarity of LRCKO :

0 : low->right, high->left).

1 : low->left, high->right so compliant to I2S

format ).

CO5 0 : data are in the last BCKO cycles of

LRCKO (right aligned data).

1 : data are in the first BCKO cycles of

LRCKO (left aligned data).

CO6 0 : the transmission is LS bit first.

1 : the transmission is MS bit first.

b7 b6 b5 b4 b3 b2 b1 b0

000000CR1CR0

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STA016A

the output crossbar according following table

Table 13. .

6.5 GPSO_CONFIGURATION registers

description

6.5.1 OUTPUT_CONF :

Address : 0x66 (102)

Type : RW - DEC

So ftware Re se t : 0

Description

Table 14. :

Note that embedded default configuration for GPSO

can be retrieved by user thanks to following setting :

– GPSO_CONF = b00000011;

Note that embedded default configuration for PCM

block is described at previous chapter.

6.5.2 GPSO_CONF :

Address : 0x6A (106)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If OUTPUT_CONF == 1, this register configure the

GPSO interface

Table 15. .

6.6 I

Sin_CONFIGURATION registers

description

6.6.1 INPUT_CO NF :

Address : 0x5A (90)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If set to 1 enable the configurability o f the I2S in I nput

thanks to following registers, else disable this config-

urability and take embedded default configuration for

I2Sin registers.

Note that this embedded def ault configuration can be

retrieved by user thanks to following setting :

– I_AUDIO _CON FI G_1 = b0000 0110;

– I_AUDIO _CON FI G_2 = b1110 0000;

– I_AUDIO _CON FI G_3 = b0000 0001;

CR1 CR0 Comment

0 0 Left channel is mapped on the left

output.

Right channel is mapped on the right

output.

0 1 Left channel is duplicated on both output

channels.

1 0 Right channel is duplicated on both

output channels.

1 1 Right and left channels are toggled.

b7 b6 b5 b4 b3 b2 b1 b0

XXXXX0C2OC1OC0

Bit fields Comment

OC0 Configuration of gpso :

0 : take embedded default configuration.

1 : configure gpso from register

GPSO_CONF.

OC1 Use of block PCM to generate clocks

(PCMCK, LRCK & BCK):

0 : no use.

1 : use it.

OC2 Configuration of PCM block:

0 : take embedded default configuration.

1 : configure PCM block from PCM_DIV

& PCM_CONF registers.

b7 b6 b5 b4 b3 b2 b1 b0

CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0

Bit

fields Comment

CF0 Polarity of GPSO_CK :

0 : data provided on rising edge & stable on

falling edge

1 : data provided on falling edge & stable on

rising edge

CF1 Polarity of GPSO_REQ :

0 : data are valid when GPSO_REQ is high

1 : data are valid when GPSO_REQ is low

CF[7:2] Reserved : to be set to 0.

b7 b6 b5 b4 b3 b2 b1 b0

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6.6.2 I_AUDIO_CONFIG_1:

Address : 0x5B (91)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, this register configure the

I2S in inter fa ce

Table 16. .

Table 17.

6.6.3 I_AUDIO_CONFIG_2 :

Address : 0x5C (92)

Type : RW - DEC

So ftware Re se t : 0

De scription :

See I_AUD IO_CONFIG_3 register description..

6.6.4 I_AUDIO_CONFIG_3 :

Address : 0x5D (93)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, thi s register is used to confi g-

ure the phase of the LRCK of the I

Sin.

Table 18.

b7 b6 b5 b4 b3 b2 b1 b0

CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0

Bit

fields Comment

CF0 Rel ative synch ro :

0 : synchro with first data bit

1 : synchro one bit before first data bit

CF1 Data reception configuration :

0 : LSB first

1 : MSB first

CF2 Polarity of bit clock BCK :

0 : data provided on falling edge & stable

on rising edge.

1 : data provided on rising edge & stable

on falling edge

CF3 Polarity of LR clock LRCK :

0 : negative

1 : positive

CF4 St art value of LRCK : combined with CF3,

this bit enable user to determine left/right

couple according to the following table.

CF[7:5] Reserved : to be set to 0.

CF3 CF4 Left/Right couples

0 0 (data1/data2), (data3/data4),...

1 0 (data0/data1), (data2/data3),...

0 1 (data0/data1), (data2/data3),...

1 1 (data1/data2), (data3/data4),...

b7 b6 b5 b4 b3 b2 b1 b0

LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0

b7 b6 b5 b4 b3 b2 b1 b0

000000LR9LR8

Bit fields Comment

LR[4:0] Position of the data within the LRCK

phase :

- if CF1 = 0 (LSB), value must be set to[31

- SL[9:5] - bit position of the first bit of data

within the LRCK phase].

- if CF1 = 1 (MSB), value must be set to bit

position of the first bit of data within the

LRCK phase.

Note that range of value for this bit

position is [0:31].

LR[9:5] Length-1 of the data.

Max value is 31.

LR[15:10] Reserved : to be set to 0

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STA016A

6.7 CDBSA_CONFIGURATION registers

description

6.7.1 INPUT_CO NF :

Address : 0x5A (90)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If set to 1 enable the configurability of the CD & BS

input interfaces in audio mode thanks to following

registers, else disable this configurability and take

emb edded default configuration.

Note that this embedded def ault configuration can be

retrieved by user thanks to following setting :

– I_AUDIO _CON FI G1 = b00010 010;

// clocks in input

// & polarity negative

– I_AUDIO _CON FI G2 = b00110 010;

// synchro with first data bit

// data unsigned , MSB first

– I_AUDIO _CON FI G3 = b11001 111;

// LRCK phase length is 1

– I_AUDIO _CON FI G4 = b00000 011;

// LRCK phase length is 16

– I_AUDIO_CONFIG5 = 0x FF;

// received 16 bits

– I_AUDIO_CONFIG6 = 0x FF;

// received 16 bits

– I_AUDIO_CONFIG7 = 0x 00;

// received 16 bits

– I_AUDIO_CONFIG8 = 0x 00;

// received 16 bits

– I_AUDIO_CONFIG9 = 16;

// data size is 16

– I_AUDIO _CON FI G10 = 0x00;

// no use because clock in input

– I_AUDIO _CON FI G11 = 0x00;

// no use because clock in input

6.7.2 _AUDIO_CONFIG_1 :

Address : 0x5B (91)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, thi s register is used to confi g-

urate CD & B S input interfaces in audio mode

Table 19.

6.7.3 I_AUDIO_CONFIG_2 :

Address : 0x5C (92)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, thi s register is used to confi g-

urate CD & B S input interfaces in audio mode

b7 b6 b5 b4 b3 b2 b1 b0

CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0

Bit Comment

CF0 Reserved : to be set to 0

CF1 Reserved : to be set to 1

CF2 Direction of bit clocks CD_BCK & BS_BCK:

0 : input

1 : output

CF3 Polarity of bit clocks CD_BCK & BS_BCK :

0 : data provided on falling edge & stable on

rising edge

1 : data provided on rising edge & stable on

falling edge

CF4 Reserved : to be set to 1

CF5 Direction of LR clocks CD_LRCK &

BS_LRCK :

0 : input

1 : output

CF6 Polarity of LR clocks CD_LRCK &

BS_LRCK :

0 : left sample corresponds to the low level

phase of LRCK

1 : left sample corresponds to the high level

phase of LRCK

CF7 Reserved : to be set to 0

b7 b6 b5 b4 b3 b2 b1 b0

CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8

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Table 20. .

6.7.4 I_AUDIO_CONFIG_3 :

Address : 0x5D (93)

Type : RW - DEC

So ftware Re se t : 0

De scription :

See I_AUD IO_CONFIG_4 register description..

6.7.5 I_AUDIO_CONFIG_4 :

Address : 0x5E (94)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, thi s register is used to confi g-

urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS

input interfaces in audio mode.

Table 21.

6.7.6 I_AUDIO_CONFIG_5:

Address : 0x5F (95)

Type : RW - DEC

So ftware Re se t : 0

De scription :

See I_AUD IO_CONFIG_8 register description.

6.7.7 I_AUDIO_CONFIG_6 :

Address : 0x60 (96)

Type : RW - DEC

So ftware Re se t : 0

De scription :

See I_AUD IO_CONFIG_8 register description..

6.7.8 I_AUDIO_CONFIG_7 :

Address : 0x61 (97)

Type : RW - DEC

So ftware Re se t : 0

De scription :

See I_AUD IO_CONFIG_8 register description..

Bit Comment

CF8 Relative synchro :

0 : synchro with first data bit

1 : synchro one bit before first data bit

CF9 Data reception configuration :

0 : LSB first

1 : MSB first

CF10 Arithmetic type of the reception :

0 : unsigned data

1 : signed data

CF11 Bit to select the reference clock used to

generate BCK if clocks are in output

(CF2=1 & CF5=1). Otherwise this bit is

useless.

0 : SYSCK

1 : PCMCK

CF12 Reserved : to be set to 1

CF13 Reserved : to be set to 1

CF14 Reserved : to be set to 0

CF15 Reserved : to be set to 0

b7 b6 b5 b4 b3 b2 b1 b0

LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0

b7 b6 b5 b4 b3 b2 b1 b0

LR15 LR14 LR13 LR12 LR11 LR10 LR9 LR8

Bit fields Comment

LR[5:0] Length-1 of phase 1 of LR clocks

CD_LRCK & BS_LRCK.

Max value is 31.

LR[11:6] Length-1 of phase 2 of LR clocks

CD_LRCK & BS_LRCK.

Max value is 31.

LR[15:12] Reserved : to be set to 0

b7 b6 b5 b4 b3 b2 b1 b0

MA7MA6MA5MA4MA3MA2MA1MA0

b7 b6 b5 b4 b3 b2 b1 b0

MA1

5MA1

4MA1

3MA1

2MA1

1MA1

0MA9 MA8

b7 b6 b5 b4 b3 b2 b1 b0

MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16

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STA016A

6.7.9 I_AUDIO_CONFIG_8 :

Address : 0x62 (98)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, those registers are used to

configure the MASK to be appllied to CD_LRCK &

BS _LRC K phas e 1 & 2.

– if MAi set to 0, then bit i of both phases is not

received.

– if MA i set to 1, th en bit i of both phas es is re-

ceived.

6.7.10 I_AUDIO_CONF IG_9 :

Address : 0x63 (99)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, thi s register is used to confi g-

urate the size of the data to be received by CD & BS

input interfaces in audio mode. Max is 32.

6.7.11 I_ AUDIO_CONF IG_10 :

Address : 0x64 (100)

Type : RW - DEC

So ftware Re se t : 0

De scription :

See I_AUD IO_CONFIG_11 register description.

6.7.12 I I_AUDIO _CONFI G_11 :

Address : 0x65 (101)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, those registers are used to

create BCK if configurated in output (so if CF2=1 &

CF5=1): then value of DV[15:0] is the divider factor to

be applied to the selec ted clock ( CF11 selec t either

SY SC LK or PC M CLK ) to create BCK.

Note : value 0 & 1 corres pond to a bypas s of the di -

viders.

6.8 B SB_CONFIGURATIO N registers

description

6.8.1 P OL _REQ :

Address : 0x59 (89)

Type : WO - DEC

So ftware Re se t : 0

De scription :

This register manage the polarity of the data REQ

signal DREQ of the BS input interface.

If set to 0, data are requested when REQ = 0.

If set to 1, data are requested when REQ = 1.

6.8.2 INPUT_CO NF :

Address : 0x5A (90)

Type : RW - DEC

So ftware Re se t : 0

De scription :

b7 b6 b5 b4 b3 b2 b1 b0

MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24

b7 b6 b5 b4 b3 b2 b1 b0

DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0

b7 b6 b5 b4 b3 b2 b1 b0

DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0

b7 b6 b5 b4 b3 b2 b1 b0

DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8

b7 b6 b5 b4 b3 b2 b1 b0

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If set to 1 enable the configurabi l ity of the BSB input

interfaces in burst mode thanks to following register,

else disable this configurability and take embedded

default configuration.

Note that this embedded def ault configuration can be

retrieved by user thanks to following setting :

– I_AUDIO_CONFIG1 = b00000000;// polarity

choice

6.8.3 I_AUDIO_CONFIG_1 :

Address : 0x5B (91)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If INPUT_CONF == 1, thi s register is used to confi g-

ure BS B bit clock

Table 22. .

6.9 CD_CONFIGURATION registers

description

BASIC_COMMAND

Address : 0x40 (64)

Type : RW - AEC

So ftware Re se t : 0

De scription :

Used for giving to dsp basic cd-player commands

Table 23. .

6.9.1 FAST_FUNCTIONAL_VAL :

Address : 0x41 (65)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the volume of fast function.

For the “fast forward function” it is a number betw een

1 and 20.

For the “fast rewind function” it is a number of second

6.9.2 REQ UIRED_TRACK :

Address : 0x42 (66)

Type : RW - ABO

So ftware Re se t : 0

De scription :

b7 b6 b5 b4 b3 b2 b1 b0

0000000CF0

Bit Comment

CF0 Polarity of bit clock BS_BCK :

0 : data provided on falling edge & stable

on rising edge.

1 : data provided on rising edge & stable

on falling edge.

b7 b6 b5 b4 b3 b2 b1 b0

Value Command

1 stop playing music

2 pause

3fast forward

4 fast rewind

5track up

6 track down

9 directory down

10 directory up

11 play specified track

12 set a play-list index

13 edit play list

14 play current dir

15 play cd from beginning

112 start playing music

113 start searching bytes/mute navigation

124 ID3 name of song required

125 ID3 name of author required

126 ID3 name of album required

127 name of file required

128 name of directory required

b7 b6 b5 b4 b3 b2 b1 b0

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This specifies the number of track to play.

6.9.3 REQ UIRED_DIR :

Address : 0x43 (67)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the number of directory to

play.

6.9.4 PL AY_ MODE :

Address : 0x44 (68)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the playing mode

Table 24. .

6.9.5 TYPE_CD_EXT_REQ:

Address : 0x46 (70)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the type of request sent to the

cd module

Table 25. .

6.9.6 MINUTE_REQ :

Address : 0x47 (71)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This regi ster specifies to the CD module t he minute

location requested.

6.9.7 SECOND_REQ :

Address : 0x48 (72)

Type : RO - AE C

So ftware Re se t : 0

b7 b6 b5 b4 b3 b2 b1 b0

Bit Mode

[1:0] end of directory:

0: play next directory

1: replay same directory

2: make pause.

other: reserved

[3:2] end of track:

0: play next track.

1: replay same track.

2: make pause.

other: reserved

4 next track choice:

0: linear mode.

1: random mode.

5 playing time for track:

0: until end of track.

1: scanning mode.

6 end of CD:

0: stop.

1: replay same CD..

b7 b6 b5 b4 b3 b2 b1 b0

Value Signification

10 application is in pause after EOT or EOD

18 request for a sector

20 begin of track reached

30 ready to receive a new command

35 dsp ready to run

40 cd application stopped.

66 time spent on track available

112 request for root

120 song information available

b7 b6 b5 b4 b3 b2 b1 b0

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De scription :

This register specifies to the CD module the second

location requested.

6.9.8 SE CTOR_RE Q :

Address : 0x49 (73)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies to the CD module the sector lo-

cation requested.

6.9.9 MINUTE_ SPENT :

Address : 0x4A (74)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the number of minute spent

from the beginning of the tr ack. It i s r eset at t he be-

ginning of a new track.

6.9.10 SECOND_SPENT :

Address : 0x4B (75)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the number of second spent

from the beginning of the track. It is resected at the

beginning of a new track.

6.9.11 SCANNING_ TIME :

Address : 0x4C (76)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies in second (<60) the playing

time for each track in scanning mode.

6.9.12 PL AY_ LIST_INDEX:

Address : 0x4D (77)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the index in the play list of the

song to enter in the play list, it is also a value between

1 and the maximum number of track in the directory.

6.9.13 PLAY_LIST _VALUE:

Address : 0x4E (78)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the song index in the directory

to enter in the play list, it is also a value between 1

and the maximum number of track in the directory.

6.9.14 CD_SONG_INFO_Cn :

Address : 0x86 (134) to 0xA5 (165)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register contains the n

character of the song

info required (ASCII code).

b7 b6 b5 b4 b3 b2 b1 b0

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6.9.15 CD_SONG_TYPE_INFO :

Address : 0xA6 (166)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the kind of current information

contained in the

Table 26.

When the track has changed the previous informa-

tion are declared “not valid”. New valid information

should be requested by user.

6.9.16 NB_OF_CUR_TRACK :

Address : 0xA7 (167)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the number of the current track

into his d irectory (sub-directories included): from 1 to

max number of track/subdirectory.

6.9.17 NB_OF_CUR_DIR :

Address : 0xA8 (168)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the number of the current di-

rectory into the CD: fro m 1 to m ax number of directo-

ry. This number is negati ve i f goi ng back ward to t he

end of the CD with the command directory-down.

6.9.18 CD_CUR_STATUS :

Address : 0xA9 (169)

Type : RO - AB O

So ftware Re se t : 0

De scription :

This register gives the status of the CD application.

Table 27.

b7 b6 b5 b4 b3 b2 b1 b0

Value Signification

0 inform ation not valid

1 ID3 song name information

2 ID3 author name information

3 ID3 album name information

4 file name information

5 directory name information

6 bytes reque sted

7 play list content

b7 b6 b5 b4 b3 b2 b1 b0

Bit Mode

0 0: unknown format.

1: recognized format

1 reserved.

2 0: searching track.

1: track founded.

3 0: ID3 present.

1: ID3 missing.

4 0: no error detected.

1: error detected.

5 0: CD application in pause.

1: CD application not in pause.

6 0: CD not p layable.

1: CD playable.

7 0: music mode.

1: searching bytes mode

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6.9.19 CD_TRACK_FORMAT :

Address : 0xAA (170)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the format of the played tr ack

considering the extension name. Only 1 bit can be set

in th e sa me time

Table 28. :

6.9.20 NB_ OF_ SUBDIR :

Address : 0xAB (171)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the number of sub-directory in

the current directory.

6.9.21 NB_ OF_ SUB_TRACK :

Address : 0xAC (172)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the number of file in the current

directory.

6.9.22 DIRECTO RY _LEVEL :

Address : 0xAD (173)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register specifies the current directory level.

6.9.23 DI R_ID ENTIFIER _Bn :

Address : 0xAE (174) to 0xB1 (177)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register s pecif ies the nth byte of the number of

byte of the current directory. Co nsidering that two di-

rectories have very few chance to have exactly the

same number of byte, thi s number all ows to i dentify

the directory. The first byte (174) is the MSB and the

last one (177) is the LSB.

6.9.24 VOL_IDENTIFIER_Bn:

Address : 0xB2 (178) to 0xB5 (181)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register s pecif ies the nth byte of the number of

byte of the CD. Considering that two CD have very

few chance to have exactly the same nu mber of byte,

this number allows to identify the CD. The first byte

(178) is the MSB and the last one (181) is the LSB.

b7 b6 b5 b4 b3 b2 b1 b0

Bit FORMAT

0 0 : UNKNOWN

1 : MP3

1 1: RESERVED

2MPEG1

3MPEG2

4MPG

b7 b6 b5 b4 b3 b2 b1 b0

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6.9.25 EX TRACT _BY TE_IDX_Bn:

Address : 0xB6 (182) to 0xB8 (185)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the n

byte of the index of the

byte block to extract from the CD. This number

should be relati ve to the begi nning of t he tr ack con-

taining these bytes.

6.9.26 EX TRACT_ADR_M O DE :

Address : 0xBA (186)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies addressing mode type for byte

extraction: if set to 0, it is a relative (to the beginning

of the current file) addressing mode, if set to 1 it is an

absolute addressi ng mode (r elati ve t o the beginning

of the CD).

6.9.27 CD_CONFIG_MO DULE :

Address : 0xBC (188)

Type : RO - AB O

So ftware Re se t : 0 xA

De scription :

This register set some parameters describing the

way the module transmit the data to the DSP

Table 29. .

6.10COMMAND reg isters descrip tion

6.10.1 SOFT_RESET :

Address : 0x10 (16)

Type : WO - DWT

So ftware Re se t : 0

De scription :

When user write 1 in this register, a soft reset occurs.

The core command register and the interrupt re gister

are cleared. The decoder goes into idle mode.

6.10.2 CK_ CMD :

Address : 0x3A (58)

Type : WO - DBO

So ftware Re se t : 1

H ar d wa r e Reset : 1

De scription :

After a soft reset, user must write 0 in CK_CMD to run

the core clock of the chi p. T his will begin the boot of

the chip, and so get it out of its idle state.

6.10.3 DEC_S EL :

Address : 0x55 (85)

Type : RW - DEC

So ftware Re se t : 0

b7 b6 b5 b4 b3 b2 b1 b0

Bit FORMAT

0 0: valid data byte swapped.

1: valid data not byte swapped.

1 0: ID3 tag not checked

1: ID3 tag checked

other reference for counting sector in

minute.

b7 b6 b5 b4 b3 b2 b1 b0

Bit FORMAT

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De scription :

This register select the decoding data flux according

the mode written in following table

Table 30. .

6.10.4 RUN :

Address : 0x56 (86)

Type : RW - DEC

So ftware Re se t : 0

De scription :

– When a soft ware reset occurs, register RUN

is reset (value 0) by the dsp (see I).

– When boot routines are finished, the dsp

write inside RUN register the value 2 : this is

the start of the external configuration period

(start of DEC : see I).

– When the external device wants to end the

external configuration period, it must write the

value 1 inside the register RUN: this is the run

command that starts the decoding process

(see I).

6.10.5 CRC_ IGNORE :

Address : 0x52 (82)

Type : RW - ABO

So ftware Re se t : 0

De scription :

For decoders having CRC abilities (see each decod-

er configuration), if set to 0 enable the check of CRC,

if set to 1 disable the check of the CRC.

6.10.6 MUTE :

Address : 0x53 (83)

Type : RW - ABO

So ftware Re se t : 0

De scription :

For decoders having MUTE abilities (see each de-

coder configuration), if set to 0 disable the mute of the

decoder, if set to 1 enable the mute of the decoder.

Note that duri ng a MUTE the i nput st ream keeps on

entering.

6.10.7 SKIP :

Address : 0x57 (87)

Type : RW - ABO

So ftware Re se t : 0

De scription :

For data fl ux using USSB Input, if SKIP == n>2, de-

coder skip (n-1) out of n frames. Note that maximum

value for n is 8, and if n==0 or n==1, no frames is

skipped.

6.10.8 PAUSE :

Address : 0x58 (88)

Type : RW - ABO

So ftware Re se t : 0

Bit(7:0) Mode

0CD_MP3

1 CD_BYPASSA

2 RESERVED

3 BSB_MP3

4 RESERVED

5 RESERVED

6 RESERVED

7 BSA_BYPASSA

8 RESERVED

9 I2Sin_BYPASSA

10 SINE (test mode chip alive)

b7 b6 b5 b4 b3 b2 b1 b0

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De scription :

For decoders having PAUSE abilities (see each de-

coder configurati on), if set to 0 disable t he pause of

the decoder, if set to 1 enable the pause of the de-

coder. Note that during a PAUSE the input stream is

stopped.

6.11STATUS registers description

6.11.1 S T ATUS_M ODE :

Address : 0xCC (204)

Type : RO - EDF

So ftware Re se t : 0

De scription :

This register give the type of the currently decoded

bitstream according following table

Table 31. .

6.11.2 ST ATUS_CHANS _NB :

Address : 0xCD (205)

Type : RO - EDF

So ftware Re se t : 0

De scription :

This register gives the number of channel currently

decoded.

6.11.3 S T ATUS_SF :

Address : 0xCE (206)

Type : RO - EDF

So ftware Re se t : 0

De scription :

This register gives the index of the sampling frequen-

cy of the stream currently decoded. Note that sam-

pling frequency indexes are given by table 5

6.11.4 S T ATUS_FE :

Address : 0x6F (111)

Type : RO - AE C

So ftware Re se t : 0

De scription :

This register give the status of the synchronization

process according following table.

Table 32.

b7 b6 b5 b4 b3 b2 b1 b0

Value Mode

0MP3

1MP3_25

2 RESERVED

3 RESERVED

4 RESERVED

5 RESERVED

6 RESERVED

7 BYPASS

8 RESERVED

9 RESERVED

10 RESERVED

11 MPG2

12 RESERVED

13 RESERVED

14 RESERVED

15 RESERVED

16 RESERVED

17 RESERVED

18 UNKNOWN

b7 b6 b5 b4 b3 b2 b1 b0

Value Level

0 Syncrho not started

1 Syncword found

2 Syncword searc h

3 Syncword hard to find

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6.11.5 HEADE R _n:

Address : 0xD4 (212) to 0xD9 (217)

Type : RO - EDF

So ftware Re se t : 0

De scription :

This register give the nth byte of the header of the

frame currently decoded

6.11.6 PC M CLK_INPUT :

Address : 0xCB (203)

Type : RW - DEC

So ftware Re se t : 0

De scription :

If set to 1, the PCMCLK pad is configure as input in

order to receive an external reference clock.

6.12MP3_CONFIGURATION registers

description

6.12.1 ERR_DEC_LEVEL :

Address : 0x6B (107)

Type : RO - EDF

So ftware Re se t : 0

De scription :

This register give the status of the mp3 decoding pro-

cess according the err or level wr itten i n fol l owing t a-

ble.

Table 33.

6.12.2 ERR_DEC_NB_1 :

Address : 0x6C (108)

Type : RO - EDF

So ftware Re se t : 0

De scription :

See E RR _DE C_NB_2 register description.

6.12.3 ERR_DEC_NB_2 :

Address : 0x6D (109)

Type : RO - EDF

So ftware Re se t : 0

De scription :

This register give the status of the mp3 decoding pro-

cess according the error number written in foll owing

table

Table 34.

b7 b6 b5 b4 b3 b2 b1 b0

Value Level

0 No error

1 Warning while decoding

2 Error while decoding

3 Fatal error while decoding

b7 b6 b5 b4 b3 b2 b1 b0

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

b7 b6 b5 b4 b3 b2 b1 b0

ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8

Event Comment

ER0 == 1 crc_erro r

ER1 == 1 cutoff_error

ER2 == 1 big_valu e_err or

ER3 == 1 hufftable_error

ER4 == 1 mod_bu f_size _erro r

ER5 == 1 huffman_de code _error

ER6 == 1 dynpart_ex chan ge_er ror

ER7 == 1 gr_lengt h_err or

ER8 == 1 input_bi t_ava ilable_error

ER9 == 1 ch_leng th_err or

ER10 == 1 head_framelength_error

ER11 == 1 dynpart_length_error

ER12 == 1 block_type_error

ER13 == 1 head_emphasis_error

ER14 == 1 head_samp_freq_error

ER15 == 1 head_layer_error

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6.13MIX_CONFIGURATION registers

description

6.13.1 MIX_MODE:

Address : 0x75 (117)

Type : RW - ABO

So ftware Re se t : 2

De scription :

This register selectes the mode of mix/volume control

Table 35. :

6.13.2 MIX_DLA:

Address : 0x76 (118)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the direct left attenuation (in

dB).

6.13.3 MIX_DLB:

Address : 0x77 (119)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specif ies the left at tenuation (in dB) on

rigth channel.

6.13.4 M I X_D RA:

Address : 0x78 (120)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the direct right attenuati on (in

dB).

6.13.5 M I X_D RB:

Address : 0x79(121)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the rigth attenuation (in dB) on

left channel.

6.14TONE_CONFIGURATION registers

description

6.14.1 TONE_O N:

Address : 0x7A(122)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register enables/diseables (1/0) the tone control.

6.14.2 T ONE_F CUTH :

Address : 0x7B(123)

Type : RW - ABO

So ftware Re se t : 2 0

b7 b6 b5 b4 b3 b2 b1 b0

Value Mode

0 diseable mix/volume control

1 volume control

2 mono to stereo (up-mix)

3 stereo to mono (down-mix)

b7 b6 b5 b4 b3 b2 b1 b0

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De scription :

This register specifies the high cut frequency: fcut(in

Hz)=(TONE_FCUTH+1)*50.

6.14.3 TONE_FCUTL :

Address : 0x7C(124)

Type : RW - ABO

So ftware Re se t : 1 0

De scription :

This register specifies the low cut frequency: fcut(in

Hz) = (T ONE_FCUT L+ 1)*10

6.14.4 T ONE_G AINH :

Address : 0x7D(125)

Type : RW - ABO

So ftware Re se t : 1 2

De scription :

This register s pecifies the gai n on high frequenc ies:

gain(in Db)=(TONE_G AINH-12)*1.5

6.14.5 TONE_GAINL :

Address : 0x7E(126)

Type : RW - ABO

So ftware Re se t : 1 2

De scription :

This register s pecifies t he gain on high fr equencies:

gain (i n Db)=(TONE_GAINL-12)*1.5. V alue of regi s-

ter fro m 0 to 2 4.

6.14.6 T ONE_G AIN_ATTEN :

Address : 0x7F(127)

Type : RW - ABO

So ftware Re se t : 0

De scription :

This register specifies the attenuation on global spec-

trum: gain (in dB)=-TONE_GAIN_ATTEN*1.5. Value

of register from 0 to 12.

b7 b6 b5 b4 b3 b2 b1 b0

6.15TABLES

Table 36. values to configure audi o PLL for ofact==256.

This table give values to configure the audio PLL according CRYCK so that to generate a PCMC K == 256*SF.

10 CRYCK in MHz

14.31818 CRYCK in MHz

14.7456

PLL_AUDIO_PEL_192 42 58 85

PLL_AUDIO_PEH_192 169 187 85

PLL_AUDIO_NDIV_192 0 0 0

PLL_AUDIO_XDIV_192 3 3 0

PLL_AUDIO_MDIV_192 18 12 2

PLL_AUDIO_PEL_176 56 54 0

PLL_AUDIO_PEH_176 16 118 64

PLL_AUDIO_NDIV_176 0 0 0

PLL_AUDIO_XDIV_176 3 2 3

PLL_AUDIO_MDIV_176 17 8 11

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Table 37. values to configure audi o PLL for ofact==384

This table give values to configure the audio PLL according CRYCK so that to generate a PCMC K == 384*SF.

Table 38. values to configure audi o PLL for ofact==512.

This table give values to configure the audio PLL according CRYCK so that to generate a PCMC K == 512*SF.

10 CRYCK in MHz

14.31818 CRYCK in MHz

14.7456

PLL_AUDIO_PEL_192 224 108 0

PLL_AUDIO_PEH_192 190 76 0

PLL_AUDIO_NDIV_192 0 0 0

PLL_AUDIO_XDIV_192 1 1 1

PLL_AUDIO_MDIV_192 13 9 9

PLL_AUDIO_PEL_176 42 54 0

PLL_AUDIO_PEH_176 140 118 48

PLL_AUDIO_NDIV_176 0 0 0

PLL_AUDIO_XDIV_176 1 1 1

PLL_AUDIO_MDIV_176 12 8 8

10 CRYCK in MHz

14.31818 CRYCK in MHz

14.7456

PLL_AUDIO_PEL_192 42 58 85

PLL_AUDIO_PEH_192 169 187 85

PLL_AUDIO_NDIV_192 0 0 0

PLL_AUDIO_XDIV_192 1 0 1

PLL_AUDIO_MDIV_192 18 5 12

PLL_AUDIO_PEL_176 56 157 0

PLL_AUDIO_PEH_176 16 157 64

PLL_AUDIO_NDIV_176 0 0 0

PLL_AUDIO_XDIV_176 1 1 1

PLL_AUDIO_MDIV_176 17 11 11

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Table 39. values to configure system PLL for SYSCK.

This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MH z.

or SYSC K == 42.5MHz.

Table 40. index of the Sampling Freque ncy.

14.31818 CRYCK in MHz

14.7456

PLL_SYSTEM_PEL_50 162 0 28

PLL_SYSTEM_PEH_50 11 0 152

PLL_SYSTEM_NDIV_50 0 0 0

PLL_SYSTEM_XDIV_50 1 1 1

PLL_SYSTEM_MDIV_50 19 13 12

PLL_SYSTEM_PEL_42_5 0 126 100

PLL_SYSTEM_PEH_42_5 0 223 135

PLL_SYSTEM_NDIV_42_5 0 0 0

PLL_SYSTEM_XDIV_42_5 1 1 1

PLL_SYSTEM_MDIV_42_5 16 10 10

Index Frequency

0 48 kHz

1 44.1 kHz

2 32 kHz

4 96 kHz

5 88.2 kHz

6 64 kHz

8 24 kHz

9 22.05 kHz

10 16 kHz

12 12 kHz

13 11.025 kHz

14 8 kHz

16 192 kHz

17 176.4 kHz

18 128 kHz

3, 7, 11, 15 or 19 illegal frequency

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6.16NOTATIONS

ABO : After BOo t ( se e I) .

AEC : After Extern a l Config ( se e I) .

BCK : Bit ClocK

BS A : BitStream input interface in Audio mode.

BS B : BitStream input interface in Burst mode.

BS : BitStream input interface.

BY PAS SA : decoder BYPASS an Audio stream.

CD : input interface for CD.

CK : ClocK.

CRY CK : CRY stal ClocK provided to the chip by an external crystal.

DBO : During BOot (see I).

DEC : During External Config (see I).

DWT : During Whole Time (see I).

EDB : Every Decoded Block (see I).

EDF : Every Decoded Fram e (see I).

LRCK : Left Right ClocK for an I2S interface.

ofact : oversampling factor for PCMCK (P CM CK == ofact * SF).

PCMCK : PCM ClocK (can be generated by the audio PLL).

SF : Sampling Frequency.

SY SC K : SY Stem C locK (clock of the core, can be generated by the system PLL).

X : don’t care.

7 I/O CE LL DESCRIPTION

7.1 TTL Tr istate Ou tp ut P ad Buf fer, 3V capa ble 4mA, with Sle w Rat e Cont rol

Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59

7.2 TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control

Pin numbers: 1, 2, 3, 7, 8, 9, 19

INPUT PIN MAX LOAD

Z 100pF

INPUT PIN CAPACITANCE OUTPUT

PIN MAX

LOAD

IO TBD IO 100pF

D98AU904

D98AU905

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7.3 TTL Schmitt Trigger Inpud Pad Buffer, 3V capable / Pin numbers:17, 60, 63

7.4 TTL Inpud Pad Buffer, 3V capable with Pull-Up / Pin numbers:15, 16

7.5 TTL Schmitt Trigger B idir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V ca pable

Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64

7.6 TTL Input Pad Buffer, 3V capable, with pull down / Pin numb ers: 12, 13, 14, 55

8 COMMAND PROTOCOL CONFIGURATION

General Information About The Command Protocol

I2C protocol :

CD_module & mmdsp are using an I2C protocol to communic ate : CD_module is master of the I 2C protocol,

and can acc ess (in read and write mode) host registers of the STA016A to w rite command s to the mmds p and

to read request from the mmdsp. It must use following I2C syntax :

device_address, host_register_number, host_reg ister_value

where : for a write acces, device_address is 0x86.

for a read acces, device_address is 0x87.

Writing a command to mmdsp :

CD_mod ule write its command inside dedicated host registers (mainly H64 to H69), then it m ust signals the writ-

ing of this com m and to mm dsp by sending the interrupt IT_CMD to the core of mmdsp.

Note that IT_CM D is generated by cd_module threw a falling edge on the input line number 0 of the STA016A

INPUT PIN CAPACITANCE

ATBD

INPUT PIN CAPACITANCE

ATBD

INPUT PIN CAPACITANCE OUTPUT

PIN MAX

LOAD

IO TBD IO 100pF

INPUT PIN CAPACITANCE

ATBD

D98AU906

D98AU907

D00AU115

D00AU122

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STA016A

(the INTLINE[0] pin).

8.0.1 Reading a request from mmdsp :

MM DSP write its request inside dedicated host registers (mainly H70 to H 78 and H134 to H169), then it signals

to cd_module that it must read a request by sending the interrupt IT_REQ.

Note that IT_REQ interrupt is generated by mm dsp on the IRQB pin of STA016A.

Note also that once it has finished to read the message, cd_module must always acknowledge it by reading

H10.

Figure 7. Block diagram for running the CD application.

power on

0000000000000000000000000000000000000000000

00000000000000000000000000000000000000000000000

0000000000000000000000

inserted ?

00000000000000

0000000

00000

0000000000000000000000000000000

wait IT_REQ

with 35 in H 70

000000000000000000000000000000000000000000000000000000000000000000000000

start cd-rom applicatio n :

write 0 i n H85, then 1 in H86

000000000000000000000000000000000000000000000000000000000000000000000000

send play_music command :

write 112 in H64

send IT_CMD

00000000000000000000000000000000000000000000000000000000000000000000000

wait IT_REQ

with 112 in H 70

00000000000000000000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000

00000000000000000000000

any

command?

000000000000000000000000000000000000000000000000

00000000000000000000000

ejected?

000000000000000000000000000000000000000000000000

00000000000000000000000

r un other

application?

000000000000000000000000000000000000000000000000

0000000000

000000

00000

000000000000000000000000000000

0000000000000

000000

00000

000000000000000000000000000

00000

00000000

0000000000000000000000000000000000000000000

send paus e command :

write 2 in H64

send IT_CMD

00000000000000000000000000000000000000000000000000000000

run the other

application

00000000000000000000000000000000000000000000000000000000

00000000000000000000000000000000000000000000000000000000000000000000

000000

00000000000000000000000

0000

000

0000

yes

000000000000000000000000000000000000000000000000

0000000000000000000000

return

to cd?

000000000000

0000000000000

000000

00000

00000000000000000000000000

yes

send other command :

write in H64

send IT_CMD

000000000000000000000000000000000000000000000000000000000000000000000

Hxx: host register

numbe r xx

write 1 in SOFT_RESET

write 0 in CK _CMD

0000000000000000000000000000000000000000000000000000000000000000000000000

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Figure 8. Block diagram for answer to a sector req uest from dsp .

power on

000000000000000000000000000000000000000000000000000

0000000000000000000000000000000000000000000000000000000000000000

000000000000000000000000000000

00000000000000000000000000000000000000000000000000000000

00000000000000000000000000

H70==18

read min ute in H7 1

0000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000

re ad fram e in H73

0000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000

read s econd in H72

0000000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000000

acknowledge

IT_REQ

0000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000

0000000000000000000000000000000000000000

0000000

000000000000000000000000000000000

0000000

000000

00000000000000000000000000000000

00000000000000000000000000000000000

000

please check

with rest of

documentation

move the pick-up

according to m, s,f

0000000000000000000000000000000000000000000000000000

000000000000000000000000000000000000000000000000000

acknowledge

IT_REQ

000000000000000000000000000000000000000000000000000

0000000000000000000000000000000000

000000

00000000000000000000000000000000000000000000000000000

Hxx: host regist er

number xx

IT_REQ occured

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STA016A

Figure 9. TQFP64 Me chanic al Data & Package Dimension s

OUTLI NE AND

MECHANICAL DATA

TQFP64

Seating Plane

0.08mm

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.0066 0.0086 0.0086

C 0.09 0.0035

D 11.80 12.00 12.20 0.464 0.472 0.480

D1 9.80 10.00 10.20 0.386 0.394 0.401

D3 7.50 0.295

e 0.50 0.0197

E 11.80 12.00 12.20 0.464 0.472 0.480

E1 9.80 10.00 10.20 0.386 0.394 0.401

E3 7.50 0.295

L 0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0393

K 0˚ (min.), 3.5˚ (min.), 7˚(max.)

ccc 0.080 0.0031

TQFP64 (10 x 10 x 1.4 mm)

0051434 E

ccc

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Table 41. Revision History

Date Revision Description of Changes

July 2004 1 First Issue

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by i m pl i cati on or otherwise un der any paten t or p aten t r i ghts of STMi croe l ectroni cs . Spec i ficati ons ment i oned in th i s pub lic ation ar e subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as c ri tica l c om ponents in l i fe su pport device s or syst em s wit hout expres s written ap prova l of STMicroe l ectro nics.

Th e ST logo is a regist ered trademark of S TMic roelectroni cs.

All other names are th e property of their resp ectiv e owners

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Obsolete Product(s) - Obsolete Product(s)