19-1133, Rev 0; 10/96 MAXIMA 12-Bit, 20Msps, TTL-Output ADC General Description Features The MAX1171 analog-to-digital converter (ADC) is a 12-bit monolithic ADC capable of sample rates greater than 20Msps. An on-board input buffer and track/noid function ensure excellent dynamic performance without the need for external components. A 5pF input capaci- @ Monolithic, 12-Bit, 20Msps Converter tance minimizes development problems. 66dB SNR at 1MHz Input o 4 On-Chip Track/Hold +2.0V Analog Input Range Logic inputs and outputs are TTL compatible. An over- Low Power: 1.1W range output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is a very low 1.1W with power-supply volt- ages of +5.0V and -5.2V. The MAX1171 also provides a wide input voltage range of +2.0V. The MAX11771 is available in a 32-lead ceramic side- brazed package and a 44-lead surface-mount CERQUAD LZELXUWN SpF input Capacitance TTL-Compatible Outputs package. Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1171CDJ OPC to +70C 32 Ceramic SB Applications MAX1171CBH O'Cto+70%S 44 CERQUAD Radar Receivers Professional Video Instrumentation imaging _ CPi Configurations Digital Communications TOP VIEW Digital Spectrum Analyzers gus [32] VFB 31} VSB 30] VATI : MAXIM j22-) vate Functional Diagram MAXI171 Pa] vin 27} VRT3 26] VST 35 | VFT 24] NC 23) Veco Vin | BUFFER 4-8 FLASH CONVERTER F7) DIGITAL OUTPUT ERROR CORRECTION, DECODING AND 12 OUTPUT TLL ANALOG GAN | | TRACK/ YNCHRONOUS DRIVERS COMPRESSION >} HOLD fom SYNCHRONOUS AN PROCESSOR | | AMPLIFIERS a CERQUAD Pin Configurations continued at end of data sheet. PA AXIS Maxim Integrated Products 7-175 For the Jatest literature: http:/jwww.maxim-ic.com, or phone 1-800-998-8800MAX1171 12-Bit, 2OMsps, TTL-Output ADC ABSOLUTE MAXIMUM RATINGS VOC co ceceeccecceeceneeeeteseene eens certs cae eeeeceegcteeaeescaneecseesatintvseeranieges +6V Digital QUtDUES....... cc ccc cceescccsccecrecssvsevensecsceaares OmA to -30mA VEE occccecccccesteceseeeeecteceaeeeectecsaeneeessecatutesievactauetseesseeseusvenee -6V Operating Temperature Range... OS to +70C Analog input. fee . Veg S$ Vin S VET Junction Temperature (Tp) ee eeeecceeetecseecsessneteecnreeessesenees +475C VFB, VFT ue . B.OV, +3.0V Storage Temperature Range 5C to +150C Reference Ladder Curren we TAMA Lead Temperature (soldering, 10sec) . beeen vaeeeeeteeneeteeess +300C CLIN oc ccccccccceeteeeesctecseseasesercsasecrtettenessesesessavienesencencets Vec Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other Gonditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vcc = +5.0V, Vee = -5.2V, DVcc = +5.0V, Vin = +2.0V, Vsp = -2.0V, VsT = +2.0V, foLk = 20MHz, 50% clock duty cycle, Ta = TMIN to Tmax, unless otherwise noted.) PARAMETER CONDITIONS eve | MIN TYP = MAX _'|_sUNITS Resolution 12 Bits DC ACCURACY (Ta = +25C) Integral Nonlinearity + full scale IV 2.0 LSB Differential Nonlinearity 250kHz sample rate Vv +0.8 LSB No Missing Codes i Guaranteed ANALOG INPUT Input Voltage Range Vi +2.0 Vv Input Bias Current Ta = +25C | 30 60 pA Input Resistance VIN = OV, Ta = +25C I 100 300 kQ Input Capacitance V 5 pF input Bandwidth 3dB small signal Vv 120 MHz Positive Full-Scale Error V +5.0 LSB Negative Full-Scale Error V +5.0 LSB REFERENCE INPUT Reference Ladder Resistance Vi 500 B00 Q Reference Ladder Tempco Vv 0.8 Nec TIMING CHARACTERISTICS Maximum Conversion Rate vi 20 MHz Overvoltage Recovery Time Vv 20 ns Pipeline Delay (Latency) vi 1 Grels Output Delay Ta = +26C Vv 14 18 ns Aperture Delay Time Ta = +25C Vv 1 ns Aperture Jitter Time TA = +25C Vv 5 ps-RMS TATB MAAXIAA12-Bit, 20Msps, TTL-Output ADC ELECTRICAL CHARACTERISTICS (continued) (Vcc = +5.0V, Vee = -5.2V, DVcc = +5.0V, VIN = +2.0V, Vsp = -2.0V, Vst = +2.0V, fcLK = 20MHz, 50% clock duty cycle, Ta = TMIN to Tmax, unless otherwise noted.) PARAMETER CONDITIONS EL MIN TYP MAX UNITS DYNAMIC PERFORMANCE fin = 500kHz 10.2 Effective Number of Bits fin = 1MHz 10.0 Bits fin = 3.58MHz 9.5 Ta = +25C | 64 67 fin = 500kHz IN Ta = TMIN to TMAX IV 58 61 Signal-to-Noise Ratio Ta = +26C | 64 66 : fin = 1MH (without Harmonics) IN 2 Ta = TMIN to TMAX IV 58 60 dB TA = +25C 62 64 fin = 3.58MHz IN Ta = TMIN to TMAX Iv 58 60 Ta = +25C I 63 66 fin = 500kH N 2 Ta = TMIN to TMAX Iv 59 62 Ta = +25C I 63 65 Harmonic Distorti fin = 1MH ic Distortion IN z Ta Twn to Tax iv 50 Bi dB Ta = +25C | 59 61 fin = 3.58MH IN 7 TTa=TmintoTwax| IV 57 59 Ta = +25C I 60 63 fin = 500kH IN 2 Ta=TwintoTwax| IV 55 58 Ta = +25C t 60 62 ignal-to-Noi istorti fin = 1MH Signal-to-Noise and Distortion IN Zz Ta = Twn to Trax iv 3 a7 dB Ta = +25C 57 59 fin = 3.58MH IN=3.68MHZ Twin to Twax | IV 5A 56 Spurious-Free Dynamic Range fin = MHz, Ta = +25C Vv 74 dBc . . fin = 9.58MHz and 4.35MHz, Differential Phase Ta = 425C v 0.2 Degrees Differential Gain fin = 3.58MHz and 4.35MHz, Vv 0.7 % Ta = +25C DIGITAL INPUTS Logic *1" Voltage Vv 2.4 4.0 Vv Logic "0" Voltage Vv 0.8 Vv Maximum Input Current Low Ta = +25C 1 0 5 20 pA Maximum Input Current High Ta = +25C | 0 5 20 yA Pulse Width Low (CLK) IV 20 ns Pulse Width High (CLIK) IV 20 300 ns DIGITAL OUTPUTS Logic 1 Voltage Ta = +25C { 2.4 Vv Logic "0" Voltage Ta = +25C | 0.6 Vv SAAXIAA J-ATT KZELLXVIN12-Bit, 20Msps, TTL-Output ADC we ELECTRICAL CHARACTERISTICS (continued) (Voc = +5.0V, Veg = -5.2V, OVcc = +5.0V, VIN = #2.0V, Vgp = -2.0V, Vst = +2.0V, foLk = 20MHz, 50% clock duty cycle, Ta = TIN to Tmax, unless otherwise noted.) = = s POWER-SUPPLY REQUIREMENTS PARAMETER CONDITIONS tae, | MIN TYP) MAX | UNITS Voc IV 4.76 5.0 5.25 Voltages DVcc lV 4.75 6.0 .25 Vv -VEE IV -4.95 6.2 -5.45 loc, Ta = +25C \ 135 150 Currents Dicc, Ta = TMIN to TMAX Iv 40 55 mA lee, Ta = +25C i 45 70 Power Dissipation vi 444 13 Ww Power-Supply Rejection 5V +0.25V, -5.2V +0.25V Vv 4.0 LSB Note 1: Typical thermal impedances (unsoldered, in free air): 32 Ceramic SB: @j4 = 50C/W 44 CERQUAD: 6ja = 78CMW, 6j, at 1m/s airflow = 58CM, jc = 3.3C/W Use forced-air cooling or heatsinking to maintain Tj < 150C. TEST LEVEL CODES TEST LEVEL TEST PROCEDURE All electrical characteristics are subject to the l following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Iv Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed; therefore, Tj = Tc = Ta. 7-178 Vi 100% production tested at the specitied temperature. 100% production tested at Ta = +25C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and charac- terization data. Parameter is a typical value for information purposes only. 100% production tested at Ta = +25C. Parameter is guaranteed over specified temperature range. MAXIMA12-Bit, 20Msps, TTL-Output ADC Typical Operating Characteristics (fg = 20Msps, fin = 1MHz, Ta = +25C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY vs. INPUT FREQUENCY SNR, THD, SINAD vs. SAMPLE RATE KZELXVIN 80 e gz g 70 F 8 60 o g g 5 a ~ g = = 40 Ss wn 30 20 0.1 1 10 0.1 1 10 1 10 100 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) SAMPLE RATE (Msps} SIGNAL-TO-NCISE AND DISTORTION vs. INPUT FREQUENCY SPECTRAL RESPONSE SNR, THO, SINAD vs. TEMPERATURE 6 8 i i E g a a 40 es =~ S a s 8 z 2 Ee 60 a = a x a a - = : < g 40 7 Pad HAT 7 ao Ce Pepe 0.1 1 10 0 1 2 3 4 5 25 a 25 0 75 INPUT FREQUENCY (MHz) FREQUENCY (MHz) TEMPERATURE (C) SPAAXLMA 7-179MAX1171 12-Bit, 2OMsps, TTL-Output ADC Pin Description PIN Ceramic SB CERQUAD NAME FUNCTION 1,15 14,44 OGND Digital Ground 2-13 43, 44, 1-10 Do-D11 TTL Outputs (D0 = LSB) 14 13 Di2 TTL Output Overrange Bit 16, 32 15, 40 DVcc Digital +5.0V Supply (TTL Outputs) 17 17 CLK TLL Clock Input 18, 31 19, 39 Vee -5.2V Supply 19, 30 21,37 AGND Analog Ground 20, 29 23, 35 Vcc +5.0V Supply 21 25 VFT Force for Top of Reference Ladder 22 26 VST Sense for Top of Reference Ladder 23 27 VRT3 Valtage Reference Tap 3 24 28 VIN Analog Input, 2.0V typical 26 29 VRAT2 Voltage Reference Tap 2 26 30 VAT Voltage Reference Tap 1 27 31 VSB Sense for Bottom of Reference Ladder 28 32 VFB Force for Bottom of Reference Ladder 11, 12, 16, 18, ~ 20, 22, 24, 33, NC. No Connection 34, 36, 38, 42 7-180 PMAAXIIA12-Bit, 20Msps, TTL-Output ADC OUTPUT N-2 Net DATA + : ' \ DATA VALID N Nat DATA VALID Figure 1a. Timing Diagram QUTPUT DATA t DATA VAUD Figure 1b. Single-Event Clock Table 1. Timing Parameters PARAMETER DESCRIPTION MIN TYP MAX UNITS to CLK to Data Valid Prap Delay 14 18 ns tPpWH CLK High Pulse Width 20 300 ns tPWL CLK Low Pulse Width 20 ns Detailed Description Power Supplies and Grounding The MAX1171 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the MAX1171 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria for achieving the optimal device performance. FAAXAAA The MAX1171 requires -5.2V and +5V analog supply voltages. The +5V supply is common to analog Vcc and digital DVcc. A ferrite bead in series with each supply line reduces the transient noise injected into the analog Vcc. These beads should be connected as close to the device as possible. The connection between the beads and the MAX1171 should not be shared with any other device. Bypass each power-sup- ply pin as close to the device as possible. Use 0.1pF for VEE and Vcc, and 0.01uF for DVcc (chip capacitors are preferred). 7-181 LZELXVINMAX1171 12-Bit, 2OMsps, TTL-Output ADC 5) R1 PROVIDES CURRENT LIMITING TO 45mA a (TH) MAM MAXTI71 7 Vin 24] VIN . COARSE _ Di2] 14 (OVERRANGE) ~~ ) we 4 pt (MSB) is 8 sv 2lyn vourl&__e. ee 425V21EVET 6 _ + (Ct + | 0104 12 ue (REF-03) uo oz - 4 OTL 29 o9yti ND TRIM Et < 10k 1 > raat 30k b 0.01 pF ANALOG pa}io _. PRESCALER 1 ole 23 & 7 wo Vv ral = > |5 O.01F ST ose ~ \3 >| = z O5]7 z Ga SUCCESSIVE z ~ 13 O.01F INTERPOLATION [esey 2416 3 2 26 STAGE 1 { vals 0.01uF 10k op-o7 4 " \ peta > a ci 30k ar | D1f3 Z\ / 0.0tur ral Py ! - 4 O0ipF SUCCESSIVE | | volo ase 18 5 a INTERPOLATION |_ ss) FG O.01uF -25V__ 28 | VFB STAGE N = iF oom | 7 sfat tf ste ae ot DGND S| 2] 2|21 S| 3] 4 = Tah 31 VW sen NOTES: 1) D1 = SCHOTTKY OR HOT CARRIER DIODE 2) FB = FERRITE BEAD, FAIR RIGHT P/N 2743001111, TO BE MOUNTED AS CLOSELY AS POSSIBLE. THE FERRITE BEAD TO ADC CONNECTION SHOULD bt NOT BE SHARED WITH ANY OTHER DEVICE. 3) C1-C3 = CHIP CAPACITOR (RECOMMENDED) MOUNTED AS CLOSELY TO THE DEVICE'S PIN AS POSSIBLE 4) USE OF A SEPARATE SUPPLY FOR Voc AND Vcc IS NOT RECOMMENDED anes) 7-182 Figure 2. Typical Interface Circuit MAAXISA12-Bit, 20Msps, TTL-Output ADC AGND and DGND are the two grounds available on the MAX1171. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVcc return path (40mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between Vcc and DVcc is not recommended due to potential power-supply sequencing latchup con- ditions. Use of the recommended interface circuit shown in Figure 2 will provide optimum device performance for the MAX1171. Voltage Reference The MAX1171 requires the use of two voltage refer- ences: Vet and Ves. VET is the force for the top of the - voltage reference ladder (+2.5V typical), Vep (-2.5V typical} is the force for the bottorn of the voltage refer- ence ladder. Both voltages are applied across an inter- nal reference ladder resistance of 800Q. The +2.5V voltage source for reference VFt must be current limit- ed to 20mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in Figures 2 and 3. In addition, there are five reference ladder taps (Vst, VRti, VRtT2, VRT3, and Vsp). Vst is the sense for the top of the reference ladder (+2.0V), VRt2 is the mid- point of the ladder (0.0V typical), and Vsp is the sense for the bottom of the reference ladder {-2.0V). VRT1 and VRT3 are quarter-point ladder taps (+1.0V and -1.0V typical, respectively). The voltages seen at Vst and Vsp are the true full-scale input volfages of the device when Vrt and Vep are driven to the recommended volt- ages (+2.5V and -2.5V typical, respectively). Vst and Vsp can be used to monitor the actual full-scale input voltage of the device. VRtT1, VRT2, and VRT3 should not be driven to the expected ideal values, as is commonly done with standard flash converters. A decoupling capacitor of 0.01pF connected to AGND from each tap is recommended to minimize high-frequency noise injection. The analog input range will scale proportionally with respect to the reference voltage if a different input FAAXLAA Ver Ver ANALOG PRESCALER Vee Figure 3. Analog Equivalent Input Circuit range is required. The maximum scaling factor for device operation is +20% of the recommended refer- ence voltages of VeT and Veg. However, because the MAX1171 is laser trimmed to optimize performance with +2.5V references, its accuracy will degrade if operated beyond a +2% range. An example of a recommended reference driver circuit is shown in Figure 2. IC1 is REF-03, the +2.5V refer- ence with a tolerance of 0.6% or +0.015V. The 10kQ potentiometer supports an adjustable range of 150mvV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3LSB matching between VrT and Ves. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the Veg voltage to the desired level. Adjust R1 and R4 such that Vst and Vsp are exactly +2.0V and -2.0V, respectively. The following errors are defined: +FS error = top of ladder offset voltage = A(+FS - Vst) -FS error = bottom of ladder offset voltage = A(-FS - Vsp) Where the +FS (full scale) input voltage is defined as the output 1LSB above the transition of 1-10 and 1-11, and the -FS input voltage is defined as the output 1LSB below the transition of 0-00 and 0-01. KZELLXVIN 7-183MAX1171 12-Bit, 20Msps, TTL-Output ADC 7-184 N Nei 4 4 ' r CLK IN 24V : 1 \ . 1 i ' 6ns oy t ons a ae ' 3.5V cis oye! NYE owvauo \ INVALIO. Le DATAQUT 1 DATA ( DATA (ACTUAL) 1 W-2} (N-1) : (N) Ce) a a = . 0.5V 1 ! i ! 1 t 1 teos ' ' ' ! 14ns typ : ; ! : ! : ' . ' \ ' 4 ' DATA OUT ! Y INVALID : INVALID (EQUIVALENT) : (N-2) DATA (N-1) 1 DATA (N-1) : i ' ' : Figure 4. Digital Output Characteristics Analog Input The clock input must be driven from fast TTL logic (ViH < VIN is the analog input. The full-scale input range will be 80% of the reference voltage or +2V with Veg = -2.5V and VFT = +2.5V. The drive requirements for the analog inputs are minimal compared to those of conventional flash converters, due to the MAX1171s extremely low SpF input capacitance and high 300kQ input impedance. For example, for an input signal of +2Vp-p with an input frequency of 1O0MHz, the peak output current required for the driving circuit is only 628yA. Clock Input The MAX1171 is driven from a single-ended TTL input (CLK). For optimal noise performance, the clock input slew rate should be a minimum of 6ns. Because of this, the use of fast logic is recommended. The clock input duty cycle should be 50% where possible, but perfor- mance will not be degraded if kept within the range of 40% to 60%. However, in any case, the ciock pulse width (tewH) must be kept at 300ns maximum to ensure proper operation of the internal track/hold amplifier (Figure 1a). The analog input signal is latched on the rising edge of the CLK. 4.5V, tRISE < 6ns). In the event the clock is driven from a high current source, use a 100Q resistor (R1, Figure 2) in series to current limit to approximately 45mA. Digital Outputs The format of the output data (DO-D11) is straight bina- ry (Table 2). The outputs are latched on the rising edge of CLK with a typical propagation delay of 14ns. There is a one clock cycle latency between CLK and the valid output data (Figure 1a). The digital outputs rise times and fall times are not symmetrical. The rise times typical propagation delay is 14ns, and the typical fall time is 6ns (Figure 4). The nonsymmetrical rise and fall times create approximately 8ns of invalid data. Table 2. Output Data Information ANALOG OVERRANGE = OUTPUT CODE INPUT p10 Ds-pe > +2.0V + 1/2LSB 1 11 1111 1444 +2.0V - 1LSB 0 11 $1111 1112 0.0V 0 Q8 220 BBG -2.0V + 1LSB 0 00 0000 0008 <-2.0V 0 00 0000 0000 (@ indicates the flickering bit between logic 0 and 1). PARAAXISA12-Bit, 2OMsps, TTL-Output ADC Overrange Output The overrange output (D12) is an indication that the an- alog input signal has exceeded the full-scale input volt- age by 1LSB. When this condition occurs, the outputs will switch to jogic 1s. All other data outputs are unaf- fected by this operation. This feature makes it possible to include the MAX1171 in higher resolution systems. Evaluation Board The MAX1170 evaluation kit (EV kit) is available to aid designers in demonstrating the full performance of the MAX1171 (or of the MAX1170/MAX1172). This board includes a reference circuit, clock driver circuit, output data latches, and on-board reconstruction of the digital data. A separate EV kit manual describing the opera- tion of this board is available. Contact the factory for price and availability. . PAAXKIAA Pin Configurations (continued) TOP VIEW peno a] * ~ 33] Vcc bo [2] ai] Vee [3] Anaxan [3] AcNo 02 [4] MAXII71 [28] Vcc 03 [5 | 28] vB 04 [6] [27] vse os [7] [26] vats 6 [3 | [25] vat2 o7 [3] [2a] VIN os [19] [23] VATS og [ii] [22] vst pio [12] fat] vet ort [13] 120] vec biz [ia] [19] AGND pen [15] 18] vee DVec [16] 17} CLK Ceramic SB 7-185 KZELXVIN