PROTECTION PRODUCTS
1www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Flip Chip TVS Diode with T-Filter
for Color LCD Interface Protection
Description Features
PIN Configuration
Revision 02/28/2003
5 x 5 Grid Flip Chip (Ball Side View)
The SFC2309-200 is a low pass filter array with
integrated TVS diodes. It is designed to suppress
unwanted EMI/RFI signals and provide electrostatic
discharge (ESD) protection in portable electronic
equipment. This state-of-the-art device utilizes solid-
state silicon-avalanche technology for superior clamp-
ing performance and DC electrical characteristics.
They have been optimized for protection of colorprotection of color
protection of colorprotection of color
protection of color
LCD panelsLCD panels
LCD panelsLCD panels
LCD panels in cellular phones and other portable
electronics.
The device consists of ten identical circuits comprised
of TVS diodes for ESD protection, and a resistor -
capacitor network for EMI/RFI filtering. A series
resistor value of 200Ω and a capacitance value of
45pF is used to achieve 25dB minimum attenuation
from 800MHz to 3GHz. Each line features two stages
of TVS diode protection. The TVS diodes provide
effective suppression of ESD voltages in excess of
15kV (air discharge) and 8kV (contact discharge) per
IEC 61000-4-2, level 4.
The device is a 25-bump, 0.5mm pitch flip chip array
with a 5x5 bump grid. It measures 2.6 x 2.6 x
0.65mm. The solder bumps have a nominal diameter
of 0.315mm.
Mechanical Characteristics
Circuit Diagram
LOW PASS FILTER
Applications
!Color LCD Panel Protection
!Cell Phone Handsets and Accessories
!Personal Digital Assistants (PDA’s)
!Notebook & Hand Held Computers
!JEDEC MO-211, Variation BF, 0.50 mm Pitch Flip
Chip
!Nominal Dimensions: 2.6 x 2.6 x 0.65 mm
!Bump Diameter: 315+/-20 µm
!Marking : Marking code, dot at ball A1
!Packaging : Tape and Reel per EIA 481
!Flip Chip bidirectional EMI/RFI filter with
integrated ESD protection
!ESD protection to IEC 61000-4-2 (ESD) Level4,
+/-15kV (air), +/-8kV (contact)
!Filter performance: 25dB minimum attenuation
800MHz to 3GHz
!TVS working voltage: 5V
!Resistor: 200Ω
!Input Capacitance:45pF
!Protection and filtering for ten lines
!Solid-state technology
Circuit 10x
C
NI
Fp54
R
S
002 Ω
22003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Absolute Maximum Rating
Electrical Characteristics (T=25oC)
gnitaRlobmySeulaVstinU
)riA(2-4-00016CEIrepDSE )tcatnoC(2-4-00016CEIrepDSE V
DSE
51-/+ 21-/+ Vk
erutarepmeTnoitcnuJT
J
521
o
C
erutarepmeTgnitarepOT
po
58+ot04-
o
C
erutarepmeTegarotST
GTS
051+ot55-
o
C
retemaraPretemaraP retemaraP retemaraPretemaraPlobmySlobmyS lobmyS lobmySlobmySsnoitidnoCsnoitidnoC snoitidnoC snoitidnoCsnoitidnoCmuminiMmuminiM muminiM muminiMmuminiMlacipyTlacipyT lacipyT lacipyTlacipyTmumixaMmumixaM mumixaM mumixaMmumixaMstinUstinU stinU stinUstinU
egatloVffO-dnatSesreveRSVTV
MWR
5V
egatloVnwodkaerBesreveRSVTV
RB
I
t
Am1=6801V
tnerruCegakaeLesreveRSVTI
R
V
MWR
V0.3=5.0Aµ
ecnatsiseRseireSlatoTReniLhcaE071002032 Ω
ecnaticapaClatoTC
ni
,dnGottupnI eniLhcaE
V
R
zHM1=f,V0=
5405Fp
3
2003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Typical Characteristics
Capacitance vs. Reverse Voltage
Typical Insertion Loss S21 (Each Line) Analog Crosstalk (Each Line)
ESD Clamping (8kV Contact)
CH1 S21 LOG 6 dB/ REF 0 dB
START . 030 000 MHz STOP 3 000 . 000 000 MHz
C
or
CH1 S21 LOG 20 dB/ REF 0 dB
START . 030 000 MHz STOP 3 000 . 000 000 MHz
C
or
25
30
35
40
45
50
0123456
Bias Voltage - Vbias (V)
Capacitance - CJ (pF)
42003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Applications Information
Device Connection Options
The SFC2309-200 has solder bumps located in a 5 x 5
matrix layout on the active side of the device. The
bumps are designated by the numbers 1 - 5 along the
horizontal axis and letters A - E along the vertical axis.
The input of the lines to be protected are connected at
bumps A1 - A5 and B1 - B5. The line outputs are
connected at bumps D1 - D5 and E1 - E5. Bumps C1 -
C5 are connected to ground. All path lengths should
be kept as short as possible to minimize the effects of
parasitic inductance in the board traces.
Wafer Level CSP TVS
CSP TVS devices are wafer level chip scale packages.
They eliminate external plastic packages and leads and
thus result in a significant board space savings. Manu-
facturing costs are minimized since they do not require
an intermediate level interconnect or interposer layer
for reliable operation. They are compatible with cur-
rent pick and place equipment further reducing manu-
facturing costs. Certain precautions and design
considerations have to be observed however for
maximum solder joint reliability. These include solder
pad definition, board finish, and assembly parameters.
Printed Circuit Board Mounting
Non-solder mask defined (NSMD) land patterns are
recommended for mounting flip chip devices. Solder
mask defined (SMD) pads produce stress points at the
solder mask to solder ball interface that can result in
solder joint cracking when exposed to extreme fatigue
conditions. The recommended pad size is 0.275 ±
0.010 mm with a minimum solder mask opening of
0.325 mm.
Grid Courtyard
The recommended grid placement courtyard is 2.7 x
2.7 mm. The grid courtyard is intended to encompass
the land pattern and the component body that is
centered in the land pattern. When placing parts on a
PCB, the highest recommended density is when one
courtyard touches another.
Pin Identification and Configuration (Ball Side View)
niPnoitacifitnedI
5A-1A5,4,3,2,1seniL,tupnI
5B-1B01,9,8,7,6seniL,tupnI
5C-1CdnuorG
5D-1D01,9,8,7,6seniL,tuptuO
5E-1E5,4,3,2,1seniL,tuptuO
Layout Example (Ball Side View)
1627384 9510
6
172839 4105
Output
Input
5
2003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Applications Information
Recommended NSMD Pad and Stencil Aperture
Solder Reflow Profile
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coat-
ings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving ad-
equate solder volume without compromising assembly
yields. A 0.100mmto 0.200mm thick, laser cut, electro-
polished stencil with 0.330mm apertures corners with
rounded corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using standard
SMT reflow processes. As with any component, ther-
mal profiles at specific board locations can vary & must
be determined by the manufacturer. The flip chip TVS
peak reflow temperature is 230 ± 10 °C, but the
device can withstand up to 260 °C peak reflow tem-
perature for a maximum time of 10 seconds). Time
above eutectic temperature (183 °C) should be 50 ±
10 seconds. During reflow, the component self-aligns
itself on the pad.
Circuit Board Layout Recommendations for Suppres-
sion of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
"Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
"Minimize the path length between the TVS and the
protected line.
"Minimize all conductive loops including power and
ground loops.
"The ESD transient return path to ground should be
kept as short as possible.
"Never run critical signals near board edges.
"Use ground planes whenever possible.
62003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Applications Information
Implementation Example
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
Baseband Controller
LCD Display
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
SFC2309-200
SFC2309-200
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
Baseband Controller
LCD Display
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
1
6
2
7
3
8
4
9
5
10
6
1
7
2
8
3
9
4
10
5
SFC2309-200
SFC2309-200
7
2003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Applications Information
50 Ohms
To Connector
(Output) To Connector
(Input)
50 Ohms
Vg
Insertion Loss Measurement Conditions
Insertion Loss
The insertion loss of the device is the ratio of the
power delivered to the load with and without the filter
in the circuit. This parameter is dependent upon the
impedance of the source and the load. The standard
impedance of test equipment that is used to measure
filter frequency response is 50Ω. In order to obtain an
accurate measurement of the filter performance, an
evaluation board with 50Ω transmission lines are
used. The test conditions for the SFC2309-200 are
shown below. The evaluation board contains SMA
connectors at each of the circuits inputs and outputs.
The connections are made with 50Ω traces. An HP
8753E network analyzer with an internal spectrum
analyzer and tracking generator is used. This equip-
ment has the capability to sweep the device from 3kHz
to 3GHz. The analyzer’s source (RS) impedance is
equal to the load (RL) impedance which is equal to
50Ω. Insertion Loss S21
CH1 S21 LOG 6 dB/ REF 0 dB
START . 030 000 MHz STOP 3 000 . 000 000 MHz
C
or
82003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Applications Information
SFC2309-200 Spice Model & Parameters
SFC2309-200 Spice Model
sretemaraPecipS002-9032CFS
retemaraPtinU)SVT(1D)SVT(2D
SIpmA41-E141-E1
VBtloV1.71.7
JVtloV26.026.0
SRmhO421.0421.0
VBIpmA3-E13-E1
OJCdaraF21-E5221-E52
TTces9-E145.29-E145.2
M--801.0801.0
N--50.150.1
GEVe11.111.1
Line In Line Out
9
2003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Land Pattern
Outline Drawing
0.275
0.5
0.5
102003 Semtech Corp. www.semtech.com
PRELIMINARY
PROTECTION PRODUCTS
SFC2309-200
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Rd., Camarillo, CA 930 12
Phone: (805)498-2111 F AX (805)498-3804
Marking Ordering Information
Top View Showing Laser Mark
-200
2309
Lotcode
rebmuNtraP seireS rotsiseR repytQ leeR eziSleeR
CT.002-9032CFS002 Ω0003hcnI7
Tape and Reel Specification
Tape Specifications Device Orientation in Tape
Pin A1
SFC2309
-200
SFC2309
-200
SFC2309
-200
SFC2309
-200
SFC2309
-200
Add “T” suffix for lead free bumps.
Ex: SFC2309-200.TCT