98DX106-B0-LKJ1C000 - MARVELL TECHNOLOGY GROUP

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G52346, Revision 4.6

September 2, 2003

VSC9180

Data Sheet

Serial 2.5Gb/s Hitless Sonet/SDH Backplane Transceiver

Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: prodinfo@vitesse.com

Internet: www.vitesse.com

1 of 28

General Description

The VSC9180 is a SONET/SDH backplane transceiver with support for working and protection hitless backplane

1+1 protection. It is designed to serialize four STS-12/STM-4 signals, or byte interleaved SONET/SDH/OTN data

from 4-bit 622MHz or 16-bit 155MHz parallel buses onto redundant 2.5Gb/s serial backplane outputs. It receives two

synchronous and serial STS-48/STM-16 signals or G.709 OTU1 signals, recovers the clock, deskews them and then

hitlessly selects between the two. Hitless selection criteria can be derived from BER monitoring or signal integrity

monitoring. The selected signal is deserialized to a 4-bit 622MHz bus, a 16-bit 155MHz bus or quad STS-12s operat-

ing at 622Mb/s.

VSC9180 Functional Block Diagram

Dual

2.5GHz

CDR

(same )

DMX A1/A2

Align

Deinter-

leave

RXLOA

SEF[B:A]

RXDATA[15:0]+/-

CHSEL

2:1

LOL[B:A]

RXINB+/-

RXINA+/-

TXDATA[15:0]+/- STS-12/STM-4

Phase Alignment

STS-48/STM-16

Interleaver

CMU

TXOUTA+/-

TXOUTB+/-

FPOUT+/-

TXLOA

INTRLV

RESET_b

BUSMODE

[3:0]

2:1

[15:0]

TXCLK+/- 16 bit 155MHz

4 bit 622MHz

Retiming FIFO

[15:0]

DMX

MUX

RXCLK+/-

2:1

LINELOOP

EQUIPLOOP

REFCLK+/-

TXCLK_SRC+/-

CLK311MODE

FRALIGNRST

REFSEL

BER[B:A]

FEATURES

• 16-Bit 155MHz/4-Bit 622MHz 2.5Gb/s Serial

Backplane Transceiver with Integrated CMU/CRU

• Serial Quad STS-12/STM-4 to 2.5Gb/s Capability

with Integrated STS-12 Input Retiming and Deskew

• Operation at 155MHz, 622MHz, 2.488GHz, 2.65GHz

• Redundant 2.5Gb/s Serial Outputs and Dual 2.5Gb/s

Serial Inputs with Hardware Driven Hitless Selection

• 2.5Gb/s Backplane Loss of Signal, Frame and

Alignment Alarms

• Deskews Incoming 2.5Gb/s Signals by ±75ns

• 16-Bit/4-Bit LVDS Parallel Bus with Both

LVPECL and CML Compatibility

• Single 2.5V Power Supply

• 2.2 Watts Power Dissipation (max)

• Ideal for low cost 2.5Gb/s Backplane Interconnect in

SONET/SDH ADM, TSI or Wavelength

Cross Connect Applications

• 195 BGA Package

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

2 of 28

Draft 8/15/03

Features Summary

Parallel to Serial Transmit Features

• Receives 16- or 4-bit parallel LVDS inputs operating at 155MHz or 622MHz, respectively, into an internal

FIFO using source synchronous timing

• 16-bit 155MHz bus or 4-bit 622MHz bus is bit multiplexed to serial 2.5GHz output

• Retimes four serial STS-12/STM-4 inputs and deskews up to +/- 3 bytes of skew using the A1/A2 bound-

aries

• Byte interleaves four serial STS-12/STM-4 inputs to create an STS-48 like signal

• Supports bit multiplexing at 2.488GHz, and 2.65GHz

Serial to Parallel Receive Features

• Dual 2.5Gb/s frequency synchronous serial CML inputs with onboard clock and data recovery

• On-board frame alignment of received signals and large internal FIFO for tolerance of up to +/- 75ns of

serial backplane skew

• Realignment of incoming signals allows hitless selection of incoming channel for maintenance purposes,

and prevents downstream devices from having to reframe in a failure condition

• Supports bit de-multiplexing at 2.488GHz and 2.65GHz

• Hardware based switch over within receipt of two or four errored frame boundaries

• Loss of lock, loss of alignment, and loss of frame alarm indication

• Receive BER monitoring with selectable error thresholds

• Received frame pointer output for SYNC distribution

• Returns 16 or 4 bit parallel LVDS bit demultiplexed outputs operating at 155MHz or 622MHz with recov-

ered bus clock

• Returns four serial STS-12/STM-4 outputs to same signal pins as received by multiplexer for transparent

STS-12/STM-4 backplane transport

Other Features

• 4-bit or 16-bit parallel bus loopback with output bus clock

• Parallel loopback also allows quad STS-12/STM-4 retime, realign, and loopback output

• Serial loopback with hitless input selection and realignment

• Onboard discrete CMU and CRU to accommodate non-synchronous TX/RX applications

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

3 of 28

Draft 8/15/03

Functional Overview

The VSC9180 Hitless Transceiver receives parallel data on a 4-bit or 16-bit bus and serializes it to redundant 2.5Gb/s

STS-48/STM-16 ‘like’ signal. The parallel data can be in the form of a 4-bit or 16-bit byte interleaved STS-48/STM-

16 SONET/SDH signal with an accompanying word clock, much like a traditional SONET/SDH transceiver like the

VSC8141 16-bit transceiver or VSC8144 4-bit transceiver. This data can also be four, frequency and nearly frame

synchronous, serial STS-12/STM-4 signals with no accompanying clock. In the quad serial STS-12/STM-4 mode, the

VSC9180 retimes the incoming STS-12/STM-4 signals using a reference clock, and deskews them up to +/- 3 bytes.

The four STS-12/STM-4 signals are interleaved according to the SONET/SDH sequence and STS-48 ‘like’ signal is

created. The bytes are derived directly from the four received STS-12/STM-4 signals, in groups of four per signal

channel, and no overwriting is performed on the A1/A2 boundary, B2 bytes, and K1/K2 protection. This allows the

four received tributaries to be transported transparently across the backplane.

The receive circuitry interfaces to two frequency synchronous serial STS-48 ‘like’ signals using two redundant

CDRs. The CDRs lock to their respective channels, recover the clocks, and deserialize each signal internally. Both

signals are then framed and dual FIFOs are used to deskew both signals by up to +/-75ns. Once this deskew has been

performed, the CHSEL signal allows the user to choose which received input is then de-multiplexed to the parallel

output. Loss of Lock (LOL), Severely Errored Frame (SEF), and Bit Error Rate (BER) alarms are provided on a per

channel basis. SEF and BER can be used to drive the CHSEL signal so a 'hitless' transition will take place in hard-

ware if the selected input fails for external reasons. LOL is not recommended for this if there is a possibility of one of

the input channels becoming disconnected. Per channel bit error rate (BER) alarms provide additional information for

controlling CHSEL. A Loss of Alignment (LOA) alarm is provided to indicate that the received signals are either

non-synchronous or are skewed beyond the capability of the VSC9180 to hitlessly switch. The INTRLV and BUS-

MODE signals select the mode to recreate either the 4-bit or 16-bit byte interleaved STS-48/STM-16 output, or the

original received STS-12/STM-4 signals.

Figure 1: Hitless Backplane Sparing in Synchronous TSI/ADM Applications

The CDR circuitry recovers the incoming clock using the same reference provided to the CMU on the transmit side.

The received signal frequency does not need to exactly match the transmitted signal frequency allowing the device to

be used in wavelength cross connect applications where the bidirectional signals will be different frequencies. The

VSC9180 supports both line and equipment loopback, though not both simultaneously.

Pointer Processor

Performance Monitor

FEC CODEC

VSC8144

4-bit

SONET

Xceiver

VSC9180

'Hitless'

Xceiver

System Timing Domain

Working

Protection

Line Timing Domain

2.5G

Backplane

Interface

2.5G SDH

Interface

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

4 of 28

Draft 8/15/03

Figure 2: Hitless backplane sparing in asynchronous wavelength cross connects

Dual Clock and Data Recovery Circuit

The dual on-board CDRs use a single PLL oscillator to lock on to the incoming phase and frequency of RXIN[B:A].

The CDR is locked to the incoming serial signal chosen by CHSEL, uses its clock to provide a timing reference for

the remainder of the receive circuitry, demultiplexers, A1/A2 aligners, and provide the output bus clock RXCLK±.

When LCK2REF[B:A] is enabled the selected input channel CDR will lock to REFCLK and will no longer adjust its

phase in an attempt to capture incoming serial data.

The PLL lock reference is provided by REFCLK and must be within +/-40ppm of the incoming RXIN[B:A] for the

CDR units to achieve lock. Note that an adjusted clock reference will be required for G.709 frequencies.

Demultiplexers and Realignment Circuit

The VSC9180 demultiplexes RXINA and RXINB signals and frames each signal by aligning to a 24-bit A1/A2

boundary (F6F628’h). These byte-aligned signals are written to internal FIFOs, and the setting of CHSEL determines

which signal is read out of the FIFOs and provided to the RXDATA[15:0] outputs.

The positions of the frame boundaries of the signal stored in the FIFOs are used to compute an offset value. This off-

set value is used to control the read pointers in the realignment FIFOs, which provides realigned data to be selected

by CHSEL.

Whatever channel is not being selected by CHSEL is in a constant state of FIFO realignment. The unselected signal

(the Protection signal) can change phase relative to the selected one (the Working signal) and it’s FIFO will continue

to realign to the selected signal. Once CHSEL is toggled the Protection signal is now output from RXDATA[15:0] in

a hitless changeover, and what was previously the Working channel is now a Protection channel constantly realigned

to the Working channel. This allows a hitless changeover from RXINA to RXINB and then back to RXINA, where

the phase of the ‘new’ RXINA signal that returned after the failure was not identical to the one before the failure.

FRALIGNRST forces the in-frame signals received on the RXIN[B:A] inputs to be re-centered in the realignment

FIFOs such that the maximum +/-75ns deskew can be achieved.

When FRALIGNRSTSEL = 0, FRALIGNRST resets both selected and unselected channel alignment FIFOs. When

FRALIGNRSTSEL = 1, FRALIGNRST resets only the unselected channel alignment FIFO.

When a SEF condition is detected on an input it automatically forces the A1/A2 alignment circuitry into a reframe

mode. The inputs will consistently attempt to reach an in-frame state without user intervention, similar to other

Vitesse products that force reframe in the presence of SEF.

Multi-Rate Operation

Multi-rate operation is not supported at this time.

LOL, SEF, LOA, and FPOUT Behavior

Loss of lock (LOL) is declared after a lack of five observed positive or negative transitions for 102.88ns (256 bit

times). LOL is also declared if the CDRs are in the process of locking on to the incoming signals.

VSC8141/4

16/4-bit

SONET

Xceiver

VSC9180

'Hitless'

Xceiver

Working

Protection

Serial 2.5G

To O/E

Crossconnect

2.5G SDH

Interface

TX Timing

RX Timing

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

5 of 28

Draft 8/15/03

LOL may inadvertently be de-asserted on an inactive input when it is unterminated and large voltage swings occur on

the used input. This can be prevented by terminating the inactive input (RXIN+ = 1, RXIN- = 0), by reducing the

voltage swings on the active input, or by asserting LCK2REF on the inactive channel.

Severely errored frame (SEF) can be declared after receipt of two errored frame boundaries, unlike the SONET/SDH

standards which calls for four received errored frame boundaries. A SEF alarm is cancelled after two consecutive

unerrored frames are received, in accordance with SONET/SDH standards.

This non-standard SEF behavior provides indication of an ‘imminent failure’ and allows the CHSEL input to be tog-

gled before downstream devices connected to RXDATA[15:0] enter a SEF state and attempt to reframe. Ideally, the

SEFA output can be driven directly into the CHSEL input to provide hitless switch over from RXINA to RXINB and

prevent downstream devices from entering an alarm state. Switching in this manner will restore the A1/A2 boundary

to a downstream device after three errored frame boundaries. Users can bypass this behavior by delaying the assertion

of CHSEL relative to SEFA by additional frames externally. In addition the SEFCNTRL signal can be used to select

the normal four errored frame boundaries to assert SEF.

Loss of Alignment (LOA) is declared when the received frame boundaries of the two RXIN[B:A] signals are too dis-

tant for the internal FIFO realignment of +/-75ns. If a channel is in a SEF or LOL state, then no frame boundary is

present and alignment is impossible, hence LOA is always present if any channel is in a SEF or LOL state. A device

in a LOA state will not perform hitless switching, but will perform asychronous selection of two inputs.

Frame Pointer Output (FPOUT) indicates the start of frame of byte aligned data output from the RXDATA[15:0] bus.

If the device is in INTRLV=1 mode, the rising edge on FPOUT is aligned with the first bit of the first A1 (F6’h) out-

put from RXDATA[3:0]. If the device is in INTRLV=0 mode (bit-multiplexing), the rising edge on FPOUT is aligned

with the first frame-aligned A1A1 (F6F6’h) output from RXDATA[15:0] or first ‘A’ byte (F’h) output from

RXDATA[3:0].

The timing behavior of these signals is shown in Figure 10.

Quad STS-12/STM-4 Mode (INTRLV=1, BUSMODE=X)

The VSC9180 accepts four STS-12/STM-4 signals with +/- 3 bytes of skew on the TXDATA[3:0] inputs, retimes and

realigns them using the A1/A2 boundaries, then four-way byte interleaves them as shown in Figure 3 to form a signal

similar to an STS-48. The REFCLK input and all TXDATA[3:0] signals must be frequency locked, the REFCLK sig-

nal is multiplied and used for digital clock recovery purposes.

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

6 of 28

Draft 8/15/03

Figure 3: Quad STS-12/STM-4 Transmit Operation (INTRLV=1, BUSMODE=X)

The RXIN[B:A] signals are framed, realigned, four-way byte de-interleaved and output serially with recovered clock

RXCLK± as shown in Figure 4. The four-way byte de-interleaving does not require the serial RXIN[B:A] input to

originate in a VSC9180 device. In this manner, a VSC9180 can be used to extract four STS-12 streams from an STS-

48 in order to perform Time Slot Interchange functions.

Note that the CLEAR input must be set to logic 0 during quad STS-12/STM-4 mode for the VSC9180 to function

properly.

Figure 4: Quad STS-12/STM-4 Receive Operation (INTRLV=1, BUSMODE=X)

TXOUT[A:B]+

TXDATA3+

TXDATA2+

TXDATA1+

TXDATA0+

All symbols are single bit serialized data. Channel skew: 4 Byte skew illustrated. 6 Byte skew maximum.

A133 A132 A131 A130 A233 A232 A231 A230 A233 A232 A231 A230

A121 A120 A123 A122 A121 A120 A223 A222 A221 A220 A223 A222

A112 A111 A110 A113 A112 A111 A110 A213 A212 A211 A210 A213

A103 A102 A101 A100 A103 A102 A101 A100 A203 A202 A201 A200

Channel

Skew

A111 A110 A233

A100

A101

A102 A232 A231 A230 A223

A113

A121 A120

A122

A123 A103

A112

A132

A133 A131 A130

RXIN[A:B]

All symbols are single bit serialized data

A122

A123

A132

A133 A131 A130 A111 A110 A233

A100

A101

A102 A232 A231 A230

A113

A121 A120 A103

A112

RXDATA 3+

RXDATA 2+

RXDATA 1+

RXDATA 0+

A133 A132 A131 A130 A233 A232

A123 A122 A121 A120 A223 A222

A113 A112 A111 A110 A213 A212

A103 A102 A101 A100 A203 A202

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

7 of 28

Draft 8/15/03

Timing of the INTRLV=1 modes is shown in Figure 8 and Figure 9.

Scramble and B1

The VSC9180 accepts four, STS-12/STM-4 serial channels on the TXDATA[3:0]signals when INTRLV=1. In this

mode, these four independent channels are four-way byte interleaved into a single STS-48/STM-16 channel. Setting

B1CALCEN=1 enables B1 calculation, checking and scrambling/descrambling to be performed. The four STS-12/

STM-4 channels are individually framed, descrambled and the B1 values checked (XORed) against values calculated

on the previous frame. The resulting error masks are saved for use in the interleaved STS-48/STM-16 frame.

The STS-48/STM-16 frame resulting from the interleaving process has a B1 value inserted into the unscrambled

frame, and the frame is then scrambled. After scrambling, a B1 value is calculated for use by the insertion process in

the following frame. Any errors detected in the four STS-12/STM-4 B1 comparisons are combined with the calcu-

lated STS-48/STM-16 B1 by a simply XORing the five values (4, STS-12/STM-4 error masks with 1, STS-48/STM-

16 B1 value). The scrambled STS-48/STM-16 frame, with the combined B1 value, is serialized and transmitted out

the TXOUT[A:B] signals.

When B1CALCEN=0, the four STS-12/STM-4 channels are still interleaved into an STS-48/STM-16 frame, but de-

scrambling/scrambling and B1 calculation/insertion are not performed.

Serial STS-48/STM-16 signals received on RXINA and RXINB can be four-way byte de-interleaved into four inde-

pendent STS-12/STM-4 channels when INTRLV=1. In all modes, a B1 value is calculated on an incoming STS-48/

STM-16 frame before it is descrambled. This value is stored for use in checking errors on the following frame. After

de-scrambling the B1 value of the current frame is checked against the previously stored value B1 value. The result-

ing error mask is saved for use in the de-interleaved STS-12/STM-4 frames when that mode is active. This error mask

is also used by the bit error rate monitoring logic.

When B1CALCEN=1, the descrambled STS-48/STM-16 frame is de-interleaved to create four independent STS-12/

STM-4 serial channels. Each of the four channels has a B1 value inserted into the unscrambled frames, and the frames

are then scrambled. After scrambling, a B1 value is calculated for use by the insertion process in the following frame.

If an error was detected in the STS-48/STM-16 B1 comparison, the saved error mask is combined with the calculated

B1 value of one of the four STS-12/STM-4 channels. The channel chosen to receive the STS-48/STM-16 frame error

mask is performed in a sequentially rotating fashion (round-robin) in which the next channel is chosen only if a non-

zero error mask was used. When B1CALCEN=0, the STS-48/STM-16 signal is still de-interleaved into four STS-12/

STM-4 channels but no de-scrambling/scrambling or B1 calculation/insertion is performed.

16-Bit and 4-Bit Multiplexing/Demultiplexing Modes

The VSC9180 functions as a typical STS-48/STM-16 transceiver, bit-serializing a 16-bit or 4-bit bus to a 2.488Gb/s

signal, and bit deserializing the same signal type to a parallel output bus. The BUSMODE pin indicates the width of

the data bus and whether the clocking interfaces are 622MHz or 155MHz. Operation and timing parameters for this

mode are shown in Figure 7 and Figure 9.

The transmit section of the VSC9180 uses source synchronous timing and provides an output clock TXCLK_SRC±

to an upstream device. The upstream device should use the TXCLK_SRC± output as the timing source for its final

output latch. The upstream device should then generate a TXCLK phase-aligned with the output data and provide

both to the VSC9180 input bus. TXDATA[15:0] must meet setup and hold times with respect to TXCLK±. An archi-

tectural representation of the parallel transmit interface is shown in Figure 5.

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

8 of 28

Draft 8/15/03

Figure 5: Parallel Bus Timing Architecture (Bit Interleaved)

The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between TXCLK_SRC and

TXCLK. Once RESET is asserted and the FIFO initialized, the delay between TXCLK_SRC and TXCLK can

decrease or increase up to one period of the low speed clock (1.6ns or 6.4ns depending on BUSMODE). Should this

delay drift exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, result-

ing in a loss of transmitted data (a FIFO overflow).

The receive section of the VSC9180 (see Demultiplexers and Realignment Circuit section) allows hitless selection of

which 2.488Gb/s signal is output to the RXDATA[15:0] bus. The data is bit-demultiplexed to either a 4-bit or 16-bit

wide RXDATA bus depending on BUSMODE, and has accompanying bus clock RXCLK. The output bus is byte

aligned to the A1/A2 frame, with FPOUT providing indication of the start of frame.

Table 1: Overview of Bus Width and Interleaving Operation

NOTES: (1) Unused I/Os may be left unconnected.

(2) Demultiplexing operation and sequencing are inverse of multiplexing operation.

(3) k+n indicates the nth received STS-12 bit following the first STS-12 bit. Assumes successful quad STS-12/STM-4 realignment.

G.709 Operation

The VSC9180 supports hitless switching of G.709 ‘Digital Wrapper’ OTN frames (see Figure 6) in addition to the tra-

ditional SONET/SDH operation. Setting this mode (WRAP = 1) changes the expected frame length from 38880 bytes

(STS-48/STM-16) to 16320 bytes. A 24-bit A1/A2 boundary is expected in this mode as well as SONET/SDH mode

(WRAP=0). This mode is available only when STS-48/STM-16 bit interleaved mode is selected (CLEAR = 0,

Clear INTRLV BUSMODE Functional

Parallel I/O(1)

TXCLK+/-

Required?

Multiplexing Sequence(2)

(in order of serial transmission)

0 0 0 T/RXDATA[3:0] Yes TXDATA3, TXDATA2,

TXDATA1, TXDATA0

0 0 1 T/RXDATA[15:0] Yes TXDATA15, TXDATA14. . .TXDATA0

0 1 X T/RXDATA[3:0] No

TXDATA3[k], TXDATA3[k+1]. . .

TXDATA3[k+7] TXDATA2[k]. . .

TXDATA2[k+7], TXDATA1[k]. . .

TXDATA1[k+7], TXDATA0[k],

TXDATA0[k+1]. . . TXDATA0[k+7](3)

write

read

4 x 16b FIFO

VSC9180

2.488 GHz

PLL

REFCLK+/- Div 4/16

TXCLK+/-

TXCLK_SRC+/-

TXDATA[15|3:0]+/-

BUSMODE

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

9 of 28

Draft 8/15/03

INTRLV = 0). The REFCLK+/- frequency must be increased such that 16 or 32 times REFCLK+/- is equal to the new

signal frequency being serialized.

Figure 6: G.709 OTUk Frame Format with FAS location

Bit Error Rate Monitor

The VSC9180 provides bit error rate monitoring (BER) for each of the STS-48/STM-16 signal channels received on

RXINA and RXINB. This is accomplished by calculating a B1 value on the incoming frame before it is descrambled.

This value is stored for use in checking errors on the following frame. After de-scrambling the B1 value of the current

frame is checked against the previously stored value B1 value. The resulting error mask is used for BER calculation.

The BER calculation is performed by counting the number of error bits of the error masks of each frame that is

received over a certain interval of frames. The number of frames in the sample interval is selectable by the BER-

SEL[2:0] signals as shown in Table 2. If the error count within a sample interval reaches the Assert Alarm level, the

BER signal is then asserted for that channel (BERA or BERB) immediately. The alarm will remain asserted until the

error count for a sample interval falls below the Cancel Alarm level. The BER alarm for a given channel will also be

immediately asserted if SEF for that channel is asserted.

Table 2: Bit Error Rate Selection

NOTES:

The BER alarm signals can be used in determining which incoming channel should be selected (CHSEL) for output.

Lower BER values from 1.0E-06 to 1.0E-10 are recommended due to their increased level of accuracy

BERSEL [2:0] Sample Period

Frames

Cancel Alarm

Error Count

Assert Alarm

Error Count BER

000 256 971 1077 1.0E-03

001 256 971 1076 1.0E-04

010 256 507 600 1.0E-05

011 65536 19292 19932 1.0E-06

100 65536 1926 2135 1.0E-07

101 65536 171 237 1.0E-08

110 16777216 5050 5386 1.0E-09

111 16777216 469 575 1.0E-10

OTUk FEC

4 x 256

Bytes

OTUk OH

1 16 17 3824 3825 4080

FAS1 FAS4FAS3FAS2 FAS6FAS5

F6'H 28'HF6'H 28'HF6'H 28'H

OTUk Payload

4 x 3808 Bytes

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

10 of 28

Draft 8/15/03

AC Characteristics

Figure 7: Bit Interleaved Transmitter Timing Waveforms (INTRLV=0)

Table 3: Multiplexer Input (TX) - Parallel Modes

Parameters Description Min Typ Max Units Conditions

tDTXCLK and TXCLK_SRC period 1.6/6.4 ns FEC rate is 15/14 of this value

tTXDSU

Data Setup time to the rising edge

of TXCLK+ 350 ps INTRLV=0, BUSMODE=0

tTXDSU

Data Setup time to the rising edge

of TXCLK+ 600 ps INTRLV=0, BUSMODE=1

tTXDH

Data hold time after the rising

edge of TXCLK+ 350 ps INTRLV=0, BUSMODE=0

tTXDH

Data hold time after the rising

edge of TXCLK+ 600 ps INTRLV=0, BUSMODE=1

tRFTXCLKSRC TXCLK_SRC rise and fall times 500 ps

tDCTXCLKSRC TXCLK_SRC duty cycle 45 55 %

tDCTXCLK TXCLK duty cycle 35 65 %

Valid Data (1) Valid Data (2)

D15

Parallel Data Clock Input

Parallel Data Inputs

Source Synchronous Clock Output

High-Speed Differential Serial Data Outputs

TXCLK+

TXDATA[15|3:0]±

TXCLK_SRC

TXOUT[B:A]+

tTXDH

tTXDSU

=Don’t care

NOTE: Bit 15/3 is MSB and is transmitted FIRST, Bit 0 is LSB and is transmitted LAST

D14 D13 .......... D2 D1 D0

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

11 of 28

Draft 8/15/03

Figure 8: Byte Interleaved Transmitter Timing Waveforms (INTRLV=1)

Table 4: Multiplexer Input (TX) - Serial Mode

Table 5: Multiplexer Output (TX)

Parameters Description Min Typ Max Units Conditions

tFRMSKEW

Skew tolerance of incoming serial

STS-12/STM-4 channels +/-24 Bit

Times

Channels must be frequency

locked to REFCLK

tTXDATA

Period of incoming STS-12/STM-4

bits 1.6 ns Channels must be frequency

locked to REFCLK

tREFCLK Period of REFCLK clock input 6.43/

12.86 ns Selected by REFSEL

Parameters Description Min Typ Max Units Conditions

tRFTXOUT TXOUT rise and fall times 150 ps 20% to 80% into 100Ω load

tJTXOUT Output data jitter 15 ps

rms, wideband with 2ps rms

jitter on REFCLK,

REFCLK=155MHz.

PREEMPEN=0

NOTE: Setting Preempen=1 will improve output data jitter performance over long cables or backplane traces.

TXDATA0 F6'h F6'h F6'h

tFRMSKEW

28'h 28'h

TXDATA1 F6'hF6'h 28'h 28'h 28'h 28'h

TXDATA2 28'h 28h 28'h 28'h

TXDATA3

TXOUT[B:A]±

All symbols are single-bit serialized data. Channel skew: 4 byte skew shown, 6 byte skew maximimum.

NOTE: A phase relationship between REFCLK± and TXDATA[3:0] is not required.

A133 A132 A131 A130 A123 A122 A121 A120 A113 A112 A111 A110 A103 A102 A101 A100 A233 A232 A231 A130 A123

F6'h F6'h F6'h F6'h 28'h 28'h

F6'h

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

12 of 28

Draft 8/15/03

Figure 9: Bit and Byte Interleaved Receiver AC Timing Waveforms

Table 6: Bit and Byte Interleaved Receiver AC Characteristics

Figure 10: Receiver Alarm and Frame Pointer AC Timing Waveforms

Parameters Description Min Typ Max Units Conditions

tRXPD Data invalid from rising edge of RXCLK+ -150 150 ps INTRLV=1, BUSMODE=X

tRXPD Data invalid from rising edge of RXCLK+ -150 150 ps INTRLV=0, BUSMODE=0

tRXPD Data invalid from rising edge of RXCLK+ -600 600 ps INTRLV=0, BUSMODE=1

tRXDR, tRXDF RXDATA[15|3:0]± rise and fall times 550 ps INTRLV=1, BUSMODE=X

tRXDR, tRXDF RXDATA[15|3:0]± rise and fall times 550 ps INTRLV=0, BUSMODE=0

tRXDR, tRXDF RXDATA[15|3:0]± rise and fall times 700 ps INTRLV=0, BUSMODE=1

tRXCLKR,

tRXCLKF

RXCLK± rise and fall times 500 ps 20% to 80% into 100Ω load

RXCLKDRXCLK± duty cycle distortion 45 55

% of

clock

cycle

NOTES: Bit 15/3 is MSB and is serially received FIRST, Bit 0 is LSB and is serially received LAST.

See Figure 4 for logical operation of receive output behavior when INTRLV=1.

RXCLK+/- Duty

Cycle Distortion

Valid Data

45% 55%

tRXPD

RXCLK+

Parallel Data Clock Output

RXDATA[15|3:0]+

Parallel Data Outputs

tRXPD

FPOUT

FRAME FRAME FRAME

SPE

SPERXDATA[15|3:0]

RXCLK+

tRXFP

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

13 of 28

Draft 8/15/03

Table 7: Receiver Frame Pointer AC Characteristics

Table 8: Input to Output Delay

NOTE: All values are only valid when FIFOSEL=0. Receive mode values are only valid for the selected channel after reset (or FRALIGNRST

when the selected channel is affected by FRALIGNRST). Transmit mode values are only valid after reset and assuming that TXCLK is

frequency locked to REFCLK. If TXCLK has any wander with respect to REFCLK, then the delay will be affected accordingly. For

INTRLV=1, the delay values apply to the earliest of the incoming TXDATA[3:0] signals

Table 9: Input to Output Delay Ambiguity

Parameters Description Min Typ Max Units Conditions

tRXFP

Delay of FPOUT+ rising edge with respect

to RXCLK+ -500 500 ps INTRLV=1, BUSMODE=X

tRXFP

Delay of FPOUT+ rising edge with respect

to RXCLK+ -500 500 ps INTRLV=0, BUSMODE=0

tRXFP

Delay of FPOUT+ rising edge with respect

to RXCLK+ -600 600 ps INTRLV=0, BUSMODE=1

tFPR, tFPF FPOUT± rise and fall times 500 ps 20% to 80% into 100Ω load

Parameters Description Min Typ Max Units Conditions

tRXDLY

Pipeline delay through the VSC9180 in

Receive mode 174 194 ns INTRLV=0, BUSMODE=0

tRXDLY

Pipeline delay through the VSC9180 in

Receive mode 177 197 ns INTRLV=0, BUSMODE=1

tRXDLY

Pipeline delay through the VSC9180 in

Receive mode 244 264 ns INTRLV=1, BUSMODE=X,

B1CALCEN=0

tRXDLY

Pipeline delay through the VSC9180 in

Receive mode 251 271 ns INTRLV=1, BUSMODE=X,

B1CALCEN=1

tTXDLY

Pipeline delay through the VSC9180 in

Transmit mode 85 105 ns INTRLV=0, BUSMODE=0

tTXDLY

Pipeline delay through the VSC9180 in

Transmit mode 70 90 ps INTRLV=0, BUSMODE=1

tTXDLY

Pipeline delay through the VSC9180 in

Transmit mode 381 401 ns INTRLV=1, BUSMODE=X,

BlCALCEN=0

tTXDLY

Pipeline delay through the VSC9180 in

Transmit mode 381 401 ns INTRLV=1, BUSMODE=X,

B1CALCEN=1

Parameters Description Min Typ Max Units Conditions

tRXDLYD

Delay ambiguity from input to output in

Receive mode -5.2 5.2 ns INTRLV=1, BUSMODE=X

tTXDLYD

Delay ambiguity from input to output in

Transmit mode -6 6 ns INTRLV=1, BUSMODE=X

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

14 of 28

Draft 8/15/03

DC Characteristics

Table 10: TTL, LVDS and CML Inputs and Outputs

NOTE: (1) The 155/622MHz LVDS input receivers can handle most LVPECL signals.

Parameters Description Min Typ Max Units Conditions

TTL Inputs and Outputs

VOH Output HIGH Voltage VDD - 0.3 VDD VI

OH = -1mA

VOL Output LOW Voltage VSS 0.4 V IOL = 2mA

VIH Input HIGH Voltage VDD - 0.5 5.0 V

VIL Input LOW Voltage 0 0.8 V

IIInput Leakage Current 100 µA0V< V

IN < 5V

LVDS Inputs and Outputs(1)

VOCMLVDS Output Common-Mode Range 1.13 1.27 V Terminated 100Ω

differential

∆VODLVDS Output Swing 150 400 mV Single-ended, p-p

Figure 11

∆VODLVDS Output Swing 125 400 mV

Single-ended, p-p

Figure 11. for RXCLK±

and TXCLK_SRC±

only when INTRLV=0,

BUSMODE=0.

ROLVDS Output Driver Impedance 80 ΩGuaranteed, but not

tested

VICMLVDS Input Common-Mode Range 0.2 2.2 V

∆VIDLVDS Input Sensitivity 100 1200 mV Single-ended, p-p

Figure 11

RILVDS Input Termination Resistance 80 120 Ω

With 910Ω, 5% resistor

connected between

IRSEL and VSS.

CML Inputs and Outputs

VOCMCML Output Common-Mode Range 1.9 2.45 V VDD-1/2 ∆V

∆VODCML Output Swing 400 650 mV Single-ended, p-p

Figure 11

ROCML Output Driver Impedance 100 ΩGuaranteed, but not

tested

VICMCML Input Common-Mode Range 1.59 1.94 V

∆VIDCML Input Sensitivity 70 900 mV Single-ended, p-p

Figure 11

RICML Input Termination Resistance 80 120 Ω

With 910Ω, 5% resistor

connect between IRSEL

and VSS.

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

15 of 28

Draft 8/15/03

Figure 11: Single-Ended Peak-to-Peak Specifications

Table 11: Internal Regulator (VDDN Supply)

Table 12: Power Dissipation

Parameters Description Min Typ Max Units Conditions

CFVDDN External filter capacitor 4.7 10 µF Tantalum - VDDN to VSS

5Ω > CSR > 0.5Ω

Parameters Description Min Typ Max Units Conditions

IDD Power Supply Current from VDD 0.83 A

PDPower Supply Dissipation (VDD = 2.65V) 2.2 W

∆

V=V

-V

NOTE: Diagram applies to all I/O swing specifications.

One side of differential signal

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

16 of 28

Draft 8/15/03

Absolute Maximum Ratings(1)

Power Supply Voltage (VDD, VDDIO, VDDA) Potential to GND.........................................................-0.5V to +3.0V

DC Input Voltage (LVDS/CML inputs)................................................................................. -0.5V to VDD + 0.5V

DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.0V

DC Output Voltage (LVDS/CML outputs) ............................................................................ -0.5V to VDD + 0.5V

DC Output Voltage (TTL outputs) ........................................................................................ -0.5V to VDD + 0.5V

Output Current (TTL outputs).................................................................................................................... ±50mA

Output Current (LVDS/CML outputs) ........................................................................................................ ±50mA

Case Temperature Under Bias ...................................................................................................... -55oC to +125oC

Storage Temperature..................................................................................................................... -65oC to +150oC

Electrostatic Discharge (Human Body Model) .............................................................................................. 500V

NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent

damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect

device reliability.

Recommended Operating Conditions

Core Power Supply Voltage (VDD,VDDIO,VDDA) .....................................................................................+2.5V±5%

Operating Temperature Range(1) (T)................................................................................................. 0oC to 105oC

NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature.

ELECTROSTATIC DISCHARGE

This device can be damaged by ESD. Vitesse recommends that all integrated circuits be

handled with appropriate precautions. Failure to observe proper handling and installation

procedures may adversely affect reliability of the device.

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

17 of 28

Draft 8/15/03

I/O Equivalent Circuits

High-Speed CML Input Equivalent Circuit

Output Equivalent Circuit

100

Ohms

PAD

VDDVDD

VSS

VDD

VSS VSS

VSS

VDD

PAD

PAD PAD

VDD

VSS

Ω

18mA

VSS

VDD

VSS

VDD

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

18 of 28

Draft 8/15/03

Parallel Input/Output Termination Schemes

Standard (LVDS)

Note: LVDS inputs are internally biased.

-Core +

Ω

250

Ω

250

Ω

100

Ω

VSC9180

LVDS Driver LVDS Receiver

100

Ω

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

19 of 28

Draft 8/15/03

Package Descriptions

Figure 12: 195 BGA Diagram—Bottom View

TXOUTA-

VSSIO

RXINB+

RXINB-

VSSIO

RXINA+

RXINA-

VDD

LCK2REFA

LCK2REFB

RATE[0]

PREEMPEN

FRALIGNRSTSEL

SCRAMOUT_EN

USEDATA

TXSTSTA

CHSEL

TXOUTA+

VDDIO

VSS

BUSMODE

IRSEL

VDDNEXT

REFSEL

LFSELAB[0]

PASSTOH

ENCODER_EN

FIFOSEL

RESET_b

RXDATA[0]-

RXDATA[1]+

VDDIO

PLLSLW

VDD

TSTINTCS

TSTINTA

WRAP

VSS

LFSELAB[1]

VSS

USEECDATA

SEFCNTRL

VSSIO

RXDATA[0]+

RXDATA[2]+

TXOUTB-

VDDIO

TSTINTB

LOLPHCHGEN

VDD

RXSTSTA

SCRAMIN_EN

TXSTSTB

VDD

VDDIO

RXDATA[2]-

VSSIO

TXOUTB+

VSSIO

NOT POPULATED

(Bottom View)

RXDATA[1]-

VSSIO

RXDATA[3]-

RXDATA[4]-

VSSIO

VDDIO

RXDATA[3]+

RXDATA[5]-

VSSIO

REFCLK+

VSSIO

TXCLK_SRC+

TXCLK_SRC-

RXDATA[4]+

VDDIO

RXDATA[5]+

RXDATA[7]-

REFCLK-

VDDIO

TXCLK-

TXCLK+

RXDATA[6]-

RXDATA[6]+

VDDIO

RXDATA[7]+

VSS

VDD

PLLFST

RXDATA[8]-

RXDATA[8]+

VSSIO

VDDIO

VSSA

VDDA

VSSIO

RXCLK-

RXDATA[10]-

VSSIO

RXDATA[9]+

RXDATA[9]-

VDDN

VDDIO

FPOUT+

VSSIO

RXDATA[11]+

RXDATA[11]-

RXDATA[10]+

RXCLK+

FPOUT-

TSTCNTRL[1]

VSS

RADATA[13]+

RXDATA[13]-

RXDATA[12]+

VDDIO

VDD

TSTCNTRL[0]

FRALIGNRST

BERSEL[0]

RXDATA[15]-

RXDATA[14]+

VDDIO

RXDATA[12]-

TSTCNTRL[2]

EQUALEN

BERSEL[1]

VSS

VDD

TXDATA[13]-

TXDATA[11]-

TXDATA[9]+

TXDATA[7]+

TXDATA[4]+

TXDATA[2]+

VSSIO

TXLOA

PROTECTERR

MULTBITERR

VDDIO

VSSIO

BIAS

BERSEL[2]

VDD

LINELOOP

TXDATA[15]+

TXDDATA[13]+

TXDATA[11]+

TXDATA[8]-

TXDATA[7]-

TXDATA[4]-

TXDATA[2]-

TXDATA[0]-

LOLA

RXLOA

VSS

WORKERR

RXDATA[14]-

B1CALCEN

CLK311MODE

CLEAR

TXDATA[15]-

TXDATA[12]-

TXDATA[12]+

TXDATA[10]-

TXDATA[8]+

TXDATA[6]-

TXDATA[5]+

TXDATA[3]-

TXDATA[3]+

TXDATA[0]+

BERB

SEFB

SEFA

RXDATA[15]+

EQUIPLOOP

INTRLV

TXDATA[14]-

TXDATA[14]+

VSS

TXDATA[10]+

TXDATA[9]-

VSSIO

VDDIO

TXDATA[6]+

TXDATA[5]-

VSS

TXDATA[1]-

TXDATA[1]+

BERA

LOLB

VSSIO

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

20 of 28

Draft 8/15/03

Table 13: Package Ball Identification

Signal BGA

Ball Name I/O Freq

Level Description

RESET_b C16 System Reset I TTL Low active asynchronous system reset.

BUSMODE L16 4-Bit/16-Bit

Parallel Bus Mode ITTL

When INTRLV = 0, BUSMODE = 0, TXDATA[3:0]

and RXDATA[3:0] contain valid 4-bit parallel

622Mb/s data.

When INTRLV = 0, BUSMODE = 1,

TXDATA[15:0] and RXDATA[15:0] contain valid

16-bit parallel 155Mb/s data.

INTRLV T1

Interleave

Serial/Parallel

Bus Mode

ITTL

When INTRLV = 0, TXDATA and RXDATA

contain parallel bit-multiplexed SONET/SDH data.

When INTRLV = 1, TXDATA[3:0] and

RXDATA[3:0] contain 4 serial STS-12/STM-4

signals of byte-interleaved data.

CLK311MODE T2 311MHz

Clock Mode ITTL

When CLK311MODE = 1, RXCLK and

TXCLK_SRC are set to 311MHz instead of

622MHz when INTRL = 1. TXDATA[3:0] is still

622Mb/s with a valid bit on both rising and falling

edges of TXCLK.

PREEMPEN F17 Pre-Emphasis

Enable ITTL

When Preempen=0, pre-emphasis on TXOUTA/B is

disabled.

When Preempen=1, pre-emphasis is enabled.

RATE[0] G17 Multi-Rate

Selection I TTL NOT SUPPORTED. Tie to logic 0.

WRAP J15 G.709 Frame Mode I TTL When WRAP = 1, framing for G.709 signals is

performed instead of SONET/SDH framing.

CLEAR R2 Non-SONET/SDH

Mode ITTL

CLEAR = 1 is no longer supported.

Set CLEAR=0.

SEFCNTRL D15 Severely Errored

Frame Control ITTL

Determines the number of consecutive errored frame

boundaries that must occur for SEFA/B to be

asserted when “in frame.”

When SEFCNTRL = 0, the number of frame

boundaries is 2. When SEFCNTRL = 1, the number

of frame boundaries is 4.

B1CALCEN U2 B1 Calculation/

Insertion Enable ITTL

A logic 1 enables calculation and insertion of the B1

byte for STS-48/STM-16 to STS-12/STM-4 and

STS12/STM-4 to STS-48/STM-16 conversions

(INTRLV = 1, EQUIPLOOP = 0, LINELOOP = 0).

BERSEL[2] T3 Bit Error Rate

Selection ITTL

These inputs determine the characteristics of the bit

error rate calculation logic. The settings are

described in Table 2.

BERSEL[1] R4

BERSEL[0] P5

EQUIPLOOP U1 Parallel Loopback

Control ITTL

When EQUIPLOOP = 1, data from TXDATA is

taken after deskew and phase alignment have been

accomplished and looped back out on RXDATA

with accompanying clock on RXCLK (B1CALCEN

= X). RXIN must be frequency locked to REFCLK

or LCK2REF must be used.

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

21 of 28

Draft 8/15/03

LINELOOP P3 Serial Loopback

Control ITTL

When LINELOOP = 1, data from the selected

channel of RXINA/B is taken after frame alignment

has been accomplished and looped back out

TXOUTA/B (B1CALCEN = X).

FRALIGNRST R5 Frame Alignment

Centering Reset ITTL

A logic 1 causes frame alignment FIFO's to be

centered allowing alignment

of maximum channel skew (+/- 75ns). When

FRALIGNRSTSEL = 01, FRALIGNRST resets both

selected and unselected channel alignment FIFOs

(normal operation). When FRALIGNRSTSEL = 1,

FRALIGNRST resets only the unselected channel

alignment FIFO.

CHSEL A17 Input A/B Channel

Select ITTL

Selects which input channel, RXINA or RXINB, is

used to provide output data on RXDATA. CHSEL =

0 selects channel A, CHSEL = 1 selects channel B.

Internally, channel switching may occur up to 18,

155MHz clock periods later, as this signal is

synchronized to the channel alignment process.

Transparent, error-free switching occurs only when

RXLOA = 0.

LCK2REFA J17 Lock To Reference

Channel A ITTL

When LCK2REFA = 1, the channel A CDR will

lock to the reference clock and no longer adjust its

phase in an attempt to capture channel A data. This

should be used when channel A is non-operational.

LCK2REFB H17 Lock To Reference

Channel B ITTL

When LCK2REFB = 1, the channel B CDR will

lock to the reference clock and no longer adjust its

phase in an attempt to capture channel B data. This

should be used when channel B is non-operational.

LFSELAB[1] G15

Loop Filter Select

Channels A/B ITTL

Adjusts the digital loop filters of the CDRs for input

channels A and B together.

00 - slightly underdamped

01 - critically damped

10(1) - slightly overdamped (recommended default)

11 - undefined

Note: Higher frequency jitter on RXIN may be

handled better by lower settings.

LFSELAB[0] G16

LOLPHCHGEN J14 Loss of Lock Phase

Change Enable ITTL

A logic 1 allows the use of phase change

information to be used to determine loss of lock.

Recommended default = 1.(1)

LOLA E3 Loss Of Lock

Channel A OTTL

A logic 1 indicates an inability of the channel A

CDR to reach lock, for channel A, generally due to

out of spec input data signals.

LOLB B1 Loss Of Lock

Channel B OTTL

A logic 1 indicates an inability of the CDR to reach

lock for channel B, generally due to out of spec

input data signals.

Signal BGA

Ball Name I/O Freq

Level Description

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

22 of 28

Draft 8/15/03

SEFA B2 Severely Errored

Frame Channel A OTTL

A logic 1 indicates a failure to reach or maintain “in

frame” status on input data for channel A. “In

frame” status is achieved, and SEFA de-asserted,

after 2 consecutive valid frame boundaries have

been observed. SEFA is asserted after 2 or 4 (see

SEFCNTRL) consecutive errored frame boundaries

have occurred.

SEFB C2 Severely Errored

Frame Channel B OTTL

A logic 1 indicates a failure to reach or maintain “in

frame” status on input data for channel B. “In

frame” status is achieved, and SEFB de-asserted,

after 2 consecutive valid frame boundaries have

been observed. SEFB is asserted after 2 or 4

consecutive (see SEFCNTRL) errored frame

boundaries have occurred.

BERA C1 Bit Error Rate

Channel A OTTL

A logic 1 indicates that the bit error rate of channel

A has reached the trigger level as determined by the

setting of the BERSEL inputs. Once asserted, the

bit error rate must fall below the cancel level as

determined by the setting of the BERSEL inputs

before this signal is deasserted.

BERB D2 Bit Error Rate

Alarm Channel B OTTL

A logic 1 indicates that the bit error rate of channel

B has reached the trigger level as determined by the

setting of the BERSEL inputs. Once asserted, the

bit error rate must fall below the cancel level as

determined by the setting of the BERSEL inputs

before this signal is deasserted.

RXLOA D3

Loss Of A/B

Channel

Alignment

OTTL

A logic 1 indicates that alignment between the frame

boundaries on channels A and B cannot be achieved.

This may be due to asynchronous A/B channels or

channel skew larger than +/-75ns. RXLOA is

automatically asserted when either LOL or SEF

conditions exist on either channel.

PASSTOH F16 I TTL Vitesse test mode - Tie to logic 0.

ENCODER_EN E16 I TTL Vitesse test mode - Tie to logic 0.

SCRAMIN_EN F14 I TTL Vitesse test mode - Tie to logic 0.

SCRAMOUT_EN D17 I TTL Vitesse test mode - Tie to logic 0.

USEDATA C17 I TTL Vitesse test mode - Tie to logic 1.

USEECDATA E15 I TTL Vitesse test mode - Tie to logic 0.

WORKERR B3 O TTL Vitesse test mode. Leave unconnected.

PROTECTERR D4 O TTL Vitesse test mode. Leave unconnected.

MULTBITERR C4 O TTL Vitesse test mode. Leave unconnected.

EQUALEN T4 Cable Equalization

Enable ITTL

A logic 1 enables cable equalization for RXINA and

RXINB. Cable equalization increases the

amplification for single bit data to improve signal

detection for long cables.

EQUALEN should be set to 1 when driving serial

signals over long cables (1-2 meters) or over

backplane traces.

Signal BGA

Ball Name I/O Freq

Level Description

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

23 of 28

Draft 8/15/03

BIAS U3 CML Input BIAS I Analog

When BIAS is connected to VSS the input

differential threshold of RXINA and RXINB is set to

the 100-200mV range. Increasing the voltage level

on this input from VSS to VDD will cause the

threshold to first decrease to a minimum and then

increase to a maximum. The relationship between

the voltage on this input and the differential

threshold is not available. Recommended default =

VSS.(1)

RXINA+/- M17,L17(2) Serial 2.5Gb/s Data

Inputs Channel A I2.5Gb/s

CML

Serial 2.5 Gb/s data input for channel A. Signals

must be frequency synchronous to within +/-40ppm

of REFCLK. When used with channel B as a

protection or working channel for hitless switching,

frames must be aligned to channel B to within +/-

75ns.

RXINB+/- R17, P17(2) Serial 2.5Gb/s Data

Inputs Channel B I2.5Gb/s

CML

Serial 2.5 Gb/s data input for channel B. Signals

must be frequency synchronous to within +/-40ppm

of REFCLK. When used with channel A as a

protection or working channel for hitless switching,

frames must be aligned to channel A to within +/-

75ns.

FPOUT+/- R7, T6(2) Frame Pointer

Output O

155/

622Mb/s

LVDS

The rising edge of FPOUT+ is coincident with the

first data word/bits of frames output on RXDATA.

Once asserted (high), it remains high for 4, 155MHz

clock periods.

RXDATA[15]+/- A2, D5(2)

Parallel/Serial

Output Bus

155Mb/s

LVDS

When INTRLV = 0, BUSMODE = 1, incoming

serial data from the selected A/B channel is bit de-

multiplexed directly to form a 16-bit parallel word

on this bus.

When INTRLV = 0, BUSMODE = 0, incoming

serial data from the selected A/B channel is bit de-

multiplexed directly to form a 4-bit parallel word on

bits [3:0] of this bus.

When INTRLV = 1, incoming serial data from the

selected A/B channel is byte de-multiplexed to

create 4, STS-12/STM-4 serial output channels on

bits [3:0].

RXDATA[14]+/- C5, A3(2)

RXDATA[13]+/- D6, C6(2)

RXDATA[12]+/- B6, A5(2)

RXDATA[11]+/- C7, B7(2)

RXDATA[10]+/- A7, D8(2)

RXDATA[9]+/- B8, A8(2)

RXDATA[8]+/- C9, D9(2)

RXDATA[7]+/- A10,

A11(2)

RXDATA[6]+/- C10,

D10(2)

RXDATA[5]+/- B11, B12(2)

RXDATA[4]+/- D11,

A13(2)

RXDATA[3]+/- C12, B13(2)

155/

622Mb/s

LVDS

RXDATA[2]+/- A15,

B14(2)

RXDATA[1]+/- A16,

D13(2)

RXDATA[0]+/- B15, B16(2)

Signal BGA

Ball Name I/O Freq

Level Description

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

24 of 28

Draft 8/15/03

RXCLK+/- U6, P8(2) Parallel Output

Clock O

155/311/

622MHz

LVDS

Output clock for RXDATA. Falling edge of

RXCLK+ is centered in output data eye. When

INTRLV = 1, the clock frequency is 622MHz

(CLK311MODE = 0) or 311MHz (CLK311MODE

= 1). When INTRLV = 0, BUSMODE = 1, the clock

frequency is 155MHz. When INTRLV = 0,

BUSMODE = 0, the clock frequency is 622MHz

TXLOA E4

Loss Of Serial

STS-12/ STM-4

Channel

Alignment

OTTL

A logic 1 indicates that alignment between the frame

boundaries of the 4 serial, STS-12/ STM-4 channels

on TXDATA[3:0] cannot be achieved. This may be

due to the serial channels being asynchronous with

respect to REFCLK or channel skew larger than +/-3

byte times.

TXDATA[15]+/- N3, P2(2)

Parallel/Serial

Input Bus

155Mb/s

LVDS

When INTRLV = 0, BUSMODE = 1, this bus

contains 16-bit parallel data that will be bit

multiplexed for output on TXOUTA/B.

When INTRLV = 0, BUSMODE = 0, bits [3:0] of

this bus contains 4-bit, parallel data that will be bit

multiplexed for output on TXOUTA/B.

When INTRLV = 1, data on bits [3:0] of this bus are

4, STS-12/ STM-4 serial data channels. These serial

data channels can be skewed from each other as

much as +/-3 byte times and will be aligned together

before being byte multiplexed for output on

TXOUTA/B.

TXDATA[14]+/- P1, R1(2)

TXDATA[13]+/- M3, M4(2)

TXDATA[12]+/- M2, N2(2)

TXDATA[11]+/- L3, L4(2)

TXDATA[10]+/- M1, L2(2)

TXDATA[9]+/- K4, L1(2)

TXDATA[8]+/- K2, K3(2)

TXDATA[7]+/- J4, J3(2)

TXDATA[6]+/- H1, J2(2)

TXDATA[5]+/- H2, G1(2)

TXDATA[4]+/- H4, H3(2)

TXDATA[3]+/- F2, G2(2)

155/

622Mb/s

LVDS

TXDATA[2]+/- G4, G3(2)

TXDATA[1]+/- D1, E1(2)

TXDATA[0]+/- E2, F3(2)

TXCLK+/- P10, R10(2) Parallel Input Bus

Clock I

155/311/

622Mb/s

LVDS

Input clock, synchronous with parallel input data

bus TXDATA. The rising edge of TXCLK+ is used

to sample data on TXDATA.

TXCLK_SRC+/- R11, P11(2) Source

Synchronous

Timing Reference

155/311/

622Mb/s

LVDS

This output clock provides external devices with a

clock to be used in driving TXDATA and TXCLK to

insure that they are synchronous with REFCLK.

TXOUTA+/- U16,

U17(2)

Serial 2.5Gb/s

Data Outputs

Channel A O2.5Gb/s

CML

Serial 2.5Gb/s data output for channel A. Serial data

is the result of the bit or byte multiplexing of the

input data on TXDATA. Channels A and B are

identical.

TXOUTB+/- U13,

U14(2)

Serial 2.5Gb/s

Data Outputs

Channel B

O2.5Gb/s

CML

Serial 2.5Gb/s data output for channel B. Serial data

is the result of the bit or byte multiplexing of the

input data on TXDATA. Channels A and B are

identical.

Signal BGA

Ball Name I/O Freq

Level Description

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VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

25 of 28

Draft 8/15/03

REFSEL H16 Reference Clock

Select ITTL

A logic 1 indicates that a nominal 78MHz PLL

reference clock is being used. A logic 0 indicates

that a nominal 155MHz PLL reference clock is

being used.

REFCLK+/- U11,

U10(2) PLL Reference

Clock I

78/

155MHz

LVDS

Fixed frequency reference for PLL operation.

Frequency must be synchronous to within +/-40ppm

of incoming data on RXINA/B. Frequency can be

either nominal 78MHz or nominal 155MHz as

indicated by REFSEL.

PLLFST P9 PLL Capacitor Analog Capacitor for PLL operation. 0.1µF between

PLLFST and PLLSLW

PLLSLW R15

IRSEL K16

LVDS/CML

Input Impedance

Reference Resistor

Analog

Reference resistor to set input resistance for LVDS/

CML inputs within 20% tolerance. Resistor must be

8.8 times desired input impedance, with 5%

tolerance, and connected to Vss. For example, a

1KΩ resistor results in 113Ω input impedance, and a

910 Ω resistor results in 103Ω input impedance.

TSTCNTRL[2] U4

Test Control I TTL Test control. Tie all bits to logic 0.TSTCNTRL[1] R6

TSTCNTRL[0] T5

RXSTSTA G14 Test Input I TTL Reserved for future use (selectable to a logic 1 or 0).

Set to logic 0.

FRALIGNRSTSEL E17 FRALIGNRST

select ITTL

When FRALIGNRSTSEL=01, FRALIGNRST

resets both selected and unselected channel

alignment FIFOs (normal operation). When

FRALIGNRSTSEL=1, FRALIGNRST resets only

the unselected channel alignment FIFO.

FIFOSEL D16 FIFO select I TTL

When FIFOSEL=0, the VSC9180 will deskew

incoming 2.5Gb/s signals up to +/- 75ns. When

FIFOSEL=1, the deskew limit will increase to

greater than +/- 75ns. In addition, the Input to

Output Delays as specified in Table 8 will also

increase.

TXSTSTA B17 Test Output O TTL Test output. Must be left unconnected.

TXSTSTB E14 Test Output O TTL Test output. Must be left unconnected.

TSTINTA K15 Test Output O Analog Test output. Must be left unconnected.

TSTINTB K14 Test Output O Analog Test output. Must be left unconnected.

TSTINTCS L15 Test Output O Analog Test output. Must be left unconnected.

VDDNEXT J16 External 1.8V

Supply Enable I TTL Test only tie to logic 0.

VDDN U7 Internal 1.8V

Supply PWR Capacitor for internal voltage regulator filter.

Connect from VDDN to VSS.

VDD

D14, H14,

K17, M15,

N4, R3, R9,

T9, U5

2.5V Power Supply PWR Main 2.5V supply that powers internal logic.

Signal BGA

Ball Name I/O Freq

Level Description

Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com

VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

26 of 28

Draft 8/15/03

NOTES:(1) Designs using the VSC9180 should allow these signals to be adjusted for optimal settings.

(2) In the Signal column, polarity ± is reflected in the BGA Ball column respectively, (A2, D5). Example A2 = (+) signal, D5 = (-) signal.

Moisture Sensitivity Level

The VSC9180 is rated moisture sensitivity level 3 or better as specified in JEDEC standard IPC/JEDEC

J-STD-020B. For more information, see the JEDEC standard.

Thermal Specifications

Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using

a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information,

see the JEDEC standard.

VDDIO

A6, A9,

B4, B5,

B10, C11,

C14, D12,

J1, L14,

P14, R16,

T7, T10,

T12, T14,

U15

2.5V Power Supply PWR Main 2.5V supply that powers I/Os.

VSS

C3, F1,

F15, H15,

M16, N1,

P4, P6, U9

0V Ground Supply PWR Main 0.0V supply for ground reference for internal

logic.

VSSIO

A1, A4,

A12, A14,

B9, C8,

C13, C15,

D7, F4, K1,

N17, P7,

R8, R13,

T11, T17,

U12

0V Ground Supply PWR Main 0.0V supply for ground reference for

I/Os.

VDDA T8 2.5V Analog

Power Supply PWR 2.5V isolated supply.

VSSA U8 0V Analog

Ground Supply PWR 0.0V isolated supply for analog ground reference.

Table 14. Thermal Resistances

Part Number θJC

θJA (°C/W) vs. Airflow (ft/min)

0100 200

VSC9180UV 1.7 17.3 14.6 13.0

Signal BGA

Ball Name I/O Freq

Level Description

Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com

VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

27 of 28

Draft 8/15/03

Package Information - 195 BGA

Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com

VSC9180

Data Sheet

G52346, Revision 4.6

September 2, 2003

28 of 28

Draft 8/15/03

ORDERING INFORMATION

VSC9180 Serial 2.5Gb/s Hitless Sonet/SDH Backplane Transceiver

Part Number Description

VSC9180UV 23mm,195 BGA

Temperature Range: 0ºC ambient to 105ºC case

PRINTED IN THE U.S.A

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