fax id: 5217 CY7C09269/79/89 PRELIMINARY CY7C09369/79/89 CYPRESS 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Features * Low operating power Active= 2 * True Dual-Ported memory ceils which allow simulta- Active= 200 mA (typical) neous access of the same memory location Standby= 0.05 mA (typical) * 6 Fiow-Through/Pipelined devices Fuily Synchronous interface for easier operation 16K x 16/18 organization (CY7C09269/369) Burst counters increment addresses internally 32K x 16/18 organization (CY7C09279/379) ~~ Shorten cycle times 64K x 16/18 organization (CY7C09289/389) Minimize bus noise * 3 Modes ~~ Supported in Flow-Through and Pipelined modes Flow-Through * Dual Chip Enables for Easy Depth Expansion Pipelined * Upper and Lower Byte Controls for Bus Matching * Automatic power-down ~~ Burst * Commercial and Industrial Temperature Ranges * Pipelined output mode on both ports aliows fast 100 . . : MHz cycle time Available jn 100-pin TQFP * 0.35-micron CMOS for optimum speed/power * Pin-compatible and functionally equivalent to 1DT709269, 1DT70927, and IDT709279 ad * High-speed clock to data access 8/10/12ns (max.) Logic Block Diagram RM, RW, UB, UBR CEor CEon CEy CEyq TB, TBR OE, L OER FT/Pipe, FT/Pipen ft} ay VOger-O4 547. B/7R vo Control vO i 89 Control al al VOo, -VO7e. BR 13) 14/15/16 14/15/16 ia} Aow-Ai3/14/4 Counter! Counter/ 13/1 4/15R ounter ounter, L CLK, Address True Dual-Ported Address aoe ADS, Register RAM Array Register R CNTENL Decode Decode CNTENA CNTRST_ CNTRSTR Notes: 1. WOg~VOys tor x16 devices; /Og-1/O,7 for x18 devices. 2. WOg-I/O7 for x16 devices. /Oo~/Og for x18 devices. 3. Ag-Atg for 16K; Ap~A,, for 32K; Ag-Ays for 64K devices. For the most recent information, visit the Cypress web site at www.cypress.com 3-119PRELIMINARY CY7C09269/79/89 CY7C09369/79/89 Functional Description The CY7C09269/79/89 and CY7C09369/79/89 are high speed synchronous CMOS 16K, 32K, and 64K x 16/18 du- al-port static RAMs. Two ports are provided permitting inde- pendent, simultaneous access for reads and writes to any jo- cation in memory, |4 y Registers an control, address and data lines allow for minimal setup and hold times. In pipelined out- put mode, data is registered for decreased cycle time. Clock to data valid tops =8 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to elimi- nate access latency. In flow-through mode data will be avail- able tcp1 = 12 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address regis- ter. The internal write puise width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. Pin Configurations A HIGH on CE, or LOW on CE, for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CTEp LOW and CE, HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A ports burst counter is loaded with the port's address strobe (ADS). When the port's count enable (CNTEN) is asserted, the address counter will increment on each LOW to HIGH transi- tion of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TOFP). 100-Pin TQFP (Top View) let wt od od dt at od ae Bey 8 BS E eeeecreece 2222322222 a 8 Bak 222222282 2 100 94 98 97 96 95 94 93 G2 91 90 BO 8B 87 BG BS B4 B3 82 81 BO 79 7B 77 76 anf] 1 7s [oO] asa Ato [I] 2 74 COT] ator AL EZ] 3 73 =e ava. CI] 4 72 Ai2aR ava. (oo) s "A A13R (Note ] atau [] 6 70 = At14R [Note 5] {Note 6] Aisi (_] 7 69 A15A [Note 6] nc fT] 3 68 [_] xc nc {=T] 9 67 Lo) ne cor FT] io 66 [I] cer ox fa] 0 CY7C09289 (64K x 16) es FS om croc CT] 12 ea (CT) ce cen a] 13 CY7C09279 (32K x 16) eo Eatoem cuTRete Co] 14 6a LOTT) cHresTA wo Lael ss CY7C09269 (16K x 16) | Esl aw awe Co) 16 so CZ] awn" vet CI] 17 so (] orm [Note 7) FrPiPEL [7] 18 58 [J ETP IPER [Note 7] end [7] 19 s7 [I] ano vors. {7} 20 s [ZT vosr vor (Oo) 21 56 [J wo1ar votat [TTT] 22 s4 [7] vo13R vora. [7] 23 53 [TT] over your [27] 24 se [XT] vorta voro. [ZZ] 2s 51 Coc] voor 26 27 28 29 30 31 92 33 34 35 36 37 98 39 40 41 42 43 44 45 46 47 48 49 50 JUUUDUUUUUU UU UU UU UU VOTL Zz 2 & g vOsL yoar vO3L #O2L 86 Qg 90 = 3 = Notes: 4. When writing simultaneously to the same location, tne final value cannot be guaranteed. 5. This pin is NG for CY7C09269. 6. This pin is NC for CY7C.09269 and CY7C09279. GND iOOR 404 O2R, OAR Oo! O6R Vv VOT vosR: VOSR 7. For CY7C09269 and CY7C09279, pin #18 connected to Vgc is equivaient to an IDT x16 pipelined device, connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-through device. 3-120CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Pin Configurations 100-Pin TQFP (Top View) seggeageglst egbSbsesgeggs NNONONNAANAANNANNGANAANAN 100 99 98 97 96 95 94 93 92 91 90 69 88 87 G6 B5 84 83 B82 81 BO 79 78 77 76 as. Co] 5 75 ] asr ait C7 2 74 [=] aor anL_E=] 3 739 EX ator avait CZ] 4 v2 Co atie| ai. 5 7 CO] arr (Note 8} A74L [La] 6 70 [J atsr INote 9] a18i | 7 69 [TT] atan [Note 2) coc C77} 3 68 [I] Aisa [Note 9] oat Co] 9 87 [I ter cet Co] to 66 [] oer cen Cid CY7C09389 (64K x 18) 65 CeOR onTAstt [(T] 12 64 GEIA rat Lo] 12 CY7C09379 (32K x 18) oo FJ owrsre ost ZI] 14 se [I] awe vec LZ] 15 61 [71] end pppa Ea CY7C09369 (16K x 18) , jo on 17 so [_] teirer VO16L 18 5a Co] voi7r eno [TZ] 19 57 CJ eno vos. {7} 20 56 [7] voier vow. [7] at 56 (TI ] vorsr vOt1at 22 54 [TT] vor Votat. 23 83 [7] voisr voit To] 24 52 [7] vo1er voto. [ZZ] 2s at CT vor, 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SESSSPESSSSESEERSSE SLE SEE Selection Guide CY7C09269/79/89 CY7C09269/79/89 CY7C09269/79/89 CY7C09369/79/69 C7C09369/79/69 CY7C09369/79/89 4 -10 -12 fyaaxe (MHZ) (Pipelined) 100 67 50 Max Access Time (ns) (Clock to data, Pipelined) 8 10 12 Typical Operating Current lec (mA) 250 220 200 Typical Standby Current for Igg, (mA) 45 35 30 (Both ports TTL Level) Typical Standby Current for Igg3 (mA) 0.05 0.05 0.05 (Both ports CMOS level) Notes: 8, This pin is NC for CY7C090369, 9, This pin is NC for CY7C090369 and CY7C090379. 3-121 ee)CY7C09269/79/89 CYPRESS PRELIMINARY CY7C09369/79/89 Pin Definitions Left Port Right Port Description Aow-Atse. Agr-Aisr Address Inputs.(Ap-A4,4 for 32K, Ap-Ay3 for 16K devices) ADS. ADS, Address Strobe Input. Used as an address qualifier. This signal should be asserted low during normal read or write transactions. Asserting this signal low also loads the burst address counter with data present on the I/O pins. CE CE CEon.CEiR | Chip Enable Input. To select either the left or right port, both CEy AND CE, must be asserted to their active states (CE) < Vy, and CE, 2 Viy) | CLK, CLKa Clock Signal. This input can be free running or strobed. Maximum clock input rate is fax. L CNTENR Counter Enable input. Asserting this signal low increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted low, CNTRST_ CNTRSTR Counter Reset Input. Asserting this signal low resets the burst address counter of its respective port to zero. C(NTRST is not disabled by asserting ADS or CNTEN YOuHO47. | YOpR-H/Oy7R | Data Bus Input/Output. (O9-1/O45 for x16 devices} TB, TBR Lower Byte Select Input. Asserting this signal low enabies read and write operations to the lower byte. (I/Og-I/Og tor x18, /Og~i/Oz for x16) of the memory array. For read operations both the EB and OE signals must be asserted to drive output data on the lower byte of the data pins. UB, UB, Upper Byte Select Input. Same function as CB, but to the upper byte (1/Ogiq, -VO45/47,) OE, OER Output Enabie input. This signal must be asserted low to enabie the I/O data pins during read operations. RW, RW, ReadMWrite Enable Input. This signal is asserted low to write to the dual port memory array. For read operations, assert this pin high. FT/PIPE, FT/PIPEa Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin low. For pipelined mode operation, assert this pin high. GND Ground Input. NC No Connect. Voc Power Input. Maximum Ratings Output Current into Outputs (LOW)... cece 20 mA i Ve tee : vee OV (Above which the useful life may be impaired. For user guide- Static Discharge Voltage 720 lines, not tested.) Latch-Up Current... cen cree nneenereiees >200mA Storage Temperature oo... cece ences 65C to + 150C Ambient Temperature with Power Applied 55C to + 125C Operating Range Supply Voltage to Ground Potential... O.3V to + 7.0V | Ambient DC Voltage Applied to Range Temperature Vec Outputs in High Z State 0.0. eee -0.5V to + 7.0V Commercial OC to 470C BV 10% DC Input Voltage... cies seetseeersreneenetees ~0.5V to + 7.0V Industrial 40C to 485C BV 210% 3-122CY7C09269/79/89 CYPRESS PRELIMINARY CY7C09369/79/89 Electrical Characteristics Over the Operating Range CY7C09269/79/89 CY7C09369/79/89 8B 10 12 Symbol Parameter Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Units Vou Output HIGH Voltage (Vec=Min, 2.4 2.4 24 v Igyu=4.0mA) Vo- Output LOW Voltage (Vcc=Min, 0.4 0.4 0.4 v loH= +4.0mA) Vin Input HIGH Voltage 2.2 2.2 2.2 v Vit Input LOW Voltage 0.8 0.8 0.8 Vv loz Output Leakage Current -10 10 | -10 10 ~10 10 pA loc Operating Current Com'l. 250 | 450 220 | 385 200 | 350 mA (Vec=Max, loyr=0mA) Outputs Disabied Indust. 245 | 410 225 | 375 mA Isp1 Standby Current (Both Com. 45 | 115 35 100 30 85 mA Ports TTL Level) CE, & CEg > Vin, fhyax Indust. 50 115 45 100 mA am Ispe Standby Curent (One Port | Com'l. 175 225 145 | 195 125 | 175 mA a TTL Level)!'91CE, | CEn> Mndust. 160 | 210 140 | 190 | mA Vin ffmax Isp3 Standby Current (Bom Com. 0.05 | 0.25 0.05 | 0.25 0.05 | 0.25 | mA Ports CMOS Level)!" CE, & CEn 2 Vg -0.2V, f=0 Indust. 0.05 | 0.25 0.05 | 0.25 | mA Igpa Standby Current (One Port | Com! 160 | 200 130 | 170 410 | 150 mA CMOS Level)!" CEL ICER [indust. 145 | 185 125 | 165 | mA 2 Vin, ffuax Capacitance Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ty = 25C, f= 1 MHz, 10 pF Cour Output Capacitance Voc = 5.0V 10 pF AC Test Loads 5V 5V Ril= 8930 Rry = 2502 OUTPUT, OUTPUT R1= 8930 OUTPUT C= 30pF C= 30pF p T R2= 3472 L C= 5pF aL = Ven = 1.4V R2= 3470 (a) Normal Load (Load 1) (b) Thvenin Equivalent (Load 1) (c) Three-State Delay (Load 2) (Used for toKiz: toxz: & tonz ALL INPUT PULSES including scope and jig) Note: 10. TE, and CER are internal signals. To select either the left or right port, both TE, AND CE, must be asserted to their active states (TE, $ Vy and CE, > Vin). 3-123a CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Switching Characteristics Over the Operating Range CY7C09269/79/a9 | CY7C09369/79/89 : 8 -10 12 Symbol Parameter Min Max Min Max Min Max Units faxs Fax Flow-Through 67 50 33 MHz fuaxe Fiax Pipelined 400 67 50 MHz teves Clock Cycle Time - Flow-Through 15 20 30 ns teyce Clock Cycle Time - Pipelined 10 15 20 ns tout Clock High Time - Flow-Through 6.5 9 12 ns tout Clock Low Time - Flow-Through 6.5 9 12 ns tone Ciock High Time - Pipelined 4 6.5 8 ns tove Clock Low Time - Pipelined 4 6.5 8 ns tr Clock Rise Time 3 3 3 ns te Clock Fall Time 3 3 3 ns tsa Address Set-up Time 3 3.5 4 ns tHa Address Hold Time 0 0 0 ns tsc Chip Enable Set-up Time 3 3.5 4 ions | tuc Chip Enable Hold Time Oo | 0 0 ns tow RAW Set-up Time 3 3.5 4 ns thw RAW Hoid Time 0 0 ns tsp Input Data Set-up Time 3 3.5 4 ns tp Input Data Hold Time 0 0 Q ns tsap ADS Set-up Time 3 3.5 4 ns tuao ADS Hold Time 0 0 0 ns tscn TNTEN Set-up Time 3 3.5 4 ns i tHon CNTEN Hoid Time 0 0 0 ns isast CNTRST Set-up Time 3 | 3.5 4 ns tHrst CNTRST Hold Time 0 0 0 ns tor Output Enable to Data Valid 8 10 12 ns toiz OE to Low Z 2 2 1 2 ns tonz OE to High Z 1 7 i 4 7 | 1 7 7 ns top: Clock to Data Valid - Flow-Through 12 17 | 25 ns i tone Clock to Data Valid - Pipetined 8 10 12 ns toc Data Output Hold After Clock High 2 2 2 ons | toxHz Clock High to Output High Z 2 9 2 9 2 9 | ns texez Clock High to Output Low Z 2 2 2 ; ons Port to Port Delays tewoo Write Port Clock High to Read Data Delay 25 35 40 ns tecs Clock to Ciock Set-up Time 9 42 15 ns 3-124CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V,,)!11-12.13.14] teyo1 bet bop fe ty 1 of clk _ Ne AN, ee oz, XA KKK KKK KKK REE tse tue tsc the ce, RAW v SW isa ADDRESS An DATAgyt 1 OE foe Read Cycle for Pipelined Operation (FT/PIPE = Vy,)/1112.13.14! love t toro tora>) K + ~4 7 wee, tga ADDRESS A DATAgyy toxtz | Notes: 11. OEis asynefroncusly controlled; all other inputs are synchronous to the rising clock edge. 12, ADS =V,,, CNTEN and CNTHST = Vi, 13. The output is disabled (high-impedance state) by CEg=V,, or CE, = Vy following the next rising edge of the clock. 14, Addresses do not have to be accessed sequentially since ADS = V\_ constantly oads the address on the rising edge of the CLK. Numbers are for reference only. 3-125CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Switching Waveforms (continued) Bank Select Pipelined Read!'5-14 tevc2 CLK, ADDRESS .@1) CE ga) DATAgut@1 ADDRESS 2) CE prea) DATAguria2) Left Port Write to Fiow-Through Right Port Read!'7:18.19.20} CLK, RA, ADDRESS, DATAWL CLK, AN ADDRESS, DATAguta log -- toc Notes: 15. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2: Each Bank consists of one Cypress dual-port device from this datasheet. AD- DRESS 91 = ADDRESS pg). 16. UB, 08, OF and ADS = Vip; CE 1791), CEy 92). RAW, CNTEN, and CNTRST = Vix. 17. The same waveforms apply for a right port write to flow-through left port read. 18. CE, UB, CB, and ADS = V,,; CE, CNTEN, and CNTRST = Vin. 19. OE = Vj), for the Right Port, which is being read trom. DE = Vy, for the Left Port, which is being written to. 20. ittecg s maximum specified, then data from right port READ is not valid untl the maximum specified for towpp, lf tecg>maximum specified, then data is not valid until tocg + tepi- tcwoo does not apply in this case. 3-126a: CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = V,, )21:22-25.24) loyc2 nuk NOIR YON ONO OO. = | AXA AX | KRA LKMA KO. | KX cs, XO TNX XXYTRXY RXY | RKY ww OY XK XXL KR KRY RKY TXRRY ADDRESS D A) . Anat Ans Ane Ans Anca ten! t i tsa tha : So SQL HD | om ex . tepe toxuz x X toniz tena ~ DATAgur Qh | Qnig - - - READ -----+}NO OPERATION-++ WRITE -sl.--- READ - - Pipelined Read-to-Write-to-Read (OE Controiled)|2! 22.23.24) tove2 ton2 tore CLK CE, CE, ADDRESS DATAgyt DATAiy OE - -- - READ WRITE READ - - - Notes: 21. Output state HIGH, ie or High-impedance) is determined by the previous cycle control signals. 22. TE, and = Vac , and CONTEST = 23. Addressed do not ve 10 be accessed sequentially since ADS = V,_ constantly loads the address on the rising edge of tha CLK; numbers are for reference only. 24. During No operation, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. 3-127CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = V,, )!12:25.26.27.28] i lever tot tou CLK CEQ CE, RAW ADDRESS DATAns DATAput Qnit toxnz NO OPERA Flow-Through Read-to-Write-to-Read (OE Controlled)!!2:25:26.27.28] ja Lover 1 tons tou CLK CE, RW ADDRESS DATA DATAgyt Qnag tonz toc OE WRITE wa READ ~ oO OT Notes: 25. OQuiput state (HIGH. bow. or High-impedance} is eyermined by the pravious cycle contro! signals. 26, CE, and =Viii SER oe oRTaeT ov. 27. Addresses do not a 16 be accessed sequentially since ADS = V,_ constantly loads the address on the rising edge of the CLK; numbers are for reference only 28. During No operation. data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.CY7C09269/79/89 i PRELIMINARY BaF 05055 CY7C09369/79/89 Switching Waveforms (continued) Pipelined Read with Address Counter Advancel@ Loyce fog toua CLK tga tua ADDRESS tsap ADS, DATAgut On Ont Qnie Qa READ ~ ~ EXTERNAL ADDRESS loc COUNTER HOLD READ WITH COUNTER READ WITH GOUNTER oO Fiow-Through Read with Address Counter Advance!@*! tever fou Ton CLK tsa tha ADDRESS thap ton DATAgut a, Qa Qne3 toc READ READ OUNTER HOLD .~ EXTERNAL READ WITH COUNTER COUNTER HO WITH ADDRESS COUNTER Note: 29. TE, and OE = Vi; CE,, AAW and CNTRST = V,,. 3-129CY7C09269/79/89 PRELIMINARY CY7C09369/79/89 CYPRESS Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)2031) ~ leyco tcHe | tore oa KN XN SVAN IVS ae tHA INTERNAL ~~ ADDRESS XK a,< Anat NK foe x Ang OK Ane tsap tHap 78 ON | ADO | SOO XO OO OO owen XY |X AKY XA KK AN AOA Iscn tHon tsp tup 1 WRITE EXTERNAL | WAITE WITH | WRITE COUNTER! ~ ADDRESS COUNTER HOLD WRITE WITH COUNTER - Notes: 30, CE, UB, CB, and AAW = V,,; CE, and CNTHST = 31. The Internal Address is equal to the External ase" when ADS = Vj, and equais the counter output when ADS = Vy. 3-130CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Switching Waveforms (continued) Counter Reset (Pipelined Outputs)2?.99.54.5] lovee tone toa CLK ADDRESS INTERNAL ~ Ay ADDRESS RW ADS ee DATA DATAgut Qo Q, COUNTER WRITE READ READ READ RESET ADDRESS 0 ADDRESS 0 ADDRESS 1 ADDRESS n Notes: 32. CE,, UB, and TB = V\_; CE, = Vy. 33. Addresses to not have to be accessed sequentially since ADS = V,, constantly loads the address on the rising edge of the CLK; numbers are for reference anly. 34. Output state (HIGH, LOW, High-impedance} is determined by the previous cycle control signals. 35. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 3-131CY7C09269/79/89 PRELIMINARY CY7C09369/79/89 CYPRESS Read/Write and Enable Operation!*3.3*) inputs Outputs OE | CLK | CE, | CE, | RAV | WO,-0,7 Operation Xx H x | xX High-2 | Deselecteci!** a x | | x L | Xx High-Z | Deselected!*! x] oe L H L Din Write Lj o-~[t oH] H Dour _ | Read!?9] H X L iH x High-Z | Outputs Disabled Address Counter Control Operation60.41.42! Previous Address | Address | CLK | ADS | CNTEN | CNTRST vo Mode Operation xX x - x x L Doutio) Reset Counter Reset to Address 0 An x 7 L Xx H Doutin) Load Address Load into Counter x An cr H H H Doutiny Hold External Address BlockedCounter Disabled x Ap _ H L H i Doutinst) | Increment | Counter Enabledinternal Address Generation Notes: 36, X" = Dont Care, H = Vi L" = Vic. 37. ADS, CNTER, CNTHST = Don't Care. 38. OE is an asynchronous input signal. 39. When CE changes state in the ave mode, deselection and read happen in the following clock cycle. 40, CE, and OE = Vi_; CE, and Ri 41, Oata shown for Flow-through mode; pipelined ed fe output wiil be delayed by one cycle. ee, 42. Counter operation is independent of CE, and C 3-132CY7C09269/79/89 PRELIMINARY CYPRESS CY7C09369/79/89 Ordering Information 16K x16 Synchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type Range 8 CY7C09269-8AC A100 100-Pin Thin Quad Flat Pack Commercial 10 CY7C09269-10AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09269-10Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09269-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09269-12Al A100 100-Pin Thin Quad Flat Pack Industrial 32K x16 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 8 CY7C09279-8AC A100 100-Pin Thin Quad Flat Pack Commercial 10 CY7C09279-10AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-10Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09279-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-12Al A100 100-Pin Thin Quad Flat Pack Industrial 64K x16 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 8 CY7C09289-8AC A100 100-Pin Thin Quad Flat Pack Commercial 10 CY7C09289- 10AC A100 100-Pin Thin Quad Fiat Pack Commercial CY7C09289-10AI A100 100-Pin Thin Quad Flat Pack Industrial : 12 CY7C09289-12AC At00 100-Pin Thin Quad Flat Pack Commercial CY7C09289-12Al A100 100-Pin Thin Quad Flat Pack industrial 16K x18 Synchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type Range 8 CY7C09369-8AC A100 100-Pin Thin Quad Flat Pack Commercial 10 CY7C09369-10AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09369-10Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09369-12AC A100 100-Pin Thin Quad Fiat Pack Commercial CY7C09369-12AI A100 100-Pin Thin Quad Flat Pack Industrial 32K x18 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 8 CY7C09379-8AC Ai00 100-Pin Thin Quad Flat Pack Commercial 10 CY7C09379-10AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-10AI A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09379-12AC A100 100-Pin Thin Quad Fiat Pack Commercial CY7C09379-12Ai A100 100-Pin Thin Quad Flat Pack Industrial 3-133CY7C09269/79/89 CYPRESS PRELIMINARY CY7C09369/79/89 64K x18 Synchronous Dual-Port SRAM Speed Package | Operating (ns) Ordering Code Name Package Type Range 8 CY7C09389-8AC A100 100-Pin Thin Quad Flat Pack Commercia! 10 CY7C09389-10AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-10Al A100 100-Pin Thin Quad Flat Pack industrial 12 CY7C09389-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-12Al A100 100-Pin Thin Quad Flat Pack Industriat Document #: 3800664 3-134