Energy Metering IC with Integrated Oscillator ADE7757* FEATURES On-Chip Oscillator as Clock Source High Accuracy, Supposes 50 Hz/60 Hz IEC 521/IEC 61036 Less than 0.1% Error over a Dynamic Range of 500 to 1 The ADE7757 Supplies Average Real Power on the Frequency Outputs F1 and F2 The High Frequency Output CF Is Intended for Calibration and Supplies Instantaneous Real Power The Logic Output REVP Can Be Used to Indicate a Potential Miswiring or Negative Power Direct Drive for Electromechanical Counters and 2-Phase Stepper Motors (F1 and F2) Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time On-Chip Power Supply Monitoring On-Chip Creep Protection (No Load Threshold) On-Chip Reference 2.5 V (20 ppm/C Typical) with External Overdrive Capability Single 5 V Supply, Low Power (20 mW Typical) Low Cost CMOS Process AC Input Only GENERAL DESCRIPTION The ADE7757 is a high accuracy electrical energy measurement IC. It is a pin reduction version of the ADE7755 with an enhancement of a precise oscillator circuit that serves as a clock source to the chip. The ADE7757 eliminates the cost of an external crystal or resonator, thus reducing the overall cost of a meter built with this IC. The chip directly interfaces with the shunt resistor and operates only with ac input. The ADE7757 specifications surpass the accuracy requirements as quoted in the IEC 61036 standard. The AN-679 Application Note can be used as a basis for a description of an IEC 61036 low cost watt-hour meter reference design. The only analog circuitry used in the ADE7757 is in the - ADCs and reference circuit. All other signal processing (e.g., multiplication and filtering) is carried out in the digital domain. This approach provides superior stability and accuracy over time and extreme environmental conditions. The ADE7757 supplies average real power information on the low frequency outputs F1 and F2. These outputs may be used to directly drive an electromechanical counter or interface with an MCU. The high frequency CF logic output, ideal for calibration purposes, provides instantaneous real power information. The ADE7757 includes a power supply monitoring circuit on the VDD supply pin. The ADE7757 will remain inactive until the supply voltage on VDD reaches approximately 4 V. If the supply falls below 4 V, the ADE7757 will also remain inactive and the F1, F2, and CF outputs will be in their nonactive modes. Internal phase matching circuitry ensures that the voltage and current channels are phase matched while the HPF in the current channel eliminates dc offsets. An internal no-load threshold ensures that the ADE7757 does not exhibit creep when no load is present. The ADE7757 is available in a 16-lead SOIC narrow-body package. FUNCTIONAL BLOCK DIAGRAM VDD DGND AGND ADE7757 POWER SUPPLY MONITOR V2P - ADC V2N V1N - ADC V1P 2.5V REFERENCE 4k REFIN/OUT SIGNAL PROCESSING BLOCK ...110101... MULTIPLIER LPF PHASE CORRECTION HPF ...11011001... DIGITAL-TO-FREQUENCY CONVERTER INTERNAL OSCILLATOR RCLKIN SCF S0 S1 REVP CF F1 F2 *U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. 5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 k, ADE7757-SPECIFICATIONS (V0.5%=5 V50ppm/C, T to T = -40C to +85C, unless otherwise noted.) DD MIN Parameter MAX Value Unit Test Conditions/Comments 0.1 % Reading typ Channel V2 with Full-Scale Signal ( 165 mV), 25C Over a Dynamic Range 500 to 1 Line Frequency = 45 Hz to 65 Hz 0.1 Degrees () max 0.1 Degrees () max 0.2 % Reading typ DC Power Supply Rejection1 Output Frequency Variation (CF) 0.3 % Reading typ ANALOG INPUTS Channel V1 Maximum Signal Level Channel V2 Maximum Signal Level Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error1 30 165 320 7 18 4 mV max mV max k min kHz nominal mV max % Ideal typ OSCILLATOR FREQUENCY (OSC) Oscillator Frequency Tolerance 1 Oscillator Frequency Stability 1 450 12 30 kHz nominal % Reading typ ppm/C typ RCLKIN = 6.2 k, 0.5% 50 ppm/C 2.7 2.3 10 V max V min pF max 2.5 V + 8% 2.5 V - 8% ON-CHIP REFERENCE Reference Error Temperature Coefficient 200 20 mV max ppm/C typ LOGIC INPUTS3 SCF, S0, S1, Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 2.4 0.8 1 10 V min V max A max pF max 4.5 V min 0.5 V max 4 V min 0.5 10 V max % Ideal typ 4.75 5.25 5 V min V max mA max 1, 2 ACCURACY Measurement Error1 on Channel V1 Phase Error1 between Channels V1 Phase Lead 37 (PF = 0.8 Capacitive) V1 Phase Lag 60 (PF = 0.5 Inductive) AC Power Supply Rejection 1 Output Frequency Variation (CF) REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @ 50 Hz Ripple on VDD of 200 mV rms @ 100 Hz S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms, VDD = 5 V 250 mV See Analog Inputs section V1P and V1N to AGND V2P and V2N to AGND OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% 50 ppm/C OSC = 450 kHz, RCLKIN = 6.2 k, 0.5% 50 ppm/C See Terminology Section and Typical Performance Characteristics External 2.5 V Reference V1 = 21.2 mV rms, V2 = 116.7 mV rms Nominal 2.5 V VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH ISOURCE = 10 mA VDD = 5 V ISINK = 10 mA VDD = 5 V Output Low Voltage, VOL CF Output High Voltage, VOH ISOURCE = 5 mA VDD = 5 V ISINK = 5 mA VDD = 5 V External 2.5 V Reference, V1 = 21.2 mV rms, V2 = 116.7 mV rms Output Low Voltage, VOL Frequency Output Error1, 2 (CF) POWER SUPPLY VDD IDD For Specified Performance 5 V - 5% 5 V + 5% Typically 4 mA NOTES 1 See Terminology section for explanation of specifications. 2 See plots in Typical Performance Characteristics. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. -2- REV. A ADE7757 (VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 k, MIN to TMAX = -40C to +85C, unless otherwise noted.) TIMING CHARACTERISTICS1, 2 0.5% 50 ppm/C, T Parameter 3 t1 t2 t3 t43, 4 t5 t6 A, B Versions Unit Test Conditions/Comments 244 See Table II 1/2 t2 173 See Table III 2 ms sec sec ms sec s F1 and F2 Pulse Width (Logic Low). Output Pulse Period. See Transfer Function section. Time between F1 Falling Edge and F2 Falling Edge. CF Pulse Width (Logic High). CF Pulse Period. See Transfer Function section. Minimum Time between F1 and F2 Pulses. NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 2 See Figure 1. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section. 4 The CF pulse is always 35 s in the high frequency mode. See Frequency Outputs section and Table III. Specifications subject to change without notice. t1 F1 t6 t2 F2 t3 t4 t5 CF Figure 1. Timing Diagram for Frequency Outputs REV. A -3- ADE7757 ABSOLUTE MAXIMUM RATINGS 1 Power Supply Rejection (TA = 25C, unless otherwise noted.) This quantifies the ADE7757 measurement error as a percentage of reading when the power supplies are varied. VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to AGND V1P, V1N, V2P, and V2N . . . . . . . . . . . . . . . . -6 V to +6 V Reference Input Voltage to AGND . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C 16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350 mW JA Thermal Impedance2 . . . . . . . . . . . . . . . . . . . 124.9C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supplies and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading--see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supplies are then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading. ADC Offset Error This refers to the small dc signal (offset) associated with the analog inputs to the ADCs. However, the HPF in Channel V1 eliminates the offset in the circuitry. Therefore, the power calculation is not affected by this offset. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 JEDEC 1S Standard (2-layer) Board Data. Frequency Output Error (CF) The frequency output error of the ADE7757 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7757 transfer function (see the Transfer Function section). ORDERING GUIDE Model Gain Error The gain error of the ADE7757 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7757 transfer function (see the Transfer Function section). Package Description Package Options ADE7757ARN ADE7757ARNRL SOIC Narrow-Body SOIC Narrow-Body in Reel EVAL-ADE7757EB Evaluation Board ADE7757ARN-REF Reference Design RN-16 RN-16 Evaluation Board Reference Design Oscillator Frequency Tolerance The oscillator frequency tolerance of the ADE7757 is defined as part-to-part frequency variation in terms of percentage at room temperature (25C). It is measured by taking the difference between the measured oscillator frequency and the nominal frequency defined in the Specifications section. TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7757 is defined by the following formula %Error = Oscillator Frequency Stability Energy Registered by ADE 7757-True Energy 100% True Energy Oscillator frequency stability is defined as frequency variation in terms of parts-per-million drift over the operating temperature range. In a metering application, the temperature range is -40C to +85C. Oscillator frequency stability is measured by taking the difference between the measured oscillator frequency at -40C and +85C and the measured oscillator frequency at +25C. Phase Error between Channels The HPF (high-pass filter) in the current channel (Channel V1) has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in Channel V1. The phase correction network matches the phase to within 0.1 over a range of 45 Hz to 65 Hz, and 0.2 over a range 40 Hz to 1 kHz (see Figures 11 and 12). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7757 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. A ADE7757 PIN CONFIGURATION VDD 1 16 F1 V2P 2 15 F2 V2N 3 14 CF ADE7757 DGND TOP VIEW V1P 5 (Not to Scale) 12 REVP 11 RCLKIN AGND 6 V1N 4 13 REFIN/OUT 7 10 S0 SCF 8 9 S1 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 VDD Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. 2, 3 V2P, V2N Analog Inputs for Channel V2 (voltage channel). These inputs provide a fully differential input pair. The maximum differential input voltage is 165 mV for specified operation. Both inputs have internal ESD protection circuitry; an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. 4, 5 V1N, V1P Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage inputs with a maximum signal level of 30 mV with respect to the V1N pin for specified operation. Both inputs have internal ESD protection circuitry and, in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. 6 AGND This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage sensors, and so forth. For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at only one point. A star ground configuration will help to keep noisy digital currents away from the analog circuits. 7 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5 V and a typical temperature coefficient of 20 ppm/C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F tantalum capacitor and a 100 nF ceramic capacitor. The internal reference cannot be used to drive an external load. 8 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table III shows calibration frequencies selection. 9, 10 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a Frequency for an Energy Meter Application section. 11 RCLKIN To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a nominal value of 6.2 k must be connected from this pin to DGND. 12 REVP This logic output will go high when negative power is detected, i.e., when the phase angle between the voltage and current signals is greater than 90. This output is not latched and will be reset when positive power is once again detected. The output will go high or low at the same time that a pulse is issued on CF. 13 DGND This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier, filters, and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and digital), MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at one point only, i.e., a star ground. 14 CF Calibration Frequency Logic Output. The CF logic output provides instantaneous real power information. This output is intended for calibration purposes. Also see SCF pin description. 15, 16 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function section. REV. A -5- ADE7757-Typical Performance Characteristics VDD 100nF VDD 602k 220V 200 150nF F2 U1 200 K7 U3 F1 V2P ADE7757 40A TO 40mA 10F CF V2N K8 PS2501-1 150nF REVP 200 V1P RCLKIN 150nF 350 VDD 200 V1N 10k 150nF S0 REFIN/OUT 100nF 1F 6.2k S1 SCF 10nF AGND DGND 10nF 10nF Figure 2. Test Circuit for Performance Curves 0.5 0.4 1.0 PF = 1 ON-CHIP REFERENCE PF = 1 0.8 EXTERNAL REFERENCE 0.3 0.6 +85C 0.2 +25C 0.1 % ERROR % ERROR 0.4 +85C 0 -0.1 -40C -0.2 -0.2 -0.4 -0.6 -0.4 -0.8 0.1 1 CURRENT - A 10 -1.0 0.01 100 TPC 1. Error as a % of Reading over Temperature with On-Chip Reference (PF = 1) 0.9 -40C 0.1 1 CURRENT - A 100 1.0 PF = 0.5 0.8 EXTERNAL REFERENCE -40C, PF = 0.5 0.6 0.5 0.4 % ERROR +85C, PF = 0.5 0.3 0.1 +25C, PF = 1.0 +85C, PF = 0.5 0.2 0 +25C, PF = 1.0 -0.2 +25C, PF = 0.5 -0.4 -0.1 -40C, PF = 0.5 -0.6 -25C, PF = 0.5 -0.3 -0.5 0.01 10 TPC 3. Error as a % of Reading over Temperature with External Reference (PF = 1) PF = 0.5 ON-CHIP REFERENCE 0.7 % ERROR 0 -0.3 -0.5 0.01 +25C 0.2 -0.8 0.1 1 CURRENT - A 10 -1.0 0.01 100 0.1 1 CURRENT - A 10 100 TPC 4. Error as a % of Reading over Temperature with External Reference (PF = 0.5) TPC 2. Error as a % of Reading over Temperature with On-Chip Reference (PF = 0.5) -6- REV. A ADE7757 45 0.5 0.4 40 PF = +0.5 0.3 35 PF = -0.5 % ERROR 0.2 30 25 0 PF = +1.0 20 -0.1 15 -0.3 10 -0.4 0.5 -0.5 45 0 50 55 FREQUENCY - Hz 60 -8 -7 -6 -5 -4 -3 -2 -1 0 1 mV 65 TPC 5. Error as a % of Reading over Input Frequency 1.0 0.8 3 4 5 6 7 8 45 PF = 1 ON-CHIP REFERENCE 40 35 5.25V 0.4 2 TPC 8. Channel V1 Offset Distribution 0.6 % ERROR MEAN: -1.04576552mV STD. DEV: 1.300956604mV 0.1 -0.2 30 DISTRIBUTION CHARACTERISTICS NUMBER POINTS: 100 MINIMUM: -9.82923mV INTERNAL REFERENCE MAXIMUM: 0.472126mV TEMPERATURE = 25C MEAN: 4.54036589mV STD. DEV: 1.89694475mV 0.2 25 5.0V 0 20 -0.2 4.75V -0.4 15 -0.6 10 -0.8 0.5 -1.0 0.01 0 0.1 1 CURRENT - A 10 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 mV 100 1.0 2 4 6 8 10 40 PF = 1 EXTERNAL REFERENCE 0.8 0 TPC 9. Channel V2 Offset Distribution TPC 6. PSR with Internal Reference 35 0.6 5.25V 30 0.4 % ERROR DISTRIBUTION CHARACTERISTICS NUMBER POINTS: 100 INTERNAL REFERENCE MINIMUM: -4.319mV TEMPERATURE = 25C MAXIMUM: 2.2828mV DISTRIBUTION CHARACTERISTICS NUMBER POINTS: 100 EXTERNAL REFERENCE MINIMUM: -6.15% TEMPERATURE = 25C MAXIMUM: 9.96% MEAN: 0% STD. DEV: 2.84% 25 0.2 5.0V 0 20 -0.2 15 4.75V -0.4 10 -0.6 -1.0 0.01 0.1 1 CURRENT - A 10 0 100 % TPC 7. PSR with External Reference REV. A -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 0.5 -0.8 TPC 10. Part-to-Part CF Distribution from Mean -7- ADE7757 The low frequency outputs (F1, F2) of the ADE7757 are generated by accumulating this real power information. This low frequency inherently means a long accumulation time between output pulses. Consequently, the resulting output frequency is proportional to the average real power. This average real power information is then accumulated (e.g., by a counter) to generate real energy information. Conversely, due to its high output frequency and hence shorter integration time, the CF output frequency is proportional to the instantaneous real power. This is useful for system calibration, which can be done faster under steady load conditions. THEORY OF OPERATION The two ADCs digitize the voltage signals from the current and voltage sensors. These ADCs are 16-bit - with an oversampling rate of 450 kHz. This analog input structure greatly simplifies sensor interfacing by providing a wide dynamic range for direct connection to the sensor and also simplifies the antialiasing filter design. A high-pass filter in the current channel removes any dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals. Because the HPF is always enabled, the IC will operate only with ac input (see HPF and Offset Effects section). Power Factor Considerations The method used to extract the real power information from the instantaneous power signal (i.e., by low-pass filtering) is still valid even when the voltage and current signals are not in phase. Figure 4 displays the unity power factor condition and a DPF (displacement power factor) = 0.5, i.e., current signal lagging the voltage by 60. If we assume the voltage and current waveforms are sinusoidal, the real power component of the instantaneous power signal (i.e., the dc term) is given by The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals. In order to extract the real power component (i.e., the dc component), the instantaneous power signal is low-pass filtered. Figure 3 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. This scheme correctly calculates real power for sinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time. ADC MULTIPLIER INSTANTANEOUS POWER SIGNAL - p(t) INSTANTANEOUS POWER SIGNAL F2 LPF INSTANTANEOUS REAL POWER SIGNAL POWER DIGITAL-TOFREQUENCY ADC CH2 This is the correct real power calculation. DIGITAL-TOFREQUENCY F1 HPF CH1 V x 1 x cos(60) 2 CF VI 2 INSTANTANEOUS REAL POWER SIGNAL 0V TIME CURRENT VOLTAGE POWER INSTANTANEOUS POWER SIGNAL TIME INSTANTANEOUS REAL POWER SIGNAL TIME Figure 3. Signal Processing Block Diagram VI COS (60) 2 TIME 0V VOLTAGE CURRENT 60 Figure 4. DC Component of Instantaneous Power Signal Conveys Real Power Information, PF < 1 -8- REV. A ADE7757 ANALOG INPUTS Channel V1 (Current Channel) Nonsinusoidal Voltage and Current The real power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications will have some harmonic content. Using the Fourier Transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content. The voltage output from the current sensor is connected to the ADE7757 here. Channel V1 is a fully differential voltage input. V1P is the positive input with respect to V1N. The maximum peak differential signal on Channel V1 should be less than 30 mV (21 mV rms for a pure sinusoidal signal) for specified operation. v(t ) = V0 + 2 x Vh x sin(ht + h ) ho (1) V1 where: +30mV v(t) is the instantaneous voltage. V0 is the average value. Vh is the rms value of voltage harmonic h. h is the phase angle of the voltage harmonic. V1P VCM DIFFERENTIAL INPUT 30mV MAX PEAK + - V1 COMMON-MODE 6.25mV MAX + - VCM i (t ) = I0 + 2 x Ih x sin(ht + h ) ho (2) AGND -30mV where: V1N Figure 5. Maximum Signal Levels, Channel V1 i(t) is the instantaneous current. I0 is the dc component. Ih is the rms value of current harmonic h. h is the phase angle of the current harmonic. The diagram in Figure 5 illustrates the maximum signal levels on V1P and V1N. The maximum differential voltage is 30 mV. The differential voltage signal on the inputs must be referenced to a common mode, e.g., AGND. The maximum commonmode signal is 6.25 mV, as shown in Figure 5. Using Equations 1 and 2, the real power P can be expressed in terms of its fundamental real power (P1) and harmonic real power (PH). Channel V2 (Voltage Channel) The output of the line voltage sensor is connected to the ADE7757 at this analog input. Channel V2 is a fully differential voltage input with a maximum peak differential signal of 165 mV. Figure 6 illustrates the maximum signal levels that can be connected to the ADE7757 Channel V2. P = P1 + PH where P1 = V1 x I1 cos 1 1 = 1 - 1 (3) V2 and +165mV V2P PH = Vh x Ih cos h h 1 h = h - h (4) VCM As can be seen from Equation 4, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has previously been shown to be accurate in the case of a pure sinusoid. Therefore, the harmonic real power must also correctly account for power factor since it is made up of a series of pure sinusoids. -165mV + - V2 COMMON-MODE 25mV MAX + - VCM V2N AGND Figure 6. Maximum Signal Levels, Channel V2 Channel V2 is usually driven from a common-mode voltage, i.e., the differential voltage signal on the input is referenced to a common mode (usually AGND). The analog inputs of the ADE7757 can be driven with common-mode voltages of up to 25 mV with respect to AGND. However, best results are achieved using a common mode equal to AGND. Note that the input bandwidth of the analog inputs is 7 kHz at the nominal internal oscillator frequency of 450 kHz. REV. A DIFFERENTIAL INPUT 165mV MAX PEAK -9- ADE7757 Typical Connection Diagrams VDD Figure 7 shows a typical connection diagram for Channel V1. A shunt is the current sensor selected for this example because of its low cost compared to other current sensors such as the CT (current transformer). This IC is ideal for low current meters. RF V1P CF 30mV SHUNT 5V 4V 0V TIME V1N CF RF INTERNAL ACTIVATION INACTIVE ACTIVE INACTIVE AGND PHASE NEUTRAL Figure 7. Typical Connection for Channel V1 Figure 9. On-Chip Power Supply Monitor Figure 8 shows a typical connection for Channel V2. Typically, the ADE7757 is biased around the phase wire, and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. Adjusting the ratio of RA, RB, and RF is also a convenient way of carrying out a gain calibration on a meter. RA* RB Figure 10 illustrates the effect of offsets on the real power calculation. As can be seen, offsets on Channel V1 and Channel V2 will contribute a dc component after multiplication. Since this dc component is extracted by the LPF and used to generate the real power information, the offsets will contribute a constant error to the real power calculation. This problem is easily avoided by the built-in HPF in Channel V1. By removing the offsets from at least one channel, no error component can be generated at dc by the multiplication. Error terms at the line frequency () are removed by the LPF and the digital-to-frequency conversion (see Digital-to-Frequency Conversion section). V2P RF CF 165mV V2N RF NEUTRAL PHASE HPF and Offset Effects CF *RA >> RB + RF The equation below shows how the power calculation is affected by the dc offsets in the current and voltage channels. Figure 8. Typical Connections for Channel V2 POWER SUPPLY MONITOR {V cos(t ) +V } x {I cos(t ) + I } OS The ADE7757 contains an on-chip power supply monitor. The power supply (VDD) is continuously monitored by the ADE7757. If the supply is less than 4 V, the ADE7757 becomes inactive. This is useful to ensure proper device operation at power-up and power-down. The power supply monitor has built in hysteresis and filtering that provide a high degree of immunity to false triggering from noisy supplies. As can be seen from Figure 9, the trigger level is nominally set at 4 V. The tolerance on this trigger level is within 5%. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5 V 5% as specified for normal operation. OS V xI = + VOS x IOS + VOS x I cos(t ) + IOS x V cos(t ) 2 V xI + x cos(2t ) 2 DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION VOS I OS VI 2 IOS V VOS I 0 FREQUENCY - RAD/s Figure 10. Effect of Channel Offset on the Real Power Calculation -10- REV. A ADE7757 For a line frequency of 50 Hz, this would give an attenuation of the 2 (100 Hz) component of approximately 22 dB. The dominating harmonic will be at twice the line frequency (2) due to the instantaneous power calculation. The HPF in Channel V1 has an associated phase response that is compensated for on-chip. Figures 11 and 12 show the phase error between channels with the compensation network activated. The ADE7757 is phase compensated up to 1 kHz as shown. This will ensure correct active harmonic power calculation even at low power factors. Figure 13 shows the instantaneous real power signal at the output of the LPF that still contains a significant amount of instantaneous power information, i.e., cos(2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time in order to produce an output frequency. The accumulation of the signal will suppress or average out any non-dc components in the instantaneous real power signal. The average value of a sinusoidal signal is zero. Thus, the frequency generated by the ADE7757 is proportional to the average real power. Figure 13 shows the digital-to-frequency conversion for steady load conditions, i.e., constant voltage and current. 0.30 0.25 0.15 0.10 0.05 DIGITAL-TOFREQUENCY F1 -0.05 V 0 100 200 300 400 500 600 700 800 TIME 900 1000 MULTIPLIER FREQUENCY - Hz Figure 11. Phase Error between Channels (0 Hz to 1 kHz) DIGITAL-TOFREQUENCY CF I LPF TO EXTRACT REAL POWER (DC TERM) 0.30 CF TIME V I 2 0.25 COS (2 ) ATTENUATED BY LPF 0.20 PHASE - Degrees F2 LPF -0.10 FREQUENCY F1 0 FREQUENCY PHASE - Degrees 0.20 0.15 0 2 FREQUENCY (RAD/s) INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN) 0.10 0.05 Figure 13. Real Power-to-Frequency Conversion 0 -0.05 -0.10 40 45 50 55 60 65 70 FREQUENCY - Hz Figure 12. Phase Error between Channels (40 Hz to 70 Hz) Digital-to-Frequency Conversion As previously described, the digital output of the low-pass filter after multiplication contains the real power information. However, since this LPF is not an ideal "brick wall" filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, i.e., cos(ht) where h = 1, 2, 3, . . . and so on. The magnitude response of the filter is given by | H ( f ) |= 1 1+ REV. A f2 4.452 (5) As can be seen in the diagram, the frequency output CF is seen to vary over time, even under steady load conditions. This frequency variation is primarily due to the cos(2t) component in the instantaneous real power signal. The output frequency on CF can be up to 2048 times higher than the frequency on F1 and F2. This higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time while converting it to a frequency. This shorter accumulation period means less averaging of the cos(2t) component. Consequently, some of this instantaneous power signal passes through the digital-to-frequency conversion. This will not be a problem in the application. Where CF is used for calibration purposes, the frequency should be averaged by the frequency counter, which will remove any ripple. If CF is being used to measure energy, for example in a microprocessor based application, the CF output should also be averaged to calculate power. Because the outputs F1 and F2 operate at a much lower frequency, a lot more averaging of the instantaneous real power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output. -11- ADE7757 Interfacing the ADE7757 to a Microcontroller for Energy Measurement INTERNAL OSCILLATOR (OSC) The easiest way to interface the ADE7757 to a microcontroller is to use the CF high frequency output with the output frequency scaling set to 2048 x F1, F2. This is done by setting SCF = 0 and S0 = S1 = 1 (see Table III). With full-scale ac signals on the analog inputs, the output frequency on CF will be approximately 2.867 kHz. Figure 14 illustrates one scheme that could be used to digitize the output frequency and carry out the necessary averaging mentioned in the previous section. The nominal internal oscillator frequency is 450 kHz when used with RCLKIN with a nominal value of 6.2 k. The frequency outputs are directly proportional to the oscillator frequency, thus RCLKIN must have low tolerance and low temperature drift to ensure stability and linearity of the chip. The oscillator frequency is inversely proportional to the RCLKIN as shown in Figure 15. Although the internal oscillator operates when used with RCLKIN values between 5.5 k and 20 k, choosing a value within the range of the nominal value, as shown in Figure 15, is recommended. CF FREQUENCY RIPPLE 490 480 AVERAGE FREQUENCY 10% FREQUENCY - kHz 470 TIME MCU ADE7757 COUNTER CF 460 450 440 430 420 410 TIMER 400 5.8 5.9 6.0 Figure 14. Interfacing the ADE7757 to an MCU The energy consumed during an integration period is given by Counter x Time = Counter Time For the purpose of calibration, this integration time could be 10 seconds to 20 seconds in order to accumulate enough pulses to ensure correct averaging of the frequency. In normal operation, the integration time could be reduced to one or two seconds, depending, for example, on the required update rate of a display. With shorter integration times on the MCU, the amount of energy in each update may still have some small amount of ripple, even under steady load conditions. However, over a minute or more the measured energy will have no ripple. Calculating and displaying power information will always have some associated ripple that will depend on the integration period used in the MCU to determine average power and also on the load. For example, at light loads, the output frequency may be 10 Hz. With an integration period of two seconds, only about 20 pulses will be counted. The possibility of missing one pulse always exists as the ADE7757 output frequency is running asynchronously to the MCU timer. This would result in a onein-twenty or 5% error in the power measurement. 6.6 6.7 TRANSFER FUNCTION Frequency Outputs F1 and F2 Counter Average Frequency = Average Power = Time Power Measurement Considerations 6.5 Figure 15. Effect of RCLKIN on Internal Oscillator Frequency (OSC) As shown, the frequency output CF is connected to an MCU counter or port. This will count the number of pulses in a given integration time, which is determined by an MCU internal timer. The average power proportional to the average frequency is given by Energy = Average Power x Time = 6.2 6.4 6.1 6.3 RESISTANCE - k The ADE7757 calculates the product of two voltage signals (on Channel V1 and Channel V2) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active low pulses. The pulse rate at these outputs is relatively low, e.g., 0.175 Hz maximum for ac signals with S0 = S1 = 0 (see Table II). This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation Freq = 515.84 x V 1rms x V 2rms x F1- 4 VREF 2 where Freq V1rms V2rms VREF F1-4 -12- = = = = = Output frequency on F1 and F2 (Hz). Differential rms voltage signal on Channel V1 (V). Differential rms voltage signal on Channel V2 (V). The reference voltage (2.5 V 8%) (V). One of four possible frequencies selected by using the logic inputs S0 and S1--see Table I. REV. A ADE7757 Table I. F1-4 Frequency Selection S1 S0 OSC Relation1 F1-4 at Nominal OSC (Hz)2 0 0 1 1 0 1 0 1 OSC/219 OSC/218 OSC/217 OSC/216 0.86 1.72 3.44 6.86 Table III. Maximum Output Frequency on CF SCF S1 S0 CF Max for AC Signals (Hz)* NOTES 1 F1-4 is a binary fraction of the internal oscillator frequency (OSC). 2 Values are generated using the nominal frequency of 450 kHz. 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 128 x F1, F2 = 22.4 64 x F1, F2 = 11.2 64 x F1, F2 = 22.4 32 x F1, F2 = 11.2 32 x F1, F2 = 22.4 16 x F1, F2 = 11.2 16 x F1, F2 = 22.4 2048 x F1, F2 = 2.867 kHz Example *Values are generated using the nominal frequency of 450 kHz. In this example, with ac voltages of 30 mV peak applied to V1 and 165 mV peak applied to V2, the expected output frequency is calculated as follows: F1-4 V1rms V2rms VREF = OSC/219 Hz, S0 = S1 = 0 = 0.03/2 V = 0.165/2 V = 2.5 V (nominal reference value) NOTE: If the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. Freq = 515.85 x 0.03 x 0.165 x F1 2 x 2 x 2.52 = 0.204 x F1 = 0.175 SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION As shown in Table I, the user can select one of four frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended for driving an energy register (electromechanical or others). Since only four different output frequencies can be selected, the available frequency selection has been optimized for a meter constant of 100 imp/kWh with a maximum current of between 10 A and 120 A. Table IV shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V. In all cases, the meter constant is 100 imp/kWh. Table II. Maximum Output Frequency on F1 and F2 Table IV. F1 and F2 Frequency at 100 imp/kWh S1 S0 OSC Relation Max Frequency* for AC Inputs (Hz) 0 0 1 1 0 1 0 1 0.204 x F1 0.204 x F2 0.204 x F3 0.204 x F4 0.175 0.35 0.70 1.40 *Values are generated using the nominal frequency of 450 kHz IMAX (A) F1 and F2 (Hz) 12.5 25.0 40.0 60.0 80.0 120.0 0.076 0.153 0.244 0.367 0.489 0.733 Frequency Output CF The pulse output CF (calibration frequency) is intended for calibration purposes. The output pulse rate on CF can be up to 2048 times the pulse rate on F1 and F2. The lower the F1-4 frequency selected, the higher the CF scaling (except for the high frequency mode SCF = 0, S1 = S0 = 1). Table III shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Due to its relatively high pulse rate, the frequency at CF logic output is proportional to the instantaneous real power. As with F1 and F2, CF is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Therefore, less averaging is carried out in the digital-to-frequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations (see the Signal Processing Block in Figure 3). REV. A The F1-4 frequencies allow complete coverage of this range of output frequencies (F1, F2). When designing an energy meter, the nominal design voltage on Channel V2 (voltage) should be set to half-scale to allow for calibration of the meter constant. The current channel should also be no more than half-scale when the meter sees maximum load. This will allow overcurrent signals and signals with high crest factors to be accommodated. Table V shows the output frequency on F1 and F2 when both analog inputs are half-scale. The frequencies listed in Table V align very well with those listed in Table IV for maximum load. -13- ADE7757 CF pulse width is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulse width is 25 ms. Table V. F1 and F2 Frequency with Half-Scale AC Inputs S1 S0 Frequency on F1 and F2- F1-4 (Hz)* CH1 and CH2 Half-Scale AC Input* 0 0 1 1 0 1 0 1 0.86 1.72 3.44 6.86 0.051 x F1 0.051 x F2 0.051 x F3 0.051 x F4 NOTE: When the high frequency mode is selected (i.e., SCF = 0, S1 = S0 = 1), the CF pulse width is fixed at 35 s. Therefore, t4 will always be 35 s, regardless of output frequency on CF. 0.044 Hz 0.088 Hz 0.176 Hz 0.352 Hz NO LOAD THRESHOLD *Values are generated using the nominal frequency of 450 kHz. When selecting a suitable F1-4 frequency for a meter design, the frequency output at IMAX (maximum load) with a meter constant of 100 imp/kWh should be compared with column four of Table V. The closest frequency in Table V will determine the best choice of frequency (F1-4). For example, if a meter with a maximum current of 25 A is being designed, the output frequency on F1 and F2 with a meter constant of 100 imp/kWh is 0.153 Hz at 25 A and 220 V (from Table IV). Looking at Table V, the closest frequency to 0.153 Hz in column four is 0.176 Hz. Therefore, F3 (3.44 Hz--see Table I) is selected for this design. Frequency Outputs Figure 1 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating low frequency pulses. The F1 and F2 pulse widths (t1) are set such that if they fall below 1062 ms (0.942 Hz) they are set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table II. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 173 ms wide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table III. As in the case of F1 and F2, if the period of CF (t5) falls below 346 ms, the The ADE7757 also includes a no-load threshold and start-up current feature that will eliminate any creep effects in the meter. The ADE7757 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2, or CF. The minimum output frequency is given as 0.0014% for each of the F1-4 frequency selections (see Table I). For example, for an energy meter with a meter constant of 100 imp/kWh on F1, F2 using F3 (3.44 Hz), the minimum output frequency at F1 or F2 would be 0.0014% of 3.44 Hz or 4.81 x 10-5 Hz. This would be 3.08 x 10-3 Hz at CF (64 x F1 Hz) when SCF = S0 = 1, S1 = 0. In this example, the no-load threshold would be equivalent to 1.7 W of load or a start-up current of 8 mA at 220 V. Compare this value to the IEC 1036 specification which states that the meter must start up with a load equal to or less than 0.4% Ib. For a 5 A (Ib) meter, 0.4% of Ib is equivalent to 20 mA. Negative Power Information The ADE7757 detects when the current and voltage channels have a phase shift greater than 90. This mechanism can detect wrong connection of the meter or generation of negative power. The REVP pin output will go active high when negative power is detected and active low if positive power is detected. The REVP pin output changes state as a pulse is issued on CF. The REVP pin is not functional in the current version and will only work in the A version (ADE7757A). -14- REV. A ADE7757 OUTLINE DIMENSIONS 16-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-16) Dimensions shown in millimeters and (inches) 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 16 9 1 8 1.27 (0.0500) BSC 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) 45 0.25 (0.0098) 8 0.51 (0.0201) SEATING 0.25 (0.0098) 0 1.27 (0.0500) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. A -15- ADE7757 Revision History Location Page 10/03--Data Sheet changed from REV. 0 to REV. A. Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to Typical Connection Diagrams section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 -16- REV. A C02898-0-10/03(A) Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1