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MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD
44165082, 44165182, 44165362
18M-BIT QDRTMII SRAM
2-WORD BURST OPERATION
Document No. M15824EJ7V0DS00 (7th edition)
Date Published February 2004 NS CP(K)
Printed in Japan
DATA SHEET
2001
Description
The
µ
PD44165082 is a 2,097,152-word by 8-bit, the
µ
PD44165182 is a 1,048,576-word by 18-bit and the
µ
PD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
µ
PD44165082,
µ
PD44165182 and
µ
PD44165362 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply and HSTL I/O
• DLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Two-tick burst for low DDR transaction size
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability with
µ
s restart
• User programmable impedance output
• Fast clock cycle time : 5.0 ns (200 MHz), 6.0 ns (167 MHz), 7.5 ns (133 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
2 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Ordering Information
Part number Cycle Clock Organization Core Supply I/O Package
Time Frequency (word x bit) Voltage Interface
ns MHz V
µ
PD44165082F5-E50-EQ1 5.0 200 2 M x 8-bit 1.8 ± 0.1 HSTL 165-pin PLASTIC
µ
PD44165082F5-E60-EQ1 6.0 167 BGA (13 x 15)
µ
PD44165082F5-E75-EQ1 7.5 133
µ
PD44165182F5-E50-EQ1 5.0 200 1 M x 18-bit
µ
PD44165182F5-E60-EQ1 6.0 167
µ
PD44165182F5-E75-EQ1 7.5 133
µ
PD44165362F5-E50-EQ1 5.0 200 512 K x 36-bit
µ
PD44165362F5-E60-EQ1 6.0 167
µ
PD44165362F5-E75-EQ1 7.5 133
3
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Pin Configurations
/××× indicates active low signal.
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
µ
µµ
µ
PD44165082F5-EQ1]
1 2 3 4 5 6 7 8 9 10 11
A /CQ VSS A /W /NW1 /K NC /R A VSS CQ
B NC NC NC A NC K /NW0 A NC NC Q3
C NC NC NC VSS A A A VSS NC NC D3
D NC D4 NC VSS VSS VSS VSS VSS NC NC NC
E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC
H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0
M NC NC NC VSS VSS VSS VSS VSS NC NC D0
N NC D7 NC VSS A A A VSS NC NC NC
P NC NC Q7 A A C A A NC NC NC
R TDO TCK A A A /C A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
D0 to D7 : Data inputs TDI : IEEE 1149.1 Test input
Q0 to Q7 : Data outputs TCK : IEEE 1149.1 Clock input
/R : Read input TDO : IEEE 1149.1 Test output
/W : Write input VREF : HSTL input reference input
/NW0, /NW1 : Nibble Write data select VDD : Power Supply
K, /K : Input clock VDDQ : Power Supply
C, /C : Output clock VSS : Ground
CQ, /CQ : Echo clock NC : No connection
ZQ : Output impedance matching
/DLL : DLL disable
Remark Refer to Package Drawing for the index mark.
4 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
µ
µµ
µ
PD44165182F5-EQ1]
1 2 3 4 5 6 7 8 9 10 11
A /CQ VSS NC /W /BW1 /K NC /R A VSS CQ
B NC Q9 D9 A NC K /BW0 A NC NC Q8
C NC NC D10 VSS A A A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDO TCK A A A /C A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
D0 to D17 : Data inputs TDI : IEEE 1149.1 Test input
Q0 to Q17 : Data outputs TCK : IEEE 1149.1 Clock input
/R : Read input TDO : IEEE 1149.1 Test output
/W : Write input VREF : HSTL input reference input
/BW0, /BW1 : Byte Write data select VDD : Power Supply
K, /K : Input clock VDDQ : Power Supply
C, /C : Output clock VSS : Ground
CQ, /CQ : Echo clock NC : No connection
ZQ : Output impedance matching
/DLL : DLL disable
Remark Refer to Package Drawing for the index mark.
5
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
µ
µµ
µ
PD44165362F5-EQ1]
1 2 3 4 5 6 7 8 9 10 11
A /CQ VSS NC /W /BW2 /K /BW1 /R NC VSS CQ
B Q27 Q18 D18 A /BW3 K /BW0 A D17 Q17 Q8
C D27 Q28 D19 VSS A A A VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS A A A VSS Q10 D9 D1
P Q35 D35 Q26 A A C A A Q9 D0 Q0
R TDO TCK A A A /C A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
D0 to D35 : Data inputs TDI : IEEE 1149.1 Test input
Q0 to Q35 : Data outputs TCK : IEEE 1149.1 Clock input
/R : Read input TDO : IEEE 1149.1 Test output
/W : Write input VREF : HSTL input reference input
/BW0 to /BW3 : Byte Write data select VDD : Power Supply
K, /K : Input clock VDDQ : Power Supply
C, /C : Output clock VSS : Ground
CQ, /CQ : Echo clock NC : No connection
ZQ : Output impedance matching
/DLL : DLL disable
Remark Refer to Package Drawing for the index mark.
6 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Pin Identification
Symbol Description
A Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for
WRITE cycles. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future
devices. All transactions operate on a burst of two words (one clock period of bus activity). These inputs are
ignored when device is deselected.
D0 to Dxx Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K
during WRITE operations. See Pin Configurations for ball site location of individual signals.
x8 device uses D0 to D7.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Q0 to Qxx Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges
if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
/R Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be
initiated. This input must meet setup and hold times around the rising edge of K.
/W Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be
initiated. This input must meet setup and hold times around the rising edge of K.
/BWx
/NWx
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
K, /K Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous
inputs must meet setup and hold times around the clock rising edges.
C, /C Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
/C is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to
force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied
HIGH, C and /C must remain HIGH and not be toggled during device operation.
CQ, /CQ Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates.
ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. This pin cannot be connected directly to GND or left unconnected. Also, in this product, there is no
function to minimize the output impedance by connecting ZQ directly to VDDQ.
/DLL DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO IEEE 1149.1 Test Output: 1.8V I/O level.
VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
VDD Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.
VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics
and Operating Conditions for range.
VSS Power Supply: Ground
NC No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level
applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.
7
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Block Diagrams
[
µ
µµ
µ
PD44165082]
/W
/NW0
/NW1
/R
K
/K K
/R
/W
K
ADDRESS 20
D0 to D7 Q0 to Q7
MUX
OUTPUT
REGISTER
/K
K
DATA
REGISTRY
& LOGIC
2
20
x 16
MEMORY
ARRAY
WRITE
DRIVER
SENSE
AMPS
OUTPUT
SELECT
OUTPUT
BUFFER
20
ADDRESS
REGISTRY
& LOGIC
WRITE
REGISTER
C, /C
OR
K, /K
CQ,
/CQ
816 16 16 8
2
[
µ
µµ
µ
PD44165182]
/W
/BW0
/BW1
/R
K
/K K
/R
/W
K
ADDRESS 19
D0 to D17 Q0 to Q17
MUX
OUTPUT
REGISTER
/K
K
DATA
REGISTRY
& LOGIC
2
19
x 36
MEMORY
ARRAY
WRITE
DRIVER
SENSE
AMPS
OUTPUT
SELECT
OUTPUT
BUFFER
19
ADDRESS
REGISTRY
& LOGIC
WRITE
REGISTER
C, /C
OR
K, /K
CQ,
/CQ
18 36 36 36 18
2
[
µ
µµ
µ
PD44165362]
/W
/BW0
/BW1
/R
K
/K K
/R
/W
K
ADDRESS 18
D0 to D35 Q0 to Q35
MUX
OUTPUT
REGISTER
/K
K
DATA
REGISTRY
& LOGIC
2
18
x 72
MEMORY
ARRAY
WRITE
DRIVER
SENSE
AMPS
OUTPUT
SELECT
OUTPUT
BUFFER
18
ADDRESS
REGISTRY
& LOGIC
WRITE
REGISTER
C, /C
OR
K, /K
CQ,
/CQ
36
72 72 72 36
2
/BW2
/BW3
8 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Truth Table
Operation CLK /R /W D or Q
WRITE cycle L → H X L Data in
Load address, input write data on Input data DA (A+0) DA (A+1)
consecutive K and /K rising edge Input clock K( t ) ↑ /K( t ) ↑
READ cycle L → H L X Data out
Load address, output data on Output data QA (A+0) QA (A+1)
consecutive C and /C rising edge Output clock /C(t+1) ↑ C(t+2) ↑
NOP (No operation) L → H H H D=X or Q=High-Z
STANDBY(Clock stopped) Stopped X X Previous state
Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
9
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Byte Write Operation
[
µ
µµ
µ
PD44165082]
Operation K /K /NW0 /NW1
Write D0 to D7 L → H – 0 0
– L → H 0 0
Write D0 to D3 L → H – 0 1
– L → H 0 1
Write D4 to D7 L → H – 1 0
– L → H 1 0
Write nothing L → H – 1 1
– L → H 1 1
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[
µ
µµ
µ
PD44165182]
Operation K /K /BW0 /BW1
Write D0 to D17 L → H – 0 0
– L → H 0 0
Write D0 to D8 L → H – 0 1
– L → H 0 1
Write D9 to D17 L → H – 1 0
– L → H 1 0
Write nothing L → H – 1 1
– L → H 1 1
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[
µ
µµ
µ
PD44165362]
Operation K /K /BW0 /BW1 /BW2 /BW3
Write D0 to D35 L → H – 0 0 0 0
– L → H 0 0 0 0
Write D0 to D8 L → H – 0 1 1 1
– L → H 0 1 1 1
Write D9 to D17 L → H – 1 0 1 1
– L → H 1 0 1 1
Write D18 to D26 L → H – 1 1 0 1
– L → H 1 1 0 1
Write D27 to D35 L → H – 1 1 1 0
– L → H 1 1 1 0
Write nothing L → H – 1 1 1 1
– L → H 1 1 1 1
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
10 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Bus Cycle State Diagram
READ DOUBLE
WRITE DOUBLE
AT /K
Power UP
Always
Supply voltage
provided
LOAD NEW
READ ADDRESS
READ PORT NOP
R_Init = 0
WRITE PORT NOP
LOAD NEW
WRITE ADDRESS
AT /K
Always /W = L
Supply voltage
provided
/W = L
/W = H
/W = H
/R = L
/R = L
/R = H
/R = H
Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
11
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply voltage VDD –0.5 +2.9 V
Output supply voltage VDDQ –0.5 VDD V
Input voltage VIN –0.5 VDD + 0.5 (2.9 V MAX.) V
Input / Output voltage VI/O –0.5 VDDQ + 0.5 (2.9 V MAX.) V
Operating ambient temperature TA 0 70 °C
Storage temperature Tstg –55 +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Supply voltage VDD 1.7 1.9 V
Output supply voltage VDDQ 1.4 VDD V 1
High level input voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 1, 2
Low level input voltage VIL (DC) –0.3 VREF – 0.1 V 1, 2
Clock input voltage VIN –0.3 VDDQ + 0.3 V 1, 2
Reference voltage VREF 0.68 0.95 V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
High level input voltage VIH (AC) VREF + 0.2 – V 1
Low level input voltage VIL (AC) – VREF – 0.2 V 1
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
12 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter Symbol Test condition MIN. TYP. MAX. Unit Note
x8, x18 x36
Input leakage current ILI –2 – +2
µ
A
I/O leakage current ILO –2 – +2
µ
A
Operating supply current IDD VIN ≤ VIL or VIN ≥ VIH, –E50 610 700 mA
(Read Write cycle) II/O = 0 mA –E60 530 600
Cycle = MAX. –E75 470 530
Standby supply current ISB1 VIN ≤ VIL or VIN ≥ VIH, –E50 270 mA
(NOP) II/O = 0 mA –E60 250
Cycle = MAX. –E75 230
High level output voltage VOH(Low) |IOH| ≤ 0.1 mA VDDQ – 0.2 – VDDQ V 3,4
VOH Note1 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 3,4
Low level output voltage VOL(Low) IOL ≤ 0.1 mA VSS – 0.2 V 3,4
VOL Note2 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 3,4
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Capacitance (TA = 25 °
°°
°C, f = 1MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input capacitance(Address, Control) CIN VIN = 0 V 4 5 pF
Input / Output capacitance(D, Q) CI/O VI/O = 0 V 6 7 pF
Clock Input capacitance Cclk Vclk = 0 V 5 6 pF
Remark These parameters are periodically sampled and not 100% tested.
13
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
AC Characteristics (TA = 0 to 70 °
°°
°C, VDD = 1.8 ± 0.1 V)
AC Test Conditions
Input waveform (Rise / Fall time ≤
≤≤
≤ 0.3 ns)
0.75 V 0.75 V
Test Points
1.25 V
0.25 V
Output waveform
V
DD
Q / 2 V
DD
Q / 2
Test Points
Output load condition
Figure 1. External load at test
V
DD
Q / 2
0.75 V 50 Ω
Z
O
= 50 Ω
250 Ω
SRAM
V
REF
ZQ
14 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Read and Write Cycle
Parameter Symbol
-E50 -E60 -E75
Unit Note
(200 MHz) (167 MHz) (133 MHz)
MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time (K, /K, C, /C) TKHKH 5.0 8.4 6.0 8.4 7.5 8.4 ns 1
Clock phase jitter (K, /K, C, /C) TKC var – 0.2 – 0.2 – 0.2 ns 2
Clock HIGH time (K, /K, C, /C) TKHKL 2.0 – 2.4 – 3.0 – ns
Clock LOW time (K, /K, C, /C) TKLKH 2.0 – 2.4 – 3.0 – ns
Clock to /clock (K→/K., C→/C.) TKH /KH 2.2 – 2.7 – 3.38 – ns
Clock to /clock (/K→K., /C→C.) T /KHKH 2.2 – 2.7 – 3.38 – ns
Clock to data clock 167 to 200 MHz TKHCH 0 2.3 – – – – ns
(K→C., /K→/C.) 133 to 167 MHz 0 2.8 0 2.8 – –
< 133 MHz 0 3.55 0 3.55 0 3.55
DLL lock time (K, C) TKC lock 1,024 – 1,024 – 1,024 – Cycle 3
K static to DLL reset TKC reset 30 – 30 – 30 – ns
Output Times
C, /C HIGH to output valid TCHQV – 0.45 – 0.5 – 0.5 ns
C, /C HIGH to output hold TCHQX –0.45 – –0.5 – –0.5 – ns
C, /C HIGH to echo clock valid TCHCQV – 0.45 – 0.5 – 0.5 ns
C, /C HIGH to echo clock hold TCHCQX –0.45 – –0.5 – –0.5 – ns
CQ, /CQ HIGH to output valid TCQHQV – 0.35 – 0.4 – 0.4 ns 4
CQ, /CQ HIGH to output hold TCQHQX –0.35 – –0.4 – –0.4 – ns 4
C HIGH to output High-Z TCHQZ – 0.45 – 0.5 – 0.5 ns
C HIGH to output Low-Z TCHQX1 –0.45 – –0.5 – –0.5 – ns
Setup Times
Address valid to K rising edge TAVKH 0.4 – 0.5 – 0.5 – ns 5
Control inputs (/R, /W) valid to K rising TIVKH 0.4 – 0.5 – 0.5 – ns 5
edge
Data inputs and write data select TDVKH 0.4 – 0.5 – 0.5 – ns 5
inputs (/BWx, /NWx) valid to K, /K
rising edge
Hold Times
K rising edge to address hold TKHAX 0.4 – 0.5 – 0.5 – ns 5
K rising edge to control inputs (/R, /W) TKHIX 0.4 – 0.5 – 0.5 – ns 5
hold
K, /K rising edge to data inputs and TKHDX 0.4 – 0.5 – 0.5 – ns 5
write data select inputs (/BWx, /NWx)
hold
15
Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3. V
DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5. VDDQ is 1.5 V DC.
16 Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
Read and Write Timing
K
Address
Data in
/K
24681013579
TKH/KH T/KHKH
C
/C
TKHCH
NOPREAD READ READ WRITEWRITE WRITE
TKHKL TKLKH
Q00 Q20
Data out
Q01 Q21 Q41Q40
/R
/W
A1 A3A2 A4 A6A5A0
D11 D31D30 D50 D61D51D10 D60
TKHKL TKLKH TKH/KH T/KHKH
TKHKH
TCHQX1
TCHQV
TCHQX TCHQX
TCHQZ
TDVKH TKHDX TDVKH TKHDX
TKHKH
TIVKH TKHIX
TAVKH TKHAX TAVKH TKHAX
NOPWRITE
CQ
/CQ
TCQHQV
TCHQV
TCHCQV
TCHCQX
TCHCQV
TKHCH
TCHCQX
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disable (high impedance) one clock cycle after a NOP.
3. In this example, if address A0=A1, data Q00=D10, Q01=D11.
Write data is forwarded immediately as read results.
17
Data Sheet M15824EJ7V0DS
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µµ
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PD44165082, 44165182, 44165362
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name Pin assignments Description
TCK 2R Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS 10R Test Mode Select. This is the command input for the TAP controller state machine.
TDI 11R Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the
output side of the serial registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD –5.0 – +5.0
µ
A
JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDDQ , –5.0 – +5.0
µ
A
Outputs disabled
JTAG input high voltage VIH 1.3 – VDD + 0.3 V
JTAG input low voltage VIL –0.3 – +0.5 V
JTAG output high voltage VOH1 | IOHC | = 100
µ
A 1.6 – – V
VOH2 | IOHT | = 2 mA 1.4 – – V
JTAG output low voltage VOL1 IOLC = 100
µ
A – – 0.2 V
VOL2 IOLT = 2 mA – – 0.4 V
18 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤
≤≤
≤ 1 ns)
0.9 V 0.9 V
Test Points
1.8 V
0 V
Output waveform
0.9 V 0.9 V
Test Points
Output load
Figure 2. External load at test
TDO Z
O
= 50 Ω
V
TT
= 0.9 V
20 pF
50 Ω
19
Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
JTAG AC Characteristics (TA = 0 to 70 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Clock
Clock cycle time tTHTH 100 – – ns
Clock frequency fTF – – 10 MHz
Clock high time tTHTL 40 – – ns
Clock low time tTLTH 40 – – ns
Output time
TCK low to TDO unknown tTLOX 0 – – ns
TCK low to TDO valid tTLOV – – 20 ns
TDI valid to TCK high tDVTH 10 – – ns
TCK high to TDI invalid tTHDX 10 – – ns
Setup time
TMS setup time tMVTH 10 – – ns
Capture setup time tCS 10 – – ns
Hold time
TMS hold time tTHMX 10 – – ns
Capture hold time tCH 10 – – ns
JTAG Timing Diagram
t
THTH
t
TLOV
t
TLTH
t
THTL
t
MVTH
t
THDX
t
DVTH
t
THMX
TCK
TMS
TDI
TDO
t
TLOX
20 Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
Scan Register Definition (1)
Register name Description
Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name Bit size Unit
Instruction register 3 bit
Bypass register 1 bit
ID register 32 bit
Boundary register 107 bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit
µ
PD44165082 2M x 8 XXXX 0000 0000 0000 1100 00000010000 1
µ
PD44165182 1M x 18 XXXX 0000 0000 0000 1101 00000010000 1
µ
PD44165362 512K x 36 XXXX 0000 0000 0000 1110 00000010000 1
21
Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
SCAN Exit Order
Bit Signal name Bump Bit Signal name Bump Bit Signal name Bump
no. x8 x18 x36 ID no. x8 x18 x36 ID no. x8 x18 x36 ID
1 /C 6R 37 NC NC D15 10D 73 NC NC Q28 2C
2 C 6P 38 NC NC Q15 9E 74 Q4 Q11 Q20 3E
3 A 6N 39 NC Q7 Q7 10C 75 D4 D11 D20 2D
4 A 7P 40 NC D7 D7 11D 76 NC NC D29 2E
5 A 7N 41 NC NC D16 9C 77 NC NC Q29 1E
6 A 7R 42 NC NC Q16 9D 78 NC Q12 Q21 2F
7 A 8R 43 Q3 Q8 Q8 11B 79 NC D12 D21 3F
8 A 8P 44 D3 D8 D8 11C 80 NC NC D30 1G
9 A 9R 45 NC NC D17 9B 81 NC NC Q30 1F
10 NC Q0 Q0 11P 46 NC NC Q17 10B 82 Q5 Q13 Q22 3G
11 NC D0 D0 10P 47 CQ 11A 83 D5 D13 D22 2G
12 NC NC D9 10N 48 – Internal 84 NC NC D31 1J
13 NC NC Q9 9P 49 A A NC 9A 85 NC NC Q31 2J
14 NC Q1 Q1 10M 50 A 8B 86 NC Q14 Q23 3K
15 NC D1 D1 11N 51 A 7C 87 NC D14 D23 3J
16 NC NC D10 9M 52 A 6C 88 NC NC D32 2K
17 NC NC Q10 9N 53 /R 8A 89 NC NC Q32 1K
18 Q0 Q2 Q2 11L 54 NC NC /BW1 7A 90 Q6 Q15 Q24 2L
19 D0 D2 D2 11M 55 /NW0 /BW0 /BW0 7B 91 D6 D15 D24 3L
20 NC NC D11 9L 56 K 6B 92 NC NC D33 1M
21 NC NC Q11 10L 57 /K 6A 93 NC NC Q33 1L
22 NC Q3 Q3 11K 58 NC NC /BW3 5B 94 NC Q16 Q25 3N
23 NC D3 D3 10K 59 /NW1 /BW1 /BW2 5A 95 NC D16 D25 3M
24 NC NC D12 9J 60 /W 4A 96 NC NC D34 1N
25 NC NC Q12 9K 61 A 5C 97 NC NC Q34 2M
26 Q1 Q4 Q4 10J 62 A 4B 98 Q7 Q17 Q26 3P
27 D1 D4 D4 11J 63 A NC NC 3A 99 D7 D17 D26 2N
28 ZQ 11H 64 /DLL 1H 100 NC NC D35 2P
29 NC NC D13 10G 65 /CQ 1A 101 NC NC Q35 1P
30 NC NC Q13 9G 66 NC Q9 Q18 2B 102 A 3R
31 NC Q5 Q5 11F 67 NC D9 D18 3B 103 A 4R
32 NC D5 D5 11G 68 NC NC D27 1C 104 A 4P
33 NC NC D14 9F 69 NC NC Q27 1B 105 A 5P
34 NC NC Q14 10F 70 NC Q10 Q19 3D 106 A 5N
35 Q2 Q6 Q6 11E 71 NC D10 D19 3C 107 A 5R
36 D2 D6 D6 10E 72 NC NC D28 1D
22 Data Sheet M15824EJ7V0DS
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µµ
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PD44165082, 44165182, 44165362
JTAG Instructions
Instructions Description
EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output driver is turned on and the PRELOAD data is driven onto the output pins.
IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR
state loads the data in the RAMs input and Q pins into the boundary scan register. Because the RAM
clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the
I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing
the TAP to sample metastable input will not harm the device, repeatable results cannot be expected.
RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus
hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except
capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state
then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an inactive
drive state (high impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2 IR1 IR0 Instruction Note
0 0 0 EXTEST
0 0 1 IDCODE
0 1 0 SAMPLE-Z 1
0 1 1 RESERVED
1 0 0 SAMPLE / PRELOAD
1 0 1 RESERVED
1 1 0 RESERVED
1 1 1 BYPASS
Note 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
23
Data Sheet M15824EJ7V0DS
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PD44165082, 44165182, 44165362
TAP Controller State Diagram
Test-Logic-Reset
Run-Test / Idle Select-DR-Scan
Capture-DR Capture-IR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Select-IR-Scan
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
10 10
11 1
0
1
1
0
1
0
11
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.
TDO should be left unconnected.
24 Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
Test Logic Operation (Instruction Scan)
TCK
Contoroller
state
TDI
TMS
TDO
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Shift-IR
Exit1-IR
Update-IR
Run-Test/Idle
IDCODE
Instruction
Register state New Instruction
Output Inactive
25
Data Sheet M15824EJ7V0DS
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PD44165082, 44165182, 44165362
Test Logic (Data Scan)
Controller
state
TDI
TMS
TDO
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Shift-DR
Exit1-DR
Update-DR
Test-Logic-Reset
Instruction
Instructin
Register state IDCODE
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Output Inactive
TCK
26 Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
Package Drawing
165-PIN PLASTIC BGA (13x15)
ITEM DIMENSIONS
D
E
w
e
A
A1
A2
13.00±0.10
15.00±0.10
0.15
0.40±0.05
1.00
1.40±0.11
1.00
0.50±0.05
(UNIT:mm)
0.08
0.10
0.20
1.50
0.50
P165F5-100-EQ1
x
y
y1
ZD
ZE
b
A
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK
ZE
ZD B
SwB
E
SwA
D
S
y
S
A
A2
A1
e
y1 S
SxbA
B
M
φφ
RPMMLKJHGFEDCBA
27
Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
µ
PD44165082F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
µ
PD44165182F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
µ
PD44165362F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
28 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
7th edition/ p.12 p.12 Modification DC Characteristics IDD (MAX.)
Feb. 2004
MAX. Unit MAX. Unit
x8, x18 x36 x8, x18 x36
-E50 560 670 mA -E50 610 700 mA
-E60 480 570 -E60 530 600
-E75 420 500 -E75 470 530
DC Characteristics ISB1 (MAX.)
MAX. Unit MAX. Unit
x8, x18 x36 x8, x18 x36
-E50 210 mA -E50 270 mA
-E60 190 -E60 250
-E75 170 -E75 230
p.26 p.26 Modification Package Drawing Preliminary version → Standardized version
29
Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
[MEMO]
30 Data Sheet M15824EJ7V0DS
µ
µµ
µ
PD44165082, 44165182, 44165362
[MEMO]
31
Data Sheet M15824EJ7V0DS
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µµ
µ
PD44165082, 44165182, 44165362
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dr y, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transpor ted in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
NOTES FOR CMOS DEVICES
µ
µµ
µ
PD44165082, 44165182, 44165362
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor,
Renesas, IDT, Micron Technology, Inc., NEC Electronics, and Samsung.
The information in this document is current as of February, 2004. The information is
subject to change without notice. For actual design-in, refer to the latest publications of
NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of
NEC Electronics products. Not all products and/or types are available in every country.
Please check with an NEC Electronics sales representative for availability and additional
information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
