DEMO MANUAL DC1532 LTC2268-14/-12, LTC2267-14/-12, LTC2266-14/-12, LTC2265-14/-12, LTC2264-14/-12, LTC2263-14/-12 12-/14-Bit, 25Msps to 125Msps Dual ADCs Description Demonstration circuit 1532 supports a family of 14-/12bit 25Msps to 125Msps ADCs. Each assembly features one of the following devices: LTC2268-14, LTC2268-12, LTC2267-14, LTC2267-12, LTC2266-14, LTC2266-12, LTC2265-14, LTC2265-12, LTC2264-14, LTC2264-12, LTC2263-14, LTC2263-12 high speed, dual ADCs. The versions of the 1532A demo board are listed in Table 1. Depending on the required resolution and sample rate, Performance Summary the DC1532 is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 140MHz. Refer to the data sheet for proper input networks for different input frequencies. Design files for this circuit board are available at http://www.linear.com/demo L, LT, LTC, LTM, Module, Linear Technology and the Linear logo are registered trademarks and QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. (TA = 25C) PARAMETER CONDITIONS VALUE Supply Voltage - DC1532A Depending on Sampling Rate and the A/D Converter Provided, this Supply Must Provide up to 500mA. Optimized for 3V [3V 6.0V Min/Max] Analog Input Range Depending on SENSE Pin Voltage 1VP-P to 2VP-P Logic Input Voltages Minimum Logic High 1.3V Maximum Logic Low 0.6V Nominal Logic Levels (100 Load, 3.5mA Mode) 350mV/1.25V Common Mode Minimum Logic Levels (100 Load, 3.5mA Mode) 247mV/1.25V Common Mode Logic Output Voltages (Differential) Sampling Frequency (Convert Clock Frequency) See Table 1 Encode Clock Level Single-Ended Encode Mode (ENC - Tied to GND) 0V to 3.6V Encode Clock Level Differential Encode Mode (ENC - Not Tied to GND) 0.2V to 3.6V Resolution See Table 1 Input Frequency Range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet dc1532f 1 DEMO MANUAL DC1532 Quick Start Procedure Table 1. DC1532 Variants DC1532 VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY 1532A-A LTC2268-14 14-Bit 125Msps 5MHz to 140MHz 1532A-B LTC2267-14 14-Bit 105Msps 5MHz to 140MHz 1532A-C LTC2266-14 14-Bit 80Msps 5MHz to 140MHz 1532A-D LTC2265-14 14-Bit 65Msps 5MHz to 140MHz 1532A-E LTC2264-14 14-Bit 40Msps 5MHz to 140MHz 1532A-F LTC2263-14 14-Bit 25Msps 5MHz to 140MHz 1532A-G LTC2268-12 12-Bit 125Msps 5MHz to 140MHz 1532A-H LTC2267-12 12-Bit 105Msps 5MHz to 140MHz 1532A-I LTC2266-12 12-Bit 80Msps 5MHz to 140MHz 1532A-J LTC2265-12 12-Bit 65Msps 5MHz to 140MHz 1532A-K LTC2264-12 12-Bit 40Msps 5MHz to 140MHz 1532A-L LTC2263-12 12-Bit 25Msps 5MHz to 140MHz Demonstration circuit 1532 is easy to set up to evaluate the performance of the LTC2268 A/D converters. Refer to Figure 1 for proper measurement equipment setup and follow the procedure: J8: Term: Enables/Disable optional output termination. (Default - Removed) Setup J14: LANE: Selects either 1 lane or 2 lane output modes (Default - Removed) NOTE: The DC1371 does not support 1 lane operation. If a DC1371 QuikEvalTM II Data Acquisition and Collection System was supplied with the DC1532 demonstration circuit, follow the DC1371 Quick Start Guide to install the required software and for connecting the DC1371 to the DC1532 and to a PC. DC1532 Demonstration Circuit Board Jumpers The DC1532 demonstration circuit board should have the following jumper settings as default positions: (as per Figure 1) J5: ILVDS: Selects either 1.75mA or 3.5mA of output current for the LVDS drivers. (Default - Removed) J15: SHDN: Enables and disables the LTC2268. (Default - Removed) J2: WP: Enable/Disables write protect for the EEPROM. (Default - Removed) Note: Optional jumper should be left open to ensure proper serial configuration. J13: PAR/SER: Selects Parallel or Serial programming mode. (Default - Serial) Optional Jumpers: dc1532f 2 DEMO MANUAL DC1532 quick start procedure 3.5V TO 6V TO PROVIDED POWER SUPPLY + ANALOG INPUTS N N CHANNEL 1 TO PROVIDED USB CABLE CHANNEL 2 PARALLEL/SERIAL SINGLE-ENDED ENCODE CLOCK (USE PROVIDED DC1075, DIVIDE BY 4 CLOCK BOARD) Figure 1. DC1532A Setup Applying Power And Signals to the DC1532 Demonstration Circuit The DC1371 is used to acquire data from the DC1532, the DC1371 must FIRST be connected to a powered USB port and have 5V applied power BEFORE applying 3.6V to 6.0V across the pins marked V+ and GND on the DC1532. DC1532 requires 3.6V for proper operation. Regulators on the board produce the voltages required for the ADC. The DC1532 demonstration circuit requires up to 500mA depending on the sampling rate and the A/D converter supplied. The DC1532 should not be removed, or connected to the DC1371 while power is applied. Analog Input Network For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequencies above 140MHz, refer to the LTC2268 datasheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz. In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50 outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion. dc1532f 3 DEMO MANUAL DC1532 quick start procedure If your generator cannot deliver full scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide Gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and High IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit. Apply the analog input signal of interest to the SMA connectors on the DC1532 demonstration circuit board marked J3 AIN1, J4 AIN2, J6 AIN3, J7 AIN4. These inputs correspond with channels 1-4 of the ADC respectively. These inputs are capacitive coupled to balun transformers ETC1-1-13. Encode Clock NOTE: Apply an encode clock to the SMA connector on the DC1532 demonstration circuit board marked J11 CLK+. As a default the DC1532 is populated to have a single-ended input. For the best noise performance, the ENCODE INPUT must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VP-P or 13dBm. When using a sinusoidal signal generator a squaring circuit can be used. Linear Technology also provides demo board DC1075A that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2268. Using bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1532 a bandpass filter used for the clock should be used prior to the DC1075A. Data sheet FFT plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non harmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used for both the Clock input and the Analog input. Digital Outputs Data outputs. data clock, and frame clock signals are available on J1 of the DC1532. This connector follows the VITA-57/FMC standard, but all signals should be verified when using an FMC carrier card other than the DC1371. Software The DC1371 is controlled by the PScopeTM System Software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. To start the data collection software if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double click the PScope Icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. If the DC1532 demonstration circuit is properly connected to the DC1371, PScope should automatically detect the DC1532, and configure itself accordingly. If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC1371A Quick Start Guide and in the online help available within the PScope program itself. dc1532f 4 DEMO MANUAL DC1532 quick start procedure Serial Programming PScope has the ability to program the DC1532 board serially through the DC1371. There are several options available in the LTC2268 family that are only available through serially programming. PScope allows all of these features to be tested. These options are available by first clicking on the Set Demo Board Options icon on the PScope toolbar (Figure 3). This menu allows any of the options available for the LTC2268 family to be programmed serially. The LTC2268 family has the following options: Randomizer: Enables Data Output Randomizer * Off (Default): Disables data output randomizer * On: Enables data output randomizer Two's complement: Enables two's complement mode * Off (Default): Selects offset binary mode * On: Selects two's complement mode Sleep Mode: Selects between normal operation, sleep mode Figure 3. PScope Toolbar This will bring up the menu shown in Figure 4. * Off (Default): Entire ADC is powered, and active * On: The entire ADC is powered down Channel 1 Nap: Selects between normal operation and putting channel 1 in nap mode * Off (Default): Channel one is active * On: Channel one is in nap mode Channel 2 Nap: Selects between normal operation and putting channel 2 in nap mode * Off (Default): Channel two is active * On: Channel two is in nap mode Output Current: Selects the LVDS output drive current * 1.75mA (Default): LVDS output driver current * 2.1mA: LVDS output driver current * 2.5mA: LVDS output driver current * 3.0mA: LVDS output driver current * 3.5mA: LVDS output driver current * 4.0mA: LVDS output driver current * 4.5mA: LVDS output driver current Figure 4: Demo Board Configuration Options dc1532f 5 DEMO MANUAL DC1532 quick start procedure Internal Termination: Enables LVDS internal termination * Off (Default): Disables internal termination * On: Enables internal termination Outputs: Enables Digital Outputs * Enabled (Default): Enables digital outputs * Disabled: Disables digital outputs Test Pattern: Selects Digital output test patterns. The desired test pattern can be entered into the text boxes provided * Off (default): ADC input data is displayed * On: Test pattern is displayed Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1532 demo board dc1532f 6 DEMO MANUAL DC1532 Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 1 2 C1, C17 CAP., X5R, 2.2F, 10V, 20%, 0603 AVX, 0603ZD225MAT2A 2 17 C2, C3, C5, C7-C9, C15, C16, C18, C28-C30, C36, C38, C48, C52, C59 CAP., X5R, 0.1F, 10V, 10%, 0402 AVX, 0402ZD104KAQ2A 3 1 C4 CAP., X5R, 1F, 10V, 10%, 0402 AVX, 0402ZC105KAT2A 4 1 C6 CAP., TANT, 100F, 10%, 6032 AVX, TAJW107K010R 5 3 C10, C53, C54 CAP., X7R, 1F, 10V, 10%, 0603 AVX, 0603ZC105KAT2A 6 4 C25, C26, C33, C34 CAP., X7R, 0.01F, 50V, 10%, 0603 AVX, 06035C103KAQ2A 7 0 R2, C27, C35, R42, R43, C49, C50, R56, R57, R58, R59, R60, R64, R100 OPT 0402 8 4 C31, C32, C39, C40 CAP., C0G, 8.2pF, 50V, 5%, 0402 AVX, 04025A8R2JAT2A 9 3 C43, C44, C45 CAP., X7R, 0.01F, 16V, 10%, 0402 AVX, 0402YC103KAQ2A 10 1 C51 CAP., X5R, 4.7F, 6.3V, 20%, 0603 AVX, 06036D475MAT2A 11 1 D1 DIODE SCHOTTKY RF SER 15V, SOT-23 AVAGO, HSMS-2822-TR1G 12 1 J1 BGA Connector 40 x 10 SAMTEC, SEAM-40-02.0-S-10-2-A 13 6 J2, J5, J8, J13, J14, J15 HEADER, 3-Pin, 0.079 Single Row SAMTEC, TMM-103-02-L-S 14 6 XJ2, XJ5, XJ8, XJ13, XJ14, XJ15 Shunt, .079" Center SAMTEC, 2SN-BK-G 15 0 J10, OPT Header, 2x7PIN, 0.079CC MOLEX, 87831-1420 16 2 J4, J3 CON., SMA 50 EDGE-LANCH E.F. JOHNSON, 142-0701-851 17 2 J12, J11 CON., SMA 50 Straight Mount Connex., 132134 18 2 L4, L5 Inductor, 56nH, 0603 Murata, LQP18MN56NG02D 19 0 L7, L8 OPT 20 2 L11, L9 Ferrite Bead, 1206 Murata, BLM31PG330SN1L 21 8 R1, C46, C47, R61, R62, R63, R65, R101 RES., CHIP, 0, 0402 VISHAY, CRCW04020000Z0ED 22 1 RN1 RES., 2 x 4 Array, CHIP, 33 ,ISO VISHAY, CRA06E08333R0JTA 23 12 R4, R5, R10, R36 RES., CHIP, 10k, 1/16W, 5%, 0402 VISHAY, CRCW040210K0JNED 24 R102-R109 25 9 R8, R30, R47, R92, R95-R99 RES., CHIP, 100, 1/16W, 5%, 0402 VISHAY, CRCW0402100RJNED 26 6 R9, R11, R14, R72, R73, R74 RES., CHIP, 1k, 1/16W, 5%, 0402 VISHAY, CRCW04021K00JNED 27 1 R12 RES., CHIP, 31.6k, 1/16W, 1%, 0402 VISHAY, CRCW040231K6FKED 28 4 R26, R29, R39, R46 RES., CHIP, 33.2, 1/16W, 1%, 0402 VISHAY, CRCW040233R2FKED 29 2 R35, R52 RES., CHIP, 86.6, 1/16W, 1%, 0402 VISHAY, CRCW040286R6FKED 30 4 R37, R38, R53, R54 RES., CHIP, 86.6, 1/16W, 1%, 0603 VISHAY, CRCW060386R6FNEA 31 2 R40, R41 RES., CHIP, 49.9, 1/16W, 1%, 0402 VISHAY, CRCW040249R9FKED 32 8 R110-R117 RES., CHIP, 33k, 1/16W, 1%, 0402 VISHAY, CRCW040233K0FKED 33 3 TP1, TP6, TP7 Testpoint, Turret, .094" pbf MILL-MAX, 2501-2-00-80-00-00-07-0 34 3 T5, T9, T11 Transformer, MABA-007159-000000 M/A-COM, MABA-007159-000000 35 2 T10, T8 Transformer, MABAES0060 M/A-COM, MABAES0060 36 1 U2 I.C. LT1763CS8-1.8, SO8 LINEAR, LT1763CS8-1.8#TRPBF 37 1 U3 I.C., Serial EEPROM TSSOP-8 MICROCHIP, 24LC32A-I/ST dc1532f 7 A B C CLK- CLK+ J12 J3 TP7 TP6 J11 AIN1 GND V+ 3V - 6V C49 OPT C50 OPT 0.01uF C25 C51 4.7uF 5 SHDN IN OPT L8 D1 HSMS-2822 R63 0 C10 1uF 2 1 T5 LTC2263IUJ-14 DC1532A-F 14 25 DC1532A-L DC1532A-K DC1532A-I DC1532A-J 65 40 80 14 LTC2264IUJ-14 DC1532A-E 14 14 LTC2266IUJ-14 LTC2265IUJ-14 DC1532A-D DC1532A-H 105 4 ASSY DC1532A-G 14 R42 OPT R43 OPT C2 0.1uF R8 100 C52 0.1uF OPT R60 OVDD 125 Msps R65 0 R40 49.9 R41 49.9 BEAD L7 VDD C29 0.1uF VCM12 C27 opt BEAD L11 BEAD AIN2- AIN2+ U1 OPT R56 C48 0.1uF 12 12 12 LTC2265IUJ-12 LTC2263IUJ-12 12 12 LTC2264IUJ-12 LTC2266IUJ-12 LTC2267IUJ-12 Bits 12 10 9 8 7 6 5 4 3 2 1 C5 0.1uF VDD C46 C47 25 40 65 80 3 105 125 Msps 0 0 AIN2- AIN2+ VCM2 REFL REFL REFH REFH VCM1 AIN1- AIN1+ R14 1K VDD C17 2.2uF C36 0.1uF VCM2 C30 0.1uF TP1 LTC2268IUJ-12 R59 OPT R57 OPT R58 OPT C3 0.1uF C1 2.2uF EXT REF MISO C4 1uF CS0 SCK MOSI OUT2A- OUT2A+ FR- FR+ OGND OVDD DCO- DCO+ OUT1B- OUT1B+ OUT1A- OUT1A+ OUT1B+ 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. ENG.CLARENCE M. PCB DES. A.K. APPROVALS OVDD 2 REV VUNREG 5V 14 10 9 11 12 6 4 7 5 DATE: N/A SIZE TECHNOLOGY RN1 33 1 8 2 7 3 6 4 5 1 DEMO CIRCUIT 1532A LTC226XIUJ FAMILY Tuesday, January 19, 2010 IC NO. MISO MOSI SCK CS0 MISO C16 0.1uF J5 OPT 2 R9 1K VDD R11 1K DATE SCK 01-08-10 SHEET 1 OF 2 2 REV 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 LTC Confidential-For Customer Use Only DUAL ADC FAMILY TITLE: SCHEMATIC NC EEVCC EESDA EESCL EEGND CS SCK/SCL MOSI/SDA MISO 1 2 C15 0.1uF C9 0.1uF J15 OPT 1.75mA MOSI 3.5mA ILVDS J8 OPT 2 C7 0.1uF C8 0.1uF RUN 2 EN DIS TERM VDD CLARENCE APPROVED OVDD CS0 SHDN R74 1K VDD R12 31.6K R10 10K PRODUCTION VDD J14 OPT 2 1 DE S CR IPTION REVISION HISTORY SHDN 3.3_AUX PAR/SER R73 1K VDD ECO J10 OPT 1 LANE 2 LANE LANE R95 100 CONTRACT NO. OUT2B- OUT2B+ OUT2A- OUT2A+ FR- FR+ DCO- DCO+ OUT1B- 2 R72 1K CUSTOMER NOTICE * PAR SER J13 PAR/SER VDD LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY T O VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. 21 22 23 24 25 26 27 28 29 30 U1 2 1 3 L9 14 Bits R101 0 R64 OPT C45 0.01uF 3 2 1 DC1532A-C LTC2267IUJ-14 4 5 VDD 100 C28 0.1uF R30 R29 33.2 R26 33.2 + C6 100uF MABA-007159-000000 DC1532A-B U1 T8 C54 1uF 4 3 MABAES0060 5 LTC2268IUJ-14 0.01uF C43 0.01uF C44 3 2 1 DC1532A-A ASSY * ASSY TABLE R62 0 C26 0.01uF C32 8.2pF C31 8.2pF R61 0 4 5 R38 86.6 R100 OPT 4 1 2 T9 MABA-007159-000000 BYP OUT SEN/ADJ R37 86.6 56nH 86.6 5 L4 R35 C53 1uF 8 12 VDD GND GND GND PAR/SER 40 VDD CLK+ 13 1 3 U2 LT1763CS8-1.8 39 VDD CLK14 33 GND 3 38 SENSE 15 SCK 4 37 GND CS 32 OUT1A+ 3 6 7 1 3 2 36 VREF 16 VDD 11 35 PAR/SER SDI 17 34 SDO GND 18 1 3 31 OUT1AOUT2B19 OUT2B+ 20 EP 41 1 3 GND GND GND 3 8 13 1 8 3 D 5 A B C D DEMO MANUAL DC1532 Schematic Diagram dc1532f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D AIN2 0.01uF C0 R110 33K 5 R54 86.6 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 C40 8.2pF R102 10K C39 8.2pF R53 86.6 L5 GND DP1_M2C_P DP1_M2C_N GND GND DP2_M2C_P DP2_M2C_N GND GND DP3_M2C_P DP3_M2C_N GND GND DP4_M2C_P DP4_M2C_N GND GND DP5_M2C_P DP5_M2C_N GND GND DP1_C2M_P DP1_C2M_N GND GND DP2_C2M_P DP2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND SEAM-10X40PIN J1A 3.3_AUX R2 OPT 0 R1 J4 C33 86.6 56nH R52 C1 R111 33K R103 10K 5 R112 33K SEAM-10X40PIN T10 2 1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 C3 R113 33K R105 10K C38 0.1uF 4 3 MABAES0060 R104 10K 3 2 1 RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6_M2C_N GND GND GBTCLK1_M2C_P GBTCLK1_M2C_N GND GND DP9_C2M_P DP9_C2M_N GND GND DP8_C2M_P DP8_C2M_N GND GND DP7_C2M_P DP7_C2M_N GND GND DP6_C2M_P DP6_C2M_N GND GND RES0 J1B C2 C34 0.01uF 4 5 T11 MABA-007159-000000 4 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 C5 C59 0.1uF GND CLK0_C2M_P CLK0_C2M_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND R114 33K R106 10K C35 opt SEAM-10X40PIN J1G C4 100 R47 R46 33.2 R39 33.2 4 R115 33K R107 10K R92 100 OUT2B+ OUT2A+ OUT1B+ OUT1A+ C6 VCM2 AIN2- AIN2+ OUT2B- OUT2A- OUT1B- OUT1A- R116 33K R108 10K R117 33K R109 10K CHANNEL 2 CHANNEL 1 C7 3 VREF_A_M2C PRSNT_M2C_N GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ SEAM-10X40PIN J1H GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND SEAM-10X40PIN J1C 3 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 R99 100 R98 100 EN DIS 2 SCK MOSI FR- FR+ CS0 GND HA01_P_CC HA01_N_CC GND GND HA05_P HA05_N GND HA09_P HA09_N GND HA13_P HA13_N GND HA16_P HA16_N GND HA20_P HA20_N GND HB03_P HB03_N GND HB05_P HB05_N GND HB09_P HB09_N GND HB13_P HB13_N GND HB21_P HB21_N GND HB20_P HB20_N GND VADJ GND E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 C18 0.1uF 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. ENG.CLARENCE M. PCB DES. A.K. APPROVALS SEAM-10X40PIN J1E SCL SDA WP A2 A1 A0 CONTRACT NO. VDD 6 5 7 3 2 1 R36 10K U3 24LC32A-I /ST MISO CUSTOMER NOTICE F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 R5 R4 10K 10K R97 100 FRAME CLOCK 2 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY T O VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. PG_M2C GND GND HA00_P_CC HA00_N_CC GND HA04_P HA04_N GND HA08_P HA08_N GND HA12_P HA12_N GND HA15_P HA15_N GND HA19_P HA19_N GND HB02_P HB02_N GND HB04_P HB04_N GND HB08_P HB08_N GND HB12_P HB12_N GND HB16_P HB16_N GND HB19_P HB19_N GND VADJ SEAM-10X40PIN J1F J2 WP R96 100 1 3 8 VCC VSS 4 5 GND CLK1_C2M_P CLK1_C2M_N GND GND HA03_P HA03_N GND HA07_P HA07_N GND HA11_P HA11_N GND HA14_P HA14_N GND HA18_P HA18_N GND HA22_P HA22_N GND HB01_P HB01_N GND PB07_P HB07_N GND HB11_P HB11_N GND HB15_P HB15_N GND HB18_P HB18_N GND VIO_B_M2C GND DATE: N/A SIZE TECHNOLOGY J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 3.3_AUX DCO- DCO+ 1 DEMO CIRCUIT 1532A SHEET 2 OF 2 2 REV 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 LTC Confidential-For Customer Use Only LTC226XIUJ FAMILY Tuesday, January 19, 2010 IC NO. C7 C6 C5 C4 C3 C2 C1 C0 DATA CLOCK VREF_B_M2C GND GND CLK1_M2C_P CLK1_M2C_N GND HA02_P HA02_N GND HA06_P HA06_N GND HA10_P HA10_N GND HA17_P_CC HA17_N_CC GND HA21_P HA21_N GND HA23_P HA23_N GND HB00_P_CC HB00_N_CC GND HB06_P_CC HB06_N_CC GND HB10_P HB10_N GND HB14_P HB14_N GND HB17_P_CC HB17_N_CC GND VIO_B_M2C SEAM-10X40PIN J1K DUAL ADC FAMILY TITLE: SCHEMATIC SEAM-10X40PIN J1J PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_N GA1 3P3V GND 3P3V GND 3P3V SEAM-10X40PIN J1D 1 A B C D DEMO MANUAL DC1532 Schematic Diagram dc1532f 9 DEMO MANUAL DC1532 DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation dc1532f 10 Linear Technology Corporation LT 0412 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2012