2018 Microchip Technology Inc. DS20006122A-page 1
MCP33131/21/11-XX
Features
• Sample Rate (Throughput):
- MCP33131/21/11-10: 1 Msps
- MCP33131/21/11-05: 500 kSPS
• 16/14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Wide Operating Voltage Range:
- Analog Supply Voltage (AVDD): 1.8V
- Digital Input/Output Interface Voltage (DVIO):
1.7V - 5.5V
- External Reference (VREF): 2.5V - 5.1V
• Pseudo-Differential Input Operation with
Single-Ended Configuration:
- Input Full-Scale Range: 0V to +VREF
• Ultra Low Current Consumption (typical):
- During Input Acquisition (Standby): ~ 0.8 µA
- During Conversion:
MCP331x1-10: ~1.6 mA
MCP331x1-05: ~1.4 mA
• SPI-Compatible Serial Communication:
- SCLK Clock Rate: up to 100 MHz
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
- During Power-Up (automatic)
- On-Demand via user’s command during
normal operation
• AEC-Q100 Qualified:
- Temperature Grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
Typical Applications
• High-Precision Data Acquisition
• Medical Instruments
• Test Equipment
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
System Design Supports
The MCP331x1-XX Evaluation Kit demonstrates the
performance of the MCP331x1-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1-XX
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 MCU firmware example codes.
Package Types
10
MSOP-10
AIN+
AVDD
AIN-
SDI
SCLK
1
2
3
4
9
8
7SDO
DVIO
VREF
TDFN-10
AIN+
AVDD
AIN-
SDI
SCLK
1
2
3
4
10
9
8
7SDO
DVIO
VREF
56
GND CNVST
56
GND CNVST
Top Vi e w
Top Vi ew
MCP331x1-XX Device Offering (Note 1):
Part Number Resolution Sample
Rate Input Type Input Range
Performance (Typical)
SNR
(dBFS)
SFDR
(dB)
THD
(dB)
INL
(LSB)
DNL
(LSB)
MCP33131-10 16-bit 1 Msps Single-Ended 0V to 5.1V 86.7 98.9 -97.4 ±2.2 ±0.9
MCP33121-10 14-bit 1 Msps Single-Ended 0V to 5.1V 83.5 98.8 -97.2 ±0.55 ±0.25
MCP33111-10 12-bit 1 Msps Single-Ended 0V to 5.1V 73.8 95.9 -93.7 ±0.12 ±0.06
MCP33131-05 16-bit 500 kSPS Single-Ended 0V to 5.1V 86.7 98.9 -97.4 ±2.2 ±0.9
MCP33121-05 14-bit 500 kSPS Single-Ended 0V to 5.1V 83.5 98.8 -97.2 ±0.55 ±0.25
MCP33111-05 12-bit 500 kSPS Single-Ended 0V to 5.1V 73.8 95.9 -93.7 ±0.12 ±0.06
Note 1: SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.
1 Msps/500 kSPS 16/14/12-Bit Single-Ended Input SAR ADC
MCP33131/21/11-XX
DS20006122A-page 2 2018 Microchip Technology Inc.
Application Diagram
Description
The MCP33131/MCP33121/MCP33111-10 and
MCP33131/MCP33121/MCP33111-05 are
single-ended 16, 14, and 12-bit, single-channel 1 Msps
and 500 kSPS ADC family devices, respectively,
featuring low power consumption and high
performance, using a successive approximation
register (SAR) architecture.
The device operates with a 2.5V to 5.1V external
reference (VREF), which supports a wide range of input
full-scale range from 0V to VREF
. The reference voltage
setting is independent of the analog supply voltage
(AVDD) and is higher than AVDD. The conversion output
is available through an easy-to-use simple SPI-
compatible 3-wire interface.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7V - 5.5V) allows the device to
interface with most host devices (Master) available in
the current industry such as the PIC32
microcontrollers, without using external voltage level
shifters.
When the device is first powered-up, it performs a
self-calibration to minimize offset, gain and linearity
errors. The device performance stays stable across the
specified temperature range. However, when extreme
changes in the operating environment, such as in the
reference voltage, are made with respect to the initial
conditions (e.g. the reference voltage was not fully
settled during the initial power-up sequence), the user
may send a recalibrate command anytime to initiate
another self-calibration to restore optimum
performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode,
where sampling capacitors are connected to the input
pins. This mode is called Standby.
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes less than 1 µA during
Standby. A new conversion is started on the rising edge
of CNVST. When the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO, and the device enters Standby to begin acquiring
the next input sample. The user can clock out the ADC
output data using the SPI-compatible serial clock
during Standby.
The ADC system clock is generated by an internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device is AEC-Q100 qualified for automotive
applications and operates over the extended
temperature range of -40°C to +125°C. The available
package options are Pb-free TDFN-10 and MSOP-10.
1.7 nF
22Ω
(0V to VREF)
AIN+
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
2.5V to 5.1V 1.8V 1.7V to 5.5V
GND
(PIC32MZ)
Host Device
MCP331x1-XX
Analog Input
Ground Reference of
Analog Input
2018 Microchip Technology Inc. DS20006122A-page 3
MCP33131/MCP33121/MCP33111-XX
1.0 KEY ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings†
External Analog Supply Voltage (AVDD) ................... -0.3V to 2.0V
External Digital Supply Voltage (DVIO) ..................... -0.3V to 5.8V
External Reference Voltage (VREF) .......................... -0.3V to 5.8V
Analog Inputs w.r.t GND .................... .......... –0.3V to VREF+0.3V
Current at Input Pins ...........................................................±2 mA
Current at Output and Supply Pins .................................±250 mA
Storage Temperature ...........................................-65°C to +150°C
Maximum Junction Temperature (TJ) ....... .........................+150°C
ESD protection on all pins .... ≤2kV HBM, ≤2kV CDM, ≤200V MM
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.2 Electrical Specifications
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF.
• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V (Note 3)
Digital Input/Output Interface Voltage
Range
DVIO 1.7 — 5.5 V (Note 3)
Analog Supply Current at AVDD pin:
During Conversion
During Standby
IDDAN
IDDAN_STBY
—
—
—
1.6
1.4
0.8
2.4
2.0
—
mA
mA
µA
fs = 1 Msps (MCP331x1-10)
fs = 500 kSPS (MCP331x1-05)
During input acquisition (tACQ)
Digital Supply Current At DVDD pin:
During Output Data Reading
During Standby
IIO_DATA
IIO_STBY
—
—
—
290
200
30
—
—
—
A
A
nA
fs = 1 Msps (MCP331x1-10)
fs = 500 kSPS (MCP331x1-05)
During input acquisition (tACQ)
External Reference Voltage Input
Reference Voltage
(Note 2), (Note 3)
VREF 2.5
2.7
5.1
5.1
V-40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Reference Load Current at VREF pin:
During Conversion
During Standby
IREF
IREF_STBY
—
—
450
220
240
600
360
—
µA
µA
nA
fs = 1 Msps (MCP331x1-10)
fs = 500 kSPS (MCP331x1-05)
During input acquisition (tACQ)
Total Power Consumption (Including AVDD, DVIO, VREF pins)
MCP331x1-10
at 1 Msps
at 500 ksps
at 100 ksps
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
—
6.2
3.1
0.6
2.6
—
—
—
—
mW
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ)
MCP331x1-05
at 500 ksps
at 100 ksps
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
4.2
0.8
2.6
—
—
—
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
DS20006122A-page 4 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Analog Inputs
Input Voltage Range VIN+ -0.1 — VREF+0.1 V (Note 2)
Input Full-Scale Voltage Range FSR 0 — +VREF VPP (Note 2)
Input Sampling Capacitance CS—31—pF(Note 1)
-3dB Input Bandwidth BW-3dB —25—MHz
(Note 1)
Aperture Delay
(Note 1)
— 2.5 — ns Time delay between CNVST rising
edge and when input is sampled
Leakage Current at Analog Input Pin ILEAK_AN_INPUT — ±2 ±200 nA During input acquisition (tACQ)
System Performance
Sample Rate
(Throughput rate)
fs— — 1 Msps MCP331x1-10
— — 500 kSPS MCP331x1-05
Resolution
(No Missing Codes)
16 — — Bits MCP33131-10 and MCP33131-05
14 — — Bits MCP33121-10 and MCP33121-05
12 — — Bits MCP33111-10 and MCP33111-05
Integral Nonlinearity INL -6 ±2.2 +6 LSB MCP33131-10 and MCP33131-05
-1.5 ±0.55 +1.5 LSB MCP33121-10 and MCP33121-05
±0.12 LSB MCP33111-10 and MCP33111-05
Differential Nonlinearity DNL -0.98 ±0.9 +1.8 LSB MCP33131-10 and MCP33131-05
-0.8 ±0.25 +0.8 LSB MCP33121-10 and MCP33121-05
-0.3 ±0.06 +0.3 LSB MCP33111-10 and MCP33111-05
Offset Error ±0.1 ±2.3 mV MCP33131-10 and MCP33131-05
— ±0.125 ±3 mV MCP33121-10 and MCP33121-05
—±0.8 ±3.66 mV MCP33111-10 and MCP33111-05
Offset Error Drift with Temperature — ±0.8 — V/oC
Gain Error GER —±4 —LSB MCP33131-10 and MCP33131-05
— ±1 — LSB MCP33121-10 and MCP33121-05
—±0.2 —LSB MCP33111-10 and MCP33111-05
Gain Error Drift with temperature — ±0.35 — V/oC
Input Common-Mode
Rejection Ratio
CMRR — 84 — dB
Power Supply Rejection Ratio PSRR — 60 — dB (Note 4)
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF.
• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc. DS20006122A-page 5
MCP33131/MCP33121/MCP33111-XX
Dynamic Performance
Signal-to-Noise Ratio SNR MCP33131-10 and MCP33131-05: 16-bit ADC
—86.8 —dBFSV
REF = 5V, fIN = 1 kHz
—80.9 — V
REF = 2.5V, fIN = 1 kHz
83.5 86.7 — VREF = 5V, fIN = 10 kHz
—80.9 — V
REF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
—83.6 —dBFSV
REF = 5V, fIN = 1 kHz
—79.8 — V
REF = 2.5V, fIN = 1 kHz
81.5 83.5 — VREF = 5V, fIN = 10 kHz
—79.8 — V
REF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
—73.8 —dBFSV
REF = 5V, fIN = 1 kHz
—73.2 — V
REF = 2.5V, fIN = 1 kHz
71.1 73.8 — VREF = 5V, fIN = 10 kHz
—73.2 — V
REF = 2.5V, fIN = 10 kHz
Signal-to-Noise and Distortion Ratio
(Note 5)
SINAD MCP33131-10 and MCP33131-05: 16-bit ADC
—86.9 —dBFSV
REF = 5V, fIN = 1 kHz
—80.9 — V
REF = 2.5V, fIN = 1 kHz
—86.6 — V
REF = 5V, fIN = 10 kHz
—80 — V
REF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
—83.6 —dBFSV
REF = 5V, fIN = 1 kHz
—79.8 — V
REF = 2.5V, fIN = 1 kHz
—83.4 — V
REF = 5V, fIN = 10 kHz
—79.1 — V
REF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
—73.8 —dBFSV
REF = 5V, fIN = 1 kHz
—73.2 — V
REF = 2.5V, fIN = 1 kHz
—73.8 — V
REF = 5V, fIN = 10 kHz
—73 — V
REF = 2.5V, fIN = 10 kHz
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF.
• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
DS20006122A-page 6 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Spurious Free Dynamic Range SFDR MCP33131-10 and MCP33131-05: 16-bit ADC
—99.4 —dBcV
REF = 5V, fIN = 1 kHz
—94.4 — V
REF = 2.5V, fIN = 1 kHz
—98.9 — V
REF = 5V, fIN = 10 kHz
—93.9 — V
REF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
—99.3 —dBcV
REF = 5V, fIN = 1 kHz
—94.4 — V
REF = 2.5V, fIN = 1 kHz
—98.8 — V
REF = 5V, fIN = 10 kHz
—93.9 — V
REF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
—97.4 —dBcV
REF = 5V, fIN = 1 kHz
—94.2 — V
REF = 2.5V, fIN = 1 kHz
—95.9 — V
REF = 5V, fIN = 10 kHz
—93.7 — V
REF = 2.5V, fIN = 10 kHz
Total Harmonic Distortion
(first five harmonics)
THD MCP33131-10 and MCP33131-05: 16-bit ADC
— -97.6 — dBc VREF = 5V, fIN = 1 kHz
— -92.5 — VREF = 2.5V, fIN = 1 kHz
— -97.4 — VREF = 5V, fIN = 10 kHz
— -92.4 — VREF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
— -97.4 — dBc VREF = 5V, fIN = 1 kHz
— -92.4 — VREF = 2.5V, fIN = 1 kHz
— -97.2 — VREF = 5V, fIN = 10 kHz
— -92.3 — VREF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
— -94.4 — dBc VREF = 5V, fIN = 1 kHz
— -91.7 — VREF = 2.5V, fIN = 1 kHz
— -93.7 — VREF = 5V, fIN = 10 kHz
— -91.5 — VREF = 2.5V, fIN = 10 kHz
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF.
• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc. DS20006122A-page 7
MCP33131/MCP33121/MCP33111-XX
System Self-Calibration
Self-Calibration Time tCAL —500650ms(Note 2)
Number of SCLK Clocks for
Recalibrate Command
ReCalNSCLK — 1024 — clocks Includes clocks for data bits
Serial Interface Timing Information: See Table 1-2
Digital Inputs/Outputs
High-level Input voltage VIH 0.7 * DVIO —DV
IO + 0.3 V DVIO ≥2.3V
0.9 * DVIO —DV
IO + 0.3 V DVIO <2.3V
Low-level input voltage VIL -0.3 — 0.3 * DVIO VDV
IO ≥2.3V
-0.3 — 0.2 * DVIO VDV
IO <2.3V
Hysteresis of Schmitt Trigger Inputs VHYST — 0.2 * DVIO — V All digital inputs
Low-level output voltage VOL ——0.2 * DV
IO VI
OL =500 µA (sink)
High-level output voltage VOH 0.8 * DVIO — —VI
OL = - 500 µA (source)
Input leakage current ILI — — ±1 µA CNVST/SDI/SCLK = GND or DVIO
Output leakage current ILO — — ±1 µA Output is high-Z, SDO = GND or
DVIO
Internal capacitance
(all digital inputs and outputs)
CINT —7—pFT
A = 25°C (Note 1)
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF.
• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
DS20006122A-page 8 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS
TABLE 1-3: TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, GND = 0V,
Analog Input (AIN) = -1 dBFS sine wave, Resolution = 16-bit (MCP33131-10), fIN = 10 kHz, CLOAD_SDO = 20 pF, +25°C is applied for typical value. All
timings are measured at 50%. See Figure 1-1 for timing diagram.
• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Symbol Min. Typ. Max. Units Conditions
Serial Clock frequency fSCLK — — 100 MHz See tSCLK specification
SCLK Period tSCLK 10 — — ns DVIO ≥ 3.3V, fSCLK = 100 MHz (Max)
12 — — ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max)
16 — — ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max)
SCLK Low Time tSCLK_L 3— —ns
DVIO ≥ 2.3V
4.5 — — ns DVIO ≥ 1.7V
SCLK High Time tSCLK_H 3— —ns
DVIO ≥ 2.3V
4.5 — — ns DVIO ≥ 1.7V
Output Valid from SCLK Low tDO —— 9.5nsDV
IO ≥ 3.3V
— — 12 ns DVIO ≥ 2.3V
— — 16 ns DVIO ≥ 1.7V
Quiet time tQUIET 10 — — ns (Note 2)
3-Wire Operation:
SDI Valid Setup time tSU_SDIH_CNV 5 — — ns SDI High to CNVST Rising Edge
CNVST Pulse Width High Time tCNVH 10 — — ns
Output Enable Time tEN — — 10 ns DVIO ≥ 2.3V
— — 15 ns DVIO ≥ 1.7V
Output Disable Time tDIS — — 15 ns (Note 2)
MCP331x1-10
Sample Rate fs— — 1 Msps Throughput rate
Input Acquisition Time
(Note 2)
tACQ 290
250
300 —
—
ns -40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Data Conversion Time tCNV —
—
700 710
750
ns -40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Time between Conversions tCYC 1— —µst
CYC = tACQ + tCNV
, fS = 1 Msps
MCP331x1-05
Sample Rate fs— — 500 kSPS Throughput rate
Input Acquisition Time (Note 2) tACQ 700 800 — ns -40°C ≤TA≤ 125°C
Data Conversion Time tCNV — 1200 1300 ns -40°C ≤TA≤ 125°C
Time between Conversions tCYC 2— —µst
CYC = tACQ + tCNV
, fS = 500 kSPS
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
Parameters Symbol Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C (Note 1)
Storage Temperature Range TA-65 — +150 °C (Note 1)
Thermal Package Resistance
Thermal Resistance, MSOP-10 JA —202—°C/W
Thermal Resistance, TDFN-10 JA —68—°C/W
Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC.
2018 Microchip Technology Inc. DS20006122A-page 9
MCP33131/MCP33121/MCP33111-XX
FIGURE 1-1: Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for More
Details.
CNVST
SDO
SCLK 123n-1 n
Dn-1 Dn-2 Dn-3 D1D0
ADC State
(MSB)
Hi-Z Hi-Z
tCNVH
tCNV (MAX)
tSCLK
tSCLK_L tSCLK_H
tDO
tDIS
Conversion
2: tEN when CNVST is lowered after tCNV (MAX).
Input Acquisition
Input Acquisition
(tCNV)(tACQ)
(tACQ)
tCYC
SDI = “High”
tSU_SDIH_CNV
tEN
tQUIET
tEN
3: tEN when CNVST is lowered before tCNV (MAX).
= 1/fS
(Note 2)
(Note 3)
(Note 1)
Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device.
DS20006122A-page 10 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
NOTES:
2018 Microchip Technology Inc. DS20006122A-page 11
MCP33131/MCP33121/MCP33111-XX
2.0 TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-1: INL vs. Output Code.
FIGURE 2-2: DNL vs. Output Code.
FIGURE 2-3: INL vs. Temperature.
FIGURE 2-4: INL vs. Output Code.
FIGURE 2-5: DNL vs. Output Code.
FIGURE 2-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 16,384 32,768 49,152 65,536
Code
-2
-1
0
1
2
INL (LSB)
VREF = 5V
0 16,384 32,768 49,152 65,536
Code
-1
-0.5
0
0.5
1
1.5
2
DNL (LSB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-3
-2
-1
0
1
2
3
INL (LSB)
Min INL (LSB)
Max INL (LSB)
VREF = 5V
0 16,384 32,768 49,152 65,536
Code
-4
-2
0
2
4
INL (LSB)
V
REF
= 2.5V
0 16,384 32,768 49,152 65,536
Code
-1
-0.5
0
0.5
1
1.5
2
DNL (LSB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.5
0
0.5
1
1.5
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
V
REF
= 5V
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 12 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-7: INL vs. Reference Voltage.
FIGURE 2-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-10: DNL vs. Reference Voltage.
FIGURE 2-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 2-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-8
-6
-4
-2
0
2
4
6
8
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 1 Msps
SNR = 86.7 dBFS
SINAD = 86.6 dBFS
SFDR = 103.6 dBc
THD = -101.4 dBc
Resolution = 16-bit
MCP33131-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 0.5 Msps
SNR = 86.7 dBFS
SINAD = 86.6 dBFS
SFDR = 105.0 dBc
THD = -101.5 dBc
Resolution = 16-bit
MCP33131-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1
-0.5
0
0.5
1
1.5
2
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 2.5V
f
s
= 1 Msps
SNR = 81.7 dBFS
SINAD = 81.6 dBFS
SFDR = 98.0 dBc
THD = -95.8 dBc
Resolution = 16-bit
MCP33131-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 2.5V
f
s
= 0.5 Msps
SNR = 81.8 dBFS
SINAD = 81.7 dBFS
SFDR = 98.9 dBc
THD = -96.0 dBc
Resolution = 16-bit
MCP33131-05
2018 Microchip Technology Inc. DS20006122A-page 13
MCP33131/MCP33121/MCP33111-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-13: SNR/SINAD/ENOB vs. VREF
FIGURE 2-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 2-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 2-16: SFDR/THD vs. VREF
FIGURE 2-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 2-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
74
76
78
80
82
84
86
88
90
SNR/SINAD (dB)
ENOB
SNR (dB)
SINAD (dB)
12
12.5
13
13.5
14
ENOB (Bits)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
83
84
85
86
87
88
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
80
81
82
83
84
85
86
87
88
89
90
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-100
-98
-96
-94
-92
-90
THD (dB)
THD (dB)
SFDR (dB)
90
92
94
96
98
100
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
74
75
76
77
78
79
80
81
82
83
84
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
75
76
77
78
79
80
81
82
83
84
85
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 2.5V
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 14 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-19: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 2-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 2-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 2-22: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 2-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 2-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
100101102103
Input Frequency (kHz)
70
72
74
76
78
80
82
84
86
88
90
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-102
-100
-98
-96
-94
-92
THD (dB)
94
96
98
100
102
104
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
THD (dB)
SFDR (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
70
72
74
76
78
80
82
84
86
88
90
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-96
-95
-94
-93
-92
-91
-90
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
100
SFDR (dB)
V
REF
= 2.5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
2018 Microchip Technology Inc. DS20006122A-page 15
MCP33131/MCP33121/MCP33111-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 2-26: Shorted Input Histogram:
VREF = 5V.
FIGURE 2-27: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 2-28: THD/SFDR vs. Input
Amplitude: VREF = 2.5V.
FIGURE 2-29: Shorted Input Histogram:
VREF = 2.5V.
FIGURE 2-30: Offset and Gain Error vs.
Temperature: VREF = 2.5V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
THD (dB)
THD (dB)
SFDR (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
V
REF
= 5V
012345678910
Output Code
0
2
4
6
8
10
Occurrences
10
5
65 3224
59995
93862
757379
119771
14132 143 5
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-100
0
100
200
300
400
500
600
700
800
Offset/Gain Error (uV)
-1.31
0
1.31
2.62
3.93
5.24
6.55
7.86
9.18
10.49
Offset/Gain Error (LSB)
Gain Error
Offset Error
V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
-5-3-113579111315
Output Code
0
1
2
3
4
5
Occurrences
105
9092
12211
79707
133072
402464
137150
128876
50970
18039
12848
27533
20814
12208
2377
1167
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-500
-400
-300
-200
-100
0
100
200
300
400
Offset/Gain Error (uV)
-13.11
-10.49
-7.86
-5.24
-2.62
0
2.62
5.24
7.86
10.49
Offset/Gain Error (LSB)
Offset Error
Gain Error
V
REF
= 2.5V
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 16 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-31: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 2-32: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 2-33: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
FIGURE 2-34: Power Consumption vs.
Temperature During Shutdown.
FIGURE 2-35: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 2-36: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Input Frequency (kHz)
74
76
78
80
82
84
86
CMRR (dB)
V
REF
= 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
10
Total Power (mW)
MCP331x1-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
2
4
6
8
Current (A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
4
8
12
16
Total Power (W)
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-05
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-05
2018 Microchip Technology Inc. DS20006122A-page 17
MCP33131/MCP33121/MCP33111-XX
3.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-1: INL vs. Output Code.
FIGURE 3-2: DNL vs. Output Code.
FIGURE 3-3: INL vs. Temperature.
FIGURE 3-4: INL vs. Output Code.
FIGURE 3-5: DNL vs. Output Code.
FIGURE 3-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
INL (LSB)
VREF = 5V
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
INL (LSB)
Min INL (LSB)
Max INL (LSB)
V
REF
= 5V
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
INL (LSB)
V
REF
= 2.5V
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.5
0
0.5
1
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
V
REF
= 5V
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 18 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-7: INL vs. Reference Voltage.
FIGURE 3-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 3-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 3-10: DNL vs. Reference Voltage.
FIGURE 3-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 3-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
INL (LSB)
Max INL (LSB)
Min INL (LSB)
MCP33121-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 0.5 Msps
SNR = 83.5 dBFS
SINAD = 83.4 dBFS
SFDR = 105.0 dBc
THD = -101.6 dBc
Resolution = 14-bit
MCP33121-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1
-0.5
0
0.5
1
DNL (LSB)
Min DNL (LSB)
Max DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 2.5V
f
s
= 1 Msps
SNR = 80.3 dBFS
SINAD = 80.2 dBFS
SFDR = 97.9 dBc
THD = -95.8 dBc
Resolution = 14-bit
MCP33121-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 2.5V
fs = 0.5 Msps
SNR = 80.6 dBFS
SINAD = 80.5 dBFS
SFDR = 99.4 dBc
THD = -96.4 dBc
Resolution = 14-bit
MCP33121-05
2018 Microchip Technology Inc. DS20006122A-page 19
MCP33131/MCP33121/MCP33111-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-13: SNR/SINAD/ENOB vs. VREF.
FIGURE 3-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 3-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 3-16: SFDR/THD vs. VREF.
FIGURE 3-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 3-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
76
78
80
82
84
86
SNR/SINAD (dB)
11.5
12
12.5
13
13.5
14
ENOB (Bits)
ENOB
SNR (dB)
SINAD (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
80
81
82
83
84
85
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
76
77
78
79
80
81
82
83
84
85
86
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-100
-98
-96
-94
-92
-90
THD (dB)
90
92
94
96
98
100
SFDR (dB)
THD (dB)
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
72
73
74
75
76
77
78
79
80
81
82
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
76
77
78
79
80
81
82
83
84
85
86
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 2.5V
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 20 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-19: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 3-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 3-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 3-22: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 3-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 3-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
100101102103
Input Frequency (kHz)
70
72
74
76
78
80
82
84
86
88
90
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-102
-100
-98
-96
-94
-92
THD (dB)
THD (dB)
SFDR (dB)
94
96
98
100
102
104
SFDR (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
70
72
74
76
78
80
82
84
86
88
90
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
Temperature (oC)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-96
-95
-94
-93
-92
-91
-90
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
100
SFDR (dB)
V
REF
= 2.5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
THD (dB)
SFDR (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
V
REF
= 2.5V
2018 Microchip Technology Inc. DS20006122A-page 21
MCP33131/MCP33121/MCP33111-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 3-26: Shorted Input Histogram:
VREF = 5V.
FIGURE 3-27: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 3-28: THD/SFDR vs. Input
Amplitude: VREF = 2.5V.
FIGURE 3-29: Shorted Input Histogram:
VREF = 2.5V.
FIGURE 3-30: Offset and Gain Error vs.
Temperature: VREF = 2.5V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
-3-2-1012345
Output Code
0
2
4
6
8
10
12
Occurrences
105
63284
985144
148
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
0
100
200
300
400
500
600
700
Offset/Gain Error (uV)
0
0.33
0.66
0.98
1.31
1.64
1.97
2.29
Offset/Gain Error (LSB)
Offset Error
Gain Error
V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
-4-3-2-10123456
Output Code
0
2
4
6
8
10
Occurrences
10
5
234082
719460
79234
15798 2
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-300
-200
-100
0
100
200
300
400
Offset/Gain Error (uV)
-1.97
-1.31
-0.66
0
0.66
1.31
1.97
2.62
Offset/Gain Error (LSB)
Offset Error
V
REF
= 2.5V
Gain Error
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 22 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-31: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 3-32: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 3-33: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
FIGURE 3-34: Power Consumption vs.
Temperature During Shutdown.
FIGURE 3-35: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 3-36: Power Consumption vs.
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Input Frequency (kHz)
74
76
78
80
82
84
86
CMRR (dB)
VREF = 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
10
Total Power (mW)
MCP331x1-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
2
4
6
8
Current (A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
4
8
12
16
Total Power (W)
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-05
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-05
2018 Microchip Technology Inc. DS20006122A-page 23
MCP33131/MCP33121/MCP33111-XX
4.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-1: INL vs. Output Code.
FIGURE 4-2: DNL vs. Output Code.
FIGURE 4-3: INL vs. Temperature.
FIGURE 4-4: INL vs. Output Code.
FIGURE 4-5: DNL vs. Output Code.
FIGURE 4-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
INL (LSB)
V
REF
= 5V
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
DNL (LSB)
VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
INL (LSB)
V
REF
= 5V
Max INL (LSB)
Min INL (LSB)
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
INL (LSB)
V
REF
= 2.5V
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
DNL (LSB)
VREF = 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
DNL (LSB)
V
REF
= 5V
Max DNL (LSB)
Min DNL (LSB)
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 24 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-7: INL vs. Reference Voltage.
FIGURE 4-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 4-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 4-10: DNL vs. Reference Voltage.
FIGURE 4-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 4-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 1 Msps
SNR = 73.8 dBFS
SINAD = 73.7 dBFS
SFDR = 99.7 dBc
THD = -98.4 dBc
Resolution = 12-bit
MCP33111-10
0 50 100 150 200 250
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 5V
f
s
= 0.5 Msps
SNR = 73.8 dBFS
SINAD = 73.8 dBFS
SFDR = 99.9 dBc
THD = -97.5 dBc
Resolution = 12-bit
MCP33111-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.5
0
0.5
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
MCP33111-10
0 50 100 150 200 250
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
V
REF
= 2.5V
f
s
= 0.5 Msps
SNR = 73.4 dBFS
SINAD = 73.4 dBFS
SFDR = 100.1 dBc
THD = -96.4 dBc
Resolution = 12-bit
MCP33111-05
2018 Microchip Technology Inc. DS20006122A-page 25
MCP33131/MCP33121/MCP33111-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-13: SNR/SINAD/ENOB vs. VREF
FIGURE 4-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 4-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 4-16: SFDR/THD vs. VREF
FIGURE 4-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 4-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
71.5
72
72.5
73
73.5
SNR/SINAD (dB)
11.5
11.6
11.7
11.8
11.9
ENOB (Bits)
ENOB
SNR (dB)
SINAD (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
72.2
72.4
72.6
72.8
73
73.2
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
70
71
72
73
74
75
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
VREF = 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-95
-94
-93
-92
-91
-90
THD (dB)
THD (dB)
SFDR (dB)
90
92
94
96
98
100
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
70
70.5
71
71.5
72
72.5
73
73.5
74
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
70
71
72
73
74
75
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
VREF = 2.5V
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 26 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-19: SNR/SINAD vs. Input
Frequency: VIN = -1 dBFS.
FIGURE 4-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 4-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 4-22: SNR/SINAD vs. Input
Frequency: VIN = -1 dBFS.
FIGURE 4-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 4-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
100101102103
Input Frequency (kHz)
60
62
64
66
68
70
72
74
76
78
80
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-96
-95
-94
-93
-92
-91
-90
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
100
SFDR (dB)
V
REF
= 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
60
62
64
66
68
70
72
74
76
78
80
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-96
-95
-94
-93
-92
-91
-90
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
100
SFDR (dB)
V
REF
= 2.5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
2018 Microchip Technology Inc. DS20006122A-page 27
MCP33131/MCP33121/MCP33111-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 4-26: Shorted Input Histogram:
VREF = 5V.
FIGURE 4-27: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 4-28: THD/SFDR vs. Input
Amplitude: VREF = 2.5V.
FIGURE 4-29: Shorted Input Histogram:
VREF = 2.5V.
FIGURE 4-30: Offset and Gain Error vs.
Temperature: VREF = 2.5V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
-3-2-10123
Output Code
0
2
4
6
8
10
12
Occurrences
105
1048576 VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-100
0
100
200
300
400
500
Offset/Gain Error (uV)
-0.08
0
0.08
0.16
0.25
0.33
0.41
Offset/Gain Error (LSB)
Offset Error
Gain Error
V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
-3-2-10123
Output Code
0
2
4
6
8
10
12
Occurrences
105
1048574
2
VREF = 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-300
-200
-100
0
100
200
300
Offset/Gain Error (uV)
-0.49
-0.33
-0.16
0
0.16
0.33
0.49
Offset/Gain Error (LSB)
Offset Error
V
REF
= 2.5V
Gain Error
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 28 2018 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-31: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 4-32: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 4-33: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
FIGURE 4-34: Power Consumption vs.
Temperature During Shutdown.
FIGURE 4-35: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
MCP331x1D-10
FIGURE 4-36: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Input Frequency (kHz)
74
76
78
80
82
84
86
CMRR (dB)
VREF = 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
10
Total Power (mW)
MCP331x1-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
2
4
6
8
Current (A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
4
8
12
16
Total Power (W)
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-05
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1-05
2018 Microchip Technology Inc. DS20006122A-page 29
MCP33131/MCP33121/MCP33111-XX
5.0 PIN FUNCTION DESCRIPTIONS
TABLE 5-1: PIN FUNCTION TABLE
5.1 Supply Voltages (AVDD, DVIO)
The device has two power supply pins:
(a) Analog power supply (AVDD): 1.8V
(b) Digital input/output interface power supply (DVIO):
1.7V to 5.5V.
The large supply voltage range of DVIO allows the
device to interface with various host devices that are
operating with different supply voltages. See Table 1-2
for timing specifications for I/O interface signal
parameters depending on DVIO voltage.
5.2 Reference Voltage (VREF)
The device requires a single-ended external reference
voltage (VREF). The external input reference range is
from 2.5V to 5.1V. This reference voltage sets the
input full-scale range from 0V to VREF. See Figure 6-1
to Figure 6-2 for example application circuit and
reference voltage settings.
5.2.1 VOLTAGE REFERENCE
SELECTION
The performance of the voltage reference has a large
impact on the accuracy of high-precision data
acquisition systems. The voltage reference should
have high-accuracy, low-noise, and low-temperature
drift. A ±0.1% output accuracy of the reference directly
corresponds to ±0.1% absolute accuracy of the ADC
output. The RMS output noise voltage of the reference
should be less than 1/2 LSB of the ADC.
Pin Number Pin Name Function
1
VREF Reference voltage input (2.5V - 5.1V).
This pin should be decoupled with a 10 F tantalum capacitor.
2AV
DD DC supply voltage input for analog section (1.8V).
This pin should be decoupled with a 1 F ceramic capacitor.
3A
IN+ Analog input.
4A
IN- Ground reference pin for analog input. Connect this pin to the ground reference of the
analog input.
5 GND Power supply ground reference. This pin is a common ground for both the analog
power supply (AVDD) and digital I/O supply (DVIO).
6 CNVST Conversion-start control and active-low SPI chip-select digital input.
A new conversion is started on the rising edge of CNVST.
When the conversion is complete, output data is available at SDO by lowering CNVST.
7 SDO SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK
clock, with MSB first.
8 SCLK SPI-compatible serial data clock digital input.
The ADC output is synchronously shifted out by this clock.
9 SDI SPI-compatible serial data digital input. Tie to DVIO for normal operation.
10 DVIO DC supply voltage for digital input/output interface (1.7V - 5.5V).
This pin should be decoupled with a 0.1 F ceramic capacitor.
Note: Proper decoupling capacitors (1 F to
AVDD, 0.1 F to DVIO) should be mounted
as close as possible to the respective
pins. See Figure 6-1 for example circuit.
Note: The reference pin needs a tantalum
decoupling capacitor (10 F, 10V rating).
Additional multiple ceramic capacitors can
be added in parallel to decouple
high-frequency noises.
Note: During the initial power-up sequence, the
reference voltage (VREF) must be
provided prior to supplying AVDD or within
about 64 ms after supplying AVDD.
Otherwise, it is strongly recommended to
send a recalibrate command. See
Section 7.1 “Recalibrate Command” for
more details.
DS20006122A-page 30 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.0 DEVICE OVERVIEW
The device converts unipolar single-ended analog
input into unipolar straight binary codes.
When the MCP33131/MCP33121/MCP33111-XX is
first powered-up, it performs a self-calibration and
enters a low current input acquisition mode (Standby)
by itself.
The external reference voltage (VREF) ranging from
2.5V to 5.1V sets the input full-scale range (FSR) from
0V to +VREF
.
During input acquisition (Standby), the internal input
sampling capacitors are connected to the input signal,
while most of the internal analog circuits are shutdown
to save power. During this input acquisition time
(tACQ), the device consumes less than 1 A.
The user can operate the device with an easy-to-use
SPI-compatible 3-wire interface.
The device initiates data conversion on the rising edge
of the conversion-start control (CNVST). The data con-
version time (tCNV) is set by the internal clock. Once
the conversion is complete, the device starts the next
input acquisition. During this input acquisition time
(tACQ), the user can clock out the output data by pro-
viding the external SPI serial clock (SCLK).
The device provides conversion data with no missing
codes. This ADC device family has a large input
full-scale range, high precision, high throughput with
no output latency, and is an ideal choice for various
ADC applications.
6.1 Analog Input
Figure shows a simplified equivalent circuit of the
input architecture with a switched capacitor input stage.
The input sampling capacitor (CS+) is about 31 pF. The
back-to-back diodes (D1 - D2) at each input pin are
ESD protection diodes. Note that these ESD diodes are
tied to VREF
, so that each input signal can swing from
0V to VREF
.
The input sampling and hold circuit in AIN+ path is also
repeated in AIN- path. This allows the device to perform
a pseudo-differential conversion of the input signal.
Therefore, the common mode signal presented at both
input pins is rejected. In applications, AIN+ pin is for the
input signal and AIN- pin is for the ground reference of
the input signal. The user must connect the AIN- pin to
a clean ground plane of the input signal externally.
During input acquisition phase (Standby), the sampling
switches are closed and each input sees the sampling
capacitor (≈ 31 pF) in series with the on-resistance of
the sampling switch, RSON (≈ 200).
For high-precision data conversion applications, the
input voltage needs to be fully settled within 1/2 LSB
during the input acquisition period (tACQ). The settling
time is directly related to the source impedance: A
lower impedance source results in faster input settling
time. Although the device can be driven directly with a
low impedance source, using a low noise input driver is
highly recommended.
Simplified Equivalent Analog Input Circuit.
Note: The ESD diodes at the analog input pins
are biased from VREF
. Any input voltage
outside the absolute maximum range can
turn on the input ESD protection diodes
and results in input leakage current which
may cause conversion errors and
permanent damage to the device. Care
must be taken in setting the input voltage
ranges so that the input voltage does not
exceed the absolute maximum input
voltage range.
VT = 0.6V
D2
D1
V
REF
ILEAKAGE
(~ ±1 nA)
AIN+
MCP331x1-XX
RSON
C
PIN
RSON
= On-resistance of the sampling switch ≈ 200 
CPIN = Package pin + ESD capacitor ≈ 2 pF.
where:
CS
+ , CS
-
= Input sample and hold capacitor ≈ 31 pF.
AIN-
(200 )
SW1
+
SW2
+
C
S
+
(31 pF)
AIN+= Analog input.
AIN-= Ground reference of analog input.
Sample VIN+
VT = 0.6V
D2
D1
V
REF
ILEAKAGE
(~ ±1 nA)
C
PIN
RSON
(200 )
SW1
-
SW2
-
C
S
-
(31 pF)
Sample VIN-
2018 Microchip Technology Inc. DS20006122A-page 31
MCP33131/MCP33121/MCP33111-XX
6.1.1 INPUT VOLTAGE RANGE
The device has two analog input pins: AIN+ and AIN-
pins. The analog input signal is applied to the AIN+ pin,
and the ground reference of the input signal is tied to
the AIN- pin.
The voltage difference between AIN+ and AIN- is the
ADC input (VIN) and needs to be between 0V and
+VREF to produce unsaturated output codes.
Equation 6-4 shows the input full-scale range (FSR)
and input range.
The device will output unipolar straight binary codes for
the analog input. If the input (VIN) is greater than the
reference voltage (VREF), the output code will be
saturated. If the input (VIN) is less than or equals to 0V,
the output will be all 0’s.
EQUATION 6-1: FSR AND INPUT RANGE
6.2 Analog Input Conditioning Circuit
The MCP33131/MCP33121/MCP33111-XX can be
driven directly when the source impedance of the input
driver is low.
Large source impedance of the input signal may affect
the ADC’s performance. In general, the source imped-
ance is less sensitive to the ADC’s DC performances
such as INL and DNL. However, it affects significantly
to the dynamic performances such as THD, SFDR and
SNR.
Therefore, it is a good design practice to isolate the
ADC input from the high impedance source using a low
noise input driver amplifier. Figure 6-1 shows an input
configuration example using a low-noise OP amplifier
such as MCP6286 and Figure 6-2 shows the transfer
function of the MCP33131/MCP33121/MCP33111-XX.
FIGURE 6-1: Unipolar-Input Application Example
FIGURE 6-2: Transfer Function for Figure 6-1.
0VV
IN VREF 1LSB–
VREF
=
Input Full-Scale Range (FSR)
Input Range:
where VIN = AIN+ - AIN-
Note 1: Contact Microchip Technology Inc. for more selections of the low-noise input driver amplifiers.
(Note 1)
2: Contact Microchip Technology Inc. for the MCP1501 application circuit.
AIN+
R1
C1
10 F
Reference
Voltage
CR
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
1.8V 1.7V to 5.5V
GND
VREF
(PIC32MZ)
Host Device
(Note 2)
VDC
Analog Input
(22

±0.1%
)
(1.7nF, NPO)
0V
V
REF
0V
V
REF
MCP331x1-XX
2.5V to 5.1V
0.1 F
0.1 F
2R1C1
1
fC =
MCP6286 VIN
MCP1501
Ground Reference of
Analog Input
0V
(Tantalum)
Analog Input Voltage
+VREF
Digital Output Code
0
VIN (V)
+VREF/2
2n/2
VIN range
2n - 1
DS20006122A-page 32 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.3 ADC Input Driver Selection
The noise and distortion of the ADC input driver can
degrade the dynamic performance (SNR, SFDR, and
THD) of the overall ADC application system. Therefore,
the ADC input driver needs better performance specifi-
cations than the ADC itself. The data sheet of the driver
typically shows the output noise voltage and harmonic
distortion parameters.
Figure 6-3 shows a simplified system noise
presentation block diagram for the front-end driver and
ADC.
FIGURE 6-3: Simplified System Noise
Representation.
• Unity-Gain Bandwidth:
An input driver with higher bandwidth usually results in
better overall linearity performance. Typically, the driver
should have the unity-gain bandwidth greater than 5
times the -3 dB cutoff frequency of the anti-aliasing fil-
ter:
EQUATION 6-2: BANDWIDTH
REQUIREMENT FOR ADC
INPUT DRIVER
where, fB = -3 dB bandwidth of RC anti-aliasing filter as
shown in Figure 6-3.
•Distortion:
The nonlinearity characteristics of the input driver
cause distortions in the ADC output. Therefore, the
input driver should have less distortion than the ADC
itself. The recommended total harmonic distortion
(THD) of the driver is at least 10 dB less than that of the
ADC:
EQUATION 6-3: RECOMMENDED THD
FOR ADC INPUT DRIVER
• ADC Input-Referred Noise:
When the ADC is operating with a full-scale input
range, the ADC input-referred RMS noise for a
single-ended input configuration is approximated as
shown in Equation 6-4.
EQUATION 6-4: ADC INPUT-REFERRED
NOISE
•Noise Contribution from the Front-End Driver:
The noise from the input driver can degrade the ADC’s
SNR performance. Therefore, the selected input driver
should have the lowest possible broadband noise den-
sity and 1/f noise. When an anti-aliasing filter is used
after the input driver, the output noise density of the
input driver is integrated over the -3 dB bandwidth of
the filter.
Equation 6-5 shows the RMS output noise voltage cal-
culation using the RC filter’s bandwidth and noise den-
sity (eN) of the input driver. GN in Equation 6-5 is the
noise gain of the driver amplifier and becomes 1 for a
unity gain buffer driver.
EQUATION 6-5: NOISE FROM FRONT-END
DRIVER AMPLIFIER
where eN is the broadband noise density (V/√Hz) of the
front-end driver amplifier and is typically given in its
data sheet. In Equation 6-5, 1/f noise (eNFlicker) is
ignored assuming it is very small compared to the
broadband noise (eN).
For high precision ADC applications, the noise
contribution from the front-end input driver amplifier is
typically constrained to be less than about 20% (or 1/5
times) of the ADC input-referred noise as shown in
Equation 6-6:
EQUATION 6-6: RECOMMENDED ADC
INPUT DRIVER NOISE
Using Equation 6-4 to Equation 6-6, the recommended
noise voltage density (eN) limit of the ADC input driver
is expressed in Equation 6-7:
ADC Input Driver
ADC
VN_ADC Input-Referred Noise
VN_RMS_Driver Noise
+- +
-
R
C
5
2RC
---------------
(Hz)
BWInput Driver 5 x fB
for a single-pole RC filter
THDInput Buffer ≤ THDADC -10 (dB)
VN_ADC Input-Referred Noise (V)
VREF
22
--------------=10
SNR
20
-----------–
VN_RMS_Driver Noise GN
eN
2
-------fB
(V)
VN_ADC Input-Referred Noise
VN_RMS_Driver Noise 1
5
---
2018 Microchip Technology Inc. DS20006122A-page 33
MCP33131/MCP33121/MCP33111-XX
EQUATION 6-7: NOISE DENSITY FOR ADC
INPUT DRIVER
Using Equation 6-7, the recommended maximum
noise voltage density limit for unity gain input driver for
single-ended input ADC can be estimated. Ta b l e 6 - 1 to
Table 6-3 show a few example results with GN = 1. The
user may use these tables as a reference when
selecting the ADC input driver amplifier.
TABLE 6-1: Noise Voltage Density (eN) of
Input Driver for MCP33131-XX
TABLE 6-2: Noise Voltage Density (eN) of
Input Driver for MCP33121-XX
TABLE 6-3: Noise Voltage Density (eN) of
Input Driver for MCP33111-XX
ADC
(Note 1)
RC
Filter
ADC Input Driver
Amplifier (GN = 1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Table 2)
Noise Voltage
Density (eN)
2.5V 81 78.8
V
3 MHZ7.3 nV/√Hz
4 MHz 6.3 nV/√Hz
5 MHZ5.6 nV/√Hz
3.3V 83 82.6 V
3 MHZ7.6 nV/√Hz
4 MHz 6.6 nV/√Hz
5 MHZ5.9 nV/√Hz
5V 87 79 V
3 MHZ7.3 nV/√Hz
4 MHz 6.3 nV/√Hz
5 MHZ5.6 nV/√Hz
Note 1: See Equation 6-4 for the ADC input-referred noise
calculation for single-ended input.
2: fB is -3dB bandwidth of the RC anti-aliasing filter.
V
Hz
-----------


eN
1
10
------1
GNfB
-------------------------- VREF 10
SNR
20
-----------–
1
5
---VN_ADC Input-Referred Noise
GN
eN
2
-------fB
ADC
(Note 1)
RC
Filter
ADC Input Driver
Amplifier (GN = 1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Note 2)
Noise Voltage
Density (eN)
2.5V 80 88.4
V
3 MHZ8.1 nV/√Hz
4 MHz 7.1 nV/√Hz
5 MHZ 6.3 nV/√Hz
3.3V 81.5 98.2 V
3 MHZ9.0 nV/√Hz
4 MHz 7.8 nV/√Hz
5 MHZ7.0 nV/√Hz
5V 83.5 118.1 V
3 MHZ10.9 nV/√Hz
4 MHz 9.4 nV/√Hz
5 MHZ8.4 nV/√Hz
Note 1: See Equation 6-4 for the ADC input-referred noise
calculation for single-ended input.
2: fB is -3dB bandwidth of the RC anti-aliasing filter.
ADC
(Note 1)
RC
Filter
ADC Input Driver
Amplifier (GN = 1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Note 2)
Noise Voltage
Density (eN)
2.5V 73.2 193.3
V
3 MHZ17.8 nV/√Hz
4 MHz 15.4 nV/√Hz
5 MHZ13.8 nV/√Hz
3.3V 73.5 246.6 V
3 MHZ22.7 nV/√Hz
4 MHz 19.7 nV/√Hz
5 MHZ17.6 nV/√Hz
5V 73.8 360.9 V
3 MHZ 33.3 nV/√Hz
4 MHz 28.8 nV/√Hz
5 MHZ25.8 nV/√Hz
Note 1: See Equation 6-4 for the ADC input-referred noise cal-
culation for single-ended input.
2: fB is -3dB bandwidth of the RC anti-aliasing filter.
DS20006122A-page 34 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.4 Device Operation
When the MCP33131/MCP33121/MCP33111-XX is
first powered-up, it self-calibrates internal systems and
enters input acquisition mode by itself. The device
operates in two phases: (a) Input Acquisition (Standby)
and (b) Data Conversion. Figure 6-4 shows the ADC
operating sequence.
6.4.1 INPUT ACQUISITION PHASE
(STANDBY)
During the input acquisition phase (tACQ), also called
Standby, the two input sampling capacitors, CS+ and
CS-, are connected to the AIN+ and AIN- pins,
respectively. The input voltage is sampled until a rising
edge on CNVST is detected. The input voltage should
be fully settled within 1/2 LSB during tACQ.
During this input acquisition time (tACQ), the ADC
consumes less than 1 A. The acquisition time (tACQ)
is user-controllable. This acquisition time (tACQ) can be
increased as long as needed for additional power
savings.
6.4.2 DATA CONVERSION PHASE
The start of the conversion is controlled by CNVST. On
the rising edge of CNVST, the sampled charge is
locked (sample switches are opened) and the ADC
performs the conversion. Once a conversion is started,
it will not stop until the current conversion is complete.
The data conversion time (tCNV) is not
user-controllable. After the conversion is complete and
the host lowers CNVST, the output data is presented on
SDO.
Any noise injection during the conversion phase may
affect the accuracy of the conversion. To reduce
environment noise, minimize I/O events and running
clocks during the conversion time.
The output data is clocked out MSB first. While the out-
put data is being transferred, the device enters the next
input acquisition phase.
FIGURE 6-4: Device Operating Sequence.
Note: Transferring output data during the
acquisition phase can disturb the next
input sample. It is highly recommended to
allow at least tQUIET (10 ns, typical)
between the last edge on the SPI
interface and the rising edge on CNVST.
See Figure 1-1 for tQUIET.
Operating tACQ
(b) All circuits are turned-on.
(a) ADC acquires input sample #1.
Condition
I
(c) Most analog circuits are
(a) Device is first powered-up and
(b) No ADC output is available yet.
(c) ADC output is not available yet.
t
ACQ
(b) Performs a power-up self-calibration.
IDDAN
(a) Conversion is initiated at the rising edge of CNVST.
(a) At the falling edge of CNVST,
ADC output is available at SDO.
(b) ADC output can be clocked out
(c) ADC acquires input sample #2.
(d) Most analog circuits are turned off.
Input Acquisition Data Conversion Input Acquisition
turned off.
SDO Output Data
~ 0.8 A
Off
(Standby) (Standby)
MCP331x1-10: 300 ns (typical)
by providing clocks.
t
CNV
tCYC = 1/fS
MCP331x1-05: 800 ns (typical)
MCP331x1-10: 700 ns (typical)
MCP331x1-05: 1200 ns (typical)
MCP331x1-10: 300 ns (typical)
MCP331x1-05: 800 ns (typical)
MCP331x1-10: ~ 1.6 mA
MCP331x1-05: ~ 1.4 mA
2018 Microchip Technology Inc. DS20006122A-page 35
MCP33131/MCP33121/MCP33111-XX
6.4.3 SAMPLE (THROUGHPUT) RATE
The device completes data conversion within the
maximum specification of the data conversion time
(tCNV). The continuous input sample rate is the inverse
of the sum of input acquisition time (tACQ) and data
conversion time (tCNV). Equation 6-8 shows the
continuous sample rate calculation using the minimum
and maximum specifications of the input acquisition
time (tACQ) and data conversion time (tCNV).
EQUATION 6-8: SAMPLE RATE
6.4.4 SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by the following equation:
EQUATION 6-9: SPI CLOCK FREQUENCY
REQUIREMENT
where fSCLK is the minimum SPI serial clock frequency
required to transfer all N-bits of output data during input
acquisition time (tACQ).
Table 6-4 and Tab le 6- 5 show the examples of calcu-
lated minimum SPI clock (fSCLK) requirements for vari-
ous input acquisition times for 1 Msps and 500 kSPS
family devices, respectively.
1
tACQ tCNV
+
----------------------------------
Sample Rate =
1
290ns 710ns+
-----------------------------------------1Msps=
(a) MCP331x1-10:
Sample Rate =
1
700ns 1300ns+
--------------------------------------------500kSPS=
(b) MCP331x1-05:
Sample Rate =
where N is the number of output data bits, given by
fSCLK
1
TSCLK
--------------- N
tACQ tQUIET tEN
+–
------------------------------------------------------==
tACQ NT
SCLK
tQUIET tEN
++=
N=16-bit for MCP33131-XX
=14-bit for MCP33121-XX
=12-bit for MCP33111-XX
TSCLK =Period of SPI clock
N x TSCLK =Output data window
tQUIET =Quiet time between the last output bit
and beginning of the next
conversion start.
=10 ns (min)
tEN =Output enable time = 10 ns (max), with
DVIO ≥2.3V
Note: See Figure 1-1 for digital interface timing dia-
gram.
TABLE 6-4: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-10
Input
Acquisition Time:
tACQ (nS)
(Note 4)
Data
Conversion Time:
tCNV (nS)
(Note 5)
SPI Clock (fSCLK) Speed Requirement
(Note 1), (Note 2) Sample Rate:
fS (Msps) Conditions
MCP33131-10
(16-bit)
MCP33121-10
(14-bit)
MCP33111-10
(12-bit)
250
750
69.57 MHz 60.87 MHz 52.17 MHz 1
85°C < TA≤ 125°C
(Note 3)
270 64 MHz 56 MHz 48 MHz 0.98
280 61.54 MHz 53.85 MHz 46.15 MHz 0.97
290
710
59.26 MHz 51.85 MHz 44.44 MHz 1
-40°C ≤TA≤ 85°C
300 57.15 MHz 50 MHz 42.86 MHz 0.99
320 53.33 MHz 46.67 MHz 40 MHz 0.97
400 42.11 MHz 36.84 MHz 30 MHz 0.9
540 30.77 MHz 26.92 MHz 23.08 MHz 0.8
720 22.86 MHz 20 MHz 17.14 MHz 0.7
720 17.2 MHz 15.05 MHz 12.9 MHz 0.6
1290 12.6 MHz 11.02 MHz 9.45 MHz 0.5
1750 9.04 MHz 7.91 MHz 6.78 MHz 0.4
2620 6.15 MHz 5.39 MHz 4.62 MHz 0.3
4290 3.75 MHz 3.28 MHz 2.81 MHz 0.2
9290 1.73 MHz 1.51 MHz 1.3 MHz 0.1
Note 1: This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the
ADC is operating in continuous input sampling mode.
2: See Equation 6-9 for the calculation of the SPI clock speed requirement.
3: In extended temperature range, the device takes longer data conversion time (tCNV: 750 nS, max). Using a shorter input acquisition time
is recommended (tACQ: 250 nS) for 1 Msps throughput rate.
4: Input acquisition time (tACQ) is user-controllable.
5: Data conversion time (tCNV) is not user-controllable.
DS20006122A-page 36 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.5 Transfer Function
The pseudo-differential analog input is:
VIN = (VIN+) - (VIN-)
where VIN+ is the analog input voltage at AIN+ pin with
respect to the ground reference (GND), and Vin- is the
voltage at AIN- pin, which is 0V when tied to the analog
input ground reference (GND).
The LSB size is given by Equation 6-10. and an
example of LSB size vs. reference voltage is
summarized in Ta b l e 6 - 6 .
EQUATION 6-10: LSB SIZE - EXAMPLE
where N is the resolution of the ADC in bits.
TABLE 6-6: LSB SIZE VS. REFERENCE
Figure 6-5 shows the ideal transfer function and
Table 6-7 shows the digital output codes for the
MCP33131/MCP33121/MCP33111-XX.
FIGURE 6-5: Ideal Transfer Function.
TABLE 6-5: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-05
Input
Acquisition Time:
tACQ (nS)
(Note 3)
Data
Conversion Time:
tCNV (nS)
(Note 4)
SPI Clock (fSCLK) Speed Requirement
(Note 1), (Note 2) Sample Rate:
fS (kSPS) Conditions
MCP33131-05
(16-bit)
MCP33121-05
(14-bit)
MCP33111-05
(12-bit)
700
1300
23.53MHz 20.59 MHz 17.65 MHz 500
-40°C ≤TA≤ 125°C
740 22.22 MHz 19.44 MHz 16.67 MHz 490
790 20.78 MHz 18.18 MHz 15.58 MHz 480
930 17.58 MHz 15.39 MHz 13.19 MHz 450
1200 13.56 MHz 11.86 MHz 10.17 MHz 400
1560 10.39 MHz 9.09 MHz 7.79 MHz 350
2030 7.96 MHz 6.97 MHz 5.97 MHz 300
2700 5.97 MHz 5.22MHz 4.48 MHz 250
3700 4.35 MHz 3.8 MHz 3.26 MHz 200
5370 2.99 MHz 2.62 MHz 2.25 MHz 150
8700 1.84 MHz 1.61 MHz 1.38 MHz 100
Note 1: This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the
ADC is operating in continuous input sampling mode.
2: See Equation 6-9 for the calculation of the SPI clock speed requirement.
3: Input acquisition time (tACQ) is user-controllable.
4: Data conversion time (tCNV) is not user-controllable.
Reference
Voltage
(VREF)
LSB Size
MCP33131-XX
(16-bit)
MCP33121-XX
(14-bit)
MCP33111-XX
(12-bit)
2.5V 38.2V 152.6 V 0.6104 mV
2.7V 41.2 V 164.8 V 0.6592 mV
3V 45.8 V 183.1 V 0.7324 mV
3.3V 50.4 V 201.4 V 0.8057 mV
3.5V 53.4 V 213.6 V 0.8545 mV
4V 61.0 V 244.1 V 0.9766 mV
4.5V 68.7 V 274.7 V 1.0986 mV
5V 76.3 V 305.2 V 1.2207 mV
LSB VREF
2N
-------------=
5.1 77.8 V311.3 V 1.2451 mV
VREF
Analog Input Voltage
0V
VREF - 1 LSB
0V + 0.5 LSB
VREF - 1.5 LSB
Digital Output Code (Unipolar Straight Binary)
111 ...111
100 ...000
111 ...110
000 ...001
000 ...000
0V+ 1 LSB 2
2018 Microchip Technology Inc. DS20006122A-page 37
MCP33131/MCP33121/MCP33111-XX
6.6 Digital Output Code
The digital output code is proportional to the input
voltage. The output data is in unipolar straight binary
format. The following is an example of the output code:
(a) for a zero or negative input:
Analog Input: VIN ≤ 0 (V)
Output Code: 0000...0000
(b) for a mid-scale input:
Analog Input: VIN = +VREF /2 (V)
Output Code: 1000...0000
(c) for a positive full-scale input:
Analog Input: VIN = +VREF (V)
Output Code: 1111...1111
The code will be locked at 1111...11 for all voltages
greater than (VREF - 1 LSB) and 0000...00 for
voltages less than 0V. Tab l e 6-7 shows an example of
output codes of various input levels.
TABLE 6-7: DIGITAL OUTPUT CODE
Input Voltage (V)
Digital Output Codes
MCP33131-XX
(16-bit)
MCP33121-XX
(14-bit)
MCP33111-XX
(12-bit)
VREF 1111-1111-1111-1111 11-1111-1111-1111 1111-1111-1111
VREF - 1 LSB 1111-1111-1111-1111 11-1111-1111-1111 1111-1111-1111
.
.
.
.
.
.
.
.
VREF/2 1000-0000-0000-0000 10-0000-0000-0000 1000-0000-0000
.
.
.
.
.
.
.
.
2LSB 0000-0000-0000-0010 00-0000-0000-0010 0000-0000-0010
1LSB 0000-0000-0000-0001 00-0000-0000-0001 0000-0000-0001
≤ 0V 0000-0000-0000-0000 00-0000-0000-0000 0000-0000-0000
DS20006122A-page 38 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
7.0 DIGITAL SERIAL INTERFACE
The device has a SPI-compatible serial digital
interface using four digital pins: CNVST, SDI, SDO and
SCLK.
Figure 7-1 shows the connection diagram with the host
device and Figure 7-2 shows the SPI-compatible serial
interface timing diagram.
The SDI pin can be tied to the digital I/O interface
supply voltage (DVIO) or just maintain logic “High” level
by the host. The CNVST pin is used for both chip select
(CS) and conversion-start control.
A rising edge on CNVST initiates the conversion
process. Once the conversion is initiated, the device
will complete the conversion regardless of the state of
CNVST. This means the CNVST pin can be used for
other purposes during tCNV.
When the conversion is complete, the output is
available at SDO by lowering CNVST. Data is sent
MSB-first and changes on the falling edge of SCLK.
Output data can be sampled on either edge of SCLK.
However, a digital host capturing data on the falling
edge of SCLK can achieve a faster read out rate.
SDO returns to high-Z state after the last data bit is
clocked out or when CNVST goes high, whichever
occurs first.
FIGURE 7-1: Digital Interface Connection
Diagram.
FIGURE 7-2: SPI Compatible Serial Interface Timing Diagram (16-bit device).
CNVST
SCLK
SDO
CS
SCLK
SDI
(a) MCP33131/21/11-XX (b) Host Device (Master)
Note 1: Adding this pull-up is needed when monitoring
status of Recalibrate.
DVIO
(Note 1)
10 k
SDI
DVIO
CNVST
SDO
SCLK 12314 15 16
4
D15 D14 D13 D12 D2 D1 D0
ADC State
(MSB)
Hi-Z Hi-Z
tCNVH
tCNV (MAX)
tSCLK
tSCLK_L tSCLK_H
tDO
tDIS
Conversion
(a) Exit input acquisition mode and
(b) Enter new conversion mode
Note 1: SDI must maintain “High” during the entire tCYC.
(Note 2)
Input Acquisition
Input Acquisition
(tCNV)(tACQ)
(tACQ)
tCYC
2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored.
SDI = DVIO
tSU_SDIH_CNV
(Note 1)
tEN
tQUIET
tEN
(Note 3)
(Note 4)
3: tEN when CNVST is lowered after tCNV (Max).
4: tEN when CNVST is lowered before tCNV (Max).
= 1/fS
(Note 5)
5: Recommended data detection: Detect SDO on the falling edge of SCLK.
2018 Microchip Technology Inc. DS20006122A-page 39
MCP33131/MCP33121/MCP33111-XX
7.1 Recalibrate Command
The user may use the recalibrate command in the
following cases:
• When the reference voltage was not fully settled
during the first-power sequence.
• During operation, to ensure optimum performance
across varying environment conditions, such as
reference voltage and temperature.
A self-calibration is initiated by sending the recalibrate
command. The host device sends a recalibrate
command by transmitting 1024 SCLK pulses (including
the clocks for data bits) while the device is in the
acquisition phase (Standby).
The device drives SDO low during the recalibration
procedure, and returns to high-Z once completed. The
status of the recalibration procedure can be monitored
by placing a pull-up on SDO, so that SDO goes high
when the recalibration is complete.
Figure 7-3 shows the recalibrate command timing
diagram. The calibration takes approximately 500 ms
(tCAL).
FIGURE 7-3: Recalibrate Command Timing Diagram.
Note: When the device performs a self-calibration, it is important to note that both AVDD and the reference
voltage (VREF) must be stabilized for a correct calibration. This is also true when the device is first
powered-up, the reference voltage (VREF) must be stabilized before self-calibration begins. This means
the VREF must be provided prior to supplying AVDD or within about 64 ms after supplying AVDD.
1024 clocks
Start recalibration
tCAL
16
1
(SPITM Recalibrate command)
Hi-Z
Hi-Z
Note
“Low”
1024
“High” with Pull-up
Hi-Z
ADC Output Data Stream
“High” with Pull-up
2: The 1024 clocks include the clocks for data bits.
tCNV
Complete da
ta reading
Finish recalibration
Device Recalibration
(Note 3)
(Note 2)
1: SDI must remain “High” during the entire recalibration cycle.
(Note 4)
3: SDO outputs “Low” during calibration, and Hi-Z when exiting the calibration.
SDI = DVIO
4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.
(Note 1)
CNVST
SDO
SCLK
ADC State
23 15
DS20006122A-page 40 2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
NOTES:
2018 Microchip Technology Inc. DS20006122A-page 41
MCP33131/MCP33121/MCP33111-XX
8.0 TERMINOLOGY
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
CNVST input and when the input signal is held for a
conversion.
Differential Nonlinearity
(DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly
1 LSB apart. DNL is the deviation from this ideal value.
No missing codes to 16-bit resolution indicates that all
65,536 codes (16,384 codes for 14-bit, 4096 codes for
12-bit) must be present over all the operating
conditions.
Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
EQUATION 8-1:
SNR is either given in units of dBc (dB to carrier), when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale), when the power
of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
EQUATION 8-2:
SINAD is either given in units of dBc (dB to carrier),
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale), when the
power of the fundamental is extrapolated to the
converter full-scale range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
EQUATION 8-3:
Gain Error
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range. Gain error is usually expressed in LSB or as a
percentage of full-scale range (%FSR).
Offset Error
Offset error is the difference between the ideal voltage
(0V + 0.5 LSB) that produces the first code transition
(“000... 000” to “000... 001”) and the actual voltage pro-
ducing that code.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value at across the TMIN to TMAX range.
The value is normalized by the reference voltage and
expressed in V/oC or ppm/oC.
Maximum Conversion Rate
The maximum clock rate at which parametric testing is
performed.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
SNR 10
PS
PN
-------



log=
SINAD 10
PS
PDPN
+
----------------------



log=
10–=10
SNR
10
-----------
–
10
THD
10
------------
–
–log
ENOB SINAD 1.76–
6.02
----------------------------------=
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 42 2018 Microchip Technology Inc.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 8-4:
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 8-5:
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential or pseudo-differential input pair. The
common-mode signal can be an AC or DC signal or a
combination of the two. CMRR is measured using the
ratio of the differential signal gain to the common-mode
signal gain and expressed in dB with the following
equation:
EQUATION 8-6:
THD 10
PS
PD
--------



log=
THD 20
V2
2V3
2V4
2
Vn
2
++++
V1
2
------------------------------------------------------------------log–=
Where:
V1= RMS amplitude of the
fundamental frequency
V1 through Vn= Amplitudes of the second
through nth harmonics
CMRR 20
ADIFF
ACM
------------------



log=
Where:
ADIFF =Output Code/Differential Voltage
ADIFF =Output Code/Common-Mode Voltage
2018 Microchip Technology Inc. DS20006122A-page 43
MCP33131/MCP33121/MCP33111-XX
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
PIN 1
10-Lead TDFN (3x3x0.9 mm) Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
311
1839
256
10-Lead MSOP (3x3 mm) Example
31-10
839256
31-10 = MCP33131-10
31-05 = MCP33131-05
21-10 = MCP33121-10
21-05 = MCP33121-05
11-10 = MCP33111-10
11-05 = MCP33111-05
XXXX
YYWW
NNN
PIN 1
311 = MCP33131-10
310 = MCP33131-05
211 = MCP33121-10
210 = MCP33121-05
111 = MCP33111-10
110 = MCP33111-05
Corresponding Part Number:
Corresponding Part Number:
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 44 2018 Microchip Technology Inc.
0.13 C A B
12
N
TOP VIEW
SIDE VIEW END VIEW
Microchip Technology Drawing C04-021D Sheet 1 of 2
http://www.microchip.com/packaging
For the most current package drawings, please see the Microchip Packaging Specification located atNote:
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
D
EE1
D
2
E1
2
E
2
0.20 H
0.25 C
0.20 H
A
B
e
8X b
AA2
A1 0.10 C
8X
C
SEATING
PLANE
H
SEE DETAIL A
2018 Microchip Technology Inc. DS20006122A-page 45
MCP33131/MCP33121/MCP33111-XX
Microchip Technology Drawing C04-021D Sheet 2 of 2
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
3.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
Notes:
2.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M.
protrusions shall not exceed 0.15mm per side.
L1Footprint
Mold Draft Angle
Lead Width
Lead Thickness c
b
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
e
N
Units
0.95 REF
-
-
0.08
0.15
0.23
0.33
MILLIMETERS
0.50 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
0.40
0.00
0.75
MIN NOM
1.10
0.80
0.15
0.95
MAX
10
-
--
8°0°
-
C
SEATING
PLANE
L
(L1)
c
Ĭ
Ĭ
DETAIL A
Foot Angle - 15°5°
Ĭ1
4X Ĭ1
4X Ĭ1
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 46 2018 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2021B
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Overall Width
Contact Pitch
Z
MILLIMETERS
0.50 BSC
MIN
E
MAX
4.40
5.80
Contact Pad Length (X10)
Contact Pad Width (X10)
Y1
X1
1.40
0.30
GDistance Between Pads (X8) 0.20
NOM
Distance Between Pads (X5) G1 3.00
E
C
ZG1
X1
G
Y1
SILK SCREEN
2018 Microchip Technology Inc. DS20006122A-page 47
MCP33131/MCP33121/MCP33111-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 48 2018 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc. DS20006122A-page 49
MCP33131/MCP33121/MCP33111-XX
APPENDIX A: REVISION HISTORY
Revision A (November 2018)
• Original release of this document.
2018 Microchip Technology Inc. DS20006122A-page 50
MCP33131/MCP33121/MCP33111-XX
NOTES:
MCP33131/MCP33121/MCP33111-XX
DS20006122A-page 51 2018 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. ─X/XXX
Tape PackageTemperat ure
Range
Device
Device: MCP33131-10: 1 Msps 16-Bit Single-Ended Input SAR ADC
MCP33121-10: 1 Msps 14-Bit Single-Ended Input SAR ADC
MCP33111-10: 1 Msps 12-Bit Single-Ended Input SAR ADC
MCP33131-05: 500 kSPS 16-Bit Single-Ended Input SAR ADC
MCP33121-05: 500 kSPS 14-Bit Single-Ended Input SAR ADC
MCP33111-05: 500 kSPS 12-Bit Single-Ended Input SAR ADC
Input Type Blank = Single-Ended Input
Sample Rate: 10 = 1 Msps
05 = 500 kSPS
Tap e and
Reel Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel
Temperature
Range:
E= -40C to +125C (Extended)
I= -40C to +85C (Industrial)
Package: MS = Plastic Micro Small Outline Package (MSOP), 10-Lead
MN = Thin Plastic Dual Flat No Lead Package (TDFN),
10-Lead
Note 1: Tape and Reel identifier appears only in the catalog part number
description. This identifier is used for ordering purposes and is not
printed on the device package. Check with your Microchip Sales Office
for package availability with the Tape and Reel option.
─XX
Sample Rate
Examples:
a) MCP33131-10-I/MS: 1 Msps, 10LD MSOP,
16-bit device
b) MCP33131-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
16-bit device
c) MCP33131-10-I/MN: 1 Msps, 10LD TDFN,
16-bit device
d) MCP33131-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
16-bit device
e) MCP33121-10-I/MS: 1 Msps, 10LD MSOP,
14-bit device
f) MCP33121-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
14-bit device
g) MCP33121-10-I/MN: 1 Msps, 10LD TDFN,
14-bit device
h) MCP33121-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
14-bit device
i) MCP33111-10-I/MS: 1 Msps, 10LD MSOP,
12-bit device
j) MCP33111-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
12-bit device
k) MCP33111-10-I/MN: 1 Msps, 10LD TDFN,
12-bit device
l) MCP33111-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
12-bit device
m) MCP33131-05-I/MS: 500 kSPS, 10LD MSOP,
16-bit device
n) MCP33131-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
16-bit device
o) MCP33131-05-I/MN: 500 kSPS, 10LD TDFN,
16-bit device
p) MCP33131-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
16-bit device
q) MCP33121-05-I/MS: 500 kSPS, 10LD MSOP,
14-bit device
r) MCP33121-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
14-bit device
s) MCP33121-05-I/MN: 500 kSPS, 10LD TDFN,
14-bit device
t) MCP33121-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
14-bit device
u) MCP33111-05-I/MS: 500 kSPS, 10LD MSOP,
12-bit device
v) MCP33111-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
12-bit device
w) MCP33111-05-I/MN: 500 kSPS, 10LD TDFN,
12-bit device
x) MCP33111-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
12-bit device
Input Type
X
Reel
and
2018 Microchip Technology Inc. DS20006122A-page 52
MCP33131/MCP33121/MCP33111-XX
NOTES:
2018 Microchip Technology Inc. DS20006122A-page 53
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3911-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20006122A-page 54 2018 Microchip Technology Inc.
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