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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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September 2015
©2015 Fairchild Semiconductor Corporation
FDMS8350LET40 Rev.1.0 www.fairchildsemi.com
1
FDMS8350LET40 N-Channel PowerTrench® MOSFET
Bottom
Power 56
Top Pin 1
G
SSS
D
DDD
D
D
D
D
S
S
S
G
Pin 1
FDMS8350LET40
N-Channel PowerTrench® MOSFET
40 V, 300 A, 0.85 mΩ
Features
Max rDS(on) = 0.85 mΩ at VGS = 10 V, ID = 47 A
Max rDS(on) = 1.2 mΩ at VGS = 4.5 V, ID = 38 A
Advanced Package and Silicon Combination for Low rDS(on)
and High Efficiency
MSL1 Robust Package Design
100% UIL Tested
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor‘s advanced PowerTrench® process that has
been especially tailored to minimize the on-state resistance and
yet maintain superior switching performance.
Applications
Primary DC-DC MOSFET
Secondary Synchronous Rectifier
Load Switch
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 40 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous TC = 25 °C (Note 5) 300
A
-Continuous TC = 100 °C (Note 5) 212
-Continuous TA = 25 °C (Note 1a) 49
-Pulsed (Note 4) 1464
EAS Single Pulse Avalanche Energy (Note 3) 1176 mJ
PDPower Dissipation TC = 25 °C 125 W
Power Dissipation TA = 25 °C (Note 1a) 3.33
TJ, TSTG Operating and Storage Junction Temperature Range -55 to + 175 °C
RθJC Thermal Resistance, Junction to Case 1.2 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 45
Device Marking Device Package Reel Size Tape Width Quantity
FDMS8350L FDMS8350LET40 Power 56 13 ’’ 12 mm 3000 units
www.fairchildsemi.com
2
©2015 Fairchild Semiconductor Corporation
FDMS8350LET40 Rev.1.0
FDMS8350LET40 N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min. Typ. Max. Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 40 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 17 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.8 3.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -6 mV/°C
rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 47 A 0.68 0.85 mΩVGS = 4.5 V, ID = 38 A 0.96 1.2
VGS = 10 V, ID = 47 A, TJ = 150 °C 1.1 1.4
gFS Forward Transconductance VDS = 5 V, ID = 47 A 247 S
Ciss Input Capacitance VDS = 20 V, VGS = 0 V,
f = 1 MHz
11850 16590 pF
Coss Output Capacitance 3430 4805 pF
Crss Reverse Transfer Capacitance 69 100 pF
RgGate Resistance 0.1 1.2 2.4 Ω
td(on) Turn-On Delay Time VDD = 20 V, ID = 47 A,
VGS = 10 V, RGEN = 6 Ω
32 51 ns
trRise Time 19 34 ns
td(off) Turn-Off Delay Time 74 118 ns
tfFall Time 15 27 ns
QgTotal Gate Charge VGS = 0 V to 10 V VDD = 20 V,
ID = 47 A
156 219 nC
QgTotal Gate Charge VGS = 0 V to 4.5 V 73 102 nC
Qgs Gate to Source Charge 33 nC
Qgd Gate to Drain “Miller” Charge 16 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2 V
VGS = 0 V, IS = 47 A (Note 2) 0.8 1.3
trr Reverse Recovery Time IF = 47 A, di/dt = 100 A/μs81 129 ns
Qrr Reverse Recovery Charge 82 131 nC
Notes:
1. RθJA is deter mined with th e de vice m ount ed on a 1 in2 pad 2 oz co pp er pad on a 1.5 x 1 .5 in. boar d of FR- 4 ma terial . RθJC is guaranteed by design while RθCA is deter mined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 1176 mJ is based on starti ng TJ = 25 °C, L = 3 mH, IAS = 28 A, VDD = 40 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 87 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actua l continuous current will be limited by thermal & electro-mechanical application board design.
G
DF
DS
SF
SS
a. 45 °C/W when mounted on a
1 in2 pad of 2 oz copper.
G
DF
DS
SF
SS
b. 115 °C/W when mounted on a
minimum pad of 2 oz copper.
www.fairchildsemi.com
3
©2015 Fairchild Semiconductor Corporation
FDMS8350LET40 Rev.1.0
FDMS8350LET40 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted.
Figure 1.
0.00.51.01.52.02.53.0
0
80
160
240
320
VGS = 4 V VGS = 3.5 V
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 80 160 240 320
0
3
6
9
12
15
VGS = 3.5 V
PULSE DURAT ION = 80 μs
DUTY CYCLE = 0.5% MA X
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, D RA IN CU RR ENT (A)
VGS = 4 V VGS = 4.5 V
VGS = 3 V
VGS = 10 V
Normalized On-Resistance
vs. Drain Current and Gate Voltage
Figure 3. Normalized On Resistance
-75 -50 -25 0 25 50 75 100 125 150 175
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
ID = 47 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
vs. Junction Temperature Figure 4.
0246810
0
5
10
15
20
TJ = 150 oC
ID = 47 A
TJ = 25 oC
VGS, G ATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN T O
SOURCE ON-RESIST ANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs. Gate to
Source Voltage
Figure 5. Transfer Characteristics
012345
0
80
160
240
320
TJ = 175 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MA X
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GA T E TO SOURCE VOL TAGE (V)
Figure 6.
0.00.20.40.60.81.01.2
0.001
0.01
0.1
1
10
100
320
TJ = -55 oC
TJ = 25 o C
TJ = 175 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FO RW ARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs. Source Current
www.fairchildsemi.com
4
©2015 Fairchild Semiconductor Corporation
FDMS8350LET40 Rev.1.0
FDMS8350LET40 N-Channel PowerTrench® MOSFET
Figure 7.
0 34 68 102 136 170
0
2
4
6
8
10 ID = 47 A
VDD = 25 V
VDD = 20 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
Gate Charge Characteristics Figure 8.
0.1 1 10 40
10
100
1000
10000
100000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF )
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Cap a cit a nce vs. D rai n
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100 1000 10000
1
10
100
200
TJ = 125 oC
TJ = 25 oC
TJ = 150 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRE NT (A)
Unc l amp ed In d uc t ive
Switching Capability Figure 10.
25 50 75 100 125 150 175
0
80
160
240
320
VGS = 4.5 V
RθJC = 1.2 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CA SE TEMPERATURE (oC)
Maximum Continuous Drain
Current vs. Case Temperature
Figure 11. Forward Bias Safe
Operating Area
0.01 0.1 1 10 100 500
0.1
1
10
100
1000
6000
10 μs
CURVE BENT TO
MEASURED DATA
100 μs
10 ms
100 ms/ DC
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS ARE A IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 1.2 oC/W
TC = 25 oC
Figure 12.
10-5 10-4 10-3 10-2 10-1 1
100
1000
10000
50000
SINGLE PULSE
RθJC = 1.2 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Single Pulse Maximum
Power Dissipation
Typical Characteristics TJ = 25°C unless otherwise noted.
www.fairchildsemi.com
5
©2015 Fairchild Semiconductor Corporation
FDMS8350LET40 Rev.1.0
FDMS8350LET40 N-Channel PowerTrench® MOSFET
Figure 13. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 1
0.001
0.01
0.1
1
2
SINGL E PU L SE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESIST ANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1t2
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 1.2 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
Typical Characteristics TJ = 25°C unless otherwise noted.
C
L
L
C
PKG
PKG
5.10
4.90
6.25
5.90
C
1.27
3.81
4.33
4.13
PIN #1
INDICATOR
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1.27
3.81
1.27
6.61
3.81
4.79
1234
8567
14
85
LAND PATTERN
RECOMMENDATION
14
8
0.10 C A B
4.66
4.46
5
0.65
0.55
1.14
A
B
(0.38)
0.61
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08JREV3.
SEE
DETAIL A
SCALE: 2:1
0.25
0.15
0.08 C
PIN #1
IDICATOR
SEATING
PLANE
0.10 C
1.10
0.90
KEEP OUT AREA
4.42
3.65
(0.35)
0.05
0.00
5.10
0.47
0.37 (8X)
0.70
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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