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Application Note 1596
ISL28233SOICEVAL1Z Evaluation Board User’s Guide
Introduction
The ISL28233SOICEVAL1Z Evaluation Board is designed
to evaluate the performance of the ISL28233 Chopper
Stabilized op amp. The evaluation board contains the
circuitry needed to evaluate the high performance of the
ISL28233 amplifier. The ISL28233 chopper stabilized
rail-to-rail dual op amp features a low 8µV maximum
VOS over-temperature and a 0.1Hz 1/f noise corner
frequency enabling very high gain single-stage DC
amplifiers that can operate from single cell batteries
while consuming only 20µA of current. The
ISL28233SOICEVAL1Z evaluation board can be
configured as a precision high-gain (G = 10,000V/V)
differential amplifier and demonstrates the level of
performance possible with this type of amplifier while
operating from battery voltages as low as 1.65V.
Reference Documents
•ISL28233 Data Sheet
Evaluation Board Key Features
• Single Supply Operation: +1.65V to +5.5V
• Dual Supply Operation: ±0.825V to ±2.75V
• Singled-Ended or Differential Input Operation with
High Gain (G = 10,000V/V)
• External VREF input
• Banana Jack Connectors for Power Supply and VREF
Inputs
• BNC Connectors for Op Amp Input and Output
Terminals
• Convenient PCB pads for Op Amp Input/Output
impedance loading.
Power Supplies (Figure 2)
External power connections are made through the V+,
V-, VREF, and GND connections on the evaluation board.
The circuit can operate from a single supply or from dual
supplies. For single supply operation, the V- and GND
pins are tied together to the negative or ground
reference of the power supply. For split supplies, V+ and
V- terminals connect to their respective supply terminals.
De-coupling capacitors C2 and C4 provide low-frequency
power-supply filtering, while additional capacitors, C3
and C5, which are connected close to the part, filter out
high frequency noise. Anti-reverse diode D1 (optional)
protects the circuit in the momentary case of accidentally
reversing the power supplies to the evaluation board.
The VREF pin can be connected to ground to establish a
ground referenced input for split supply operation, or can
be externally set to any reference level for single supply
operation.
VREF
IN -
IN +
GND
1MΩ
OPEN
OUT
ISL28233
V-
0Ω
VCM
IN-
IN+
VREF
V+
100Ω
100Ω
-
+
100kΩOPEN
FIGURE 1. BASIC DIFFERENTIAL AMPLIFIER CONFIGURATION
R13/R23
R11/R24
R14/R21
R18/R19
R26/R27
1/7
R28/R29
INA-
INA+
INB-
INB+
6
5
2
3
8
4
R15/R22
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
October 5, 2010
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Amplifier Configuration (Figure 3)
The schematic of the op amp input stage with the
components supplied is shown in Figure 3, with a closed
loop gain of 10,000. The circuit implements a Hi-Z
differential input with unbalanced common mode
impedance. The differential amplifier gain is expressed in
Equation 1:
For single-ended input with an inverting gain
G = -10,000V/V, the IN+ input is grounded and the
signal is supplied to the IN- input. VREF must be
connected to a reference voltage between the V+ and
V- supply rails. For non-inverting operation with
G = 10,001V/V, the IN- input is grounded and the
signal is supplied to the IN+ input. The non-inverting
gain is strongly dependent on any resistance from IN-
to GND. For good gain accuracy, a 0Ω resistor should
be installed on the empty R5 pad.
User-Selectable Options
(Figures 3 and 4)
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier
inputs, the VREF input, outputs and the amplifier
feedback loops.
A voltage divider (Figure 3, R18 and R15) can be added
to establish a power supply-tracking common mode
reference using the VREF input. The inverting and
non-inverting inputs have additional resistor placements
for adding input attenuation, or to establish input DC
offsets through the VREF pin.
The output (Figure 4) also has additional resistor and
capacitor placements for filtering and loading.
NOTE: Operational amplifiers are sensitive to output
capacitance and may oscillate. In the event of oscillation,
reduce output capacitance by using shorter cables, or
add a resistor in series with the output.
FIGURE 2. POWER SUPPLY CIRCUIT
CLOSE TO DUT
21 R31
21 R16
3
2
1
D1
C2 C4
C3
3
2
1
J11
1
J14
1
J12
1
J13
3
2
1
J6
1
J8
0
1µF
0.01µF
0
1µF
0.01µF
C5
V- V+ VREF
VOUT VIN+
(VIN-)RF
(• RIN)⁄–VREF
+= (EQ. 1)
IN+A
IN-A
DNP
R5
R4
J2
J1 R1
R2
R14
R18
R15
R13
R11
100
DNP
DNP
0
100
DNP
1M
OPEN
100k
VREF
TO INA -
TO INA +
FROM OUTA
FIGURE 3. INPUT STAGE
C6
OUT A
R26
J12
C8
R28
DNP
OPEN
0
FIGURE 4. OUTPUT STAGE
C6
OUT_A
TABLE 1. ISL28233SOICEVAL1Z COMPONENTS PARTS LIST
DEVICE # DESCRIPTION COMMENTS
C2, C4 CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling
C3, C5 CAP, SMD, 0603, 0.01µF, 50V, 10%, X7R, ROHS Power Supply Decoupling
C1, C6, C7, C8, C9, C10 CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable capacitors - not populated
R11, R14, R21, R24 RESISTOR, SMD, 0603, 100Ω, 1%, 1/16W, ROHS Gain Setting Resistor
R13, R23 RESISTOR, SMD, 0603, 10MΩ, 1%, 1/16W, ROHS Gain Setting Feedback Resistor
R1-R3, R5-R8, R10, R12, R15,
R17, R20, R22, R28, R29, R30,
R32, R34, R35, R36
RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable resistors - not populated
D1 40V SERIES SCHOTTKY BARRIER DIODE Reverse Power Protection
U1 (ISL28233FBZ) ISL28233FBZ, IC-RAIL-TO-RAIL OP AMP, SOIC, ROHS
Application Note 1596
3
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
AN1596.0
October 5, 2010
Application Note 1596
ISL28233SOICEVAL1Z Top View
4AN1596.0
October 5, 2010
Application Note 1596
ISL28233SOICEVAL1Z Schematic Diagram
IN+
CLOSE TO DUT
NODEIN- OUT IN-OUT NODEIN+
DNP
R18
J17
J20
DNP
1
DNP
2
1R31
2
1R16
2
1
J23
1
J18
2
1
J24
2
1
J22
2
1
J21
2
1
2
1
J19
1
2
1R36
21 R32 2
1R34
21 R35
1R30
32
1
D1
21
C1
21 R22
2
1R19
R21
2
1R20
1
C10
21 R8
21 R7
2
1R5
21 R4 R24
C2 C4
C3
5
4
3
2
1J15
5
4
3
2
1J16
5
4
3
2
1
J2
5
4
3
2
1
J1
5
4
3
2
1
J3
5
4
3
2
1
J4
3
2
1
J11
1
J14
1
J12
1
J13
3
2
1
J6
1
J8
21 R26
21 R27
21
C7
21
C6
21
C8
21
C9
21 R1
21 R29
2
1R25
R23
2
1R6
2
1R17
21 R2
21 R28
R14
2
R3
2
1
2
1R15
2
1R12
2
1R10
R13R11
8
7
54
3
2
1
U1
OPEN
DNP
0
1µF
100k
0.01µF
0
DNP
0
DNP
OPEN
DNP
OPEN
OPEN
0
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
OPEN
DNP 100k
0 DNP
1µF
OPEN
DNP
DNP
100
100
100100 1M1M
SOIC8
0
6
2
2
0.01µF
C5
2
2
5
6
7
8
3
4
1
2
GENERIC
PACK.
V- V+ VREF
VREF
IN-A
IN+A
IN-B
IN+B
OUT A
OUT B
Mouser Electronics
Authorized Distributor
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