A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Discontinued Product This device is no longer in production. The device should not be purchased for new design applications. Samples are no longer available. Date of status change: October 31, 2011 Recommended Substitutions: * for the A1242ELHLT-I2-T use the A1244LLHLX-I2-T * for the A1242ELHLT-I1-T use the A1244LLHLX-I1-T * for the A1242LLHLT-I2-T use the A1244LLHLX-I2-T * for the A1242LLHLT-I1-T use the A1244LLHLX-I1-T * for the A1242EUA-I1-T and A1242LUA-I1-T use the A1244LUA-I1-T * for the A1242LUA-I2-T use the A1244LUA-I2-T NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Features and Benefits Description Chopper stabilization Superior temperature stability Extremely low switchpoint drift Insensitive to physical stress Reverse battery protection Solid-state reliability Small size Robust EMC capability High ESD ratings (HBM) The A1242 Hall effect latch is a two-wire latch especially suited for operation over extended temperature ranges, from -40 to +150C. Superior high-temperature performance is made possible through the Allegro(R) patented dynamic offset cancellation technique, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. Packages: 3 pin SOT23W (suffix LH), and 3 pin SIP (suffix UA) The current-switching output technique allows for the reduction in cost in the wiring harness because only two connections to the device are required. The current-switching output structure also inherently provides more immunity against EMC/ESD transients. These devices have low magnetic thresholds, thereby enabling more flexibility in the magnetic circuit design. The Hall effect latch will be in the high output current state in the presence of a magnetic South Pole field of sufficient magnitude and will remain in this state until a sufficient North Pole field is present. The A1242 includes the following on a single silicon chip: a voltage regulator, Hall-voltage generator, small-signal amplifier, chopper stabilization, Schmitt trigger, and a current source output. Advanced BiCMOS wafer fabrication processing takes advantage of low-voltage requirements, component Continued on the next page... Not to scale Functional Block Diagram VCC Regulator To All Subcircuits Amp Sample and Hold Dynamic Offset Cancellation Clock/Logic Low-Pass Filter GND Package UA Only 1242-DS, Rev. 6 GND A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Description (continued) matching, very low input-offset errors and small component geometries. provide magnetically optimized solutions for most applications. Package LH is a SOT23W, a miniature low-profile surface-mount package, while package UA is a three-pin ultramini SIP for through- Suffix `L-' devices are rated for operation over a temperature range of -40C to +150C; suffix `E-' devices are rated for operation over a temperature range of -40C to +85C. Two A1242 package styles hole mounting. Each package is available lead (Pb) free, with 100% matte tin plated leadframes. Selection Guide Part Number Packaging* Mounting A1242ELHLT-I1-T 7-in. reel, 3000 pieces/reel A1242ELHLT-I2-T A1242EUA-I1-T Bulk, 500 pieces/bag A1242LLHLT-I1-T 7-in. reel, 3000 pieces/reel A1242LLHLT-I2-T A1242LUA-I1-T Bulk, 500 pieces/bag A1242LUA-I2-T *Contact Allegro for additional packing options. 3-pin SOT23W surface mount 3-pin SIP through hole 3-pin SOT23W surface mount 3-pin SIP through hole Low Current, ICC(L) (mA) 5.0 to 6.9 2.0 to 5.0 5.0 to 6.9 5.0 to 6.9 2.0 to 5.0 5.0 to 6.9 2.0 to 5.0 Ambient, TA (C) BRP(MIN) (G) BOP(MAX) (G) -80 80 -40 to 85 -40 to 150 Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit* Supply Voltage VCC 28 V Reverse Supply Voltage VRCC -18 V Magnetic Flux Density B Unlimited G Range E -40 to 85 C Range L Operating Ambient Temperature TA -40 to 150 C Maximum Junction Temperature TJ(max) 165 C Tstg -65 to 170 C Storage Temperature *1 G (gauss) = 0.1 mT (millitesla) Pin-out Diagrams LH Package UA Package 3 Terminal List Name VCC GND NC Number Function Package LH Package UA 1 1 Connects power supply to chip 3 2,3 Ground 2 - No internal connection NC 1 2 1 2 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch ELECTRICAL CHARACTERISTICS over full operating voltage and temperature ranges, unless otherwise specified Characteristic Min. Typ.1 Max. Units 3.5 - 24 V -I1, B < BRP 5 - 6.9 mA -I2, B < BRP 2 - 5 mA ICC(H) -I1 and -I2, B > BOP 12 - 17 mA dI/dt RS = 100 , CS = 20 pF, no bypass capacitor - 36 - mA/s - 200 - kHz - - 25 s Symbol Test Conditions Electrical Characteristics Supply Voltage2 3 Supply Current Output Slew Rate4 VCC ICC(L) Chopping Frequency fC Power-On Time tPO Power-On State5 POS Operating, TJ < 165C VCC > VCC(MIN) tPO < tPO(max), dVCC / dt > 25 mV / s - ICC(H) - - Supply Zener Clamp Voltage VZ(supply) ICC = 20 mA; TA = 25C 28 - - V Supply Zener Current6 IZ(supply) VS = 28 V - - 20 mA IRCC VRCC = -18 V - - 2.5 mA BOP South pole adjacent to branded face of device 5 32 80 G Release Point BRP North pole adjacent to branded face of device -80 -32 -5 G Hysteresis BHYS BOP - BRP 40 64 110 G Reverse Battery Current Magnetic Characteristics7 Operate Point 1 Typical values are at TA = 25C and VCC = 12 V. Performance may vary for individual units, within the specified maximum and minimum limits. 2 Maximum voltage must be adjusted for power dissipation and junction temperature; see Power Derating section. 3V CC represents the generated voltage between the VCC pin and the GND pin. 4 The value of dI is the difference between 90% of I CC(H) and 10% of ICC(L), and the value of dt is time period between those two points. The value of dI/dt depends on the value of the bypass capacitor, if one is used, with greater capacitances resulting in lower rates of change. 5 For t > t PO(max), and BRP < B < BOP, POS is undefined. 6 Maximum current limit is equal to the maximum I CCL(max) + 3 mA. 7 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity magnetic fields. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field is indicated by the absolute value of B, and the sign indicates the polarity of the field (for example, a -100 G field and a 100 G field have equivalent strength, but opposite polarity). DEVICE QUALIFICATION PROGRAM Contact Allegro for information. EMC (Electromagnetic Compatibility) PERFORMANCE Contact Allegro for information. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol RJA Package Thermal Resistance Test Conditions* Package LH, minimum-K PCB (single layer, single-sided with copper limited to solder pads) Package LH, low-K PCB (single layer, double-sided with 0.926 in2 copper area) Package UA, minimum-K PCB (single layer, single-sided with copper limited to solder pads) Value Units 228 C/W 110 C/W 165 C/W *Additional information available on the Allegro Web site. Maximum Allowable VCC (V) Power Derating Curve TJ(max) = 165C; ICC = ICC(max) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VCC(max) Low-K PCB, Package LH (R JA = 110 C/W) Minimum-K PCB, Package UA (R JA = 165 C/W) Minimum-K PCB, Package LH (R JA = 228 C/W) 20 40 60 80 100 VCC(min) 120 140 160 180 Temperature (C) Power Dissipation, P D (mW) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Low-K PCB, Package LH (R JA = 110 C/W) Min-K PCB, Package UA (R JA = 165 C/W) Min-K PCB, Package LH (R JA = 228 C/W) 20 40 60 80 100 120 140 160 180 Temperature (C) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Characteristic Data Supply Current (Low) versus Ambient Temperature (1242- I1) Supply Current (Low) versus Supply Voltage (A1242-I1) 7.0 7.0 6.8 6.8 6.6 6.6 6.4 Vcc (V) 24 12 3.75 6.2 6.0 5.8 5.6 ICC(L) (mA) ICC(L) (mA) 6.4 TA (C) -40 25 85 150 6.2 6.0 5.8 5.6 5.4 5.4 5.2 5.2 5.0 5.0 -50 0 50 100 0 150 5 10 TA (C) 5.0 5.0 4.5 4.5 4.0 Vcc (V) 24 12 3.75 3.5 3.0 ICC(L) (mA) ICC(L) (mA) 20 25 Supply Current (Low) versus Supply Voltage (A1242-I2) Supply Current (Low) versus Ambient Temperature (1242- I2) 4.0 TA (C) -40 25 150 3.5 3.0 2.5 2.5 2.0 2.0 -50 0 50 100 0 150 5 10 15 20 25 VCC (V) T A (C) Supply Current (High) versus Ambient Temperature 17 17 16 16 15 Vcc (V) 24 12 3.75 14 ICC(H) (mA) ICC(H) (mA) 15 VCC (V) Supply Current (High) versus Supply Voltage 15 TA (C) -40 25 85 150 14 13 13 12 12 -50 0 50 TA (C) 100 150 0 5 10 15 20 25 VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Operate Point versus Supply Voltage 80 65 65 50 Vcc (V) 24 12 3.5 35 BOP (G) B OP (G) Operate Point versus Ambient Temperature 80 20 50 TA (C) -40 25 150 35 20 5 5 -50 0 50 100 0 150 5 10 TA (C) 20 25 Release Point versus Supply Voltage -5 -5 -20 -20 -35 Vcc (V) 24 12 3.5 -50 BRP (G) B RP (G) Release Point versus Ambient Temperature -65 -35 TA (C) 150 25 -40 -50 -65 -80 -80 -50 0 50 100 150 0 5 10 15 20 25 VCC (V) TA (C) Hysteresis versus Ambient Temperature Hysteresis versus Supply Voltage 110 110 100 100 90 90 80 Vcc (V) 24 12 3.5 70 60 Bhys (G) Bhys (G) 15 VCC (V) 80 TA (C) -40 25 150 70 60 50 50 40 40 -50 0 50 TA (C) 100 150 0 5 10 15 20 25 VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Functional Description * Hall-Effect IC Applications Guide, AN27701, * Guidelines for Designing Subassemblies Using Hall-Effect Devices, AN27703.1 * Soldering Methods for Allegro Products - SMD and ThroughHole, AN26009 All are provided in Allegro Electronic Data Book, AMS-702 and the Allegro Web site: www.allegromicro.com. I+ Installation of CBYP must ensure that the traces that connect it to the A1242 pins are no greater than 5 mm in length. All high-frequency interferences conducted along the supply lines are passed directly to the load through CBYP , and it serves only to protect the A1242 internal circuitry. As a result, the load ECU (electronic control unit) must have sufficient protection, other than CBYP, installed in parallel with the A1242. ICC(L) 0 B- B+ BHYS Figure 1. Switching Behavior of the A1242. On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B- direction indicates decreasing south polarity field strength (including the case of increasing north polarity). V+ A series resistor on the supply side, RS (not shown), in combination with CBYP, creates a filter for EMI pulses. When determining the minimum VCC requirement of the A1242 device, the voltage drops across RS and the ECU sense resistor, RSENSE, must be taken into consideration. The typical value for RSENSE is approximately 100 . 0 BRP The A1242 should be protected by an external bypass capacitor, CBYP, connected between the supply, VCC, and the ground, GND, of the device. CBYP reduces both external noise and the noise generated by the chopper-stabilization function. As shown in figure 2, a 0.01 F capacitor is typical. ICC . Typical Application Circuit Switch to High ICC(H) Switch to Low The output, ICC, of the A1242 switches to the high current state when a magnetic field perpendicular to the Hall element exceeds the operate point threshold, BOP. Note that the device latches, that is, a south pole of sufficient strength towards the branded surface of the device switches the device output to ICC(H). The device retains its output state if the south pole is removed. When the magnetic field is reduced to below the release point threshold, BRP, the device output goes to the low current state. The difference between the magnetic operate and release points is called the hysteresis of the device, BHYS. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. Extensive applications information on magnets and Hall-effect devices is available in: BOP Operation VCC B A1242 GND CBYP 0.01 uF GND B A A Package UA Only B Maximum separation 5 mm RSENSE ECU Figure 2. Typical Application Circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall element. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulationdemodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field induced signal to recover its original spectrum at baseband, while the DC offset becomes a high-frequency signal. The magnetic sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. This configuration is illustrated in Figure 3. The chopper stabilization technique uses a 200 kHz high frequency clock. For demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency (400 kHz). This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. The repeatability of magnetic field-induced switching is affected slightly by a chopper technique. However, the Allegro high frequency chopping approach minimizes the affect of jitter and makes it imperceptible in most applications. Applications that are more likely to be sensitive to such degradation are those requiring precise sensing of alternating magnetic fields; for example, speed sensing of ring-magnet targets. For such applications, Allegro recommends its digital device families with lower sensitivity to jitter. For more information on those devices, contact your Allegro sales representative. Regulator Hall Element Amp Sample and Hold Clock/Logic Low-Pass Filter Figure 3. Chopper stabilization circuit (dynamic quadrature offset cancellation) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Power Derating Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RJC, is relatively small component of RJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN x IIN (1) T = PD x RJA Example: Reliability for VCC at TA = 150C, package LH, using minimum-K PCB. Observe the worst-case ratings for the device, specifically: RJA = 228C/W, TJ(max) = 165C, VCC(max) = 24 V, and ICC(max) = 17 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: Tmax = TJ(max) - TA = 165 C - 150 C = 15 C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = Tmax / RJA = 15C / 228 C/W = 66 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) / ICC(max) = 66 mW / 17 mA = 3.9 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages VCC(est). Compare VCC(est) to VCC(max). If VCC(est) VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RJA. If VCC(est) VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. (2) TJ = TA + T (3) For example, given common conditions such as: TA= 25C, VCC = 12 V, ICC = 6 mA, and RJA = 165 C/W, then: PD = VCC x ICC = 12 V x 6 mA = 72 mW T = PD x RJA = 72 mW x 165 C/W = 12C TJ = TA + T = 25C + 12C = 37C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RJA and TA. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Package LH, 3-Pin (SOT-23W) +0.12 2.98 -0.08 1.49 D 44 3 A +0.020 0.180-0.053 0.96 D +0.10 2.90 -0.20 +0.19 1.91 -0.06 2.40 0.70 D 0.25 MIN 1.00 2 1 0.55 REF 0.25 BSC 0.95 Seating Plane Gauge Plane 8X 10 REF B PCB Layout Reference View Branded Face 1.00 0.13 +0.10 0.05 -0.05 0.95 BSC 0.40 0.10 For Reference Only; not for tooling use (reference dwg. 802840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Active Area Depth, 0.28 mm REF B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall element, not to scale NNT 1 C Standard Branding Reference View N = Last two digits of device part number T = Temperature code Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1242 Two-Wire Chopper-Stabilized Hall Effect Latch Package UA, 3-Pin SIP +0.08 4.09 -0.05 45 B C E 2.04 1.52 0.05 1.44 E Mold Ejector Pin Indent +0.08 3.02 -0.05 E Branded Face 45 1 2.16 MAX D Standard Branding Reference View = Supplier emblem N = Last two digits of device part number T = Temperature code 0.79 REF A 0.51 REF NNT 1 2 3 +0.03 0.41 -0.06 15.75 0.51 For Reference Only; not for tooling use (reference DWG-9049) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Dambar removal protrusion (6X) B Gate burr area C Active Area Depth, 0.50 mm REF +0.05 0.43 -0.07 D Branding scale and appearance at supplier discretion E Hall element, not to scale 1.27 NOM Copyright (c)2005-2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11