A1242EUA-I1-T - Allegro Microsystems

NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan

for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The

information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-

sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

Recommended Substitutions:

Two-Wire Chopper-Stabilized Hall Effect Latch

A1242

• for the A1242ELHLT-I2-T use the A1244LLHLX-I2-T

• for the A1242ELHLT-I1-T use the A1244LLHLX-I1-T

• for the A1242LLHLT-I2-T use the A1244LLHLX-I2-T

• for the A1242LLHLT-I1-T use the A1244LLHLX-I1-T

• for the A1242EUA-I1-T and A1242LUA-I1-T use the A1244LUA-I1-T

• for the A1242LUA-I2-T use the A1244LUA-I2-T

Date of status change: October 31, 2011

This device is no longer in production. The device should not be

purchased for new design applications. Samples are no longer available.

Discontinued Product

Description

The A1242 Hall effect latch is a two-wire latch especially

suited for operation over extended temperature ranges, from

–40 to +150°C. Superior high-temperature performance is

made possible through the Allegro® patented dynamic offset

cancellation technique, which reduces the residual offset

voltage normally caused by device overmolding, temperature

dependencies, and thermal stress.

The current-switching output technique allows for the reduction

in cost in the wiring harness because only two connections to

the device are required. The current-switching output structure

also inherently provides more immunity against EMC/ESD

transients. These devices have low magnetic thresholds, thereby

enabling more flexibility in the magnetic circuit design.

The Hall effect latch will be in the high output current state

in the presence of a magnetic South Pole field of sufficient

magnitude and will remain in this state until a sufficient North

Pole field is present.

The A1242 includes the following on a single silicon chip:

a voltage regulator, Hall-voltage generator, small-signal

amplifier, chopper stabilization, Schmitt trigger, and a current

source output. Advanced BiCMOS wafer fabrication processing

takes advantage of low-voltage requirements, component

1242-DS, Rev. 6

Features and Benefits

▪ Chopper stabilization

▫ Superior temperature stability

▫ Extremely low switchpoint drift

▫ Insensitive to physical stress

▪ Reverse battery protection

▪ Solid-state reliability

▪ Small size

▪ Robust EMC capability

▪ High ESD ratings (HBM)

Two-Wire Chopper-Stabilized Hall Effect Latch

Continued on the next page…

Functional Block Diagram

Not to scale

A1242

Packages: 3 pin SOT23W (suffix LH), and

3 pin SIP (suffix UA)

Not to scale

Amp

Regulator

Low-Pass

Filter

GND

VCC

GND

Package UA Only

Clock/Logic

Dynamic Offset

Cancellation

Sample and Hold

To All Subcircuits

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Description (continued)

Pin-out Diagrams

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit*

Supply Voltage VCC 28 V

Reverse Supply Voltage VRCC –18 V

Magnetic Flux Density B Unlimited G

Operating Ambient Temperature TA

Range E –40 to 85 ºC

Range L –40 to 150 ºC

Maximum Junction Temperature TJ(max) 165 ºC

Storage Temperature Tstg –65 to 170 ºC

*1 G (gauss) = 0.1 mT (millitesla)

matching, very low input-offset errors and small component

geometries.

Suffix ‘L-’ devices are rated for operation over a temperature range

of –40°C to +150°C; suffix ‘E-’ devices are rated for operation over

a temperature range of –40°C to +85°C. Two A1242 package styles

provide magnetically optimized solutions for most applications.

Package LH is a SOT23W, a miniature low-profile surface-mount

package, while package UA is a three-pin ultramini SIP for through-

hole mounting. Each package is available lead (Pb) free, with 100%

matte tin plated leadframes.

123

Selection Guide

Part Number Packaging* Mounting Low Current, ICC(L)

(mA)

Ambient, TA

(°C)

BRP(MIN)

(G)

BOP(MAX)

(G)

A1242ELHLT-I1-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount 5.0 to 6.9

–40 to 85

–80 80

A1242ELHLT-I2-T 2.0 to 5.0

A1242EUA-I1-T Bulk, 500 pieces/bag 3-pin SIP through hole 5.0 to 6.9

A1242LLHLT-I1-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount 5.0 to 6.9

–40 to 150

A1242LLHLT-I2-T 2.0 to 5.0

A1242LUA-I1-T Bulk, 500 pieces/bag 3-pin SIP through hole 5.0 to 6.9

A1242LUA-I2-T 2.0 to 5.0

*Contact Allegro for additional packing options.

Terminal List

Name Number Function

Package LH Package UA

VCC 1 1 Connects power supply to chip

GND 3 2,3 Ground

NC 2 – No internal connection

LH Package UA Package

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

DEVICE QUALIFICATION PROGRAM

Contact Allegro for information.

EMC (Electromagnetic Compatibility) PERFORMANCE

Contact Allegro for information.

ELECTRICAL CHARACTERISTICS over full operating voltage and temperature ranges, unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ.1Max. Units

Electrical Characteristics

Supply Voltage2 3VCC Operating, TJ < 165°C 3.5 – 24 V

Supply Current ICC(L)

-I1, B < BRP 5 – 6.9 mA

-I2, B < BRP 2–5mA

ICC(H) -I1 and -I2, B > BOP 12 – 17 mA

Output Slew Rate4dI/dt RS = 100 Ω, CS = 20 pF, no bypass capacitor – 36 – mA/μs

Chopping Frequency fC– 200 – kHz

Power-On Time tPO VCC > VCC(MIN) ––25μs

Power-On State5POS tPO < tPO(max), dVCC

/ dt > 25 mV / μs–I

CC(H) ––

Supply Zener Clamp Voltage VZ(supply) ICC = 20 mA; TA = 25°C 28 – – V

Supply Zener Current6IZ(supply) VS = 28 V – – 20 mA

Reverse Battery Current IRCC VRCC = –18 V – – 2.5 mA

Magnetic Characteristics7

Operate Point BOP South pole adjacent to branded face of device 5 32 80 G

Release Point BRP North pole adjacent to branded face of device –80 –32 –5 G

Hysteresis BHYS BOP – BRP 40 64 110 G

1 Typical values are at TA = 25°C and VCC = 12 V. Performance may vary for individual units, within the specified maximum and mini-

mum limits.

2 Maximum voltage must be adjusted for power dissipation and junction temperature; see Power Derating section.

3 VCC represents the generated voltage between the VCC pin and the GND pin.

4 The value of dI is the difference between 90% of ICC(H) and 10% of ICC(L), and the value of dt is time period between those two

points. The value of dI/dt depends on the value of the bypass capacitor, if one is used, with greater capacitances resulting in lower

rates of change.

5 For t > tPO(max), and BRP < B < BOP

, POS is undefined.

6 Maximum current limit is equal to the maximum ICCL(max) + 3 mA.

7 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity

magnetic fields. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the rela-

tive strength of the field is indicated by the absolute value of B, and the sign indicates the polarity of the field (for example, a –100 G

field and a 100 G field have equivalent strength, but opposite polarity).

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA

Package LH, minimum-K PCB (single layer, single-sided with

copper limited to solder pads) 228 ºC/W

Package LH, low-K PCB (single layer, double-sided with

0.926 in2 copper area) 110 ºC/W

Package UA, minimum-K PCB (single layer, single-sided with

copper limited to solder pads) 165 ºC/W

*Additional information available on the Allegro Web site.

Power Derating Curve

J(max)

= 165°C; I

= I

CC(max)

20 40 60 80 100 120 140 160 180

Temperature (°C)

Maximum Allowable V

(V)

Minimum-K PCB, Package UA

= 165 °C/W)

Minimum-K PCB, Package LH

= 228 °C/W)

CC(max)

CC(min)

Low-K PCB, Package LH

= 110 °C/W)

Power Dissipation versus Ambient Temperature

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

20 40 60 80 100 120 140 160 180

Temperature (°C)

Power Dissipation, P

(mW)

Low-K PCB, Package LH

= 110 °C/W)

Min-K PCB, Package LH

= 228 °C/W)

Min-K PCB, Package UA

= 165 °C/W)

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristic Data

Supply Current (Low) versus Ambient Temperature

(1242- I1)

5.0

5.2

5.4

5.6

5.8

6.0

6.2

6.4

6.6

6.8

7.0

-50 0 50 100 150

(°C)

CC(L)

(mA)

Vcc (V)

3.75

Supply Current (Low) versus Ambient Temperature

(1242- I2)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-50 0 50 100 150

(°C)

CC(L)

(mA)

Vcc (V)

3.75

Supply Current (High) versus Ambient Temperature

-50 0 50 100 150

TA (°C)

ICC(H) (mA)

Vcc (V)

3.75

Supply Current (Low) versus Supply Voltage

(A1242-I1)

5.0

5.2

5.4

5.6

5.8

6.0

6.2

6.4

6.6

6.8

7.0

0 5 10 15 20 25

VCC (V)

ICC(L) (mA)

(°C)

-40

150

Supply Current (Low) versus Supply Voltage

(A1242-I2)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 5 10 15 20 25

VCC (V)

ICC(L) (mA)

(°C)

-40

150

Supply Current (High) versus Supply Voltage

0 5 10 15 20 25

VCC (V)

ICC(H) (mA)

(°C)

-40

150

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Operate Po int ver sus Ambie nt Temp era t ure

-50 0 50 100 150

(°C)

BOP (G)

Vcc (V)

3.5

Release Point versus Ambient Temperature

-80

-65

-50

-35

-20

-5

-50 0 50 100 150

(°C)

BRP (G)

Vcc (V)

3.5

Hysteresi s versu s Ambi ent Temp eratu re

100

110

-50 0 50 100 150

(°C)

Bhys (G)

Vcc (V)

3.5

Operate Po int versus Supply Voltage

0 5 10 15 20 25

(V)

BOP (G)

(°C)

-40

150

Rel ease Point versus Supply Volt age

-80

-65

-50

-35

-20

-5

0 5 10 15 20 25

(V)

BRP (G)

(°C)

150

-40

Hy steres is versus Sup pl y Vol t age

100

110

0 5 10 15 20 25

(V)

Bhys (G)

(°C)

-40

150

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

Operation

The output, ICC, of the A1242 switches to the high current state

when a magnetic field perpendicular to the Hall element exceeds

the operate point threshold, BOP. Note that the device latches,

that is, a south pole of sufficient strength towards the branded

surface of the device switches the device output to ICC(H). The

device retains its output state if the south pole is removed. When

the magnetic field is reduced to below the release point thresh-

old, BRP, the device output goes to the low current state. The dif-

ference between the magnetic operate and release points is called

the hysteresis of the device, BHYS. This built-in hysteresis allows

clean switching of the output even in the presence of external

mechanical vibration and electrical noise.

Typical Application Circuit

The A1242 should be protected by an external bypass capaci-

tor, CBYP, connected between the supply, VCC, and the ground,

GND, of the device. CBYP reduces both external noise and the

noise generated by the chopper-stabilization function. As shown

in figure 2, a 0.01 μF capacitor is typical.

Installation of CBYP must ensure that the traces that connect it to

the A1242 pins are no greater than 5 mm in length.

All high-frequency interferences conducted along the supply

lines are passed directly to the load through CBYP

, and it serves

only to protect the A1242 internal circuitry. As a result, the load

ECU (electronic control unit) must have sufficient protection,

other than CBYP, installed in parallel with the A1242.

A series resistor on the supply side, RS (not shown), in combina-

tion with CBYP, creates a filter for EMI pulses.

When determining the minimum VCC requirement of the A1242

device, the voltage drops across RS and the ECU sense resistor,

RSENSE, must be taken into consideration. The typical value for

RSENSE is approximately 100 Ω.

Extensive applications information on magnets and Hall-effect

devices is available in:

• Hall-Effect IC Applications Guide, AN27701,

• Guidelines for Designing Subassemblies

Using Hall-Effect Devices, AN27703.1

• Soldering Methods for Allegro Products – SMD and Through-

Hole, AN26009

All are provided in Allegro Electronic Data Book, AMS-702 and

the Allegro Web site: www.allegromicro.com.

Figure 1. Switching Behavior of the A1242. On the horizontal axis, the

B+ direction indicates increasing south polarity magnetic field strength,

and the B– direction indicates decreasing south polarity field strength

(including the case of increasing north polarity).

BOP

BRP

BHYS

ICC(H)

ICC

ICC(L)

Switch to High

Switch to Low

B+

I+

B–

GND

A1242

VCC

V+

0.01 uF

GND

ECU

Package UA Only

BMaximum separation 5 mm

RSENSE

CBYP

Figure 2. Typical Application Circuit

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figure 3. Chopper stabilization circuit (dynamic quadrature offset cancellation)

Amp

Regulator

Clock/Logic

Hall Element

Sample and

Hold

Low-Pass

Filter

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small signal voltage developed

across the Hall element. This voltage is disproportionally small

relative to the offset that can be produced at the output of the

Hall element. This makes it difficult to process the signal while

maintaining an accurate, reliable output over the specified oper-

ating temperature and voltage ranges.

Chopper stabilization is a unique approach used to minimize

Hall offset on the chip. The patented Allegro technique, namely

Dynamic Quadrature Offset Cancellation, removes key sources

of the output drift induced by thermal and mechanical stresses.

This offset reduction technique is based on a signal modulation-

demodulation process. The undesired offset signal is separated

from the magnetic field-induced signal in the frequency domain,

through modulation. The subsequent demodulation acts as a

modulation process for the offset, causing the magnetic field

induced signal to recover its original spectrum at baseband,

while the DC offset becomes a high-frequency signal. The

magnetic sourced signal then can pass through a low-pass filter,

while the modulated DC offset is suppressed. This configuration

is illustrated in Figure 3.

The chopper stabilization technique uses a 200 kHz high

frequency clock. For demodulation process, a sample and hold

technique is used, where the sampling is performed at twice the

chopper frequency (400 kHz). This high-frequency operation

allows a greater sampling rate, which results in higher accuracy

and faster signal-processing capability. This approach desensi-

tizes the chip to the effects of thermal and mechanical stresses,

and produces devices that have extremely stable quiescent Hall

output voltages and precise recoverability after temperature

cycling. This technique is made possible through the use of a

BiCMOS process, which allows the use of low-offset, low-noise

amplifiers in combination with high-density logic integration

and sample-and-hold circuits.

The repeatability of magnetic field-induced switching is affected

slightly by a chopper technique. However, the Allegro high

frequency chopping approach minimizes the affect of jitter and

makes it imperceptible in most applications. Applications that

are more likely to be sensitive to such degradation are those

requiring precise sensing of alternating magnetic fields; for

example, speed sensing of ring-magnet targets. For such applica-

tions,

Allegro recommends its digital device families with lower sen-

sitivity to jitter. For more information on those devices, contact

your Allegro sales representative.

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Power Derating

The device must be operated below the maximum junction

temperature of the device, TJ(max). Under certain combinations of

peak conditions, reliable operation may require derating sup-

plied power or improving the heat dissipation properties of the

application. This section presents a procedure for correlating

factors affecting operating TJ. (Thermal data is also available on

the Allegro MicroSystems Web site.)

The Package Thermal Resistance, RJA, is a figure of merit sum-

marizing the ability of the application and the device to dissipate

heat from the junction (die), through all paths to the ambient air.

Its primary component is the Effective Thermal Conductivity,

K, of the printed circuit board, including adjacent devices and

traces. Radiation from the die through the device case, RJC, is

relatively small component of RJA. Ambient air temperature,

TA, and air motion are significant external factors, damped by

overmolding.

The effect of varying power levels (Power Dissipation, PD), can

be estimated. The following formulas represent the fundamental

relationships used to estimate TJ, at PD.

PD = VIN × IIN

(1)

 T = PD × RJA (2)

TJ = TA + ΔT

(3)

For example, given common conditions such as: TA= 25°C,

VCC = 12 V, ICC = 6 mA, and RJA = 165 °C/W, then:

D = VCC × ICC = 12 V × 6 mA = 72 mW

T = PD × RJA = 72 mW × 165 °C/W = 12°C

J = TA + T = 25°C + 12°C = 37°C

A worst-case estimate, PD(max), represents the maximum allow-

able power level (VCC(max), ICC(max)), without exceeding TJ(max),

at a selected RJA and TA.

Example: Reliability for VCC at TA =

150°C, package LH, using

minimum-K PCB.

Observe the worst-case ratings for the device, specifically:

RJA

228°C/W, TJ(max) =

165°C, VCC(max)

= 24 V, and

ICC(max) = 17 mA.

Calculate the maximum allowable power level, PD(max). First,

invert equation 3:

Tmax = TJ(max) – TA = 165

°C

–

150

°C = 15

°C

This provides the allowable increase to TJ resulting from internal

power dissipation. Then, invert equation 2:

PD(max) = Tmax ÷ RJA = 15°C ÷ 228 °C/W = 66 mW

Finally, invert equation 1 with respect to voltage:

VCC(est) = PD(max) ÷ ICC(max) = 66 mW ÷ 17 mA = 3.9 V

The result indicates that, at TA, the application and device can

dissipate adequate amounts of heat at voltages ≤VCC(est).

Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-

able operation between VCC(est) and VCC(max) requires enhanced

RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and

VCC(max) is reliable under these conditions.

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package LH, 3-Pin (SOT-23W)

0.55 REF

Gauge Plane

Seating Plane

0.25 BSC

0.95 BSC

0.95

1.00

0.70 2.40

AActive Area Depth, 0.28 mm REF

Reference land pattern layout

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

Branding scale and appearance at supplier discretion

PCB Layout Reference View

Standard Branding Reference View

Branded Face

N = Last two digits of device part number

T = Temperature code

NNT

2.90 +0.10

–0.20

4°±4°

8X 10° REF

0.180+0.020

–0.053

0.05 +0.10

–0.05

0.25 MIN

1.91 +0.19

–0.06

2.98 +0.12

–0.08

1.00 ±0.13

0.40 ±0.10

For Reference Only; not for tooling use (reference dwg. 802840)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

DHall element, not to scale

1.49

0.96

T wo-Wire Chopper-Stabilized Hall Effect Latch

A1242

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package UA, 3-Pin SIP

231

0.79 REF

1.27 NOM

2.16

MAX

0.51

REF

45°

2.04

1.44

Gate burr area

Dambar removal protrusion (6X)

Branding scale and appearance at supplier discretion

Hall element, not to scale

Active Area Depth, 0.50 mm REF

For Reference Only; not for tooling use (reference DWG-9049)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Standard Branding Reference View

= Supplier emblem

N = Last two digits of device part number

T = Temperature code

NNT

Mold Ejector

Pin Indent

Branded

Face

4.09 +0.08

–0.05

0.41 +0.03

–0.06

3.02 +0.08

–0.05

0.43 +0.05

–0.07

15.75 ±0.51

1.52 ±0.05

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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