SDAS211C − DECEMBER 1982 − REVISED JULY 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DLook-Ahead Circuitry Enhances Cascaded
Counters
DFully Synchronous in Count Modes
DParallel Asynchronous Load for Modulo-N
Count Lengths
DAsynchronous Clear
DPackage Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’ALS193A are synchronous, reversible, 4-bit
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous (ripple-
clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of either count/clock
(UP or DOWN) input. The direction of the count is
determined by which count input is pulsed while
the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent
of the count and LOAD inputs. The UP, DOWN, and LOAD inputs are buffered to lower the drive requirement,
which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words.
These counters are designed to be cascaded without the need for external circuitry. The borrow (BO) output
produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the
carry (CO) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input
is low. The counters can then be easily cascaded by feeding BO and CO to the count-down and count-up inputs,
respectively, of the succeeding counter.
The SN54ALS193A is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ALS193A is characterized for operation from 0°C to 70°C.
Copyright 1996, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
QB
QA
DOWN
UP
QC
QD
GND
VCC
A
CLR
BO
CO
LOAD
C
D
SN54ALS193A ...J PACKAGE
SN74ALS193A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS193A . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
CLR
BO
NC
CO
LOAD
QA
DOWN
NC
UP
QC
B
NC
D
CA
Q
GND
NC
DQ
B
VCC
NC − No internal connection
SDAS211C − DECEMBER 1982 − REVISED JULY 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic symbol†
CTRDIV16
LOAD
CO1CT = 15
2CT = 0
12
3D
15
A1
B10
C9
D
CT = 0
14
CLR
2+
G1
C3
11
5
UP
1−
G2
4
DOWN 13
3
2
6
7
BO
QA
QB
QC
QD
[1]
[2]
[4]
[8]
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SDAS211C − DECEMBER 1982 − REVISED JULY 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic diagram (positive logic)
15
4
5
CO
A
1
10
9
B
C
D
UP
DOWN
QA
QB
QC
QD
12
13
3
2
6
7
1D
R
CLR
LOAD
S
R
S
R
R
R
1D
1D
1D
C1
C1
C1
C1
S
S
S
BO
14
11
Pin numbers shown are for the D, J, and N packages.
SDAS211C − DECEMBER 1982 − REVISED JULY 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
typical clear, load, and count sequence
the following sequence is illustrated below:
1. Clear outputs to zero
2. Load (preset) to binary 13
3. Count up to 14, 15 (carry), 0, 1, and 2
4. Count down to 1, 0 (borrow), 15, 14, and 13
0
A
B
C
D
UP
DOWN
QA
QD
QC
QB
Count Up Count Down
13 0 2110
Data
Inputs
CLR
Data
Outputs
LOAD
CO
BO 14 15 15 14 13
Sequence
Illustrated
Clear Preset
NOTES: A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must be high; when counting down, count-up input must be high.
SDAS211C − DECEMBER 1982 − REVISED JULY 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS193A −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS193A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS193A SN74ALS193A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
fclock Clock frequency 0 20 0 30 MHz
CLR high 10 10
t
w
Pulse duration LOAD low 25 20 ns
tw
Pulse duration
UP or DOWN high or low 30 16.5
ns
Data before LOAD↑25 20
t
su
Setup time CLR inactive before UP or DOWN 20 20 ns
tsu
Setup time
LOAD inactive before UP or DOWN 20 20
ns
Data after LOAD↑5 5
t
h
Hold time UP high after DOWN↑5 0 ns
th
Hold time
DOWN high after UP↑5 0
ns
TAOperating free-air temperature −55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS193A SN74ALS193A
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIK VCC = 4.5 V, II = −18 mA −1.5 −1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = −0.4 mA VCC −2 VCC −2 V
VOL
VCC = 4.5 V
IOL = 4 mA 0.25 0.4 0.25 0.4
V
VOL VCC = 4.5 V IOL = 8 mA 0.35 0.5 V
IIVCC = 5.5 V, VI = 7 V 0.1 0.35 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL
UP or DOWN
VCC = 5.5 V,
VI = 0.4 V
−0.2 −0.2
mA
IIL All others VCC = 5.5 V, VI = 0.4 V −0.1 −0.1 mA
IO§VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA
ICC VCC = 5.5 V, See Note 1 12 22 12 22 mA
‡All typical values are at VCC = 5 V, TA = 25°C.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with the clear and load inputs grounded and all other inputs at 4.5 V.
SDAS211C − DECEMBER 1982 − REVISED JULY 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = R2 = 500 Ω,
TA = MIN to MAX†UNIT
PARAMETER
(INPUT)
(OUTPUT)
SN54ALS193A SN74ALS193A
UNIT
MIN MAX MIN MAX
fmax 25 30 MHz
tPLH
UP
CO
3 20 3 16
ns
tPHL UP CO 3 21 5 18 ns
tPLH
DOWN
BO
4 20 4 16
ns
tPHL DOWN BO 5 22 5 18 ns
tPLH
UP or DOWN
Any Q
3 27 3 19
ns
tPHL UP or DOWN Any Q 4 23 4 17 ns
tPLH
LOAD
Any Q
7 38 7 30
ns
tPHL LOAD Any Q 8 37 8 28 ns
tPHL CLR Any Q 5 20 5 17 ns
†For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
SDAS211C − DECEMBER 1982 − REVISED JULY 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B) [0 V
VOH
VOL
[3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-88698012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8869801EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-8869801FA ACTIVE CFP W 16 1 TBD Call TI Call TI
SN54ALS193AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN74ALS193AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS193ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS193ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS193ADR ACTIVE SOIC D 16 TBD Call TI Call TI
SN74ALS193ADRE4 ACTIVE SOIC D 16 TBD Call TI Call TI
SN74ALS193ADRG4 ACTIVE SOIC D 16 TBD Call TI Call TI
SN74ALS193AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS193ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS193ANSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS193ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS193ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54ALS193AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54ALS193AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54ALS193AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS193A, SN74ALS193A :
•Catalog: SN74ALS193A
•Military: SN54ALS193A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS193ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS193ANSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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