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SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
LM5100A/B/C, LM5101A/B/C 3-A, 2-A, and 1-A High-Voltage, High-Side
and Low-Side Gate Drivers
An integrated high-voltage diode is provided to
1 Features charge the high-side gate drive bootstrap capacitor. A
1• Drives Both a High-Side and Low-Side N-Channel robust level shifter operates at high speed while
MOSFETs consuming low power and providing clean level
• Independent High- and Low-Driver Logic Inputs transitions from the control logic to the high-side gate
driver. Undervoltage lockout is provided on both the
• Bootstrap Supply Voltage up to 118 V DC low-side and the high-side power rails. These devices
• Fast Propagation Times (25-ns Typical) are available in the standard SOIC-8 pin, SO
• Drives 1000-pF Load With 8-ns Rise and Fall PowerPAD-8 pin, and the WSON-10 pin packages.
Times The LM5100C and LM5101C are also available in
MSOP-PowerPAD-8 package. The LM5101A is also
• Excellent Propagation Delay Matching (3-ns available in WSON-8 pin package.
Typical)
• Supply Rail Undervoltage Lockout Device Information(1)
• Low Power Consumption PEAK OUTPUT
PART NUMBER INPUT THRESHOLD CURRENT
• Pin Compatible With HIP2100/HIP2101 LM5100A CMOS 3 A
2 Applications LM5101A TTL 3 A
LM5100B CMOS 2 A
• Current-Fed Push-Pull Converters LM5101B TTL 2 A
• Half and Full Bridge Power Converters LM5100C CMOS 1 A
• Synchronous Buck Converters LM5101C TTL 1 A
• Two Switch Forward Power Converters (1) For all available packages, see the orderable addendum at
• Forward with Active Clamp Converters the end of the data sheet.
3 Description
The LM5100A/B/C and LM5101A/B/C high-voltage
gate drivers are designed to drive both the high-side
and the low-side N-Channel MOSFETs in a
synchronous buck or a half-bridge configuration. The
floating high-side driver is capable of operating with
supply voltages up to 100 V. The A versions provide
a full 3-A of gate drive, while the B and C versions
provide 2 A and 1 A, respectively. The outputs are
independently controlled with CMOS input thresholds
(LM5100A/B/C) or TTL input thresholds
(LM5101A/B/C).
Simplified Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................. 14
1 Features.................................................................. 18.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 19 Application and Implementation ........................ 16
3 Description............................................................. 19.1 Application Information............................................ 16
4 Revision History..................................................... 29.2 Typical Application ................................................. 16
5 Device Comparison Table..................................... 310 Power Supply Recommendations ..................... 20
6 Pin Configuration and Functions......................... 311 Layout................................................................... 21
7 Specifications......................................................... 511.1 Layout Guidelines ................................................. 21
7.1 Absolute Maximum Ratings ..................................... 511.2 Layout Example .................................................... 21
7.2 ESD Ratings.............................................................. 512 Device and Documentation Support ................. 22
7.3 Recommended Operating Conditions....................... 512.1 Documentation Support ....................................... 22
7.4 Thermal Information.................................................. 612.2 Related Links ........................................................ 22
7.5 Electrical Characteristics ......................................... 612.3 Community Resources.......................................... 22
7.6 Switching Characteristics......................................... 812.4 Trademarks........................................................... 22
7.7 Typical Characteristics............................................ 10 12.5 Electrostatic Discharge Caution............................ 22
8 Detailed Description............................................ 14 12.6 Glossary................................................................ 22
8.1 Overview................................................................. 14 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram....................................... 14 Information........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2013) to Revision Q Page
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changes from Revision O (March 2013) to Revision P Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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Exposed Pad
Connect to VSS
HO 3
HS 4
VDD 1
HB 2
8LO
7VSS
6LI
5HI
SO
PowerPad-8
WSON-8
1
2
3
4 5
6
7
8VDD
HB
HO
HS HI
LI
VSS
LO
WSON-10
1
2
3
4
9
6
7
8
VDD
HB
HO
HS HI
LI
VSS
LO
NC 5
10
NC
VDD
HB
HO
HS
LO
VSS
LI
HI
18
27
36
4 5
SOIC-8
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
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SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
5 Device Comparison Table
PART NUMBER PACKAGE BODY SIZE (NOM)
WSON (10) 4.00 mm × 4.00 mm
LM5100A, LM5100C SO PowerPAD™ (8) 3.90 mm × 4.89 mm
SOIC (8) 3.91 mm × 4.90 mm
WSON (10) 4.00 mm × 4.00 mm
LM5100B, LM5101B SOIC (8) 3.91 mm × 4.90 mm
WSON (8) 4.00 mm × 4.00 mm
WSON (10) 4 .00mm × 4.00 mm
LM5101A SO PowerPAD (8) 3.90 mm × 4.89 mm
SOIC (8) 3.91 mm × 4.90 mm
MSOP PowerPAD (8) 3.00 mm × 3.00 mm
LM5101C WSON (10) 4.00 mm × 4.00 mm
SOIC (8) 3.91 mm × 4.90 mm
6 Pin Configuration and Functions
D Package DPR Package
8-Pin SOIC 10-Pin WSON With Exposed Thermal Pad
Top View Top View
NGT Package
8-Pin WSON With Exposed Thermal Pad DDA Package
Top View 8-Pin SO PowerPAD
Top View
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Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
VDD
HB
HO
HS
LO
VSS
LI
HI
MSOP-
PowerPad-8
1
2
3
4 5
6
7
8
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
DGN Package
8-Pin MSOP-PowerPAD
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME 8 PINS 10 PINS(1)
High-side gate driver bootstrap supply. Connect the positive terminal of the bootstrap
HB 2 2 I capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be
placed as close to the IC as possible.
High-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
HI 5 7 I The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
High-side gate driver output. Connect to the gate of high-side MOSFET with a short,
HO 3 3 O low inductance path.
High-side MOSFET source connection. Connect to the bootstrap capacitor negative
HS 4 4 — terminal and the source of the high-side MOSFET.
Low-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
LI 6 8 I The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
Low-side gate driver output. Connect to the gate of the low-side MOSFET with a
LO 8 10 O short, low inductance path.
Positive gate drive supply . Locally decouple to VSS using low ESR/ESL capacitor
VDD 1 1 I located as close to the IC as possible.
VSS 7 9 — Ground return. All signals are referenced to this ground.
TI recommends that the exposed pad on the bottom of the package is soldered to
EP(2) — ground plane on the PC board, and that ground plane should extend out from
beneath the IC to help dissipate heat.
(1) For WSON-10 package, pins 5 and 6 have no connection.
(2) Exposed pad is not available on the 8-pin SOIC package.
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LM5101A
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,
LM5101C
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SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
See (1)(2)
MIN MAX UNIT
VDD to VSS −0.3 18 V
HB to HS −0.3 18 V
LI or HI input −0.3 VDD + 0.3 V
LO output −0.3 VDD + 0.3 V
HO output VHS −0.3 VHB + 0.3 V
HS to VSS (3) −5 100 V
HB to VSS 118 V
Junction temperature 150 °C
Storage temperature −55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example if VDD = 10 V, the
negative transients at HS must not exceed –5 V.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Electrostatic
V(ESD) Option A 50 V
discharge Machine Model (MM) (2) Option B and C 100
(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000 V for HBM.
(2) Machine Model (MM) ratings are: 100 V(MM) for Options B and C; 50 V(MM) for Option A.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
VDD 9 14 V
HS –1 100 V
HB VHS + 8 VHS + 14 V
HS slew rate < 50 V/ns
Junction temperature −40 125 °C
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LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
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7.4 Thermal Information LM5100A, LM5100x,
LM5100C, LM5101C LM5101A LM5101x
LM5101A
THERMAL METRIC(1) UNIT
MSOP-
SO PowerPAD WSON(2) WSON(2) SOIC
PowerPAD(2)
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(3) 40 80 37.8 40 170 °C/W
RθJC(top) Junction-to-case (top) thermal resistance — — 36.7 — — °C/W
RθJB Junction-to-board thermal resistance — — 14.9 — — °C/W
ψJT Junction-to-top characterization parameter — — 0.3 — — °C/W
ψJB Junction-to-board characterization parameter — — 15.2 — — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 4.4 — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) 4-layer board with Cu finished thickness 1.5, 1, 1, 1.5 oz. Maximum die size used. 5× body length of Cu trace on PCB top.
50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 (SNOA401).
(3) The RθJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
7.5 Electrical Characteristics
unless otherwise specified, limits are for TJ= 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
TJ= 25°C 0.1
VDD quiescent current, LI = HI = 0 V mA
LM5100A/B/C TJ= –40°C to 125°C 0.2
IDD TJ= 25°C 0.25
VDD quiescent current, LI = HI = 0 V mA
LM5101A/B/C TJ= –40°C to 125°C 0.4
TJ= 25°C 2
IDDO VDD operating current f = 500 kHz mA
TJ= –40°C to 125°C 3
TJ= 25°C 0.06
IHB Total HB quiescent current LI = HI = 0 V mA
TJ= –40°C to 125°C 0.2
TJ= 25°C 1.6
IHBO Total HB operating current f = 500 kHz mA
TJ= –40°C to 125°C 3
TJ= 25°C 0.1
IHBS HB to VSS current, quiescent HS = HB = 100 V µA
TJ= –40°C to 125°C 10
IHBSO HB to VSS current, operating f = 500 kHz 0.4 mA
INPUT PINS
TJ= 25°C 5.4
Input voltage threshold
VIL Rising Edge V
LM5100A/B/C TJ= –40°C to 125°C 4.5 6.3
TJ= 25°C 1.8
Input voltage threshold
VIL Rising Edge V
LM5101A/B/C TJ= –40°C to 125°C 1.3 2.3
Input voltage hysteresis
VIHYS 500 mV
LM5100A/B/C
Input voltage hysteresis
VIHYS 50 mV
LM5101A/B/C TJ= 25°C 200
RIInput pulldown resistance kΩ
TJ= –40°C to 125°C 100 400
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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LM5101A
,
LM5101B
,
LM5101C
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SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Electrical Characteristics (continued)
unless otherwise specified, limits are for TJ= 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UNDER VOLTAGE PROTECTION
TJ= 25°C 6.9
VDDR VDD rising threshold V
TJ= –40°C to 125°C 6 7.4
VDDH VDD threshold hysteresis 0.5 V
TJ= 25°C 6.6
VHBR HB rising threshold V
TJ= –40°C to 125°C 5.7 7.1
VHBH HB threshold hysteresis 0.4 V
BOOT STRAP DIODE
TJ= 25°C 0.52
VDL Low-current forward voltage IVDD-HB = 100 µA V
TJ= –40°C to 125°C 0.85
TJ= 25°C 0.8
VDH High-current forward voltage IVDD-HB = 100 mA V
TJ= –40°C to 125°C 1
TJ= 25°C 1.0
Dynamic resistance
RDIVDD-HB = 100 mA Ω
LM5100A/B/C, LM5101A/B/C TJ= –40°C to 125°C 1.65
LO AND HO GATE DRIVER
TJ= 25°C 0.12
Low-level output voltage V
LM5100A/LM5101A TJ= –40°C to 125°C 0.25
TJ= 25°C 0.16
Low-level output voltage
VOL IHO = ILO = 100 mA V
LM5100B/LM5101B TJ= –40°C to 125°C 0.4
TJ= 25°C 0.28
Low-level output voltage V
LM5100C/LM5101C TJ= –40°C to 125°C 0.65
TJ= 25°C 0.24
High-level output voltage V
LM5100A/LM5101A TJ= –40°C to 125°C 0.45
IHO = ILO = 100 mA TJ= 25°C 0.28
High-level output voltage
VOH VOH = VDD– LO or V
LM5100B/LM5101B TJ= –40°C to 125°C 0.60
VOH = HB - HO TJ= 25°C 0.6
High-level output voltage V
LM5100C/LM5101C TJ= –40°C to 125°C 1.10
Peak pullup current 3 A
LM5100A/LM5101A
Peak pullup current
IOHL HO, LO = 0 V TJ= 25°C 2 A
LM5100B/LM5101B
Peak pullup current 1 A
LM5100C/LM5101C
Peak pulldown current 3 A
LM5100A/LM5101A
Peak pulldown current
IOLL HO, LO = 12 V TJ= 25°C 2 A
LM5100B/LM5101B
Peak pulldown current 1 A
LM5100C/LM5101C
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,
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,
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LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
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7.6 Switching Characteristics
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LO turnoff propagation delay LM5100A/B/C 20 45 ns
tLPHL LI Falling to LO Falling
LO turnoff propagation delay LM5101A/B/C 22 56 ns
LO turnon propagation delay LM5100A/B/C 20 45 ns
tLPLH LI Rising to LO Rising
LO turnon propagation delay LM5101A/B/C 26 56 ns
HO turnoff propagation delay 20 45 ns
LM5100A/B/C
tHPHL HI Falling to HO Falling
HO turnoff propagation delay 22 56 ns
LM5101A/B/C
LO turnon propagation delay LM5100A/B/C 20 45 ns
tHPLH HI Rising to HO Rising
LO turnon propagation delay LM5101A/B/C 26 56 ns
Delay matching: LO on and HO off 1 10 ns
LM5100A/B/C
tMON Delay matching: LO on and HO off 4 10 ns
LM5101A/B/C
Delay matching: LO off and HO on 1 10 ns
LM5100A/B/C
tMOFF Delay matching: LO on and HO off 4 10 ns
LM5101A/B/C
tRC, tFC Either output rise and fall time CL= 1000 pF 8 ns
Output rise time (3 V to 9 V) 430 ns
LM5100A/LM5101A
Output rise time (3 V to 9 V)
tRCL= 0.1 µF 570 ns
LM5100B/LM5101B
Output rise time (3 V to 9 V) 990 ns
LM5100C/LM5101C
Output fall time (3 V to 9 V) 260 ns
LM5100A/LM5101A
Output fall time (3 V to 9 V)
tFCL= 0.1 µF 430 ns
LM5100B/LM5101B
Output fall time (3 V to 9 V) 715 ns
LM5100C/LM5101C
Minimum input pulse width that changes
tPW 50 ns
the output IF= 100 mA,
tBS Bootstrap diode reverse recovery time 37 ns
IR= 100 mA
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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LI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
HO
LI
HI
tMOFF
tMON
LO
HO
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
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SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Figure 1. Timing Diagram
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0.1 1 10 100 1000
FREQUENCY (kHz)
10
100
1000
10000
100000
CURRENT ( A)μ
VDD = 12 V
CL= 0 pF
CL= 4400 pF
CL= 1000 pF
0.1 1 10 100 1000
FREQUENCY (kHz)
100
1000
10000
100000
CURRENT ( A)μ
VDD = 12 V
CL= 4400 pF
CL= 1000 pF
CL= 0 pF
02 4 68 10 12
OUTPUT VOLTAGE (V)
0.0
3.5
CURRENT (A)
0.5
1.0
1.5
2.0
2.5
3.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12 V
02 4 68 10 12
OUTPUT VOLTAGE (V)
0.0
3.5
CURRENT (A)
0.5
1.0
1.5
2.0
2.5
3.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12 V
7 8 9 10 11 12 13 14 15
CURRENT (A)
VDD (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
7 8 9 10 11 12 13 14 15
CURRENT (A)
VDD (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
7.7 Typical Characteristics
Figure 3. Peak Sinking Current vs VDD
Figure 2. Peak Sourcing Current vs VDD
Figure 4. Sink Current vs Output Voltage Figure 5. Source Current vs Output Voltage
Figure 7. LM5101A/B/C IDD vs Frequency
Figure 6. LM5100A/B/C IDD vs Frequency
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-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
6.30
6.40
6.50
6.60
6.70
6.80
6.90
7.00
7.10
7.20
7.30
THRESHOLD (V)
VHBR
VDDR
TEMPERATURE (oC)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
HYSTERESIS (V)
-50
VHBH
VDDH
0 25
8 9 10 11 12 13 14 15 16
VDD, VHB (V)
0
50
100
150
200
250
300
350
400
CURRENT ( A)μ
IDD (LM5101A/B/C)
IDD (LM5100A/B/C)
IHB
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
CURRENT ( A)μ
IDD (LM5101A/B/C)
IDD (LM5100A/B/C)
IHB
0
50
100
150
200
250
300
350
0.1 1 10 100 1000
FREQUENCY (kHz)
10
100
1000
10000
100000
CURRENT (PA)
HB = 12 V,
HS = 0 V
CL= 0 pF
CL= 4400 pF
CL= 1000 pF
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (oC)
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
CURRENT (mA)
IDDO (LM5101A/B/C)
IDDO (LM5100A/B/C)
IHBO
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
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SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Typical Characteristics (continued)
Figure 8. Operating Current vs Temperature Figure 9. IHB vs Frequency
Figure 10. Quiescent Current vs Supply Voltage Figure 11. Quiescent Current vs Temperature
Figure 13. Undervoltage Threshold Hysteresis vs
Figure 12. Undervoltage Rising Thresholds vs Temperature Temperature
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-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
15
20
25
30
35
DELAY (ns)
T_PHL
T_PLH
THRESHOLD VOLTAGE (V)
8 9 10 11 12 13 14 15 16
VDD (V)
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
1.91
1.92
Rising
Falling
8 9 10 11 12 13 14 15 16
VDD (V)
40
41
42
43
44
45
46
47
48
49
50
THRESHOLD VOLTAGE (%VDD)
Rising
Falling
THRESHOLD VOLTAGE (V)
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
1.91
1.92
Rising
Falling
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
ID(A)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VD(V)
T = 25°C
T = -40°C
T = 150°C
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
40
41
42
43
44
45
46
47
48
49
50
THRESHOLD VOLTAGE (%VDD)
Rising
Falling
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
Typical Characteristics (continued)
Figure 15. LM5100A/B/C Input Threshold vs Temperature
Figure 14. Bootstrap Diode Forward Voltage
Figure 16. LM5101A/B/C Input Threshold vs Temperature Figure 17. LM5100A/B/C Input Threshold vs VDD
Figure 18. LM5101A/B/C Input Threshold vs VDD Figure 19. LM5100A/B/C Propagation Delay vs Temperature
12 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
78 9 10 11 12 13 14 15
VDD (V)
VOL (V)
0.10
0.15
0.35
0.20
0.25
0.30
LM5100B/LM5101B
LM5100A/LM5101A
IOUT = 100 mA
LM5100C/LM5101C
-50 -25 0 25 50 75 100 125 150
VOL (V)
TEMPERATURE (°C)
0.00
0.50
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12 V
78 9 10 11 12 13 14
VDD (V)
15
0.1
0.8
VOH (V)
0.2
0.3
0.4
0.5
0.6
0.7
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
IOUT = -100 mA
T_PLH
T_PHL
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
15
25
30
35
40
DELAY (ns)
20
-50 -25 0 25 50 75 100 125 150
VOH (V)
TEMPERATURE (°C)
0.0
1.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12 V
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Typical Characteristics (continued)
Figure 21. LO and HO Gate Drive - High Level Output
Figure 20. LM5101A/B/C Propagation Delay vs Temperature Voltage vs Temperature
Figure 22. LO and HO Gate Drive - Low Level Output Figure 23. LO and HO Gate Drive - Output High Voltage vs
Voltage vs Temperature VDD
Figure 24. LO and HO Gate Drive - Output Low Voltage vs VDD
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
UVLO LEVEL
SHIFT DRIVER
DRIVER
UVLO
HB
HO
HS
VDD
LO
GND
HI
LI
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The LM5100A/B/C and LM5101A/B/C are designed to drive both the high-side and the low-side N-channel FETs
in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with CMOS input
thresholds(LM5101A/B/C) or TTL input thresholds(LM5101A/B/C). The floating high-side driver is capable of
working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate
drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing
clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on
both the low side and the high side power rails.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Start-up and UVLO
Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the
supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each
driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO
hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD
pin of the LM5100A/B/C and LM5101A/B/C, the outputs of the low-side and high-side are held low until VDD
exceeds the UVLO threshold, typically about 6.6 V. Any UVLO condition on the bootstrap capacitor will disable
only the high-side output (HO).
8.3.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
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Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Feature Description (continued)
8.3.3 Bootstrap Diode
The bootstrap diode necessary to generate the high-side bias is included in the LM5100/1 family. The diode
anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS
pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode
provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable
operation.
8.3.4 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
8.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO
operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.
Table 1. Input/Output Logic Table
HI LI HO(1) LO(2)
LLLL
L H L H
H L H L
HHHH
x(3) x L L
(1) HO is measured with respect to the HS.
(2) LO is measured with the respect to the VSS.
(3) x is floating condition
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
HB
PWM
Controller
VIN
T1
RGATE
CBOOT
0.1 µF
1.0 µF
VDD
VCC
OUT1
OUT2
VDD
HI
LI
VSS
HS
LO
HO
Optional external
fast recovery diode
LM5101A
RBOOT DBOOT
RGATE
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
The LM5100A/B/C and LM5101A/B/C are the high voltage gate drivers that are designed to drive both the high-
side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit.
The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The
outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing
full and independent flexibility to control on and off state of the output.
9.2 Typical Application
Figure 25. LM5101A Driving MOSFETs in Half-Bridge Configuration
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Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
TOTAL
BOOT
HB
Q43.01nC
C 1 8.7 nF
V 2.3 V
= = =
D
MAX
TOTAL gmax HBS
SW
D0.95
Q Q I 43 nC 10 µA 43.01nC
F 100 kHz
= + = + =
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Typical Application (continued)
9.2.1 Design Requirements
See Table 2 for the parameter and values.
Table 2. Operating Parameters
PARAMETER VALUE
Gate Driver LM5101A
MOSFET CSD18531Q5A
VDD 10 V
Qgmax 43 nC
Fsw 100 kHz
Dmax 95%
IHBS 10 µA
VDH 1.0 V
VHBR 7.1 V
VHBH 0.4 V
9.2.2 Detailed Design Procedure
9.2.2.1 Select Bootstrap and VDD capacitor
The bootstrap capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit in any
circumstances during normal operation. Calculate the maximum allowable drop across the bootstrap capacitor
with Equation 1.
ΔVHB = VDD – VDH – VHBL= 10 V – 1.0 V – 6.7 V = 2.3 V
where
• VDD = Supply voltage of the gate drive IC
• VDH = Bootstrap diode forward voltage drop
• VHBL = VHBR – VHBH = 6.7 V, HB falling threshold (1)
The quiescent current of the bootstrap circuit is 10 µA, which is negligible compared to the Qgs of the MOSFET
(see Equation 2 and Equation 3).
(2)
(3)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. It is recommended to place the bootstrap capacitor as
close to the HB and HS pins as possible.
CBOOT = 100 nF (4)
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
CVDD = 10 × CBOOT = 1 µF (5)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
2
DGATES DD L sw
P 2 V C f= ´ ´ ´
DD OH
LOL
GATE
V V 10 V 0.25 V
I 2.074 A
R 4.7
--
= = =
W
DD DH OL
HOL
GATE
V V V 10 V 1.0 V 0.25 V
I 1.862 A
R 4.7
- - - -
= = =
W
DD OH
LOH
GATE
V V 10 V 0.45 V
I 2.032 A
R 4.7
--
= = =
W
DD DH OH
HOH
GATE
V V V 10 V 1.0 V 0.45 V
I 1.819 A
R 4.7
- - - -
= = =
W
( ) DD DBOOT
DBOOT pk
BOOT
V V 10 V 0.6 V
I 4.27 A
R 2.2
--
= = =
W
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
9.2.2.2 Select External Bootstrap Diode and Resistor
The bootstrap capacitor is charged by the VDD through the internal bootstrap diode every cycle when low side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the internal bootstrap diode may be significant and dependent on its forward voltage drop. Both the
diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver and need to
be considered in the gate driver IC power dissipation.
For high frequency and high capacitive loads, it may be necessary to consider using an external bootstrap diode
placed in parallel with internal bootstrap diode to reduce power dissipation of the driver. For the selection of
external bootstrap diodes for LM510x device, please refer to the application note SNVA083.
Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of HB-HS. It is recommended that RBOOT is between 2 Ωand 10 Ω. For this design, a current limiting
resistor of 2.2 Ωis selected to limit inrush current of bootstrap diode.
(6)
9.2.2.3 Select Gate driver Resistor
Resistor RGATE is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the
current coming out of the gate driver. For this design 4.7-Ωresistors were selected for this design. Maximum HO
and LO drive current are calculated by Equation 7 through Equation 10.
(7)
(8)
(9)
where
• IHOH = Maximum HO source current
• ILOH = Maximum LO source current
• IHOL = Maximum HO sink current
• ILOH = Maximum HO sink current
• VOH = High-Level output voltage drop across HB to HO or VDD to LO
• VOL = Low-Level output voltage drop across HO to HS or LO to GND (10)
9.2.2.4 Estimate the Driver Power Losses
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (fsw), output load capacitance on LO and HO (CL), and supply
voltage (VDD). The gate charge losses can be calculated by Equation 11.
(11)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with Equation 11.Figure 26 can be used to approximate
the power losses due to the gate drivers.
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Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
J A
loss
JA
T T
P
Rq
-
=
110 100 1000
SWITCHING FREQUENCY (kHz)
POWER (W)
0.001
0.010
0.100
CL= 4400 pF
CL= 0 pF
0.1 1.0 10.0 100.0 1000.0
SWITCHING FREQUENCY (kHz)
0.001
0.010
0.100
1.000
POWER (W)
CL= 4400 pF
CL= 0 pF
CL= 1000 pF
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
Figure 26. Gate Driver Power Dissipation (LO + HO)
VDD = 12 V, Neglecting Diode Losses
The internal bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculation
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the internal diode power dissipation. If the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode can be helpful to reduce power dissipation within the IC.
Figure 27. Diode Power Dissipation VIN = 50 V
The total IC power dissipation can be estimated from the plots shown in Figure 26 and Figure 27 by summing the
gate drive losses with the internal bootstrap diode losses for the intended application. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as equation Equation 12.
where
• Ploss = The total power dissipation of the driver
• TJ= Junction temperature
• TA= Ambient temperature
• RθJA = Junction-to-ambient thermal resistance (12)
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
The thermal metrics for the driver package is summarized in the Thermal Information table. For detailed
information regarding the thermal information table, refer to the Application Note from Texas Instruments entitled
Semiconductor and IC Package Thermal Metrics SPRA953.
9.2.3 Application Curves
Figure 28. HI/LI to HO/LO Turnon Propagation Delay Figure 29. HI/LI to HO/LO Turnoff Propagation Delay
10 Power Supply Recommendations
The bias supply voltage range for which the device is rated to operate is from 9 V to 14 V. The lower end of this
range is governed by the internal under voltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VDDR supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 18-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 4-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 14 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDDH.
Therefore, ensuring that, while operating at or near the 9-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the
threshold (VDDR – VDDH), which must be accounted for while evaluating system shutdown timing design
requirements. Likewise, at system start up, the device does not begin operation until the VDD pin voltage has
exceeded above the VDDR threshold. The quiescent current consumed by the internal circuit blocks of the device
is supplied through the VDD pin. Keep in mind that the charge for source current pulses delivered by the LO pin
is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin a
corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass
capacitor is provided between the VDD and GND pins and located as close as possible to the device for the
purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is necessary. TI recommends
using two capacitors between VDD and GND: a 100-nF ceramic surface-mount capacitor that can be nudged
very close to the pins of the device and another surface-mount capacitor in the range 0.22 µF to 10 µF added in
parallel. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore,
a 0.022-µF to 1-µF local decoupling capacitor is recommended between the HB and HS pins.
20 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
To Hi-Side FET To Low-Side FET
HO
Single Layer
Option
LO
GND
Multi Layer
Option
Recommended Layout for Driver IC and
Passives
VSS
LO
LI
SO
PowerPAD-8
HI
VDD
HB
HO
HS
HO
HS
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
www.ti.com
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
11 Layout
11.1 Layout Guidelines
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low-ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turnon of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
A recommended layout pattern for the driver is shown in Figure 30. If possible a single layer placement is
preferred.
11.2 Layout Example
Figure 30. PCB Layout Recommendation
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A
,
LM5100B
,
LM5100C
LM5101A
,
LM5101B
,
LM5101C
SNOSAW2Q –SEPTEMBER 2006–REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
•AN-1317 Selection of External Bootstrap Diode for LM510X Devices (SNVA083)
•Semiconductor and IC Package Thermal Metrics (SPRA953)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LM5100A Click here Click here Click here Click here Click here
LM5100B Click here Click here Click here Click here Click here
LM5100C Click here Click here Click here Click here Click here
LM5101A Click here Click here Click here Click here Click here
LM5101B Click here Click here Click here Click here Click here
LM5101C Click here Click here Click here Click here Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5100AM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR L5100
AMR
LM5100AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green Call TI | SN Level-3-260C-168 HR L5100
AMR
LM5100AMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100ASD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5100ASD
LM5100BMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BSD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5100BSD
LM5100CMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5100
CMA
LM5101AM/NOPB ACTIVE SOIC D 8 95 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR L5101
AMR
LM5101AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR L5101
AMR
LM5101AMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101ASD NRND WSON DPR 10 1000 Non-RoHS
& Green Call TI Call TI -40 to 125 5101ASD
LM5101ASD-1/NOPB ACTIVE WSON NGT 8 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 5101A-1
LM5101ASD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASDX NRND WSON DPR 10 4500 Non-RoHS
& Green Call TI Call TI -40 to 125 5101ASD
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5101ASDX-1/NOPB ACTIVE WSON NGT 8 4500 RoHS & Green SN Level-1-260C-UNLIM 5101A-1
LM5101ASDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101BMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BSD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101CMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM SXDB
LM5101CMYE/NOPB ACTIVE HVSSOP DGN 8 250 RoHS & Green SN Level-1-260C-UNLIM SXDB
LM5101CMYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM SXDB
LM5101CSD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101CSD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 3
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5100AMRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101AMRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASD-1/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LM5101ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LM5101ASDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5101BSD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LM5101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101CMY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CMYE/NOPB HVSSOP DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CMYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CSD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5100AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LM5100AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5100BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5100CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LM5101AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101ASD WSON DPR 10 1000 210.0 185.0 35.0
LM5101ASD-1/NOPB WSON NGT 8 1000 200.0 183.0 25.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5101ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5101ASD/NOPB WSON DPR 10 1000 200.0 183.0 25.0
LM5101ASDX WSON DPR 10 4500 367.0 367.0 35.0
LM5101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0
LM5101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101BSD/NOPB WSON DPR 10 1000 200.0 183.0 25.0
LM5101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101CMY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0
LM5101CMYE/NOPB HVSSOP DGN 8 250 210.0 185.0 35.0
LM5101CMYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0
LM5101CSD/NOPB WSON DPR 10 1000 200.0 183.0 25.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
www.ti.com
PACKAGE OUTLINE
C
10X 0.35
0.25
3 0.1
2.6 0.1
0.8
0.7
8X 0.8
10X 0.5
0.3
(0.1) TYP
2X
3.2
0.05
0.00
B4.1
3.9 A
4.1
3.9
(0.2)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SEE ALTERNATIVE
LEAD DETAIL
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
20.000
FULL R
ALTERNATIVE LEAD
DETAIL
BOTTOM VIEW SIDE VIEW
www.ti.com
EXAMPLE BOARD LAYOUT
(R0.05) TYP
8X (0.8)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(2.6)
(3.8)
10X (0.3)
10X (0.6)
(3)
( 0.2) VIA
TYP
(1.25)
(1.05)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
SYMM
1
56
10
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
11
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
EDGE
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
10X (0.3)
10X (0.6)
8X (0.8)
4X
(1.31)
4X (1.15)
(0.76)
(3.8)
(R0.05) TYP
(0.68)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
SYMM
1
56
10
SYMM
METAL
TYP
11
www.ti.com
PACKAGE OUTLINE
C
6X 0.65
2X
1.95
8X 0.38
0.25
5.05
4.75 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.1 MAX
0.23
0.13
1.88
1.58
2.0
1.7
B3.1
2.9
NOTE 4
A
3.1
2.9
NOTE 3
0.7
0.4
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
1
4
5
8
0.13 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
PowerPAD is a trademark of Texas Instruments.
TM
A 20
DETAIL A
TYPICAL
SCALE 4.000
EXPOSED THERMAL PAD
1
45
8
9
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(2)
NOTE 9
(3)
NOTE 9
(1.22)
(0.55)
( 0.2) TYP
VIA
(1.88)
(2)
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SYMM
SYMM
1
45
8
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
SEE DETAILS
9
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(1.88)
BASED ON
0.125 THICK
STENCIL
(2)
BASED ON
0.125 THICK
STENCIL
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
1.59 X 1.690.175 1.72 X 1.830.15 1.88 X 2.00 (SHOWN)0.125 2.10 X 2.240.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
1
45
8
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
www.ti.com
PACKAGE OUTLINE
C
6X 1.27
8X 0.51
0.31
2X
3.81
TYP
0.25
0.10
0 - 8 0.15
0.00
2.71
2.11
3.4
2.8 0.25
GAGE PLANE
1.27
0.40
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
PowerPAD is a trademark of Texas Instruments.
TM
18
0.25 C A B
5
4
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
EXPOSED
THERMAL PAD
4
1
5
8
9
TYP
6.2
5.8
1.7 MAX
A
NOTE 3
5.0
4.8
B4.0
3.8
www.ti.com
EXAMPLE BOARD LAYOUT
(5.4)
(1.3) TYP
( ) TYP
VIA
0.2
(R ) TYP0.05
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.55)
8X (0.6)
6X (1.27)
(2.95)
NOTE 9
(4.9)
NOTE 9
(2.71)
(3.4)
SOLDER MASK
OPENING
(1.3)
TYP
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
SOLDER MASK
OPENING
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
9
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(R ) TYP0.05
8X (1.55)
8X (0.6)
6X (1.27)
(5.4)
(2.71)
(3.4)
BASED ON
0.125 THICK
STENCIL
4214849/A 08/2016
PowerPAD SOIC - 1.7 mm max heightDDA0008B
PLASTIC SMALL OUTLINE
2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
SYMM
SYMM
1
45
8
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
9
www.ti.com
PACKAGE OUTLINE
C
8X 0.35
0.25
3 0.05
2X
2.4
2.6 0.05
6X 0.8
0.8 MAX
0.05
0.00
8X 0.5
0.3
A4.1
3.9 B
4.1
3.9
(0.2) TYP
WSON - 0.8 mm max heightNGT0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214935/A 08/2020
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SYMM
SYMM
9
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.3)
(3)
(3.8)
6X (0.8)
(2.6)
( 0.2) VIA
TYP (1.05)
(1.25)
8X (0.6)
(R0.05) TYP
WSON - 0.8 mm max heightNGT0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214935/A 08/2020
SYMM
1
45
8
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
(1.31)
(0.675)
8X (0.3)
8X (0.6)
(1.15)
(3.8)
(0.755)
6X (0.8)
WSON - 0.8 mm max heightNGT0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214935/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
METAL
TYP
SYMM 9
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