LTC2481HDD#PBF - Linear Technology Corporation

LTC2481

2481fc

TYPICAL APPLICATION

FEATURES DESCRIPTION

16-Bit ΔΣ ADC with Easy Drive

Input Current Cancellation

and I2C Interface

The LTC

2481 combines a 16-bit plus sign No Latency ΔΣ™

analog-to-digital converter with patented Easy Drive

technology and I2C digital interface. The patented sampling

scheme eliminates dynamic input current errors and the

shortcomings of on-chip buffering through automatic

cancellation of differential input current. This allows large

external source impedances and input signals, with rail-to-

rail input range to be directly digitized while maintaining

exceptional DC accuracy.

The LTC2481 includes on-chip programmable gain, a

temperature sensor and an oscillator. The LTC2481 can

be conﬁ gured through an I2C interface to provide a pro-

grammable gain from 1 to 256 in 8 steps, to digitize an

external signal or internal temperature sensor, reject line

frequencies (50Hz, 60Hz or simultaneous 50Hz/60Hz) as

well as a 2x speed-up mode.

The LTC2481 allows a wide common mode input range

(0V to VCC) independent of the reference voltage. The

reference can be as low as 100mV or can be tied directly

to VCC. The LTC2481 includes an on-chip trimmed oscil-

lator eliminating the need for external crystals or oscil-

lators. Absolute accuracy and low drift are automatically

maintained through continuous, transparent, offset and

full-scale calibration.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Patents Pending.

+FS Error vs RSOURCE at IN+ and IN–

APPLICATIONS

n Easy Drive™ Technology Enables Rail-to-Rail Inputs

with Zero Differential Input Current

n Directly Digitizes High Impedance Sensors with

Full Accuracy

n Programmable Gain from 1 to 256

n Integrated Temperature Sensor

n GND to VCC Input/Reference Common Mode Range

n 2-Wire I2C Interface

n Programmable 50Hz, 60Hz or Simultaneous

50Hz/60Hz Rejection Mode

n 2ppm (0.25LSB) INL, No Missing Codes

n 1ppm Offset and 15ppm Full-Scale Error

n Selectable 2x Speed Mode

n No Latency: Digital Filter Settles in a Single Cycle

n Single Supply 2.7V to 5.5V Operation

n Internal Oscillator

n Six Addresses Available and One Global Address for

Synchronization

n Available in a Tiny (3mm × 3mm) 10-Lead DFN Package

n Direct Sensor Digitizer

n Weight Scales

n Direct Temperature Measurement

n Strain Gauge Transducers

n Instrumentation

n Industrial Process Control

n DVMs and Meters

LTC2481

VIN+REF+VCC

VCC

GND

VIN–

1µF

SDA

2-WIRE

I2C INTERFACE

0.1µF

10k IDIFF = 0

10k

CA0/f0

2481 TA01a

CA1

SCL

6 ADDRESSES

REF–

SENSE

RSOURCE ()

+FS ERROR (ppm)

–20

1k 100k

2481 TA01b

–40

–60

–80 10 100 10k

80 VCC = 5V

VREF = 5V

VIN+ = 3.75V

VIN– = 1.25V

fO = GND

TA = 25°C

CIN = 1µF

LTC2481

2481fc

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) to GND ...................... –0.3V to 6V

Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)

Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)

Digital Input Voltage to GND ....... –0.3V to (VCC + 0.3V)

Digital Output Voltage to GND ...... –0.3V to (VCC + 0.3V)

Operating Temperature Range

LTC2481C .................................................... 0°C to 70°C

LTC2481I .................................................–40°C to 85°C

LTC2481H .............................................. –40°C to 125°C

Storage Temperature Range ................. –65°C to 125°C

(Notes 1, 2)

TOP VIEW

DD PACKAGE

10-LEAD

(

3mm s 3mm

)

PLASTIC DFN

1CA0/f0

CA1

GND

SDA

SCL

REF+

VCC

REF–

IN+

IN–

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2481CDD#PBF LTC2481CDD#TRPBF LBPV 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C

LTC2481IDD#PBF LTC2481IDD#TRPBF LBPV 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC2481HDD#PBF LTC2481HDD#TRPBF LBPV 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ

cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS (NORMAL SPEED)

The l denotes the speciﬁ cations which

apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) l16 Bits

Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)

2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)

10 ppm of VREF

ppm of VREF

Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l0.5 2.5 µV

Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 10 nV/°C

Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF

2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF (H-Grade)

l25

ppm of VREF

ppm

Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF /°C

Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF

2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF (H-Grade)

l25

ppm of VREF

ppm

Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF

, IN+ = 0.25VREF 0.1 ppm of VREF/°C

Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)

5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)

2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)

ppm of VREF

Output Noise 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 12) 0.6 µVRMS

Internal PTAT Signal TA = 27°C 420 mV

Internal PTAT Temperature Coefﬁ cient 1.4 mV/°C

Programmable Gain See Table 2a l1 256

LTC2481

2481fc

ELECTRICAL CHARACTERISTICS (2X SPEED)

The l denotes the speciﬁ cations which apply over

the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) l16 Bits

Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)

2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)

10 ppm of VREF

Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l0.5 2 mV

Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 100 nV/°C

Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l25 ppm of VREF

Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C

Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF l25 ppm of VREF

Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF 0.1 ppm of VREF/°C

Output Noise 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC 0.84 µVRMS

Programmable Gain See Table 2b l1 128

CONVERTER CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Notes 3, 4)

ANALOG INPUT AND REFERENCE

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN+Absolute/Common Mode IN+ Voltage GND – 0.3V VCC + 0.3V V

IN–Absolute/Common Mode IN– Voltage GND – 0.3V VCC + 0.3V V

FS Full Scale of the Differential Input (IN+ – IN–)l0.5VREF/GAIN V

LSB Least Signiﬁ cant Bit of the Output Code lFS/216

VIN Input Differential Voltage Range (IN+ – IN–)l–FS +FS V

VREF Reference Voltage Range (REF+ – REF–)l0.1 VCC V

CS (IN+)IN

+ Sampling Capacitance 11 pF

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) l140 dB

Input Common Mode Rejection

50Hz ±2%

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) l140 dB

Input Common Mode Rejection

60Hz ±2%

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) l140 dB

Input Normal Mode Rejection

50Hz ±2%

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7)

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (H-Grade)

110

104

120 dB

Input Normal Mode Rejection

60Hz ±2%

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8)

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (H-Grade)

110

104

120 dB

Input Normal Mode Rejection

50Hz/60Hz ±2%

2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9) l87 dB

Reference Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) l120 140 dB

Power Supply Rejection DC VREF = 2.5V, IN– = IN+ = GND 120 dB

Power Supply Rejection, 50Hz ±2% VREF = 2.5V, IN– = IN+ = GND (Notes 7, 9) 120 dB

Power Supply Rejection, 60Hz ±2% VREF = 2.5V, IN– = IN+ = GND (Notes 8, 9) 120 dB

LTC2481

2481fc

ANALOG INPUT AND REFERENCE

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CS (IN–)IN

– Sampling Capacitance 11 pF

CS (VREF)V

REF Sampling Capacitance 11 pF

IDC_LEAK (IN+)IN

+ DC Leakage Current Sleep Mode, IN+ = GND l–10 1 10 nA

IDC_LEAK (IN–)IN

– DC Leakage Current Sleep Mode, IN– = GND l–10 1 10 nA

IDC_LEAK (VREF)REF

+, REF– DC Leakage Current Sleep Mode, VREF = VCC l–100 1 100 nA

I2C DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁ cations which apply over

the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Notes 3, 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage l0.7VCC V

VIL Low Level Input Voltage l0.3VCC V

VIL(CA1) Low Level Input Voltage for Address Pin l0.05VCC V

VIH(CA0/f0,CA1) High Level Input Voltage for Address Pins l0.95VCC V

RINH Resistance from CA0/f0, CA1 to VCC to Set

Chip Address Bit to 1

l 10 k

RINL Resistance from CA1 to GND to Set Chip

Address Bit to 0

l 10 k

RINF Resistance from CA0/f0, CA1 to VCC or

GND to Set Chip Address Bit to Float

l2 M

IIDigital Input Current l–10 10 µA

VHYS Hysteresis of Schmitt Trig ger Inputs (Note 5) 0.05VCC V

VOL Low Level Output Voltage SDA I = 3mA l 0.4 V

tOF Output Fall Time from VIHMIN to VILMAX Bus Load CB 10pF to 400pF (Note 14) l20+0.1CB250 ns

tSP Input Spike Suppression l50 ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ VCC l 1µA

CICapacitance for Each I/O Pin l 10 pF

CBCapacitance Load for Each Bus Line l 400 pF

CCAX External Capacitive Load On-Chip Address

Pins (CA0/f0,CA1) for Valid Float

l10 pF

VIH(EXT,OSC) High Level CA0/f0 External Oscillator 2.7V ≤ VCC < 5.5V lVCC – 0.5V V

VIL(EXT,OSC) Low Level CA0/f0 External Oscillator 2.7V ≤ VCC < 5.5V l0.5 V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l2.7 5.5 V

ICC Supply Current Conversion Mode (Note 11)

Sleep Mode (Note 11)

H-Grade

160

250

µA

POWER REQUIREMENTS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 3)

LTC2481

2481fc

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fEOSC External Oscillator Frequency Range l10 4000 kHz

tHEO External Oscillator High Period l0.125 100 µs

tLEO External Oscillator Low Period l0.125 100 µs

tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode

50Hz Mode (H-Grade)

60Hz Mode

60Hz Mode (H-Grade)

Simultaneous 50Hz/60Hz Mode

Simultaneous 50Hz/60Hz Mode (H-Grade)

External Oscillator (Note 10)

157.2

131.0

144.1

160.3

133.6

146.9

41036/fEOSC

163.5

165.1

136.3

137.6

149.9

151.0

tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode

50Hz Mode (H-Grade)

60Hz Mode

60Hz Mode (H-Grade)

Simultaneous 50Hz/60Hz Mode

Simultaneous 50Hz/60Hz Mode (H-Grade)

External Oscillator (Note 10)

78.7

65.6

72.2

80.3

66.9

73.6

20556/fEOSC

81.9

82.7

68.2

68.9

75.1

75.6

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 3)

I2C TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Notes 3, 15)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(SDA) Hold Time (Repeated) START Condition l0.6 µs

tLOW LOW Period of the SCL Clock Pin l1.3 µs

tHIGH HIGH Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated START Condition l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time for Both SDA and SCL Signals (Note 14) l20+0.1CB 300 ns

tfFall Time for Both SDA and SCL Signals (Note 14) l20+0.1CB 300 ns

tSU(STO) Set-Up Time for STOP Condition l0.6 µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: VCC = 2.7V to 5.5V unless otherwise speciﬁ ed.

REF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF/GAIN;

IN = IN+ – IN–, VINCM = (IN+ + IN–)/2.

Note 4: Use internal conversion clock or external conversion clock source

with fEOSC = 307.2kHz unless otherwise speciﬁ ed.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is deﬁ ned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external

oscillator).

Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external

oscillator).

Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =

280kHz ±2% (external oscillator).

Note 10: The external oscillator is connected to the CA0/f0 pin. The

external oscillator frequency, fEOSC, is expressed in kHz.

Note 11: The converter uses the internal oscillator.

Note 12: The output noise includes the contribution of the internal

calibration operations.

Note 13: Guaranteed by design and test correlation.

Note 14: CB = capacitance of one bus line in pF.

Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.

LTC2481

2481fc

TYPICAL PERFORMANCE CHARACTERISTICS

Total Unadjusted Error

(VCC = 5V, VREF = 5V)

Total Unadjusted Error

(VCC = 5V, VREF = 2.5V)

Total Unadjusted Error

(VCC = 2.7V, VREF = 2.5V)

Noise Histogram (6.8sps) Noise Histogram (7.5sps) Long-Term ADC Readings

Integral Nonlinearity

(VCC = 5V, VREF = 5V)

Integral Nonlinearity

(VCC = 5V, VREF = 2.5V)

Integral Nonlinearity

(VCC = 2.7V, VREF = 2.5V)

INPUT VOLTAGE (V)

–3

INL (ppm OF VREF)

–1

–2

–1.5 –0.5 0.5 1.5

2481 G01

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

85°C

–45°C 25°C

INPUT VOLTAGE (V)

–3

INL (ppm OF VREF)

–1

–2

–0.75 –0.25 0.25 0.75

2481 G02

1.25–1.25

VCC = 5V

VREF = 2.5V

VIN(CM) = 1.25V

–45°C, 25°C, 90°C

INPUT VOLTAGE (V)

–3

INL (ppm OF VREF)

–1

–2

–0.75 –0.25 0.25 0.75

2481 G03

1.25–1.25

VCC = 2.7V

VREF = 2.5V

VIN(CM) = 1.25V

–45°C, 25°C, 90°C

INPUT VOLTAGE (V)

–12

TUE (ppm OF VREF)

–4

–8

–1.5 –0.5 0.5 1.5

2481 G04

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V 85°C

25°C

–45°C

INPUT VOLTAGE (V)

–12

TUE (ppm OF VREF)

–4

–8

–0.75 –0.25 0.25 0.75

2481 G05

1.25–1.25

VCC = 5V

VREF = 2.5V

VIN(CM) = 1.25V 85°C

25°C

–45°C

INPUT VOLTAGE (V)

–12

TUE (ppm OF VREF)

–4

–8

–0.75 –0.25 0.25 0.75

2481 G06

1.25–1.25

VCC = 2.7V

VREF = 2.5V

VIN(CM) = 1.25V

85°C

25°C

–45°C

OUTPUT READING (µV)

–3

NUMBER OF READINGS (%)

0.6

2481 G07

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

14 10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 5V

VIN = 0V

GAIN = 256

TA = 25°C

RMS = 0.60µV

AVERAGE = –0.69µV

OUTPUT READING (µV)

–3

NUMBER OF READINGS (%)

0.6

2481 G08

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

14 10,000 CONSECUTIVE

READINGS

VCC = 2.7V

VREF = 2.5V

VIN = 0V

GAIN = 256

TA = 25°C

RMS = 0.59µV

AVERAGE = –0.19µV

TIME (HOURS)

–5

ADC READING (MV)

–3

–1

10 20 30 40

2481 G09

–4

–2

VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V

GAIN = 256, TA = 25°C, RMS NOISE = 0.60µV

LTC2481

2481fc

TYPICAL PERFORMANCE CHARACTERISTICS

RMS Noise vs VCC RMS Noise vs VREF Offset Error vs VIN(CM)

Offset Error vs Temperature Offset Error vs VCC Offset Error vs VREF

RMS Noise

vs Input Differential Voltage RMS Noise vs VIN(CM) RMS Noise vs Temperature (TA)

INPUT DIFFERENTIAL VOLTAGE (V)

0.4

RMS NOISE (ppm OF VREF)

0.6

0.8

1.0

0.5

0.7

0.9

–1.5 –0.5 0.5 1.5

2481 G10

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

VIN(CM) (V)

–1

RMS NOISE (µV)

0.8

0.9

1.0

2481 G11

0.7

0.6

01 356

0.5

0.4

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

GAIN = 256

TA = 25°C

TEMPERATURE (°C)

–45

0.4

RMS NOISE (µV)

0.5

0.6

0.7

0.8

1.0

–30 –15 15

0 304560

2481 G12

75 90

0.9

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

GAIN = 256

VCC (V)

2.7

RMS NOISE (µV)

0.8

0.9

1.0

3.9 4.7

2481 G13

0.7

0.6

3.1 3.5 4.3 5.1 5.5

0.5

0.4

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

GAIN = 256

TA = 25°C

VREF (V)

0.4

RMS NOISE (µV)

0.5

0.6

0.7

0.8

0.9

1.0

1234

2481 G14

VCC = 5V

VIN = 0V

VIN(CM) = GND

GAIN = 256

TA = 25°C

VIN(CM) (V)

–1

OFFSET ERROR (ppm OF VREF)

0.1

0.2

0.3

2481 G15

–0.1

01 356

–0.2

–0.3

VCC = 5V

VREF = 5V

VIN = 0V

TA = 25°C

TEMPERATURE (°C)

–45

–0.3

OFFSET ERROR (ppm OF VREF)

–0.2

0.1

0.2

–15 15 30 90

2481 G16

–0.1

–30 0 45 60 75

0.3 VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

VCC (V)

2.7

OFFSET ERROR (ppm OF VREF)

0.1

0.2

0.3

3.9 4.7

2481 G17

–0.1

3.1 3.5 4.3 5.1 5.5

–0.2

–0.3

REF+ = 2.5V

REF– = GND

VIN = 0V

VIN(CM) = GND

TA = 25°C

VREF (V)

–0.3

OFFSET ERROR (ppm OF VREF)

–0.2

–0.1

0.1

0.2

0.3

1234

2481 G18

VCC = 5V

REF– = GND

VIN = 0V

VIN(CM) = GND

TA = 25°C

LTC2481

2481fc

TYPICAL PERFORMANCE CHARACTERISTICS

On-Chip Oscillator Frequency

vs VCC PSRR vs Frequency at VCC PSRR vs Frequency at VCC

PSRR vs Frequency at VCC

Conversion Current

vs Temperature

Sleep Mode Current

vs Temperature

Temperature Sensor

vs Temperature

Temperature Sensor Error

vs Temperature

On-Chip Oscillator Frequency

vs Temperature

TEMPERATURE (°C)

–60

VPTAT/VREF (V)

0.35

0.40

120

2481 G19

0.30

0.20 30090–30 60

0.25

VCC = 5V

VREF = 1.4V

TEMPERATURE (°C)

–60

TEMPERATURE ERROR (°C)

2481 G20

–1

–3

–2

–4

–5 –30 030 90 120

VCC = 5V

VREF = 1.4V

TEMPERATURE (°C)

–45 –30

300

FREQUENCY (kHz)

304

310

–15 30 45

2481 G21

302

308

306

150 60 75 90

VCC = 4.1V

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

VCC (V)

2.5

300

FREQUENCY (kHz)

302

304

306

308

310

3.0 3.5 4.0 4.5

2481 G22

5.0 5.5

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

FREQUENCY AT VCC (Hz)

–20

–40

–60

–80

–100

–120

–140 1k 100k

2481 G23

10 100 10k 1M

REJECTION (dB)

VCC = 4.1V DC

VREF = 2.5V

IN+ = GND

IN– = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

–140

REJECTION (dB)

–120

–80

–60

–40

20 100 140

2481 G24

–100

–20

80 180 220200

40 60 120 160

VCC = 4.1V DC ±1.4V

VREF = 2.5V

IN+ = GND

IN– = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

30600

–60

–40

30750

2481 G25

–80

–100

30650 30700 30800

–120

–140

–20

REJECTION (dB)

VCC = 4.1V DC ±0.7V

VREF = 2.5V

IN+ = GND

IN– = GND

TA = 25°C

TEMPERATURE (°C)

–45

100

CONVERSION CURRENT (µA)

120

160

180

200

–15 15 30 90

2481 G26

140

–30 0 45 60 75

VCC = 5V

VCC = 2.7V

TEMPERATURE (°C)

–45

SLEEP MODE CURRENT (µA)

0.2

0.6

0.8

1.0

2.0

1.4

–15 15 30 90

2481 G27

0.4

1.6

1.8

1.2

–30 0 45 60 75

VCC = 5V

VCC = 2.7V

LTC2481

2481fc

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (2x Speed

Mode; VCC = 2.7V, VREF = 2.5V)

Noise Histogram

(2x Speed Mode)

RMS Noise vs VREF

(2x Speed Mode)

Offset Error vs VIN(CM)

(2x Speed Mode)

Offset Error vs Temperature

(2x Speed Mode)

Conversion Current

vs Output Data Rate

Integral Nonlinearity (2x Speed

Mode; VCC = 5V, VREF = 5V)

Integral Nonlinearity (2x Speed

Mode; VCC = 5V, VREF = 2.5V)

OUTPUT DATA RATE (READINGS/SEC)

SUPPLY CURRENT (µA)

500

450

400

350

300

250

200

150

100 80

2481 G28

20 40 60 1007010 30 50 90

VCC = 5V

VCC = 3V

VREF = VCC

IN+ = GND

IN– = GND

CA0/f0 = EXT OSC

TA = 25°C

INPUT VOLTAGE (V)

–3

INL (ppm OF VREF)

–1

–2

–1.5 –0.5 0.5 1.5

2481 G29

2.5–2–2.5 –1 0 1 2

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

25°C, 90°C

–45°C

INPUT VOLTAGE (V)

–3

INL (ppm OF VREF)

–1

–2

–0.75 –0.25 0.25 0.75

2481 G30

1.25–1.25

VCC = 5V

VREF = 2.5V

VIN(CM) = 1.25V

90°C

–45°C, 25°C

INPUT VOLTAGE (V)

–3

INL (ppm OF VREF)

–1

–2

–0.75 –0.25 0.25 0.75

2481 G31

1.25–1.25

VCC = 2.7V

VREF = 2.5V

VIN(CM) = 1.25V

90°C

–45°C, 25°C

OUTPUT READING (µV)

179

NUMBER OF READINGS (%)

186.2

2481 G32

181.4 183.8 188.6

10,000 CONSECUTIVE

READINGS

VCC = 5V

VREF = 5V

VIN = 0V

GAIN = 256

TA = 25°C

RMS = 0.86µV

AVERAGE = 0.184mV

VREF (V)

RMS NOISE (µV)

0.6

0.8

1.0

2481 G33

0.4

0.2

01235

VCC = 5V

VIN = 0V

VIN(CM) = GND

TA = 25°C

VIN(CM) (V)

–1

180

OFFSET ERROR (µV)

182

186

188

190

200

194

134

2481 G34

184

196

198

192

0256

VCC = 5V

VREF = 5V

VIN = 0V

TA = 25°C

TEMPERATURE (°C)

–45

OFFSET ERROR (µV)

200

210

220

2481 G35

190

180

160 –15 15 45

–30 90

030 60

170

240

230

VCC = 5V

VREF = 5V

VIN = 0V

VIN(CM) = GND

LTC2481

2481fc

PIN FUNCTIONS

REF+ (Pin 1), REF– (Pin 3): Differential Reference Input.

The voltage on these pins can have any value between

GND and VCC as long as the reference positive input,

REF+, is more positive than the reference negative input,

REF–, by at least 0.1V.

VCC (Pin 2): Positive Supply Voltage. Bypass to GND

(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF

ceramic capacitor as close to the part as possible.

IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The

voltage on these pins can have any value between GND

– 0.3V and VCC + 0.3V. Within these limits the converter

bipolar input range (VIN = IN+ – IN–) extends from –0.5

• VREF /GAIN to 0.5 • VREF/GAIN. Outside this input

range the converter produces unique overrange and

underrange output codes.

TYPICAL PERFORMANCE CHARACTERISTICS

PSRR vs Frequency at VCC

(2x Speed Mode)

PSRR vs Frequency at VCC

(2x Speed Mode)

Offset Error vs VCC

(2x Speed Mode)

Offset Error vs VREF

(2x Speed Mode)

PSRR vs Frequency at VCC

(2x Speed Mode)

VCC (V)

2.7

OFFSET ERROR (µV)

100

250

344.5

2481 G36

200

150

3.5 55.5

VREF = 2.5V

VIN = 0V

VIN(CM) = GND

TA = 25°C

VREF (V)

OFFSET ERROR (µV)

190

200

210

2481 G37

180

170

160 12 4

220

230

240 VCC = 5V

VIN = 0V

VIN(CM) = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

–20

–40

–60

–80

–100

–120

–140 1k 100k

2481 G38

10 100 10k 1M

REJECTION (dB)

VCC = 4.1V DC

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

–140

RREJECTION (dB)

–120

–80

–60

–40

20 100 140

2481 G39

–100

–20

80 180 220200

40 60 120 160

VCC = 4.1V DC ±1.4V

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

TA = 25°C

FREQUENCY AT VCC (Hz)

30600

–60

–40

30750

2481 G40

–80

–100

30650 30700 30800

–120

–140

–20

REJECTION (dB)

VCC = 4.1V DC ±0.7V

REF+ = 2.5V

REF– = GND

IN+ = GND

IN– = GND

TA = 25°C

LTC2481

2481fc

PIN FUNCTIONS

FUNCTIONAL BLOCK DIAGRAM

SCL (Pin 6): Serial Clock Pin of the I2C Interface. The

LTC2481 can only act as a slave and the SCL pin only ac-

cepts external serial clock. Data is shifted into the SDA pin

on the rising edges of the SCL clock and output through

the SDA pin on the falling edges of the SCL clock.

SDA (Pin 7): Bidirectional Serial Data Line of the I2C Inter-

face. In the transmitter mode (Read), the conversion result

is output through the SDA pin, while in the receiver mode

(Write), the device conﬁ guration bits are input through the

SDA pin. At data input mode, the pin is high impedance;

while at data output mode, it is an open-drain N-channel

driver and therefore an external pull-up resistor or current

source to VCC is needed.

GND (Pin 8): Ground. Connect this pin to a ground plane

through a low impedance connection.

CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is

conﬁ gured as a three state (LOW, HIGH, or Floating) ad-

dress control bit for the device I2C address.

CA0/f0 (Pin 10): Chip Address Control Pin/External Clock

Input Pin. When no transition is detected on the CA0/f0

pin, it is a two state (HIGH or Floating) address control

bit for the device I2C address. When the pin is driven by

an external clock signal with a frequency fEOSC of at least

10kHz, the converter uses this signal as its system clock

and the fundamental digital ﬁ lter rejection null is located

at a frequency fEOSC/5120 and sets the Chip Address CA0

internally to a HIGH.

3RD ORDER

$3ADC

REF+

IN+

1REF+

IN–

REF–(1-256)

GAIN

I2C

SERIAL

INTERFACE

TEMP

SENSOR

MUX

SCL

VCC

REF–

GND

CA0/f0

2481 FD

SDA

CA1

AUTOCALIBRATION

AND CONTROL

INTERNAL

OSCILLATOR

LTC2481

2481fc

CONVERTER OPERATION

Converter Operation Cycle

The LTC2481 is a low power, ΔΣ analog-to-digital converter

with an I2C interface. After power on reset, its operation

is made up of three states. The converter operating cycle

begins with the conversion, followed by the low power sleep

state and ends with the data output/input (see Figure 1).

The device will not acknowledge an external request during

the conversion state. After a conversion is ﬁ nished, the

device is ready to accept a read/write request. Once the

LTC2481 is addressed for a read operation, the device begins

outputting the conversion result under control of the serial

clock (SCL). There is no latency in the conversion result.

The data output is 24 bits long and contains a 16-bit plus

sign conversion result plus a readback of the conﬁ guration

bits corresponds to the conversion just performed. This

result is shifted out on the SDA pin under the control of the

SCL. Data is updated on the falling edges of SCL allowing

the user to reliably latch data on the rising edge of SCL.

In write operation, the device accepts one conﬁ guration

byte and the data is shifted in on the rising edges of the

SCL. A new conversion is initiated by a STOP condition

following a valid write operation or at the conclusion of a

data read operation (read out all 24 bits).

I2C INTERFACE

The LTC2481 communicates through an I2C interface. The

I2C interface is a 2-wire open-drain interface supporting

multiple devices and masters on a single bus. The

connected devices can only pull the bus wires LOW and

can never drive the bus HIGH. The bus wires are externally

connected to a positive supply voltage via a current-

source or pull-up resistor. When the bus is free, both

lines are HIGH. Data on the I2C-bus can be transferred

at rates of up to 100kbit/s in the Standard-mode and up

to 400kbit/s in the Fast-mode. The VCC power should not

be removed from the device when the I2C bus is active to

avoid loading the I2C bus lines through the internal ESD

protection diodes.

Each device on the I2C bus is recognized by a unique

address stored in that device and can operate as either

a transmitter or receiver, depending on the function of

the device. In addition to transmitters and receivers,

devices can also be considered as masters or slaves when

performing data transfers. A master is the device which

initiates a data transfer on the bus and generates the clock

signals to permit that transfer. At the same time any device

addressed is considered a slave.

APPLICATIONS INFORMATION

Initially, the LTC2481 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

While in this sleep state, power consumption is reduced

by two orders of magnitude. The part remains in the sleep

state as long as it is not addressed for a read/write opera-

tion. The conversion result is held indeﬁ nitely in a static

shift register while the converter is in the sleep state.

Figure 1. LTC2481 State Transition Diagram

CONVERSION

POWER ON RESET

DEFAULT CONFIGURATION:

EXTERNAL INPUT GAIN = 1

50/60Hz REJECTION

1X SPEED, AUTOCAL

SLEEP

2481 F01

YES

NO ACKNOWLEDGE

YES

NO STOP

OR READ

24-BITS

DATA OUTPUT/INPUT

LTC2481

2481fc

APPLICATIONS INFORMATION

The LTC2481 can only be addressed as a slave. Once

addressed, it can receive conﬁ guration bits or transmit the

last conversion result. Therefore the serial clock line SCL

is an input only and the data line SDA is bidirectional. The

device supports the Standard-mode and the Fast-mode

for data transfer speeds up to 400kbit/s. Figure 2 shows

the deﬁ nition of timing for Fast/Standard-mode devices

on the I2C-bus.

The START and STOP Conditions

A START condition is generated by transitioning SDA from

HIGH to LOW while SCL is HIGH. The bus is considered to

be busy after the START condition. When the data transfer

is ﬁ nished, a STOP condition is generated by transitioning

SDA from LOW to HIGH while SCL is HIGH. The bus is free

again a certain time after the STOP condition. START and

STOP conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The repeated

START (Sr) conditions are functionally identical to the

START (S).

Data Transferring

After the START condition, the I2C bus is busy and data

transfer is set between a master and a slave. Data is

transferred over I2C in groups of nine bits (one byte) followed

by an acknowledge bit, therefore each group takes nine

SCL cycles. The transmitter releases the SDA line during

the acknowledge clock pulse and the receiver issues an

Acknowledge (ACK) by pulling SDA LOW or leaves SDA

HIGH to indicate a Not Acknowledge (NACK) condition.

Change of data state can only happen while SCL is LOW.

Accessing the Special Features of the LTC2481

The LTC2481 combines a high resolution, low noise ΔΣ

analog-to-digital converter with an on-chip selectable

temperature sensor, programmable gain, programmable

digital ﬁ lter and output rate control. These special features

are selected through a single 8-bit serial input word during

the data input/output cycle (see Figure 3).

The LTC2481 powers up in a default mode commonly

used for most measurements. The device will remain in

this mode until a valid write cycle is performed. In this

default mode, the measured input is external, the GAIN is 1,

the digital ﬁ lter simultaneously rejects 50Hz and 60Hz

line frequency noise, and the speed mode is 1x (offset

automatically, continuously calibrated).

The I2C serial interface grants access to any or all special

functions contained within the LTC2481. In order to change

the mode of operation, a valid write address followed by 8

bits of data are shifted into the device (see Table 1). The ﬁ rst

3 bits (GS2, GS1, GS0) control the GAIN of the converter

from 1 to 256. The 4th bit is reserved and should be low.

The 5th bit (IM) is used to select the internal temperature

sensor as the conversion input, while the 6th and 7th bits

(FA, FB) combine to determine the line frequency rejection

mode. The 8th bit (SPD) is used to double the output rate

by disabling the offset auto calibration.

Figure 2. Deﬁ nition of Timing for F/S-Mode Devices on the I2C-Bus

SDA

SCL

SSrPS

tftLOW

tHD;STA

tHD;STA tBUF

tSP

tSU;STA tSU;STO

tHD;DAT tHIGH

tSU;DAT

trtrtr

2481 F02

LTC2481

2481fc

APPLICATIONS INFORMATION

Figure 3. Timing Diagram for Writing to the LTC2481

SDA

SCL

GS2 GS1 GS0 IM FA FB SPD

SLEEP DATA INPUT

7 8 9 1 2 3 4 5 6 7 8 9

1 2 …

START BY

MASTER

7-BIT ADDRESS

ACK BY

LTC2481

ACK BY

LTC2481

2481 F03

GS2 GS1

Gain

Any Gain

2481 TBL1

Any

Speed

Any

Rejection

Mode

GS0

IM FA FB SPD

External Input, Gain = 1, Autocalibration

External Input, Gain = 4, Autocalibration

External Input, Gain = 8, Autocalibration

External Input, Gain = 16, Autocalibration

External Input, Gain = 32, Autocalibration

External Input, Gain = 64, Autocalibration

External Input, Gain = 128, Autocalibration

External Input, Gain = 256, Autocalibration

External Input, Gain = 1, 2x Speed

External Input, Gain = 2, 2x Speed

External Input, Gain = 4, 2x Speed

External Input, Gain = 8, 2x Speed

External Input, Gain = 16, 2x Speed

External Input, Gain = 32, 2x Speed

External Input, Gain = 64, 2x Speed

External Input, Gain = 128, 2x Speed

External Input, Simultaneous 50Hz/60Hz Rejection

External Input, 50Hz Rejection

External Input, 60Hz Rejection

Reserved, Do Not Use

Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration

Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration

Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration

Reserved, Do Not Use

Rejection

Mode

Comments

Table 1. Selecting Special Modes

LTC2481

2481fc

APPLICATIONS INFORMATION

Table 2a. The LTC2481 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V)

GAIN 1 4 8 16 32 64 128 256 UNIT

Input Span ±2.5 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m ±9.76m V

LSB 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 µV

Noise Free Resolution* 65536 65536 65536 65536 65536 65536 32768 16384 Counts

Gain Error 5 5 5 5 5 5 5 8 ppm of FS

Offset Error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 µV

Table 2b. The LTC2481 Performance vs GAIN in 2x Speed Mode (VCC = 5V, VREF = 5V)

GAIN 1 2 4 8 16 32 64 128 UNIT

Input Span ±2.5 ±1.25 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m V

LSB 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 µV

Noise Free Resolution* 65536 65536 65536 65536 65536 65536 45875 22937 Counts

Gain Error 5 5 5 5 5 5 5 5 ppm of FS

Offset Error 200 200 200 200 200 200 200 200 µV

*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.

GAIN (GS2, GS1, GS0)

The input referred gain of the LTC2481 is adjustable from

1 to 256. With a gain of 1, the differential input range is

±VREF/2 and the common mode input range is rail-to-rail.

As the GAIN is increased, the differential input range is re-

duced to ±VREF/2 • GAIN but the common mode input range

remains rail-to-rail. As the differential gain is increased,

low level voltages are digitized with greater resolution. At

a gain of 256, the LTC2481 digitizes an input signal range

of ±9.76mV with over 16,000 counts.

Temperature Sensor (IM)

The LTC2481 includes an on-chip temperature sensor.

The temperature sensor is selected by setting IM = 1 in

the serial input data stream. Conversions are performed

directly on the temperature sensor by the converter. While

operating in this mode, the device behaves as a temperature

to bits converter. The digital reading is proportional to

the absolute temperature of the device. This feature

allows the converter to linearize temperature sensors or

continuously remove temperature effects from external

sensors. Several applications leveraging this feature are

presented in more detail in the applications section. While

operating in this mode, the gain is set to 1 and the speed

is set to normal independent of the control bits (GS2,

GS1, GS0 and SPD).

Rejection Mode (FA, FB)

The LTC2481 includes a high accuracy on-chip oscilla-

tor with no required external components. Coupled with

a 4th order digital lowpass ﬁ lter, the LTC2481 rejects

line frequency noise. In the default mode, the LTC2481

simultaneously rejects 50Hz and 60Hz by at least 87dB.

The LTC2481 can also be conﬁ gured to selectively reject

50Hz or 60Hz to better than 110dB.

Speed Mode (SPD)

The LTC2481 continuously performs offset calibrations.

Every conversion cycle, two conversions are automatically

performed (default) and the results combined. This result

is free from offset and drift. In applications where the offset

is not critical, the autocalibration feature can be disabled

with the beneﬁ t of twice the output rate.

Linearity, full-scale accuracy and full-scale drift are identi-

cal for both 2x and 1x speed modes. In both the 1x and

2x speed there is no latency. This enables input steps or

multiplexer channel changes to settle in a single conver-

sion cycle easing system overhead and increasing the

effective conversion rate.

LTC2481

2481fc

APPLICATIONS INFORMATION

LTC2481 Data Format

After a START condition, the master sends a 7-bit address

followed by a R/W bit. The bit R/W is 1 for a Read request

and 0 for a Write request. If the 7-bit address agrees with

an LTC2481’s address, that device is selected. When the

device is in the conversion state, it does not accept the

request and issues a Not-Acknowledge (NACK) by leaving

SDA HIGH. If the conversion is complete, it issues an

acknowledge (ACK) by pulling SDA LOW.

The LTC2481 has two registers. The output register contains

the result of the last conversion and a user programmable

conﬁ guration register that sets the converter operation

mode.

The output register contains the last conversion result. After

each conversion is completed, the device automatically

enters the sleep state where the supply current is reduced

to 1µA. When the LTC2481 is addressed for a Read

operation, it acknowledges (by pulling SDA LOW) and

acts as a transmitter. The master and receiver can read up

to three bytes from the LTC2481. After a complete Read

operation (3 bytes), the output register is emptied, a new

conversion is initiated, and a following Read request in the

same input/output phase will be NACKed. The LTC2481

output data stream is 24 bits long, shifted out on the falling

edges of SCL. The ﬁ rst bit is the conversion result sign bit

(SIG), see Tables 3 and 4. This bit is HIGH if VIN ≥ 0. It is

LOW if VIN <0. The second bit is the most signiﬁ cant bit

(MSB) of the result. The ﬁ rst two bits (SIG and MSB) can

be used to indicate over range conditions. If both bits are

HIGH, the differential input voltage is above +FS and the

following 16 bits are set to LOW to indicate an overrange

condition. If both bits are LOW, the input voltage is below

–FS and the following 16 bits are set to HIGH to indicate

an underrange condition. The function of these two bits

is summarized in Table 3. The next 16 bits contain the

conversion results in binary two’s complement format.

The remaining six bits are a readback of the conﬁ guration

Table 3. LTC2481 Status Bits

INPUT RANGE BIT 23 SIG BIT 22 MSB

VIN ≥ 0.5 • VREF 11

0V ≤ VIN < 0.5 • VREF 1/0 0

–0.5 • VREF ≤ VIN < 0V 0 1

VIN < –0.5 • VREF 00

As long as the voltage on the IN+ and IN– pins is main-

tained within the – 0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF/GAIN

to +FS = 0.5 • VREF/GAIN. For differential input voltages

greater than +FS, the conversion result is clamped to the

value corresponding to the +FS + 1LSB. For differential

input voltages below –FS, the conversion result is clamped

to the value corresponding to –FS – 1LSB.

Table 4. LTC2481 Output Data Format

DIFFERENTIAL INPUT VOLTAGE VIN* BIT 23 SIG BIT 22 MSB BIT 21 BIT 20 BIT 19 … BIT 6

VIN* ≥ FS** 1 1 0 0 0 … 0

FS** – 1LSB 1 0 1 1 1 … 1

0.5 • FS** 1 0 1 0 0 … 0

0.5 • FS** – 1LSB 1 0 0 1 1 … 1

0 1/0*** 0 0 0 0 … 0

–1LSB 0 1 1 1 1 … 1

–0.5 • FS** 0 1 1 0 0 … 0

–0.5 • FS** – 1LSB 0 1 0 1 1 … 1

–FS** 0 1 0 0 0 … 0

VIN* < –FS** 0 0 1 1 1 … 1

* The differential input voltage VIN = IN+ – IN–.

** The full-scale voltage FS = 0.5 • VREF/GAIN.

*** The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.

LTC2481

2481fc

APPLICATIONS INFORMATION

Initiating a New Conversion

When the LTC2481 ﬁ nishes a conversion, it automatically

enters the sleep state. Once in the sleep state, the device

is ready for Read/Write operations. After the device ac-

knowledges a Read or Write request, the device exits the

sleep state and enters the data input/output state. The data

input/output state concludes and the LTC2481 starts a new

conversion once a STOP condition is issued by the master

or all 24 bits of data are read out of the device.

During the data read cycle, a stop command may be issued

by the master controller in order to start a new conversion

and abort the data transfer. This stop command must be

issued during the 9th clock cycle of a byte read when the

bus is free (the ACK/NACK cycle).

LTC2481 Address

The LTC2481 has two address pins, enabling one in 6

possible addresses, as shown in Table 5.

Table 5. LTC2481 Address Assignment

CA1 CA0/f0 * Address

LOW HIGH 001 01 00

LOW Floating 001 01 01

Floating HIGH 001 01 11

Floating Floating 010 01 00

HIGH HIGH 010 01 10

HIGH Floating 010 01 11

* CA0/f0 is treated as HIGH when driven by a valid external clock.

In addition to the conﬁ gurable addresses listed in Table 5, the

LTC2481 also contains a global address (1110111) which

may be used for synchronizing multiple LTC2481s.

OPERATION SEQUENCE

The LTC2481 acts as a transmitter or receiver. The device

may be programmed to perform several functions. These

include measuring an external differential input signal or

an integrated temperature sensor, setting a programmable

gain (from 1 to 256), selecting line frequency rejection

(50Hz, 60Hz, or simultaneous 50Hz and 60Hz), and a 2x

speed up mode.

Continuous Read

In applications where the conﬁ guration does not need to

change for each conversion cycle, the conversion result

can be continuously read. The conﬁ guration remains

unchanged from the last value written into the device.

If the device has not been written to since power up, the

conﬁ guration is set to the default value (Input External,

GAIN=1, simultaneous 50Hz/60Hz rejection, and 1x

speed mode). The operation sequence is shown in Figure

6. When the conversion is ﬁ nished, the device may be

addressed for a read operation. At the end of a read

operation, a new conversion begins. At the conclusion

of the conversion cycle, the next result may be read

using the method described above. If the conversion

cycle is not concluded and a valid address selects the

device, the LTC2481 generates a NACK signal indicating

the conversion cycle is in progress.

Figure 4. Timing Diagram for Reading from the LTC2481

SLEEP DATA OUTPUT

START BY

MASTER

ACK BY

LTC2481

ACK BY

MASTER

NAK BY

MASTER

PG2 PG1 PG0 X IM SPDLSBR MSBSGN D15

7 … …89 1 2 9 1 2 3 4 5 6 7 8 9

7-BIT

ADDRESS

2481 F04

LTC2481

2481fc

APPLICATIONS INFORMATION

Continuous Read/Write

Once the conversion cycle is concluded, the LTC2481 can

be written to then read from, using the repeated Start (Sr)

command.

Figure 7 shows a cycle which begins with a data Write, a

repeated start, followed by a read, and concluded with a

stop command. The following conversion begins after all 24

bits are read out of the device or after the STOP command

and uses the newly programmed conﬁ guration data.

Discarding a Conversion Result and Initiating a New

Conversion with Optional Conﬁ guration Updating

At the conclusion of a conversion cycle, a Write cycle

can be initiated. Once the Write cycle is acknowledged,

a stop (P) command initiates a new conversion. If a new

conﬁ guration is required, this data can be written into the

device and a stop command initiates a new conversion,

see Figure 8.

Synchronizing Multiple LTC2481s with the Global

Address Call

In applications where several LTC2481s are used on the

same I2C bus, all LTC2481s can be synchronized with the

global address call. To achieve this, ﬁ rst all the LTC2481s

must have completed the conversion cycle. The master

issues a Start, followed by the LTC2481 global address

1110111 and a Write request. All LTC2481s will be selected

and acknowledge the request. The master then sends

the write byte (Optional) and ends the Write operation

with a STOP. This will update the conﬁ guration registers

(if a write byte was sent) and initiate a new conversion

simultaneously on all the LTC2481s, as shown in Figure 9.

In order to synchronize the start of conversion without

affecting the conﬁ guration registers, the Write operation

can be aborted with a STOP. This initiates a new conversion

on all the LTC2481s without changing the conﬁ guration

registers.

Figure 5. The LTC2481 Conversion Sequence

Figure 6. Consecutive Reading at the Same Conﬁ guration

Figure 7. Write, Read, Start Conversion

S ACK DATA Sr DATA TRANSFERRING P

SLEEP DATA INPUT/OUTPUT CONVERSIONCONVERSION

7-BIT ADDRESS R/W

2481 F05

7-BIT ADDRESS

CONVERSION CONVERSION

CONVERSION

SLEEP SLEEPDATA OUTPUT DATA OUTPUT

7-BIT ADDRESSSSRRACK ACKREAD READPP

2481 F06

7-BIT ADDRESS

CONVERSION CONVERSIONADDRESSSLEEP DATA OUTPUTDATA INPUT

7-BIT ADDRESSS RW ACK ACKWRITE Sr PREAD

2481 F08

LTC2481

2481fc

APPLICATIONS INFORMATION

Easy Drive Input Current Cancellation

The LTC2481 combines a high precision delta-sigma ADC

with an automatic differential input current cancellation

front end. A proprietary front-end passive sampling

network transparently removes the differential input

current. This enables external RC networks and high

impedance sensors to directly interface to the LTC2481

without external ampliﬁ ers. The remaining common

mode input current is eliminated by either balancing the

differential input impedances or setting the common

mode input equal to the common mode reference (see

Automatic Input Current Cancellation section). This unique

architecture does not require on-chip buffers enabling

input signals to swing all the way to ground and up to

VCC. Furthermore, the cancellation does not interfere with

the transparent offset and full-scale auto-calibration and

the absolute accuracy (full-scale + offset + linearity) is

maintained even with external RC networks.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital ﬁ lter

(commonly implemented as a SINC or Comb ﬁ lter). For

high resolution, low frequency applications, this ﬁ lter is

typically designed to reject line frequencies of 50Hz or 60Hz

plus their harmonics. The ﬁ lter rejection performance is

directly related to the accuracy of the converter system

clock. The LTC2481 incorporates a highly accurate on-chip

oscillator. This eliminates the need for external frequency

setting components such as crystals or oscillators.

Frequency Rejection Selection (CA0/f0)

The LTC2481 internal oscillator provides better than 110dB

normal mode rejection at the line frequency and all its

harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,

or better than 87dB normal mode rejection from 48Hz to

62.4Hz. The rejection mode is selected by writing to the

on-chip conﬁ guration register (the default mode at power-

up is simultaneous 50Hz/60Hz rejection).

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2481 can

operate with an external conversion clock. The converter

automatically detects the presence of an external clock

signal at the CA0/f0 pin and turns off the internal oscilla-

tor. The chip address for CA0 is internally set HIGH. The

frequency fEOSC of the external signal must be at least

10kHz to be detected. The external clock signal duty cycle

is not signiﬁ cant as long as the minimum and maximum

speciﬁ cations for the high and low periods tHEO and tLEO

are observed.

Figure 8. Start a New Conversion without Reading Old Conversion Result

Figure 9. Synchronize the LTC2481s with the Global Address Call

7-BIT ADDRESS

CONVERSION CONVERSIONSLEEP DATA INPUT

S W ACK WRITE (OPTIONAL) P

2481 F08

GLOBAL ADDRESS

SCL

SDA

LTC2481 LTC2481 … LTC2481

ALL LTC2481s IN SLEEP CONVERSION OF ALL LTC2481s

DATA INPUT

S W ACK WRITE (OPTIONAL) P

2481 F09

LTC2481

2481fc

APPLICATIONS INFORMATION

While operating with an external conversion clock of a

frequency fEOSC, the LTC2481 provides better than 110dB

normal mode rejection in a frequency range of fEOSC/5120

±4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from fEOSC/5120

is shown in Figure 10.

Whenever an external clock is not present at the CA0/f0 pin,

the converter automatically activates its internal oscillator

and enters the Internal Conversion Clock mode. CA0/f0

may be tied HIGH or left ﬂ oating in order to set the chip

address. The LTC2481 operation will not be disturbed if

the change of conversion clock source occurs during the

sleep state or during the data output state while the con-

verter uses an external serial clock. If the change occurs

during the conversion state, the result of the conversion in

progress may be outside speciﬁ cations but the following

conversions will not be affected.

Table 6 summarizes the duration of the conversion state

of each state and the achievable output data rate as a

function of fEOSC.

Ease of Use

The

LTC2481

data output has no latency, ﬁ lter settling

delay or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy.

The LTC2481 performs offset and full-scale calibrations

every conversion cycle. This calibration is transparent to

the user and has no effect on the cyclic operation described

above. The advantage of continuous calibration is extreme

stability of offset and full-scale readings with respect to

time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2481 automatically enters an internal reset

state when the power supply voltage VCC drops below

approximately 2V. This feature guarantees the integrity of

the conversion result.

When the VCC voltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with a duration of approximately 4ms. The POR

signal clears all internal registers. Following the POR signal,

the LTC2481 starts a normal conversion cycle and follows

the succession of states described in Figure 1. The ﬁ rst

Figure 10. LTC2481 Normal Mode Rejection When

Using an External Oscillator

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)

–12 –8 –4 0 4 8 12

NORMAL MODE REJECTION (dB)

2481 F10

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

Table 6. LTC2481 State Duration

STATE OPERATING MODE DURATION

CONVERSION Internal Oscillator 60Hz Rejection 133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode 67ms,

Output Data Rate ≤ 15 Readings/s for 2x Speed Mode

50Hz Rejection 160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode 80ms,

Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode

50Hz/60Hz Rejection 147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode 73.6ms,

Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode

External Oscillator CA0/f0 = External Oscillator

with Frequency fEOSC Hz

(fEOSC/5120 Rejection)

41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for 1x Speed Mode

20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for 2x Speed Mode

LTC2481

2481fc

APPLICATIONS INFORMATION

conversion result following POR is accurate within the

speciﬁ cations of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

On-Chip Temperature Sensor

The LTC2481 contains an on-chip PTAT (proportional to

absolute temperature) signal that can be used as a tempera-

ture sensor. The internal PTAT has a typical value of 420mV

at 27°C and is proportional to the absolute temperature

value with a temperature coefﬁ cient of 420/(27 + 273) =

1.40mV/°C (SLOPE), as shown in Figure 11. The internal

PTAT signal is used in a single-ended mode referenced to

device ground internally. The GAIN is automatically set to

one (independent of the values of GS0, GS1, GS2) in order

to preserve the PTAT property at the ADC output code

and avoid an out of range error. The 1x speed mode with

automatic offset calibration is automatically selected for

the internal PTAT signal measurement as well.

When using the internal temperature sensor, if the output

code is normalized to RSDA = VPTAT/VREF, the temperature

is calculated using the following formula:

K=RSDA •V

REF

SLOPE in Kelvin

and

TC=RSDA •V

REF

SLOPE – 273 in °C

where SLOPE is nominally 1.4mV/°C.

Since the PTAT signal can have an initial value variation

which results in errors in SLOPE, to achieve absolute

temperature measurements, a one-time calibration is

needed to adjust the SLOPE value. The converter output of

the PTAT signal, R0SDA, is measured at a known temperature

T0 (in °C) and the SLOPE is calculated as:

SLOPE =R0SDA •V

REF

T0 +273

This calibrated SLOPE can be used to calculate the tem-

perature.

If the same VREF source is used during calibration and

temperature measurement, the actual value of the VREF

is not needed to measure the temperature as shown in

the calculation below:

TC=RSDA •V

REF

SLOPE – 273

=RSDA

R0SDA

•T0+273

(

)

– 273

Reference Voltage Range

The LTC2481 external reference voltage range is 0.1V

to VCC. The converter output noise is determined by

the thermal noise of the front-end circuits, and as such,

its value in nanovolts is nearly constant with reference

voltage. Since the transition noise (600nV) is much less

than the quantization noise (VREF/217), a decrease in the

reference voltage will increase the converter resolution. A

reduced reference voltage will also improve the converter

performance when operated with an external conversion

clock (external fO signal) at substantially higher output

data rates (see the Output Data Rate section). VREF must

be ≥1.1V to use the internal temperature sensor.

The reference input is differential. The differential reference

input range (VREF = REF+ – REF–) is 100mV to VCC and the

common mode reference input range is 0V to VCC.

Figure 11. Internal PTAT Signal vs Temperature

TEMPERATURE (°C)

–60

VPTAT (mV)

500

600

120

2481 F11

400

200 30090–30 60

300

VCC = 5V

IM = 1

SLOPE = 1.40mV/°C

LTC2481

2481fc

APPLICATIONS INFORMATION

Input Voltage Range

The analog input is truly differential with an absolute/

common mode range for the IN+ and IN– input pins

extending from GND – 0.3V to VCC + 0.3V. Outside these

limits, the ESD protection devices begin to turn on and the

errors due to input leakage current increase rapidly. Within

these limits, the LTC2481 converts the bipolar differential

input signal, VIN = IN+ – IN–, from – FS to +FS where FS = 0.5

• VREF/GAIN. Beyond this range, the converter indicates the

overrange or the underrange condition using distinct output

codes. Since the differential input current cancellation does

not rely on an on-chip buffer, current cancellation as well

as DC performance is maintained rail-to-rail.

nput signals applied to IN+ and IN– pins may extend by

300mV below ground and above VCC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN+ and IN– pins without affecting the performance

of the devices. The effect of the series resistance on the

converter accuracy can be evaluated from the curves

presented in the Input Current/Reference Current sections.

In addition, series resistors will introduce a temperature

dependent offset error due to the input leakage current.

A 1nA input leakage current will develop a 1ppm offset

error on a 5k resistor if VREF = 5V. This error has a very

strong temperature dependency.

Driving the Input and Reference

The input and reference pins of the LTC2481 converter

are directly connected to a network of sampling capaci-

tors. Depending upon the relation between the differential

input voltage and the differential reference voltage, these

capacitors are switching between these four pins transfer-

ring small amounts of charge in the process. A simpliﬁ ed

equivalent circuit is shown in Figure 12.

For a simple approximation, the source impedance RS

driving an analog input pin (IN+, IN–, REF+ or REF–) can be

considered to form, together with R

SW and CEQ (see Fig-

ure 12), a ﬁ rst order passive network with a time constant

τ = (RS + RSW) • CEQ. The converter is able to sample the

input signal with better than 1ppm accuracy if the sampling

period is at least 14 times greater than the input circuit time

constant τ. The sampling process on the four input analog

pins is quasi-independent so each time constant should be

considered by itself and, under worst-case circumstances,

the errors may add.

When using the internal oscillator, the LTC2481’s front-end

switched-capacitor network is clocked at 123kHz corre-

sponding to an 8.1µs sampling period. Thus, for settling

errors of less than 1ppm, the driving source impedance

should be chosen such that τ ≤ 8.1µs/14 = 580ns. When an

external oscillator of frequency fEOSC is used, the sampling

period is 2.5/fEOSC and, for a settling error of less than

1ppm, τ ≤ 0.178/fEOSC.

VREF+

VIN+

VCC

RSW (TYP)

10k

ILEAK

VCC

ILEAK

VCC

RSW (TYP)

10k

CEQ

12pF

(TYP)

RSW (TYP)

10k

ILEAK

IIN+

VIN–

IIN–

IREF+

IREF–

2481 F12

ILEAK

VCC

ILEAK

SWITCHING FREQUENCY

fSW = 123kHz INTERNAL OSCILLATOR

fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR

VREF–

RSW (TYP)

10k

IIN IIN VV

I REF VV V

VV V

where

AVG AVG

IN CM REF CM

AVG

REF INCM REFCM

REF EQ

REF T

REF REF CM IN CM

REF EQ



REFREF–











v 

vv





–() ()

() ()

.• • .–

.• –•

05 15

VININ

VIN IN

R M INTERNAL OSCILLATOR Hz MODE

REFCM

INCM









¦´



v





V, REF 

REFREF–



¦´

271 60

R 2.98M INTERNAL OSCILLATOR 50Hz AND 60Hz MODE

R 0.833 10 / f EXTERNAL OSCILLATOR

D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT

EQ 12 EOSC

WHERE REF– IS INTERNALLY TIED TO GND

Figure 12. LTC2481 Equivalent Analog Input Circuit

LTC2481

2481fc

APPLICATIONS INFORMATION

Automatic Differential Input Current Cancellation

In applications where the sensor output impedance is

low (up to 10k with no external bypass capacitor or up

to 500 with 0.001µF bypass), complete settling of the

input occurs. In this case, no errors are introduced and

direct digitization of the sensor is possible.

For many applications, the sensor output impedance

combined with external bypass capacitors produces RC

time constants much greater than the 580ns required for

1ppm accuracy. For example, a 10k bridge driving a 0.1µF

bypass capacitor has a time constant several orders of

magnitude greater than the required maximum. Historically,

settling issues were solved using buffers. These buffers led

to increased noise, reduced DC performance (Offset/Drift),

limited input/output swing (cannot digitize signals near

ground or VCC), added system cost and increased power.

The LTC2481 uses a proprietary switching algorithm that

forces the average differential input current to zero inde-

pendent of external settling errors. This allows accurate

direct digitization of high impedance sensors without the

need of buffers (see Figures 13 to 15). Additional errors

resulting from mismatched leakage currents must also

be taken into account.

The switching algorithm forces the average input current

on the positive input (IIN+) to be equal to the average input

current on the negative input (IIN–). Over the complete

conversion cycle, the average differential input current

(IIN+ – IIN–) is zero. While the differential input current

is zero, the common mode input current (IIN++ IIN–)/2 is

proportional to the difference between the common mode

input voltage (VINCM) and the common mode reference

voltage (VREFCM).

In applications where the input common mode voltage

is equal to the reference common mode voltage, as in

the case of a balance bridge type application, both the

differential and common mode input current are zero.

The accuracy of the converter is unaffected by settling

errors. Mismatches in source impedances between IN+

and IN– also do not affect the accuracy.

In applications where the input common mode voltage is

constant but different from the reference common mode

voltage, the differential input current remains zero while

Figure 13. An RC Network at IN+ and IN–

Figure 14. +FS Error vs RSOURCE at IN+ and IN–

Figure 15. –FS Error vs RSOURCE at IN+ and IN–

CEXT

2481 F13

VINCM + 0.5VIN

RSOURCE

IN+

LTC2481

CPAR

20pF

CEXT

VINCM – 0.5VIN

RSOURCE

IN–

CPAR

20pF

RSOURCE (Ω)

+FS ERROR (ppm)

–20

1k 100k

2481 F14

–40

–60

–80 10 100 10k

80 VCC = 5V

VREF = 5V

VIN+ = 3.75V

VIN– = 1.25V

TA = 25°C CEXT = 0pF

CEXT = 100pF

CEXT = 1nF, 0.1µF, 1µF

RSOURCE ()

–FS ERROR (ppm)

–20

1k 100k

2481 F15

–40

–60

–80 10 100 10k

80 VCC = 5V

VREF = 5V

VIN+ = 1.25V

VIN– = 3.75V

TA = 25°C

CEXT = 0pF

CEXT = 100pF

CEXT = 1nF, 0.1µF, 1µF

LTC2481

2481fc

APPLICATIONS INFORMATION

the common mode input current is proportional to the

difference between VINCM and VREFCM. For a reference

common mode of 2.5V and an input common mode of

1.5V, the common mode input current is approximately

0.74µA (in simultaneous 50Hz/60Hz rejection mode). This

common mode input current has no effect on the accuracy

if the external source impedances tied to IN+ and IN– are

matched. Mismatches in these source impedances lead

to a ﬁ xed offset error but do not affect the linearity or full-

scale reading. A 1% mismatch in 1k source resistances

leads to a 15ppm shift (74µV) in offset voltage.

In applications where the common mode input voltage

varies as a function of input signal level (single-ended

input, RTDs, half bridges, current sensors, etc.), the com-

mon mode input current varies proportionally with input

voltage. For the case of balanced input impedances, the

common mode input current effects are rejected by the

large CMRR of the LTC2481 leading to little degradation in

accuracy. Mismatches in source impedances lead to gain

errors proportional to the difference between the common

mode input voltage and the common mode reference

voltage. 1% mismatches in 1k source resistances lead

to worst-case gain errors on the order of 15ppm or 1LSB

(for 1V differences in reference and input common mode

voltage). Table 7 summarizes the effects of mismatched

source impedance and differences in reference/input

common mode voltages.

Table 7. Suggested Input Conﬁ guration for LTC2481

BALANCED INPUT

RESISTANCES

UNBALANCED INPUT

RESISTANCES

Constant

VIN(CM) – VREF(CM)

CEXT > 1nF at Both IN+

and IN–. Can Take Large

Source Resistance with

Negligible Error

CEXT > 1nF at Both IN+

and IN–. Can Take Large

Source Resistance.

Unbalanced Resistance

Results in an Offset Which

Can be Calibrated

Varying

VIN(CM) – VREF(CM)

CEXT > 1nF at Both IN+

and IN–. Can Take Large

Source Resistance with

Negligible Error

Minimize IN+ and

IN– Capacitors and Avoid

Large Source Impedance

(<5k Recommended)

The magnitude of the dynamic input current depends upon

the size of the very stable internal sampling capacitors and

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typically better than 0.5%. Such

a speciﬁ cation can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by IN+ and

IN–, the expected drift of the dynamic current and offset

will be insigniﬁ cant (about 1% of their respective values

over the entire temperature and voltage range). Even for

the most stringent applications, a one-time calibration

operation may be sufﬁ cient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

in a small offset shift. A 1k source resistance will create a

1µV typical and 10µV maximum offset voltage.

Reference Current

In a similar fashion, the LTC2481 samples the differential

reference pins REF+ and REF– transferring small amount

of charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gain and INL performance. The effect of this current can

be analyzed in two distinct situations.

For relatively small values of the external reference capaci-

tors (CREF < 1nF), the voltage on the sampling capacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for CREF will deteriorate the converter offset and

gain performance without signiﬁ cant beneﬁ ts of reference

ﬁ ltering and the user is advised to avoid them.

Larger values of reference capacitors (CREF > 1nF) may be

required as reference ﬁ lters in certain conﬁ gurations. Such

capacitors will average the reference sampling charge and

the external source resistance will see a quasi constant

reference differential impedance.

In the following discussion, it is assumed the input and

reference common mode are the same. Using internal

oscillator for 60Hz mode, the typical differential reference

resistance is 1M which generates a full-scale (VREF/2) gain

error of 0.51ppm for each ohm of source resistance driving

the REF+ and REF– pins. For 50Hz/60Hz mode, the related

difference resistance is 1.1M and the resulting full-scale

error is 0.46ppm for each ohm of source resistance driving

LTC2481

2481fc

APPLICATIONS INFORMATION

the REF+ and REF– pins. For 50Hz mode, the related differ-

ence resistance is 1.2M and the resulting full-scale error

is 0.42ppm for each ohm of source resistance driving the

REF+ and REF– pins. When CA0/f0 is driven by an external

oscillator with a frequency fEOSC (external conversion clock

operation), the typical differential reference resistance is

0.30 • 1012/fEOSC  and each ohm of source resistance

driving the REF+ or REF– pins will result in 1.67 • 10–6 •

fEOSCppm gain error. The typical +FS and –FS errors for

various combinations of source resistance seen by the

REF+ or REF– pins and external capacitance connected to

that pin are shown in Figures 16-19.

In addition to this gain error, the converter INL per-

formance is degraded by the reference source imped-

ance. The INL is caused by the input dependent terms

–VIN2/(VREF • REQ) – (0.5 • VREF • DT

)/REQ in the reference

Figure 16. +FS Error vs RSOURCE at REF+ or REF– (Small CREF)

Figure 17. –FS Error vs RSOURCE at REF+ or REF– (Small CREF)

Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Large CREF)

Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Large CREF)

RSOURCE (Ω)

+FS ERROR (ppm)

300

400

500

800

2481 F18

200

100

0200 400 600 1000

VCC = 5V

VREF = 5V

VIN+ = 3.75V

VIN– = 1.25V

TA = 25°C

CREF = 1µF, 10µF

CREF = 0.1µF

CREF = 0.01µF

RSOURCE ()

+FS ERROR (ppm)

10k

2481 F16

–10 10 100 1k 100k

VCC = 5V

VREF = 5V

VIN+ = 3.75V

VIN– = 1.25V

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

RSOURCE ()

–FS ERROR (ppm)

–200

–100

800

2481 F19

–300

–400

–500 200 400 600 1000

VCC = 5V

VREF = 5V

VIN+ = 1.25V

VIN– = 3.75V

TA = 25°C

CREF = 1µF, 10µF

CREF = 0.1µF

CREF = 0.01µF

RSOURCE ()

–FS ERROR (ppm)

–30

–10

10k

2481 F17

–50

–70

–40

–20

–60

–80

–90 10 100 1k 100k

VCC = 5V

VREF = 5V

VIN+ = 1.25V

VIN– = 3.75V

TA = 25°C

CREF = 0.01µF

CREF = 0.001µF

CREF = 100pF

CREF = 0pF

pin current as expressed in Figure 12. When using internal

oscillator and 60Hz mode, every 100 of reference source

resistance translates into about 0.67ppm additional INL

error. When using internal oscillator and 50Hz/60Hz mode,

every 100 of reference source resistance translates into

about 0.61ppm additional INL error. When using internal

oscillator and 50Hz mode, every 100 of reference source

resistance translates into about 0.56ppm additional INL

error. When CA0/f0 is driven by an external oscillator

with a frequency fEOSC, every 100 of source resistance

driving REF+ or REF– translates into about 2.18 • 10–6 •

fEOSCppm additional INL error. Figure 20 shows the typical

INL error due to the source resistance driving the REF+

or REF– pins when large CREF values are used. The user

is advised to minimize the source impedance driving the

REF+ and REF– pins.

LTC2481

2481fc

APPLICATIONS INFORMATION

In applications where the reference and input common

mode voltages are different, extra errors are introduced.

For every 1V of the reference and input common mode

voltage difference (VREFCM – VINCM) and a 5V reference,

each Ohm of reference source resistance introduces an

extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,

which is 0.074ppm when using internal oscillator and 60Hz

mode. When using internal oscillator and 50Hz/60Hz mode,

the extra full-scale gain error is 0.067ppm. When using

internal oscillator and 50Hz mode, the extra gain error is

0.061ppm. If an external clock is used, the corresponding

extra gain error is 0.24 • 10–6 • fEOSCppm.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capacitors

and upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

Figure 21. Offset Error vs Output Data Rate and Temperature

Figure 22. +FS Error vs Output Data Rate and Temperature

OUTPUT DATA RATE (READINGS/SEC)

–10

OFFSET ERROR (ppm OF VREF)

20 40 60 80

2481 F21

10010030507090

VIN(CM) = VREF(CM)

VCC = VREF = 5V

VIN = 0V

CA0/f0 = EXT CLOCK

TA = 85°C

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

+FS ERROR (ppm OF VREF)

500

1500

2000

2500

3500

10 50 70

2481 F22

1000

3000

40 90 100

20 30 60 80

VIN(CM) = VREF(CM)

VCC = VREF = 5V

CA0/f0 = EXT CLOCK

TA = 85°C

TA = 25°C

Figure 23. –FS Error vs Output Data Rate and Temperature

OUTPUT DATA RATE (READINGS/SEC)

–3500

–FS ERROR (ppm OF VREF)

–3000

–2000

–1500

–1000

10 50 70

2481 F23

–2500

–500

40 90 100

20 30 60 80

VIN(CM) = VREF(CM)

VCC = VREF = 5V

CA0/f0 = EXT CLOCK

TA = 85°C

TA = 25°C

Figure 20. INL vs DIFFERENTIAL Input Voltage and

Reference Source Resistance for CREF > 1μF

VIN/VREF (V)

–0.5

INL (ppm OF VREF)

0.3

2481 F20

–2

–6

–4

–8

–10 –0.3 –0.1 0.1 0.5

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

CREF = 10µF

R = 1k

R = 100

R = 500

and power supply range is typically better than 0.5%. Such

a speciﬁ cation can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by VREF+

and VREF–, the expected drift of the dynamic current gain

error will be insigniﬁ cant (about 1% of its value over the

entire temperature and voltage range). Even for the most

stringent applications a one-time calibration operation

may be sufﬁ cient.

In addition to the reference sampling charge, the refer-

ence pins ESD protection diodes have a temperature de-

pendent leakage current. This leakage current, nominally

1nA (±100nA max), results in a small gain error. A 100

source resistance will create a 0.05µV typical and 5µV

maximum full-scale error.

LTC2481

2481fc

APPLICATIONS INFORMATION

Output Data Rate

When using its internal oscillator, the LTC2481 produces up

to 7.5 samples per second (sps) with a notch frequency of

60Hz, 6.25sps with a notch frequency of 50Hz and 6.82sps

with the 50Hz/60Hz rejection mode. The actual output

data rate will depend upon the length of the sleep and

data output phases which are controlled by the user and

which can be made insigniﬁ cantly short. When operated

with an external conversion clock (CA0/f0 connected to

an external oscillator), the LTC2481 output data rate can

be increased as desired. The duration of the conversion

phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter

behaves as if the internal oscillator is used and the notch

is set at 60Hz.

An increase in fEOSC over the nominal 307.2kHz will

translate into a proportional increase in the maximum

output data rate. The increase in output rate is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

First, a change in fEOSC will result in a proportional change

in the internal notch position and in a reduction of the

converter differential mode rejection at the power line fre-

quency. In many applications, the subsequent performance

degradation can be substantially reduced by relying upon

the LTC2481’s exceptional common mode rejection and by

carefully eliminating common mode to differential mode

conversion sources in the input circuit. The user should

avoid single-ended input ﬁ lters and should maintain a

very high degree of matching and symmetry in the circuits

driving the IN+ and IN– pins.

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

input and/or reference capacitors (CIN, CREF) are used, the

previous section provides formulae for evaluating the effect

of the source resistance upon the converter performance for

any value of fEOSC. If small external input and/or reference

capacitors (CIN, CREF) are used, the effect of the external

source resistance upon the LTC2481 typical performance

can be inferred from Figures 14, 15, 16 and 17 in which

the horizontal axis is scaled by 307200/fEOSC.

Third, an increase in the frequency of the external oscillator

above 1MHz (a more than 3x increase in the output data

rate) will start to decrease the effectiveness of the internal

autocalibration circuits. This will result in a progressive

degradation in the converter accuracy and linearity. Typical

measured performance curves for output data rates up to

100 readings per second are shown in Figures 21 to 28. In

order to obtain the highest possible level of accuracy from

this converter at output data rates above 20 readings per

second, the user is advised to maximize the power supply

voltage used and to limit the maximum ambient operating

temperature. In certain circumstances, a reduction of the

differential reference voltage may be beneﬁ cial.

Input Bandwidth

The combined effect of the internal SINC4 digital ﬁ lter and

of the analog and digital autocalibration circuits determines

the LTC2481 input bandwidth. When the internal oscillator

is used with the notch set at 60Hz, the 3dB input bandwidth

is 3.63Hz. When the internal oscillator is used with the

notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If

an external conversion clock generator of frequency fEOSC

is connected to the CA0/f0 pin, the 3dB input bandwidth

is 11.8 • 10–6 • fEOSC.

Due to the complex ﬁ ltering and calibration algorithms

utilized, the converter input bandwidth is not modeled

very accurately by a ﬁ rst order ﬁ lter with the pole located

at the 3dB frequency. When the internal oscillator is used,

the shape of the LTC2481 input bandwidth is shown in

Figure 29. When an external oscillator of frequency fEOSC

is used, the shape of the LTC2481 input bandwidth can

be derived from Figure 29, 60Hz mode curve in which

the horizontal axis is scaled by fEOSC/307200.

The conversion noise (600nVRMS typical for VREF = 5V)

can be modeled by a white noise source connected to a

noise free converter. The noise spectral density is 47nV√Hz

for an inﬁ nite bandwidth source and 64nV√Hz for a single

0.5MHz pole source. From these numbers, it is clear that

particular attention must be given to the design of external

ampliﬁ cation circuits. Such circuits face the simultaneous

requirements of very low bandwidth (just a few Hz) in

order to reduce the output referred noise and relatively

LTC2481

2481fc

APPLICATIONS INFORMATION

Figure 24. Resolution

(NoiseRMS ≤ 1LSB) vs Output

Data Rate and Temperature

Figure 25. Resolution

(INLMAX ≤ 1LSB) vs Output

Data Rate and Temperature

Figure 26. Offset Error vs Output

Data Rate and Reference Voltage

Figure 27. Resolution (NoiseRMS ≤ 1LSB)

vs Output Data Rate and Reference Voltage

Figure 28. Resolution (INLMAX ≤ 1LSB)

vs Output Data Rate and Reference Voltage

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

10 50 70

2481 F24

40 90 100

20 30 60 80

VIN(CM) = VREF(CM)

VCC = VREF = 5V

VIN = 0V

CA0/f0 = EXT CLOCK

RES = LOG 2 (VREF/NOISERMS)

TA = 85°C

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

10 50 70

2481 F25

40 90 100

20 30 60 80

TA = 85°C TA = 25°C

VIN(CM) = VREF(CM)

VCC = VREF = 5V

CA0/f0 = EXT CLOCK

RES = LOG 2 (VREF/INLMAX)

OUTPUT DATA RATE (READINGS/SEC)

–10

OFFSET ERROR (ppm OF VREF)

–5

10 50 70

2481 F26

40 90 100

20 30 60 80

VCC = 5V, VREF = 2.5V

VCC = VREF = 5V

VIN(CM) = VREF(CM)

VIN = 0V

CA0/f0 = EXT CLOCK

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

10 50 70

2481 F27

40 90 100

20 30 60 80

VIN(CM) = VREF(CM)

VIN = 0V

CA0/f0 = EXT CLOCK

TA = 25°C

RES = LOG 2 (VREF/NOISERMS)

VCC = 5V, VREF = 2.5V

VCC = VREF = 5V

OUTPUT DATA RATE (READINGS/SEC)

RESOLUTION (BITS)

10 50 70

2481 F28

40 90 100

20 30 60 80

VIN(CM) = VREF(CM)

VIN = 0V

CA0/f0 = EXT CLOCK

TA = 25°C

RES = LOG 2 (VREF/INLMAX)

VCC = 5V, VREF = 2.5V

VCC = VREF = 5V

Figure 29. Input Signal Using

the Internal Oscillator

Figure 30. Input Referred Noise Equivalent Bandwidth

of an Input Connected White Noise Source

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

INPUT SIGNAL ATTENUATION (dB)

–3

–2

–1

2481 F29

–4

–5

–6 1235

50Hz MODE 60Hz MODE

50Hz AND

60Hz MODE

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

INPUT REFERRED NOISE

EQUIVALENT BANDWIDTH (Hz)

0.1 1 10 100 1k 10k 100k 1M

2481 F30

0.1

100

50Hz MODE

60Hz MODE

LTC2481

2481fc

APPLICATIONS INFORMATION

high bandwidth (at least 500kHz) necessary to drive the

input switched-capacitor network. A possible solution is

a high gain, low bandwidth ampliﬁ er stage followed by a

high bandwidth unity-gain buffer.

When external ampliﬁ ers are driving the LTC2481, the

ADC input referred system noise calculation can be

simpliﬁ ed by Figure 30. The noise of an ampliﬁ er driving

the LTC2481 input pin can be modeled as a band limited

white noise source. Its bandwidth can be approximated

by the bandwidth of a single pole lowpass ﬁ lter with a

corner frequency fi. The ampliﬁ er noise spectral density

is ni. From Figure 30, using fi as the x-axis selector, we

can ﬁ nd on the y-axis the noise equivalent bandwidth freqi

of the input driving ampliﬁ er. This bandwidth includes

the band limiting effects of the ADC internal calibration

and ﬁ ltering. The noise of the driving ampliﬁ er referred

to the converter input and including all these effects can

be calculated as N = ni • √freqi. The total system noise

(referred to the LTC2481 input) can now be obtained by

summing as square root of sum of squares the three

ADC input referred noise sources: the LTC2481 internal

noise, the noise of the IN+ driving ampliﬁ er and the noise

of the IN– driving ampliﬁ er.

If the CA0/f0 pin is driven by an external oscillator of

frequency fEOSC, Figure 30 can still be used for noise

calculation if the x-axis is scaled by fEOSC/307200.

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

S2fS3fS4fS5fS6fS7fS8fS9fS10fS

11fS

12fS

INPUT NORMAL MODE REJECTION (dB)

2481 F31

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

For large values of the ratio fEOSC/307200, the Figure 30

plot accuracy begins to decrease, but at the same time

the LTC2481 noise ﬂ oor rises and the noise contribution

of the driving ampliﬁ ers lose signiﬁ cance.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over

conventional ADCs is on-chip digital ﬁ ltering. Combined

with a large oversampling ratio, the LTC2481 signiﬁ cantly

simpliﬁ es antialiasing ﬁ lter requirements. Additionally,

the input current cancellation feature of the LTC2481

allows external lowpass ﬁ ltering without degrading the

DC performance of the device.

The SINC4 digital ﬁ lter provides greater than 120dB normal

mode rejection at all frequencies except DC and integer

multiples of the modulator sampling frequency (fS). The

LTC2481’s autocalibration circuits further simplify the

antialiasing requirements by additional normal mode

signal ﬁ ltering both in the analog and digital domain.

Independent of the operating mode, fS = 256 • fN = 2048

• fOUTMAX where fN is the notch frequency and fOUTMAX

is the maximum output data rate. In the internal oscilla-

tor mode with a 50Hz notch setting, fS = 12800Hz, with

50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch

setting fS = 15360Hz. In the external oscillator mode, fS =

fEOSC/20. The performance of the normal mode rejection

is shown in Figures 31 and 32.

Figure 31. Input Normal Mode Rejection,

Internal Oscillator and 50Hz Notch Mode

Figure 32. Input Normal Mode Rejection at DC

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

INPUT NORMAL MODE REJECTION (dB)

2481 F32

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 2fS3fS4fS5fS6fS7fS8fS9fS10fS

LTC2481

2481fc

APPLICATIONS INFORMATION

In 1x speed mode, the regions of low rejection occurring

at integer multiples of fS have a very narrow bandwidth.

Magniﬁ ed details of the normal mode rejection curves

are shown in Figure 33 (rejection near DC) and Figure 34

(rejection at fS = 256fN) where fN represents the notch

frequency. These curves have been derived for the exter-

nal oscillator mode but they can be used in all operating

modes by appropriately selecting the fN value.

The user can expect to achieve this level of performance

using the internal oscillator as it is demonstrated by

Figures 35, 36 and 37. Typical measured values of the

normal mode rejection of the LTC2481 operating with an

internal oscillator and a 60Hz notch setting are shown in

Figure 35 superimposed over the theoretical calculated

curve. Similarly, the measured normal mode rejection of

the LTC2481 for the 50Hz rejection mode and 50Hz/60Hz

rejection mode are shown in Figures 36 and 37.

As a result of these remarkable normal mode speciﬁ ca-

tions, minimal (if any) antialias ﬁ ltering is required in front

of the LTC2481. If passive RC components are placed in

front of the LTC2481, the input dynamic current should

be considered (see Input Current section). In this case,

the differential input current cancellation feature of the

LTC2481 allows external RC networks without signiﬁ cant

degradation in DC performance.

Traditional high order delta-sigma modulators, while

providing very good linearity and resolution, suffer

from potential instabilities at large input signal levels.

The proprietary architecture used for the LTC2481 third

order modulator resolves this problem and guarantees a

predictable stable behavior at input signal levels of up to

150% of full-scale. In many industrial applications, it is

not uncommon to have to measure microvolt level signals

superimposed on volt level perturbations and the LTC2481

is eminently suited for such tasks. When the perturbation

is differential, the speciﬁ cation of interest is the normal

mode rejection for large input signal levels. With a refer-

ence voltage VREF = 5V, the LTC2481 has a full-scale dif-

ferential input range of 5V peak-to-peak. Figures 38 and

39 show measurement results for the LTC2481 normal

mode rejection ratio with a 7.5V peak-to-peak (150% of

full scale) input signal superimposed over the more tradi-

tional normal mode rejection ratio results obtained with a

5V peak-to-peak (full-scale) input signal. In Figure 38, the

LTC2481 uses the internal oscillator with the notch set at

60Hz and in Figure 39 it uses the internal oscillator with

the notch set at 50Hz. It is clear that the LTC2481 rejection

performance is maintained with no compromises in this

extreme situation. When operating with large input signal

levels, the user must observe that such signals do not

violate the device absolute maximum ratings.

Figure 33. Input Normal Mode Rejection at DC Figure 34. Input Normal Mode Rejection at fs = 256fN

INPUT SIGNAL FREQUENCY (Hz)

INPUT NORMAL MODE REJECTION (dB)

2481 F33

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 fN

0 2fN3fN4fN5fN6fN7fN8fN

fN= fEOSC/5120

INPUT SIGNAL FREQUENCY (Hz)

250fN252fN254fN256fN258fN260fN262fN

INPUT NORMAL MODE REJECTION (dB)

2481 F34

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

LTC2481

2481fc

APPLICATIONS INFORMATION

Figure 35. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full-Scale (60Hz Notch)

Figure 36. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full-Scale (50Hz Notch)

Figure 37. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full-Scale (50Hz/60Hz Mode)

Figure 38. Measured Input Normal Mode Rejection

vs Input Frequency with Input Perturbation of 150%

Full-Scale (60Hz Notch)

Figure 39. Measured Input Normal Mode Rejection

vs Input Frequency with Input Perturbation of 150%

Full-Scale (50Hz Notch)

INPUT FREQUENCY (Hz)

015 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2481 F35

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

INPUT FREQUENCY (Hz)

012.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

NORMAL MODE REJECTION (dB)

2481 F36

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

INPUT FREQUENCY (Hz)

020 40 60 80 100 120 140 160 180 200 220

NORMAL MODE REJECTION (dB)

2481 F37

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

INPUT FREQUENCY (Hz)

015 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2481 F38

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VINCM = 2.5V

TA = 25°C

VIN(P-P) = 5V

VIN(P-P) = 7.5V

(150% OF FULL SCALE)

INPUT FREQUENCY (Hz)

NORMAL MODE REJECTION (dB)

2481 F39

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VIN(CM) = 2.5V

TA = 25°C

VIN(P-P) = 5V

VIN(P-P) = 7.5V

(150% OF FULL SCALE)

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

LTC2481

2481fc

APPLICATIONS INFORMATION

Figure 40. Input Normal Mode Rejection 2x Speed Mode Figure 41. Input Normal Mode Rejection 2x Speed Mode

Figure 42. Input Normal Mode Rejection vs Input

Frequency, 2x Speed Mode and 50Hz/60Hz Mode

Figure 43. Input Normal Mode Rejection 2x Speed Mode

Figure 44. Calibration Setup

INPUT SIGNAL FREQUENCY (fN)

INPUT NORMAL REJECTION (dB)

2481 F40

–20

–40

–60

–80

–100

–120 0fN2fN3fN4fN5fN6fN7fN8fN

INPUT SIGNAL FREQUENCY (fN)

INPUT NORMAL REJECTION (dB)

2481 F41

–20

–40

–60

–80

–100

–120 250248 252 254 256 258 260 262 264

INPUT FREQUENCY (Hz)

NORMAL MODE REJECTION (dB)

50 100 125 225

2481 F42

25 75 150 175 200

–20

–40

–60

–80

–100

–120

VCC = 5V

VREF = 5V

VINCM = 2.5V

VIN(P-P) = 5V

TA = 25°C

MEASURED DATA

CALCULATED DATA

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

–70

–80

–90

–100

–110

–120

–130

–140 54 58

2481 F43

50 52 56 60 62

NORMAL MODE REJECTION (dB)

NO AVERAGE

WITH

RUNNING

AVERAGE

SCL

SDA

CA1

CA0/f0

VCC

LTC2481

REF+

GND

IN–

IN+

ISOTHERMAL

0.1µF

1.7k

1µF

4R8

1k 5

2481 F44

26.3C

TYPE K

THERMOCOUPLE

JACK

(OMEGA MPJ-K-F)

REF–

IN OUT

NC1M4V0

TRIM

GND

LT1236

1.7k

LTC2481

2481fc

APPLICATIONS INFORMATION

Using the 2x speed mode of the LTC2481, the device

bypasses the digital offset calibration operation to double

the output data rate. The superior normal mode rejection

is maintained as shown in Figures 31 and 32. However,

the magniﬁ ed details near DC and fS = 256fN are different,

see Figures 40 and 41. In 2x speed mode, the bandwidth is

11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz

rejection mode and 12.4Hz for the 50Hz/60Hz rejection

mode. Typical measured values of the normal mode rejec-

tion of the LTC2481 operating with the internal oscillator

and 2x speed mode is shown in Figure 42.

When the LTC2481 is conﬁ gured in 2x speed mode, by

performing a running average, a SINC1 notch is combined

with the SINC4 digital ﬁ lter, yielding the normal mode

rejection identical as that for the 1x speed mode. The

averaging operation still keeps the output rate with the

following algorithm:

Result 1 = average (sample 0, sample 1)

Result 2 = average (sample 1, sample 2)

……

Result n = average (sample n – 1, sample n)

The main advantage of the running average is that it

achieves simultaneous 50Hz/60Hz rejection at twice the

effective output rate, as shown in Figure 43. The raw output

data provides a better than 70dB rejection over 48Hz to

62.4Hz, which covers both 50Hz ±2% and 60Hz ±2%. With

running average on, the rejection is better than 87dB for

both 50Hz ±2% and 60Hz ±2%.

Complete Thermocouple Measurement System with

Cold Junction Compensation

The LTC2481 is ideal for direct digitization of thermo-

couples and other low voltage output sensors. The input

has a typical offset error of 500nV (2.5µV max) offset

drift of 10nV/°C and a noise level of 600nVRMS. The input

span may be optimized for various sensors by setting the

gain of the PGA. Using an external 5V reference with a

PGA gain of 64 gives a ±78mV input range—perfect for

thermocouples.

Figure 45 (page 39 of this data sheet) is a complete type

K thermocouple meter. The only signal conditioning is a

simple surge protection network. In any thermocouple

meter, the cold junction temperature sensor must be at

the same temperature as the junction between the ther-

mocouple materials and the copper printed circuit board

traces. The tiny LTC2481 can be tucked neatly underneath

an Omega MPJ-K-F thermocouple socket ensuring close

thermal coupling.

The LTC2481’s 1.4mV/°C PTAT circuit measures the cold

junction temperature. Once the thermocouple voltage

and cold junction temperature are known, there are

many ways of calculating the thermocouple temperature

including a straight-line approximation, lookup tables or a

polynomial curve ﬁ t. Calibration is performed by applying

an accurate 500mV to the ADC input derived from an

1236 reference and measuring the local temperature

with an accurate thermometer as shown in Figure 44. In

calibration mode, the up and down buttons are used to

adjust the local temperature reading until it matches an

accurate thermometer. Both the voltage and temperature

calibration are easily automated.

The complete microcontroller code for this application is

available on the LTC2481 product webpage at:

http://www.linear.com

It can be used as a template for may different instruments

and it illustrates how to generate calibration coefﬁ cients

for the onboard temperature sensor. Extensive comments

detail the operation of the program. The read_LTC2481()

function controls the operation of the LTC2481 and is

listed below for reference.

LTC2481

2481fc

APPLICATIONS INFORMATION

LTC248X.h

Processor setup and

Lots of useful deﬁ nes for conﬁ guring the LTC2481 and LTC2485.

#include <16F73.h> // Device

#use delay(clock=6000000) // 6MHz clock

//#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT // Conﬁ guration fuses

#rom 0x2007={0x3F3A} // Equivalent and more reliable fuse conﬁ g.

#use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port

#include “PCM73A.h” // Various deﬁ nes

#include “lcd.c” // LCD driver functions

// Useful deﬁ nes for the LTC2481 and LTC2485 - OR them together to make the

// 8 bit conﬁ g word.

#deﬁ ne READ 0x01 // bitwise OR with address for read or write

#deﬁ ne WRITE 0x00

#deﬁ ne LTC248XADDR 0b01001000 // The one and only LTC248X in this circuit,

// with both address lines ﬂ oating.

// Select gain - 1 to 256 (also depends on speed setting)

#deﬁ ne GAIN1 0b00000000 // G = 1 (SPD = 0), G = 1 (SPD = 1)

#deﬁ ne GAIN2 0b00100000 // G = 4 (SPD = 0), G = 2 (SPD = 1)

#deﬁ ne GAIN3 0b01000000 // G = 8 (SPD = 0), G = 4 (SPD = 1)

#deﬁ ne GAIN4 0b01100000 // G = 16 (SPD = 0), G = 8 (SPD = 1)

#deﬁ ne GAIN5 0b10000000 // G = 32 (SPD = 0), G = 16 (SPD = 1)

#deﬁ ne GAIN6 0b10100000 // G = 64 (SPD = 0), G = 32 (SPD = 1)

#deﬁ ne GAIN7 0b11000000 // G = 128 (SPD = 0), G = 64 (SPD = 1)

#deﬁ ne GAIN8 0b11100000 // G = 256 (SPD = 0), G = 128 (SPD = 1)

// Select ADC source - differential input or PTAT circuit

#deﬁ ne VIN 0b00000000

#deﬁ ne PTAT 0b00001000

// Select rejection frequency - 50, 55, or 60Hz

#deﬁ ne R50 0b00000010

#deﬁ ne R55 0b00000000

#deﬁ ne R60 0b00000100

// Speed settings is bit 7 in the 2nd byte

#deﬁ ne SLOW 0b00000000 // slow output rate with autozero

#deﬁ ne FAST 0b00000001 // fast output rate with no autozero

LTC2481

2481fc

APPLICATIONS INFORMATION

LTC2481.c

Basic voltmeter test program for LTC2481

Reads LTC2481 input at gain = 1, 1X speed mode, converts to volts,

and prints voltage to a 2 line by 16 character LCD display.

Mark Thoren

Linear Technology Corporation

June 23, 2005

Written for CCS PCM compiler, Version 3.182

#include “LTC248X.h”

/*** read_LTC2481() ************************************************************

This is the function that actually does all the work of talking to the LTC2481.

Arguments: addr - device address

conﬁ g - conﬁ guration bits for next conversion

Returns: zero if conversion is in progress,

32 bit signed integer with lower 8 bits clear, 24 bit LTC2481

output word in the upper 24 bits. Data is left-justiﬁ ed for

compatibility with the 24 bit LTC2485.

the i2c_xxxx() functions do the following:

void i2c_start(void): generate an i2c start or repeat start condition

void i2c_stop(void): generate an i2c stop condition

char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack

boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device

These functions are very compiler speciﬁ c, and can use either a hardware i2c

port or software emulation of an i2c port. This example uses software emulation.

A good starting point when porting to other processors is to write your own

i2c functions. Note that each processor has its own way of conﬁ guring

the i2c port, and different compilers may or may not have built-in functions

for the i2c port.

When in doubt, you can always write a “bit bang” function for troubleshooting purposes.

The “fourbytes” structure allows byte access to the 32 bit return value:

struct fourbytes // Deﬁ ne structure of four consecutive bytes

{ // To allow byte access to a 32 bit int or ﬂ oat.

int8 te0; //

int8 te1; // The make32() function in this compiler will

int8 te2; // also work, but a union of 4 bytes and a 32 bit int

int8 te3; // is probably more portable.

};

Also note that the lower 4 bits are the conﬁ guration word from the previous conversion.

LTC2481

2481fc

APPLICATIONS INFORMATION

*******************************************************************************/

signed int32 read_LTC2481(char addr, char conﬁ g)

{

struct fourbytes // Deﬁ ne structure of four consecutive bytes

{ // To allow byte access to a 32 bit int or ﬂ oat.

int8 te0; //

int8 te1; // The make32() function in this compiler will

int8 te2; // also work, but a union of 4 bytes and a 32 bit int

int8 te3; // is probably more portable.

};

union // adc_code.bits32 all 32 bits

{ // adc_code.by.te0 byte 0

signed int32 bits32; // adc_code.by.te1 byte 1

struct fourbytes by; // adc_code.by.te2 byte 2

} adc_code; // adc_code.by.te3 byte 3

// Start communication with LTC2481:

i2c_start();

if(i2c_write(addr | WRITE))// If no acknowledge, return zero

{

i2c_stop();

return 0;

}

i2c_write(conﬁ g);

i2c_start();

i2c_write(addr | READ);

adc_code.by.te3 = i2c_read();

adc_code.by.te2 = i2c_read();

adc_code.by.te1 = i2c_read();

adc_code.by.te0 = 0;

i2c_stop();

return adc_code.bits32;

} // End of read_LTC2481()

/*** initialize() **************************************************************

Basic hardware initialization of controller and LCD, send Hello message to LCD

*******************************************************************************/

void initialize(void)

{

// General initialization stuff.

setup_adc_ports(NO_ANALOGS);

setup_adc(ADC_OFF);

setup_counters(RTCC_INTERNAL,RTCC_DIV_1);

setup_timer_1(T1_DISABLED);

setup_timer_2(T2_DISABLED,0,1);

// This is the important part - conﬁ guring the SPI port

setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock

CKP = 0; // Set up clock edges - clock idles low, data changes on

CKE = 1; // falling edges, valid on rising edges.

LTC2481

2481fc

APPLICATIONS INFORMATION

lcd_init(); // Initialize LCD

delay_ms(6);

printf(lcd_putc, “Hello!”); // Obligatory hello message

delay_ms(500); // for half a second

} // End of initialize()

*** main() ********************************************************************

Main program initializes microcontroller registers, then reads the LTC2481

repeatedly

*******************************************************************************/

void main()

{

signed int32 x; // Integer result from LTC2481

ﬂ oat voltage; // Variable for ﬂ oating point math

int16 timeout;

initialize(); // Hardware initialization

while(1)

{

delay_ms(1); // Pace the main loop to something more than 1 ms

// This is a basic error detection scheme. The LTC248X will never take more than

// 163.5ms, 149.9ms, or 136.5ms to complete a conversion in the 50Hz, 55Hz, and 60Hz

// rejection modes, respectively.

// If read_LTC248X() does not return non-zero within this time period, something

// is wrong, such as an incorrect i2c address or bus conﬂ ict.

if((x = read_LTC2481(LTC248XADDR, GAIN1 | VIN | R55)) != 0)

{

// No timeout, everything is okay

timeout = 0; // reset timer

x &= 0xFFFFFFC0; // clear conﬁ g bits so they don’t affect math

x ^= 0x80000000; // Invert MSB, result is 2’s complement

voltage = (ﬂ oat) x; // convert to ﬂ oat

voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31

lcd_putc(‘\f’); // Clear screen

lcd_gotoxy(1,1); // Goto home position

printf(lcd_putc, “V %01.4f”, voltage); // Display voltage

}

else

{

++timeout;

}

if(timeout > 200)

{

timeout = 200; // Prevent rollover

lcd_gotoxy(1,1);

printf(lcd_putc, “ERROR - TIMEOUT”);

delay_ms(500);

}

} // End of main loop

} // End of main()

LTC2481

2481fc

PACKAGE DESCRIPTION

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev B)

3.00 p0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 p 0.10

(2 SIDES)

0.75 p0.05

R = 0.125

TYP

2.38 p0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV B 0309

0.25 p 0.05

2.38 p0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 p0.05

(2 SIDES)

2.15 p0.05

0.50

BSC

0.70 p0.05

3.55 p0.05

PACKAGE

OUTLINE

0.25 p 0.05

0.50 BSC

LTC2481

2481fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 11/09 Update Tables 3 and 4 16

B 04/10 Added H-grade to Absolute Maximum Ratings, Order Information, Electrical Characteristics (Normal Speed),

Converter Characteristics, Power Requirements, Timing Characteristics, and Typical Performance Characteristics

2-10

C 06/10 Revised Typical Application drawing

Added text to I2C Interface section

LTC2481

2481fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0610 REV C • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

Figure 45. Complete Type K Thermocouple Meter

PART NUMBER DESCRIPTION COMMENTS

LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift

LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift

LT1790 Micropower SOT-23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift

LTC2400 24-Bit, No Latency ΔΣ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2410 24-Bit, No Latency ΔΣ ADC with Differential Inputs 0.8µVRMS Noise, 2ppm INL

LTC2411/

LTC2411-1 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP 1.45µVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection

(LTC2411-1)

LTC2413 24-Bit, No Latency ΔΣ ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise

LTC2415/

LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate Pin Compatible with the LTC2410

LTC2414/LTC2418 8-/16-Channel 24-Bit, No Latency ΔΣ ADCs 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA

LTC2440 High Speed, Low Noise 24-Bit ΔΣ ADC 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs

LTC2480 16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise,

Programmable Gain, and Temperature Sensor

Pin Compatible with LTC2482/LTC2484

LTC2482 16-Bit ΔΣ ADC with Easy Drive Inputs Pin Compatible with LTC2480/LTC2484

LTC2483 16-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface Pin Compatible with LTC2481/LTC2483

LTC2484 24-Bit ΔΣ ADC with Easy Drive Inputs Pin Compatible with LTC2480/LTC2482

LTC2485 24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface and

Temperature Sensor

Pin Compatible with LTC2481/LTC2483

SCL

SDA

CAO/fO

VCC

LTC2481

REF

REF–

IN–

IN+

ISOTHERMAL

0.1µF

1µF C6

0.1µF

TYPE K

THERMOCOUPLE

JACK

(OMEGA MPJ-K-F)

389

GNDCA1

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RA5

RA4

RA3

RA2

RA1

RA0

VDD

OSC1

OSC2

MCLR

6MHz

10k

BAT54

VSS

2481 F45

VSS

PIC16F73

10k

CALIBRATE

CONTRAST

GND D0

VCC

D1 D2 D3

2s 16 CHARACTER

LCD DISPLAY

(OPTREX DMC162488

OR SIMILAR)

DOWN UP

1.7k 1.7k