FUJITSU MICROELECTRONICS DATA SHEET DS04-29138-3E ASSP Spread Spectrum Clock Generator MB88182 DESCRIPTION MB88182 is the multi-output clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It is possible to set the frequency in the built-in register using the I2C bus that can vary depending on the application. FEATURES * Built-in PLL : 3 Without spread-spectrum function : 1 (PLL) With spread-spectrum function : 2 (SSCG1, SSCG2) * Clock output pins : 5 pins CLK1 : Clock output when setting to CLK1 (PLL). CLK2 : Clock output when setting to CLK2 (SSCG1) . CLK3 : Clock output when setting to CLK3 (SSCG2) . CLK4 : Clock output when setting to CLK4 (SSCG2) . Note: It is not possible to output CLK3 and CLK4 at the same time. CKREF : Buffered output for CKIN clock. * Power down pins : 5 pins XPD1 : Control the stop state of PLL and the CLK1 output. XPD2 : Control the stop state of SSCG1 and the CLK2 output. XPD3 : Control the stop state of the CLK3 output. XPD4 : Control the stop state of the CLK4 output. Note: Halting both CLK3 and CLK4 stops operating the SSCG2. XPDREF: Control the stop state of the CKREF output. (Continued) Copyright(c)2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.12 MB88182 (Continued) * Modulation enable pins : ENS Switch on and off for the modulation (For SSCG1, SSCG2) * Function to set the output clock frequency This has the slave transfer function for the I2C bus, and can set the output frequency of CLK1 (when setting to CLK1), CLK2 (when setting to CLK2), CLK3 (when setting to CLK3) and CLK4 (when setting to CLK4) from the outside. Also, it is possible to set the output drive ability of CLK1, CLK2, CLK3 and CLK4. Output frequency* : 8 MHz to 100 MHz, internal oscillation frequency : 16 MHz to 168 MHz *: When VDP is 1.8 V 0.15 V, the frequency range to output is 8 MHz to 50 MHz. Programmable of the parameter of N divider, M divider, K divider Setting to CLK1 : N divider : 5-bit, M divider : 6-bit, K divider : 5-bit Setting to CLK2, 3, 4 : N divider : 11-bit, M divider : 12-bit, K divider : 5-bit Modulation rate : Selectable from no modulation, 0.25%, 0.5%, 0.75%, 1.0%, 1.25%, 1.5% and 1.75%. * * * * Input clock 10 MHz to 30 MHz Power supply voltage: 1.8 V 0.15 V (VDD), 2.6 V 0.1 V (VDDE), 1.65 V to 2.7 V (VDP) Operating temperature: - 40 C to + 85 C Power consumption: At operation 18 mW (Power supply voltage:1.8 V (VDD), 2.6 V (VDDE, VDP) normal temperature, no load, CKREF(19.2 MHz), CLK1 (48 MHz, 1.8 V), CLK2 (27 MHz), CLK3 (37 MHz) during the clock output) During the power down state for all outputs 0.01 mW (Power supply voltage: 1.8 V (VDD) , 2.6 V (VDDE, VDP), normal temperature) * Cycle-Cycle Jitter : Less than 100 ps-rms * Package : BCC20 (3.50 mm x 3.50 mm, Lead pitch 0.50 mm, Mounting height 0.60 mm) QFN24 (2.50 mm x 3.50 mm, Lead pitch 0.40 mm, Mounting height 0.80 mm) PRODUCT LINEUP MB88182 has the following lineups corresponding to the different voltages of CLK1 pin and I2C addresses. Part number BCC20 package QFN24 package CLK1 MB881821APVA1 MB881821AWQN 1.8 V MB881822APVA1 MB881822AWQN 2.6 V MB881821BPVA1 MB881821BWQN 1.8 V MB881822BPVA1 MB881822BWQN 2.6 V 2 CLK2 CLK3/CLK4/CKREF 2.6 V VDP level (1.8 V / 2.6 V) I2C address 1001111B 1011111B DS04-29138-3E MB88182 PIN ASSIGNMENT * BCC20 CLK4 CLK3 19 18 17 ENS 2 16 VDDE CKIN 3 15 VSS VSS 4 14 CLK2 VDD 5 13 XPD4 CLK1 6 12 XPD3 XPDREF 7 11 XPD2 8 9 10 XPD1 CKREF 20 SDA 1 SCL VDP VSS (TOP VIEW) (LCC-20P-M06) DS04-29138-3E 3 MB88182 * QFN24 SDA SCL 24 1 23 22 21 XPDREF XPD1 VSS XPD2 (TOP VIEW) 20 19 VSS XPD4 3 17 VDD CLK2 4 16 VSS VSS 5 15 CKIN VDDE 6 14 CKREF NC 7 8 CLK3 ENS 9 10 11 13 12 VDP CLK1 VSS 18 CLK4 2 VSS XPD3 (LCC-24P-M61) 4 DS04-29138-3E MB88182 PIN DESCRIPTION Pin name I/O VDP Pin no. Description BCC20 QFN24 1 12 Power supply pin (2.6 V / 1.8 V) NC 13 NC pin CKREF O 2 14 Reference clock output pin CKIN I 3 15 Clock input pin (19.2 MHz) VSS 4 16 GND pin VDD 5 17 Power supply pin (1.8 V) CLK1 O 6 18 Clock output pin 1 VSS 19 GND pin XPDREF I 7 20 CKREF Power down pin SCL I 8 21 I2C bus clock input pin SDA I/O 9 22 I2C bus data I/O pin XPD1 I 10 23 CLK1 Power down pin XPD2 I 11 24 CLK2 Power down pin VSS 1 GND pin XPD3 I 12 2 CLK3 Power down pin XPD4 I 13 3 CLK4 Power down pin CLK2 O 14 4 Clock output pin 2 VSS 15 5 GND pin VDDE 16 6 Power supply pin (2.6 V) ENS I 17 7 Modulation enable pin CLK3 O 18 8 Clock output pin 3 VSS 9 GND pin CLK4 O 19 10 Clock output pin 4 VSS 20 11 GND pin DS04-29138-3E 5 MB88182 I/O CIRCUIT TYPE Pin Circuit type XPDREF XPD1 XPD2 XPD3 XPD4 ENS SCL SDA 2.6 V 2.6 V Remarks * CMOS hysteresis input * With pull-up resistor (20 k) The pull-up resistor is cut off during the "L" input. CMOS hysteresis input CMOS hysteresis input * CMOS hysteresis input * N-ch open drain output * IOL = 4 mA (Continued) 6 DS04-29138-3E MB88182 Pin CKIN CLK1 Circuit type 1.8 V Remarks * Feedback resistors 1 M * Possible to input clock via the coupling capacity 1 M 1.8 V or 2.6 V * CMOS output * IOH = - 2 mA or - 4 mA * IOL = 2 mA or 4 mA (Switchable by the output drive ability setting bit) * Operates at 1.8 v or 2.6 v depending on the part number. CLK2 2.6 V CLK3 CLK4 VDP * CMOS output * IOH = - 2 mA or - 4 mA * IOL = 2 mA or 4 mA (Switchable by the output drive ability setting bit) * CMOS output * At VDP = 2.6 V 0.1 V IOH = - 2 mA or - 4 mA IOL = 2 mA or 4 mA (Switchable by the output drive ability setting bit) * At VDP = 1.8 V 0.15 V IOH = - 1 mA or - 2 mA IOL = 1 mA or 2 mA (Continued) DS04-29138-3E 7 MB88182 (Continued) Pin CKREF 8 Circuit type Remarks VDP * CMOS output * At VDP = 2.6 V 0.1 V IOH = - 2 mA IOL = 2 mA * At VDP = 1.8 V 0.15 V IOH = - 1 mA IOL = 1 mA DS04-29138-3E MB88182 HANDLING DEVICES (1) Preventing latch-up A latch-up may occur in a CMOS IC if a voltage greater than power supply voltage or a voltage less than GND is applied to an input or output pin, or if an above-rating voltage is applied between power supply and GND. A latch-up, if it occurs, significantly increases the power-supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating. (2) Handling control input pins The input pins (ENS, XPD1, XPD2, XPD3, XPD4, and XPDREF) of this device should be high or low level preventing the pins from being undefined by connecting a pull-down or pull-up resistor, or performing level input by control signals. The wait time for clock stabilization is needed after turning the power on or when changing the setting of ENS pin or power down control pins (XPD1, XPD2, XPD3, XPD4, and XPDREF). Please use the clock after the lockup time has passed. (The lock-up time varies depending on the setting value to the respective register. Please confirm the recommended value with the Fujitsu Microelectronics support tool.) (3) Power supply pins Ensure that the impedance of the connection from the power supply source to the power supply pins on the device is as low as possible. We recommend connecting the electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between power supply and GND near the device, as a bypass capacitor. We also recommend inserting a low pass filter less than 3.4 kHz of a cutoff frequency to the power-supply line of MB88182 for not being affected by the power-supply noise on the customer's system. The supply voltage to MB88182 is decreased when a resistor is inserted; therefore, please use the resistor less than 10 in case of inserting a resistor. (An example of recommended combination is 4.7 F for a capacitance and 10 for a resistor.) * Example of recommended circuit of low pass filter to remove power-supply noise VCC 10 4.7 F (Power supply line) MB88182 0.1 F (Bypass capacitor) DS04-29138-3E 9 MB88182 BLOCK DIAGRAM Power down control XPD4 CLK4 SSCG2 XPD3 CLK3 Oscillates when setting to the enable side Setting to CLK4 SCL Setting to CLK3 SDA I2C circuit Setting to CLK2 Setting to CLK1 XPD2 XPD1 CKIN SSCG1 PLL CLK2 CLK1 CKREF XPDREF ENS 10 DS04-29138-3E MB88182 PIN SETTING ENS Modulation enable setting ENS Modulation 0 No modulation 1 (2.6 V) Modulation When setting "0" to the ENS pin, the spectrum will not spread. The setting is for CLK2 (SSCG1) and CLK3, and CLK4 (SSCG2). XPD Power down setting XPDREF XPD1 XPD2 XPD3 XPD4 0 CKREF is fixed to the output "L". 1 (2.6 V) CKREF is the clock output. 0 PLL1 is in the power down state. CLK1 is fixed to the output "L". 1 (2.6 V) PLL1 and CLK1 are in operation. 0 SSCG1 is in the power down state. CLK2 is fixed to the output "L". 1 (2.6 V) SSCG1 and CLK2 are in operation. 0 CLK3 is fixed to the output "L". 1 (2.6 V) SSCG2 and CLK3 are in operation. 0 CLK4 is fixed to the output "L". 1 (2.6 V) SSCG2 and CLK4 are in operation. The pin in XPDREF, XPD1, XPD2, XPD3 and XPD4 is connected to the pull-up resistor. However, the pull-up resistor is cut off during "0" input. When both XPD3 and XPD4 are "0", SSCG2 is in the power down state. DS04-29138-3E 11 MB88182 SETTING REGISTER <Memory map> Setting register for CLK2, CLK3, CLK4 (All registers have the same configurations.) Address Function Remarks bit0 to 11 M divider setting (12-bit) Selectable in the range of 100 to 3600 bit12 to 22 N divider setting (11-bit) Selectable in the range of 3 to 2047 bit23 to 27 K divider setting (5-bit) Selectable in the range of 1 to 32 bit28 to 30 L divider setting (3-bit) Modulation frequency setting (selectable in the range of 1 to 8) bit31 to 34 Charge Pump setting (4-bit) Charge pump current setting due to internal oscillation frequency and M divider setting bit35 to 40 VCO Gain setting (6-bit) Gain setting due to internal oscillation frequency bit41 to 43 Modulation rate setting (3-bit) modulation off, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75% are selectable bit44 Output drive setting 0 : Ability small, 1 : Ability large bit45 Slewing rate setting 0 : Slewing rate low, 1 : Slewing rate high bit46, 47 Invalid bit CLK1 setting register Address Function When in writing : The written data is ignored. When in reading : Undefined Remarks bit0 to 5 M divider setting (6-bit) Selectable in the range of 3 to 52 bit6 to 10 N divider setting (5-bit) Selectable in the range of 3 to 31 bit11 to 15 K divider setting (5-bit) Selectable in the range of 1 to 32 bit16 to 19 Charge Pump setting (4-bit) bit20 to 25 VCO Gain setting (6-bit) bit26 Output drive setting 0 : Ability small, 1 : Ability large bit27 Slewing rate setting 0 : Slewing rate low, 1 : Slewing rate high bit28 to 31 Invalid bit Charge pump current setting due to internal oscillation frequency and M divider setting Gain setting due to internal oscillation frequency When in writing : The written data is ignored. When in reading : Undefined Note: The bit's initial value in a register is undefined. Therefore, if the power down of clock output is released before the register setting, the clock is output with settings unintended. The power down of the clock output for CLK1, CLK2, CLK3 and CLK4 should be released after setting to registers. 12 DS04-29138-3E MB88182 <Frequency setting> When setting each divider parameter of the oscillator to a register, the output frequency can be set. Internal oscillation frequency and output frequency can be calculated with following formula: Internal oscillation frequency (fvco*) = Input frequency (fin) x M/N * : Please set the fvco range from 16 MHz to 168 MHz. Output frequency (fout*) = fvco/K * : Please set the fout range from 8 MHz to 100 MHz. Set the output frequency to 8 MHz to 50 MHz for CLK3 and CLK4 setting registers when VDP is 1.8 V 0.15 V. (Setting example) fin : 19.2 MHz, fout : 29.6 MHz M divider parameter : 222 ( = 0DEH) , N divider parameter : 144 ( = 090H) , K divider parameter : 1 ( = 01H) (19.2 x 222 / 144) / 1 = 29.6 (MHz) (fvco : 19.2 x 222 / 144 = 29.6 (MHz) ) Note: The recommended setting value of the VCO gain and the M divider depends on the internal oscillation frequency. Also, the recommended setting value of the Charge Pump depends on the setting values of the VCO gain and the M divider. Please confirm the recommended value with the Fujitsu Microelectronics support tool. Contact the sales representatives for details on the support tools. <Modulation frequency setting> Modulation frequency can be set by writing L divider parameter to the register. The average of modulation frequency can be calculated with following formula: Input frequency 266 x L (L = 1, 2, 3, 4, 5, 6, 7, 8) (Setting example) fin : 19.2 MHz, average of modulation freq. 19.2 / (266 x 6) x 1000 = Approximately 12.0 (kHz) bit30 bit29 bit28 L divider parameter 0 0 0 8 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Recommended value) 1 1 1 7 DS04-29138-3E 13 MB88182 <Modulation rate setting> Modulation rate can be selectable from no modulation, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75%. bit43 bit42 bit41 Modulation rate setting 0 0 0 No modulation 0 0 1 0.25% 0 1 0 0.50% 0 1 1 0.75% 1 0 0 1.00% 1 0 1 1.25% 1 1 0 1.50% 1 1 1 1.75% <Charge Pump setting, VCO gain setting> Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. <Output drive ability setting> Output drive ability of clock output pin can be selected. bit44 Output drive ability 0 Small 1 Large <Slew rate setting> Slew rate of clock output pin can be selected. bit45 Slew rate 14 0 Low 1 High DS04-29138-3E MB88182 I2C This device contains the I2C macro and enables the slave transfer operation. The I2C is set to the corresponding registers via the I2C bus. <Bus specification> * The transfer rate should be in either standard mode or the fast mode (The high speed mode is not supported) . * 7-bit address specified (The general call and the 10-bit address specifications are not supported). <Bus format when writing register> first S6 S0 R/W Slave address (7 bit) S 0 C0 Command (8 bit) A : Transmit from master device S : START condition C7 D7 A D0 Register setting (8 bit) Last A Register setting A P : Transmit from this device (slave) A : Acknowledge P : STOP condition <Slave address> When receiving the slave address, the address is compared with the address in the following table. If the slave address matches the address in the table only, I2C judges to access to this device. Slave address (7-bit) S6 S5 S4 S3 S2 S1 S0 Part number 1 0 0 1 1 1 1 MB881821APVA1/MB881822APVA1 1 0 1 1 1 1 1 MB881821BPVA1/MB881822BPVA1 <Select R/W> "0" : Write to slave device "1" : Read from slave device DS04-29138-3E 15 MB88182 <Command> Set for the CLK2, CLK3 and CLK4 setting registers with either individual or successive settings. Settings other than those in the following table are prohibited. Command (8-bit) C7 C6 C5 C4 C3 C2 C1 C0 Transfer bytes 0 0 0 0 0 0 0 1 4 Set to CLK1 setting register 0 0 0 0 0 0 1 0 6 Set to CLK2 setting register 0 0 0 0 0 1 0 0 6 Set to CLK3 setting register 0 0 0 0 1 0 0 0 6 Set to CLK4 setting register 0 0 0 0 1 1 1 1 22 Successive set to all registers 0 0 0 0 Other than "0000" or those above 10 to 18 Successive set to the register corresponding to the bit which is set "1". <Register setting for writing data> Transfer data from the upper address. When writing successively to the setting registers of multiple clocks, the data will be written from the setting registers CLK1, CLK2, CLK3 and to CLK4 in order. <Bus format for reading register> first S6 S0 R/W D7 S Slave address (7 bit) 1 A CLK1 setting register bit31-24 output : Transmit from master device S : START condition D0 D7 A D0 CLK1 setting register bit23-16 output Last A output register A values P : Transmit from this device (slave) A : Acknowledge P : STOP condition When reading data, the data will be output from the upper address of the CLK1 setting register, then CLK2 setting register, CLK3 setting register, CLK4 setting register, in order. The data will be output 22 bytes in total. Note: When all outputs in this device are powered down, the I2C function also stops. Therefore, setting by the I2C should be performed when the CKREF clock is being output. 16 DS04-29138-3E MB88182 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Pin VDD 1 Power supply voltage* Input voltage*1 Unit Min Max VDD - 0.5 + 2.5 V VDDE VDDE - 0.5 + 4.0 V VDP VDP - 0.5 + 4.0 V CKIN VSS - 0.5 VDD + 0.5 V XPDREF, XPD1, XPD2, XPD3, XPD4, SCL, SDA VSS - 0.5 VDDE + 0.5 V CLK1 VSS - 0.5 VDD + 0.5*2 VDDE + 0.5*3 V CLK2, SDA VSS - 0.5 VDDE + 0.5 V CLK3, CLK4, CKREF VSS - 0.5 VDP + 0.5 V VI Output voltage*1 Rating VO Storage temperature TST - 55 + 125 C Operation junction temperature TJ - 40 + 125 C Output current IO - 13 + 13 mA Overshoot VIOVER VDDE + 1.0 (tOVER 50 ns) V Undershoot VIUNDER XPDREF, XPD1, XPD2, XPD3, XPD4, SCL, SDA VSS - 1.0 (tUNDER 50 ns) V *1 : The parameter is based on VSS = 0.0 V. *2 : Part number: MB881821A/MB881821B *3 : Part number: MB881822A/MB881822B WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot / Undershoot tunder 50 ns VIOVER VDDE + 1.0 V VDDE Input pin VSS tOVER 50 ns DS04-29138-3E VIUNDER VSS - 1.0 V 17 MB88182 RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Symbol Pin Condition VDD VDD VDDE VDDE Value Min Typ Max 1.65 1.8 1.95 2.5 2.6 2.7 1.65 1.8 1.95 2.5 2.6 2.7 Unit V VDP VDP VIH1 CKIN VDD x 0.8 VDD + 0.3 VIH2 ENS, XPDREF, XPD1, XPD2,XPD3, XPD4 VDDE x 0.8 VDDE + 0.3 VIH3 SDA, SCL VDDE x 0.7 VDDE + 0.3 VIL1 CKIN Vss - 0.3 VDD x 0.2 VIL2 ENS, XPDREF, XPD1, XPD2, XPD3, XPD4 Vss - 0.3 VDDE x 0.2 VIL3 SDA, SCL Vss - 0.3 VDDE x 0.3 Input clock amplitude level VIC CKIN 0.45 VDD V p-p Input coupling capacity CC * 20 pF Input clock duty cycle tDCI CKIN 19.2 [MHz] 40 50 60 % Operating temperature Ta - 40 + 85 C "H" level input voltage "L" level input voltage During clock input of capacitive coupling V V * : Capacity value when clock signal is input to the CKIN pin via coupling capacity. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Input clock duty cycle (tDCI = th/tp) tP th VDD/2 CKIN 18 DS04-29138-3E MB88182 ELECTRICAL CHARACTERISTICS * DC Characteristics (Ta = - 40 C to + 85 C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V) Parameter Symbol Power supply current Pin Conditions ICC VDD*1 ICCE VDDE CKREF = 19.2 MHz, CLK1 = 48 MHz*2, CLK2 = 27 MHz, CLK3 = 37 MHz, CLK4 output stop, output no load, CKIN direct input ICCP VDP ICCH VDD ICCEH VDDE ICCPH VDP VOH1 VOL1 CLK1* , CLK2, CLK3, CLK4 Min Typ Max 7 11 0.5 0.9 2 50 1 5 1 5 Driving ability small setting VDDE - 0.2 "H" level output VDP - 0.2 IOH = - 2 mA VDDE VDP Driving ability small setting "L" level output IOL = 2 mA 0.2 When all clock output disable VSS A V VDDE VDP VOL2 Driving ability large setting "L" level output IOL = 4 mA VSS 0.2 VOH1 "H" level output IOL = - 2 mA VDP - 0.2 VDP "L" level output IOL = 2 mA VSS CKREF VOL1 V 0.2 VOH3 Driving ability small setting VDD - 0.2 "H" level output IOH = - 2 mA VDD VOL3 Driving ability small setting "L" level output IOL = 2 mA 0.2 CLK1*2 Unit mA Driving ability large setting VDDE - 0.2 "H" level output VDP - 0.2 IOH = - 4 mA VOH2 Output voltage 3 Value VSS V VOH4 Driving ability large setting VDD - 0.2 "H" level output IOH = - 4 mA VDD VOL4 Driving ability large setting "L" level output IOL = 4 mA 0.2 VSS (Continued) DS04-29138-3E 19 MB88182 (Continued) Parameter (Ta = - 40 C to + 85 C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V) Symbol Pin Conditions Output voltage VOL2 SDA Pull-up resistance value*4 RPU CIN Input capacitance Value Unit Min Typ Max "L" level output IOL = 4 mA VSS 0.2 V XPDREF, XPD1, XPD2, XPD3, XPD4 VIH = VDDE x 0.8 10 20 30 k CKIN, ENS, XPDREF, XPD1, XPD2, XPD3, XPD4, SDA, SCL Ta = + 25 C VDD = VDDE = VI = 0 V f = 1 MHz 10 pF *1 : Excluding power supply current in the CLK1 output *2 : Part number: MB881821APVA1/MB881821BPVA1 *3 : Part number: MB881822APVA1/MB881822BPVA1 *4 : The pull up resistor for each pin is cut off when the pin input is in "L" level. (Ta = - 40 C to + 85 C, VDP = 1.8 V 0.15 V) Parameter Symbol Pin Typ Max VOH5 Driving ability small setting "H" level output IOH = - 1 mA VDP - 0.2 VDP VOL5 Driving ability small setting "L" level output IOL = 1 mA VSS 0.2 VOH6 Driving ability large setting "H" level output IOH = - 2 mA VDP - 0.2 VDP VOL6 Driving ability large setting "L" level output IOL = 2 mA VSS 0.2 VOH5 "H" level output IOL = - 1 mA VDP - 0.2 VDP "L" level output IOL = 1 mA VSS CKREF VOL5 20 Value Min CLK3, CLK4 Output voltage Conditions Unit V V 0.2 DS04-29138-3E MB88182 * AC characteristics 1 (Ta = - 40 C to + 85 C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V) Parameter Symbol Pin Conditions Input frequency fIN CKIN Output frequency Output slewing rate Min Typ Max 10 19.2 30 CKREF Load capacitance 15 pF or less 10 19.2 30 CLK1*1 Load capacitance 15 pF or less 8 100 Load capacitance 15 pF or less 8 90 Load capacitance 10 pF or less 8 100 Slewing rate low, Driving ability small setting 15 pF load capacitance 8 MHz to 70 MHz 0.32 Slewing rate high, Driving ability small setting 15 pF load capacitance 8 MHz to 70 MHz 0.33 Slewing rate low, Driving ability large setting 15 pF load capacitance 8 MHz to 80 MHz 0.37 Slewing rate high, Driving ability large setting 15 pF load capacitance 8 MHz to 100 MHz 0.43 fOUT CLK1*2, CLK2, CLK3, CLK4 SR Value CLK1*1 Unit MHz MHz V/ns (Continued) DS04-29138-3E 21 MB88182 (Ta = - 40 C to + 85 C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V) Parameter Output slewing rate Symbol SR Pin Value Min Typ Max Slewing rate low, Driving ability small setting 15 pF load capacitance 8 MHz to 50 MHz 0.31 Slewing rate high, Driving ability small setting 15 pF load capacitance 8 MHz to 60 MHz 0.33 Slewing rate low, Driving ability large setting 15 pF load capacitance 8 MHz to 60 MHz 0.46 Slewing rate high, Driving ability large setting 15 pF load capacitance 8 MHz to 90 MHz 0.50 Slewing rate high, Driving ability large setting 10 pF load capacitance 90 MHz to 100 MHz 0.63 15 pF load capacitance 0.33 Driving ability small setting 40 Driving ability large setting 28 Driving ability small setting 60 Driving ability large setting 30 CLK2, CLK3, CLK4 Driving ability small setting 60 Driving ability large setting 30 CKREF 60 CLK1*2, CLK2, CLK3, CLK4 CKREF CLK1*1 Output impedance Conditions CLK1*2 ZO Unit V/ns (Continued) 22 DS04-29138-3E MB88182 (Continued) Parameter (Ta = - 40 C to + 85 C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V, VDP = 2.6 V 0.1 V) Symbol Pin CLK1*1 Output clock duty cycle Modulation frequency Lock-up time*6 CLK1*2 tDCC FMOD tLK Conditions Value Min Typ Max VDD / 2*3 40 60 VDD / 2*4 45 55 VDDE / 2*3 40 60 VDDE / 2*4 45 55 Unit % CLK2, CLK3, CLK4 VDDE / 2, VDP / 2*3 40 60 VDDE / 2, VDP / 2*4 45 55 CKREF VDP / 2 tDCI - 5*5 tDCI + 5*5 CLK2, CLK3, CLK4 CLK1 0.3 ms CLK2, CLK3, CLK4 16 ms No load capacitance 100 ps-rms fin/ (224 x L) fin/ (266 x L) fin/ (308 x L) ( 224 x L ) ( 266 x L ) ( 308 x L ) kHz (clks) Cycle-cycle jitter tJC CLK1, CLK2, CLK3, CLK4 CKREF Power down tRPD CKREF tP x 2 + 2 ns CKREF Power down release tROE CKREF tP x 2 + 2 ns *1: Part number: MB881821APVA1/MB881821BPVA1 *2: Part number: MB881822APVA1/MB881822BPVA1 *3 : When K divider parameter = 1 and output frequency is above 50 MHz. *4 : When K divider parameter 1, or K divider parameter = 1 and output frequency is 50 MHz or less. *5 : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle. *6 : The wait time for clock stabilization is needed after turning the power on or when changing the setting of ENS/ power down pins. The lock-up time varies depending on the setting value to the respective register. Please confirm the recommended value with the Fujitsu Microelectronics support tool. Contact the sales representatives for details on the support tools. DS04-29138-3E 23 MB88182 (Ta = - 40 C to + 85 C, VDP = 1.8 V 0.15 V) Parameter Output frequency Output slewing rate Output impedance Symbol fOUT SR ZO Pin Conditions Value Min Typ Max Load capacitance 10 pF or less 8 50 Load capacitance 15 pF or less 8 40 Slewing rate low, Driving ability small setting 15 pF load capacitance 8 MHz to 25 MHz 0.13 Slewing rate high, Driving ability small setting 15 pF load capacitance 8 MHz to 30 MHz 0.14 Slewing rate low, Driving ability large setting 15 pF load capacitance 8 MHz to 30 MHz 0.19 Slewing rate high, Driving ability large setting 15 pF load capacitance 8 MHz to 40 MHz 0.22 Slewing rate high, Driving ability large setting 10 pF load capacitance 8 MHz to 50 MHz 0.29 CKREF 15 pF load capacitance 0.14 CLK3, CLK4 Driving ability small setting 80 Driving ability large setting 40 CKREF 80 CLK3, CLK4 VDP / 2 45 55 CKREF VDP / 2 tDCI - 5* tDCI + 5* CLK3, CLK4 CLK3, CLK4 Unit MHz V/ns Output clock duty cycle tDCC CKREF Power down tRPD CKREF tP x 2 + 2 ns CKREF Power down release tROE CKREF tP x 2 + 2 ns % * : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle. 24 DS04-29138-3E MB88182 <Definition of modulation frequency and number of input clocks per modulation> f (Output frequency) Modulation waveform t FMOD (Min) FMOD (Max) V Input clock Clock count NMOD (Max) t Clock count NMOD (Min) This product contains the modulation period to realize the efficient EMI reduction. The modulation period FMOD depends on the input frequency and changes between FMOD (Min) and FMOD (Max). Furthermore, the typical value of the electrical characteristics is equivalent to the average value of the modulation period FMOD. <Output slew rate (SR) > CLK1 (VDD - 0.2) V*,(VDP - 0.2) V*, (VDDE - 0.2) V* CLK2 CLK3 CLK4 0.2 V tf tr * : The value is differ depending on the power supply pin. CLK1 : (VDD - 0.2)V or (VDDE - 0.2)V (depending on models) CLK2 : (VDDE - 0.2)V CLK3 : CLK4: (VDP - 0.2)V Note: SR = (power supply voltage - 0.4) / tr, SR = (power supply voltage - 0.4) / tf <Cycle-cycle jitter (tJC = |tn - tn + 1|)> CLK1 CLK2 CLK3 CLK4 DS04-29138-3E tn tn+1 25 MB88182 <Output timing with XPDREF control> VIL XPDREF CKREF tP tRPD VIH XPDREF CKREF tROE <Lock-up time> CKIN VIH XPD1, XPD2, XPD3, XPD4 VIL tLK (lock-up time) CLK1, CLK2, CLK3, CLK4 If the power down control is performed on pins XPD1, XPD2, XPD3 and XPD4, the desired clock frequency will be obtained once the power down pin becomes at the "H" level and after the lock-up time tLK has passed at maximum. CKIN ENS VIH tLK (lock-up time) VIL tLK (lock-up time) CLK2, CLK3,CLK4 If the ENS pin setting changes during the normal operation, setting clocks CLK2, CLK3 and CLK4 will be output once the ENS pin level is decided and after lock-up time tLK has passed at maximum. Note: When the ENS pin setting is changed, the stabilization wait time is needed for the output clock from CLK2, CLK3 and CLK4 pins. During the stabilization wait time, the output frequency, output clock duty cycle, modulation frequency, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. 26 DS04-29138-3E MB88182 * AC characteristics 2 (Serial timing) Parameter (Ta = - 40 C to + 85 C, VDD = 1.8 V 0.15 V, VDDE = 2.6 V 0.1 V) Symbol Pin Conditions SCL clock frequency fSCL SCL During data input set up time tISU During data input hold time Noise removal width Value Unit Min Max 0 400 kHz SDA 100 ns tIH SDA 0 ns tNC SDA SCL 100 160 ns Input hysteresis VHYS SDA SCL 0.3 V (Repeat) START condition hold time tSTAH SDA SCL 0.5 s Repeat START condition setup time tSTASU SDA SCL 0.5 s SCL clock "L" width tCL SCL 1 s SCL clock "H" width tCH SCL 0.5 s STOP condition setup time tSTOSU SDA SCL 0.5 s Bus free time between stop condition and start condition tBUF SDA SCL 1 s During bus drive set up time tOSU SDA 1 s During bus drive hold time tOH SDA 0 0.6 s During bus drive fall time tOF SDA 300 ns DS04-29138-3E Bus load: under 400 pF, Resistor value for bus pull-up: at least 750 27 MB88182 * During data input/bus drive + VDDE 0.7 SCL + VDDE 0.3 tISU, tOSU tIH, tOH SDA * Noise cancel operation tNC tNC External SCL signal Internal SCL signal after noise removal The pulse in the tNC range is removed. * (Repeat) Start operation, Stop operation tSTOSU tSTASU SCL tBUF tSTAH SDA 28 DS04-29138-3E MB88182 RECOMMENDED CIRCUIT CLK4 CLK3 2.6 V to 1.8 V + ENS R3 R4 C3 2.6 V 1 R5 C6 20 19 18 17 CKREF 2 16 CKIN 3 15 4 14 1.8 V R1 MB88182 5 13 6 12 7 8 9 10 C4 R7 R6 R1, R2, R3, R4, R5 R6, R7 DS04-29138-3E 11 XPD3 XPD2 C5 XPD1 + C1 C1, C2, C3 C4, C5, C6 CLK2 XPD4 CLK1 XPDREF R2 + SCL SDA C2 : Capacitor of 10 F or higher : Capacitor of about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) : Impedance matching resistor for board pattern : I2C bus Pull-up resistor 29 MB88182 CLOCK INPUT VIA COUPLING CAPACITY It is possible to input clocks to the CKIN pin via the coupling capacity as shown in the following figure. The device input part contains the CMOS inverter and the feedback resistor (1 M). The clock input via the coupling capacity operates near the threshold level of the CMOS inverter, therefore the current for the capacity connection clock input increases compared to the normal input. Input clock LSI external Clock after the coupling capacity passes by LSI internal VIC CC CKIN pin Input via coupling capacity Rf (1 M) 30 DS04-29138-3E MB88182 ORDERING INFORMATION Part number Package MB881821APVA1-GE1 MB881821APVA1-G-ERE1 MB881821APVA1-G-EFE1 MB881821BPVA1-GE1 MB881821BPVA1-G-ERE1 MB881821BPVA1-G-EFE1 MB881822APVA1-GE1 MB881822APVA1-G-ERE1 MB881822APVA1-G-EFE1 MB881822BPVA1-GE1 MB881822BPVA1-G-ERE1 MB881822BPVA1-G-EFE1 20-pin plastic BCC (LCC-20P-M06) MB881821AWQN-G-JNE1 MB881821AWQN-G-JN-ERE1 MB881821AWQN-G-JN-EFE1 MB881821BWQN-G-JNE1 MB881821BWQN-G-JN-ERE1 MB881821BWQN-G-JN-EFE1 MB881822AWQN-G-JNE1 MB881822AWQN-G-JN-ERE1 MB881822AWQN-G-JN-EFE1 MB881822BWQN-G-JNE1 MB881822BWQN-G-JN-ERE1 MB881822BWQN-G-JN-EFE1 24-pin plastic QFN (LCC-24P-M61) DS04-29138-3E 31 MB88182 PACKAGE DIMENSION 20-pin plastic BCC Lead pitch 0.50 mm Package width x package length 3.50 mm x 3.50 mm Sealing method Plastic mold Mounting height 0.60 mm MAX Weight 0.01 g (LCC-20P-M06) 20-pin plastic BCC (LCC-20P-M06) 3.00(.118)REF. 0.550.050 (.022.0020) Mount height 3.500.10 (.138.004) 0.500.10 (.020.004) 11 17 0.50(.020) TYP 11 0.50(.020) TYP. 2.90(.114) TYP. INDEX AREA 3.500.10 (.138.004) 2.90(.114) TYP. 7 0.0750.025 (.003.001) (Stand off) 0.95 (.037) "A" 1.00(.004) REF. 1 17 7 1PIN INDEX "B" 1.55(.061) 1 Details of "A" part Details of "B" part 0.400.06 (.016.002) 0.14(.006) MIN 0.400.06 (.016.002) 0.300.06 (.012.002) 0.20(.008) 0.05(.002) 0.300.06 (.012.002) (c)2004-2008 FUJITSU MICROELECTRONICS LIMITED C20057S-c-1-2 C 2004 FUJITSU LIMITED C20057S-c-1-1 0.20(.008) 1PIN INDEX Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 32 DS04-29138-3E MB88182 (Continued) 24-pin plastic QFN Lead pitch 0.40 mm Package width x package length 2.50 mm x 3.50 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.02 g (LCC-24P-M61) 24-pin plastic QFN (LCC-24P-M61) 2.600.10 (.102.004) 3.500.10 (.138.004) 2.500.10 (.098.004) INDEX AREA 1.600.10 (.063.004) 0.40(.016) TYP 0.02 +0.03 -0.02 (.001 +.001 -.001 ) C 0.150.05 (.006.002) 0.240.05 (.009.002) 1PIN CORNER (C0.50(C.020)) 0.750.05 (.030.002) (0.20(.008)) 2009 FUJITSU MICROELECTRONICS LIMITED C24061S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS04-29138-3E 33 MB88182 MEMO 34 DS04-29138-3E MB88182 MEMO DS04-29138-3E 35 MB88182 FUJITSU MICROELECTRONICS LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-8508, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. 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