MC33882EK - Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

Document Number: MC33882

Rev.9.0, 6/20 1 2

Freescale Semiconductor

Technical Data

Six Output Low Side Switch with

SPI and Parallel Input Control

The 33882 is a smart 6 output low side switch able to control system

loads up to 1.0 A. The six outputs can be controlled via both serial

peripheral interface (SPI) and parallel input control, making the device

attractive for fault tolerant system applications. There are two

additional 30 mA low side switches with SPI diagnostic reporting

(parallel input control only).

The 33882 is designed to interface directly with industry standard

microcontrollers via SPI to contro l both inductive and incandescent

loads. Outputs are configured as open drain power MOSFETs

incorporating internal dynamic clamping and current limiting. The

device has multiple monitoring and protection features, including low

standby current, fault status reporting, internal 52 V clamp on each

output, output specific diagnostics, and protective shutdown.

Additionally, it has a mode select pin affording a dual means of input

control.

Features

• Outputs clamped for switching inductive loads

• Very low operational bias currents (< 2.0 mA)

• CMOS input logic compatible with 5.0 V logic levels

• Robust load dump (60 V transient at VPWR on OUT0 – OUT5)

• Daisy chain operation of multiple devices possible

• Switch outputs can be paralleled for higher currents

•R

DS(ON) of 0.4 Ω per ou tp u t (25 °C) at 13 V VPWR

• SPI operation guaranteed to 2.0 MHz

Figure 1. 33882 Simplified Application Diagram

SIX OUTPUT LOW SIDE SWITCH

VW SUFFIX

(PB-FREE)

98ASH70693A

30-PIN HSOP

33882

ORDERING INFORMATION

Device

(For Tape and

Reel, add an R2

Suffix)

Temperature

Range (TA)Package

MC33882PVW

-40 to 125 °C

30 HSOP

MC33882PEP 32 QFN

MC33882EK 32 SOIC-EP

EP SUFFIX

(PB-FREE)

98ARH99032A

32-PIN QFN

EK SUFFIX

(PB-FREE)

98ARL10543D

32-PIN SOIC

VPWR

VDD

SCLK

IN0

MODE

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT0

IN0 & IN1

IN2 & IN3

IN4 & IN5

GND

33882

VDD VPWR

Optional Parallel

Control of

Outputs 0 through 7

High Power

Outputs

Low Power

LED

Outputs

Optional Control

of Paired Outputs

MCU

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Analog Integrated Circuit Device Data

2Freescale Semiconductor

33882

INTERNAL BLOCK DIAGRAM

Figure 2. 33882 Simplified Internal Block Diagram

-+-+

+ -

(OUT7)

30 (OUT6)

26 (OUT5)

23 (OUT4)

20 (OUT3)

10 (OUT2)

7 (OUT1)

5 (OUT0)

16 (V

)1 (V

PWR

)

12 (SI)

3 (

MODE

)

18 (IN7)

29 (IN6)

24 (IN4)

28 (IN4 & IN5)

(IN3)

27 (IN5)

9 (IN2)

19 (IN2 & IN3)

6 (IN1)

4 (IN0)

2 (IN0 & IN1)

13 (SCLK)

14 (CS)

15 (SO)

Serial Out

Serial In

DDDDDD D D

CCCCCC C C

QQQQQQ Q Q

Tri-state Shift

Enable

SO Fault Latch/Shift Register

Output 0 Status

Output Status

1 through 7

Gate 0

Gate 2

Gate 3

Gate 4

Gate 5

Gate 6

Gate 7

Over-voltage

Shutdown Under-voltage

Shutdown Internal

Bias

Detect

Logic

On Open

Open

Load

OFF/ON

Detect

Load

Short

3.0 A

Detect

REF

LIM

OF (th)

O(OFF)

I40

3.0 V

52 V

OUT6

and OUT7

Unclamped

Low

Power

OUT1

to OUT5

Power

01234567

GND (Heat Sink)

Note Pin numbers shown in this figure are applicable only to the 30-lead HSOP package.

High

Analog Integrated Circuit Device Data

3Freescale Semiconductor

33882

PIN CONNECTIONS

Figure 3. HSOP, QFN, and SOIC Pin Connections

Table 1. HSOP Pin Function Description

30 Pin

HSOP 32 Pin

QFN 32 Pin

SOIC Pin Name Formal Name Definition

1 6 18 VPWR Load Supply Voltage This pin is connected to battery voltage. A decoupling cap is required from

VPWR to ground.

IN0 & IN1

IN2 & IN3

IN4 & IN5

Input 0 & Input 1

Input 2 & Input 3

Input 4 & Input 5

These input pins control two output channels each when the MODE pin is

pulled high. These pins may be connected to pulse width modulated (PWM)

outputs of the control IC while the MODE pin is high. The states of these pins

are ignored during normal operation (MODE pin low), and override the

normal inputs (serial or parallel) when the MODE pin is high. These pins

have internal active 25 μA pull-downs.

3 8 20 MODE Mode Select The MODE pin is connected to the MODE pin of the control IC. This pin has

an internal active 25 μA pull-up.

VPWR

IN0&IN1

MODE

IN0

OUT0

IN1

OUT1

IN2

OUT2

SCLK

OUT6

IN6

IN4&IN5

IN5

OUT5

IN4

OUT4

IN3

OUT3

IN2&IN3

IN7

OUT7

VDD

HEATSINK

GND

TRANSPARENT TOP VIEW

30 PIN HSOP

IN4&IN5

IN6

OUT6

GND

VPWR

IN0&IN1

MODE

IN0

OUT0

IN1

OUT1

IN2

OUT2

SCLK

OUT7

VDD

GND

IN5

OUT5

IN4

OUT4

IN3

OUT3

IN2&IN3

IN7

TRANSPARENT TOP VIEW

32 PIN QFN

HEATSINK

GND

VDD

OUT7

IN7

IN2&IN3

OUT3

IN3

OUT4

IN4

OUT5

IN5

IN4&IN5

IN6

OUT6

GND

SCLK

OUT2

IN2

OUT1

IN1

OUT0

IN0

MODE

IN0&IN1

VPWR

GND

16 17

TRANSPARENT TOP VIEW

32 PIN SOIC

HEATSINK

Analog Integrated Circuit Device Data

4Freescale Semiconductor

33882

PIN CONNECTIONS

IN0

IN1

IN2

IN7

IN3

IN4

IN5

IN6

Input 0 – Input7 These are parallel control input pins. These pins have internal 25 μA active

pull-downs.

OUT0

OUT1

OUT2

OUT7

OUT3

OUT4

OUT5

OUT6

Output 0 – Output7 Each pin is one channel's drain, sinking current for the respective load.

8, 11, 22,

25 2,31 NC No Connect Not connected.

12 15 27 SI Serial Input The Serial Input pin is connected to the SPI Serial Data Output pin of the

control IC from where it receives output command data. This input has an

internal active 25 μA pull-down and requires CMOS logic levels.

13 16 28 SCLK Serial Clock The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It

transitions one time per bit transferred when in operation. It is idle between

command transfers. It is 50% duty cycle, and has CMOS levels.

14 17 29 CS Chip Select This pin is connected to a chip select output of the control IC. This input has

an internal active 25 μA pull-up and requires CM OS logic levels.

15 18 30 SO Serial Output This pin is connected to the SPI Serial Data Input pin of the control IC or to

the SI pin of the next device in a daisy chain. This output will remain tri-

stated unless the device is selected by a low CS pin or the MODE pin goes

low. The output signal generated will have CMOS logic levels and the output

data will transition on the falling edges of SCLK. The serial output data

provides fault information for each output and is returned MSB first when the

device is addressed.

16 23 3VDD Logic Supply Voltage This pin is connected to the 5.0 V power supply of the system. A decoupling

capacitor is required from VDD to ground .

Heat

Sink

(exposed

pad)(1)

4,5,19-

22 1,16,17,

32 GND Ground Ground continuity is required for the outputs to turn on. The heat sink must

be electrically connected to GND.

Notes

1. The exposed pad on this package provides the circuit ground connection for the IC.

Table 1. HSOP Pin Function Description (continued)

30 Pin

HSOP 32 Pin

QFN 32 Pin

SOIC Pin Name Formal Name Definition

Analog Integrated Circuit Device Data

Freescale Semiconductor 5

33882

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Limit

ELECTRICAL RATINGS

Load Supply Voltage

Normal Operation (Steady-state)

Transient Survival (2)

VPWR(SS)

VPWR(T)

-1.5 to 60

Logic Supply Voltage (3) VDD -0.3 to 7.0 V

Input Pin Voltage (4) VIN -0.3 to VDD + 0.3 V

Output Clamp Voltage (OUT0 to OUT5) (5)

20 mA = IO = 0.2 A VO(OFF) 48 to 64 V

Output Self-limit Current

OUT0 to OUT5

OUT6 and OUT7

IO(LIM) 3.0 to 6.0

0.05 to 0.15

ESD Voltage (HSOP, QFN, and SOIC)

Human Body Model (6)

Machine Model (7)

VESD1

VESD2

±2000

±200

Output Clamp Energy (8)

OUT0 to OUT5: Single Pulse at 1.5 A, TJ = 150°C

OUT6 and OUT7: Single Pulse at 0.45 A, TJ = 150°C

ECLAMP 100

Maximum Operating Frequency (SPI) SO (9) fOF 3.2 MHz

THERMAL RATINGS

Storage Temperature TSTG -55 to 150 °C

Operating Junction Temperature TJ-40 to 150 °C

Peak Package Reflow Temperature During Reflow (10), (11) TPPRT Note 11 °C

Notes

2. Transient capability with external 100 Ω resistor in series with the VPWR pin and supply.

3. Exceeding these voltages may cause a malfunction or permanent damage to the device.

4. Exceeding the limits on any parallel inputs or SPI pins may cause permanent damage to the device.

5. With output OFF.

6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).

7. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

8. Maximum output clamp energy capability at indicated junction temperature using a single pulse method.

9. Serial Frequency Specifications assume the IC is driving 8 tri-stated devices (20 pF each).

10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-ST D-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data

6Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

THERMAL RESISTANCE (12), (13)

Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (14)

HSOP

QFN

SOIC

RθJA 41

°C/W

Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (15)

HSOP

QFN

SOIC(17)

RθJMA 18

TBD

°C/W

Junction-to-Board (Bottom)

HSOP

QFN

SOIC(17)

RθJB 3.0

TBD

°C/W

Junction-to-Case (Top) (16)

HSOP

QFN

SOIC

RθJC 0.2

1.2

1.0

°C/W

Notes

12. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

14. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

15. Per JEDEC JESD51-6 with the board horizo n tal.

16. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC

883, Method 1012.1) with the cold plate temperature used for the case temperature.

17. This value will be included when available.

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Limit

Analog Integrated Circuit Device Data

Freescale Semiconductor 7

33882

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise

noted.

Characteristic Symbol Min Typ Max Unit

POWER INPUT

Supply Voltage Ranges

Functional Threshold (18)

Full Operation

Logic Supply Voltage

V PWR

VDD

4.5

8.0

4.5

5.5

–

5.0

8.0

5.5

VPWR Supply Current (All Outputs ON) (19)

IO = 1.0 A Each I PWR (ON) – – 7.5 mA

Over-voltage Shutdown (20) V PWR (OV) 30 –40 V

Over-voltage Shutdown Hysteresis (21) V PWR (OV) HYS 0.4 –1.5 V

Power-ON Reset Threshold, VDD (22) V POR 2.5 –3.5 V

Logic Supply Current (All Outputs ON)

VDD = 5.5 VI DD – – 5.0 mA

POWER OUTPUT

Output Drain-to-Source ON Resistance

OUT0 to OUT5: TJ = 150°C, VPWR = 13.0 V, IO = 1.0 ARDS(ON) –0.6 0.8

Output Drain-to-Source ON Resistance

OUT0 to OUT5: TJ = 25°C, VPWR = 13.0 V, IO = 1.0 ARDS(ON) –0.4 0.6

Output Self-limiting Current

VPWR = 13.0 V, VDD = 4.5 V, VIN = 5.0 VI O (LIM) 3.0 –6.0 A

Open Load OFF Detection (Outputs Programmed OFF) V OFF (TH) 2.5 –3.5 V

Output OFF (Open Load Detect) Drain Current (Output Pins

Programmed OFF) (23)

OUT0 to OUT5

OUT6 and OUT7

I O (OFF)

20 –

–120

μA

Output ON (Open Load Detect) Drain Current (Output Pins Programmed

ON) (24) –20 –200 mA

Output Clamp Voltage

OUT0 to OUT5: IO = 20 mA, tCLAMP = 100 μsV OK 48 52 64 V

Output Leakage Current

VDD = VPWR = 0.5 V, VOUT = 24 VI OLK –1.0 10

μA

Drain-to-Source Diode Forward Voltage

ISD = 1.0 mA @ 25 °C

ISD = 1.0 mA @ 125 °C

V SD –

––

–1.4

0.9

Analog Integrated Circuit Device Data

8Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

DIGITAL INTERFACE

SI Logic High SIV IH 4.0 – – V

SI Logic Low SIV IL – – 2.0 V

CS and SCLK Logic High CSV IH 3.0 – – V

CS and SCLK Logic Low CSV IL – – 3.0 V

Input Logic High V IH 3.15 – – V

Input Logic Low V IL – – 1.35 V

Input Pull-down Current (25)

VIN = 1.5 VI IN (PD) 5.0 –25

μA

Input Pull-up Current (26)

VIN = 3.5 VI IN (PU) -25 –-5.0

μA

SO and High-state Output Voltage

IOH = -1.0 mA V SOH 3.5 – – V

SO and Low-state Output Voltage

IOL = 1.0 mA V SOL 0 – 0.4 V

SO and Tri-state Leakage Current

CS = 0.7 VDD, VSO = 0.3 VDD

CS = 0.7 VDD, VSO = 0.7 VDD

I SOT -10

––

μA

Input Capacitance (27)

0 = VIN = 5.5 VC IN – – 12 pF

SO and Tri-state Capacitance (28)

0 = VIN = 5.5 VC SOT – – 20 pF

Notes

18. Outputs of device functionally turn-on (RDS(ON) = 0.95 Ω @125 °C). SPI / parallel inputs and power outputs are operational. Fault

detection and reporting may not be fully operational within this range.

19. Value reflects all outputs ON and equally conducting 1.0 A each. VPWR = 5.5 V, CS = 5.0 V.

20. An over-voltage condition will cause any enabled outputs to latch OFF (disabled).

21. This parameter is guaranteed by design; however, it is not production tested.

22. For VDD less than the Power-ON Reset voltage, all outputs are disabled and the serial fault register is reset to all 0s.

23. Drain current per output with VPWR = 24 V and VLOAD = 9.0 V.

24. Drain current per output with VPWR = 13 V, VLOAD = 9.0 V.

25. Inputs SI, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7 incorporate active internal pull-down current sinks for noise immunity

enhancement.

26. The MODE and CS inputs incorporate active internal pull-up current sources for noise immunity en hancement.

27. This parameter applies to inputs SI, CS, SCLK, MODE, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7. It is guaranteed by design;

however, it is not production tested.

28. This parameter applies to the OFF state (tri-stated) condition of SO and is guaranteed by design; however, it is not production t ested.

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise

noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 9

33882

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125°C, unless otherwise

noted.

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING

Output Rise Time (29) t R1.0 –10 μs

Output Fall Time (29) tF1.0 –10 μs

Output Turn-ON Delay Time (30) t DLY (ON) 1.0 –10 μs

Output Turn-OFF Delay Time (31) t DLY (OFF) 1.0 –10 μs

Output Short Fault Sense Time (32)

RLOAD = < 1.0 V t SS 25 –100

μs

Output Short Fault Refresh Time (33)

RLOAD = < 1.0 Vt REF 3.0 4.5 6.0 ms

Output OFF Open Load Sense Time (34) t OS(OFF) 25 60 100 μs

Output ON Open Load Sense Time (35) t OS(ON) 3.0 –12 ms

Output Short Fault ON Duty Cycle (36) SC DC 0.42 –3.22 %

DIGITAL INTERFACE TIMING

SCLK Clock High Time (SCLK = 3.2 MHz) (37) t SCLKH – – 141 ns

SCLK Clock Low Time (SCLK = 3.2 MHz) (37) t SCLKL – – 141 ns

Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK

Required Setup Time (37) t LEAD – – 140 ns

Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS

Required Setup Time (37) t LAG – – 50 ns

SI, CS, SCLK Incoming Signal Rise Time (37) t RSI – – 50 ns

SI, CS, SCLK Incoming Signal Fall Time (37) t FSI – – 50 ns

Notes

29. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 Ω resistive load to a VBAT

of 15 V, VPWR = 15 V.

30. Output Turn-ON Delay Time measured from rising edge (3.0 V) VIN (CS for serial) to 90% VO using a 15 Ω load to a VBAT of 15 V,

VPWR = 15 V.

31. Output Turn-OFF Delay Time measured from falling edge (1.0 V) VIN (3.0 V rising edge of CS for serial) to 10% VO using a 15 Ω load

to a VBAT of 15 V, VPWR = 15 V.

32. The shorted output is turned ON during tSS to retry and check if the short has cleared. The shorted output is in current limit during tSS.

The tSS is measured from the start of current limit to the end of current limit.

33. The Short Fault Refresh Time is the waiting period between tSS retry signals. The shorted output is disabled during this refresh time.

The tREF is measured from the end of current limit to the start of cur rent limit.

34. The tOS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault

register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 μs after the faulted output is off.

35. The tOS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault

register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.

36. Percent Output Short Fault ON Duty Cycle is defined as (tSS) ÷ (tREF) x 100. This specification item is provided FYI and is not tested.

37. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

SI Setup to Rising Edge (2.0 V) of SCLK (at 3.2 MHz)

Required Setup Time (38) t SISU – – 45 ns

SO Setup to SCLK Rising (2.0 V) / Falling (0.8 V) Edge

Required Setup Time (38) t SOSU 90 – – ns

SI Hold After Rising Edge (2.0 V) of SCLK (at 3.2 MHz)

Required Hold Time (38) t SIHOLD – – 45 ns

SO Hold After SCLK Rising (2.0 V) / Falling (0.8 V) Edge

Required Hold Time (38) t SOHOLD 90 – – ns

SO Rise Time

CL = 200 pF t RSO – – 50 ns

SO Fall Time

CL = 200 pF t FSO ––50 ns

Falling Edge of CS (0.8 V) to SO Low-impedance (39) t SOEN – – 110 ns

Rising Edge of CS (2.0 V) to SO High-impedance (40) t SODIS – – 110 ns

Falling Edge of SCLK (0.8 V) to SO Data Valid

CL = 200 pF at 3.2 MHz (41)

t SOVALID –65 80 ns

CS Rising Edge to Next Falling Edge (38) Xfer DELAY – – 1.0 μs

Notes

38. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.

39. Enable time required for SO. Pull-up resistor = 10 kΩ.

40. Disable time required for SO. Pull-up resistor = 10 kΩ.

41. Time required to obtain valid data out of SO following the falling edge of SCLK.

Table 4. Dynamic Electrical Characteris tics (continued)

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40 °C ≤ TA ≤ 125°C, unless otherwise

noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 11

33882

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 4. Short Occurri ng While On, Ending During Refresh (ILOAD = 1.0 A)

GATE X = COM MAND SIGNAL AT THE GATE OF DRIVER X

FA U L T B IT X = IN T E R N A L F A U L T R E G IS T E R B IT S T A T E

TREF x = FIRST REFRESH TIM E MAY BE LESS THAN TREF

ILO A D = 1A

NORM AL OPERATIO N

IN P UT X

GATE X

OUT X

FAULT BIT X FAULT FAULT

ILOAD

0A TREFTREFTREF

TREF

IDLIM TSSA

OFF

SH O RT E D LOA D / S H OR T - TO - V B A T

SHORT OCCURS WHILE ON, ENDS DURING REFRESH

NPUT X

GATE X

OUT X

FAULT BIT X

IDLIM

ILOAD

OFF

CSB

TSSD TSSD

Input X

Gate X

OUT

5.0 V

0 V

OFF

ILOAD

0 A

IO(LIM)

Fault Bit X

Shorted Load/Short-to-VPWR

tREF tREF

tSSD tSSA tSSD

tREF tREF

Fault

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

OFF

Gate X = Command Signal at the Gate of Driver X

Fault Bi t X = Internal Fault Register Bit State

tREF X = First R efresh T i me may be le ss than t REF

ILOAD = 1.0 A

Normal

Operation

Shorted

Operation

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 5. Short Occurring While On, Ending During Retry (ILOAD = 1.0 A)

Figure 6. Short Occurring While On, Ending During Refresh (ILOAD = 20 mA)

GATE X = COMMAND SIGNAL AT THE GATE OF DRIVER X

FAULT BIT X = INTERNAL FAULT REGISTER BIT STATE

TREF x = FIRST REFRESH TIME MA Y BE LESS THA N TREF

ILO AD = 1 A

NORMAL OPERATION

IN P UT X

GATE X

IO UT X

FAULT BIT X FAULT FAULT

ILOAD

0A TREFTREFTREF

TREF

IDLIM TSSA

OFF

SHORTED LOAD / SHORT - TO - VBAT

SHORT OCCURS WHILE ON, ENDS DURING RETRY

IN P UT X

GATE X

IO U T X

FAULT BIT X

IDLIM

ILOAD

OFF

CSB

TSSD TSSD

Gate X = Command Signal at the Gate of Driver X

Fault Bit X = Internal Fault Register Bit State

tREF X = First Refresh Time may be les s than tREF

ILOAD = 1.0 A

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

OFF

Shorted Load/Short-to-VPWR

tSSD

tREF

tSSD

tSSA

tREF

Fault

Shorted

Operation

Normal

Operation

OFF

GATE X = COMMAND SIGNAL AT THE GATE OF DRIVER X

FAULT BIT X = INTERNAL FAULT R EGISTER B IT STATE

TREF x = FIRST REFRESH TIM E MAY BE LESS THAN TREF

ILOA D = 2 0mA

NORMAL OPERATION

IN P U T X

GATE X

IO U T X

FAULT BIT X FAULT FAULT

ILOAD

0A TREFTREFTREF

TREF

IDLIM TSSD

OFF

S H O R T E D L O A D / S H O R T - T O - VB A T

S HO RT OC CU R S WHILE O N, E N DS DURIN G R E FRE S H

IN P UT X

GATE X

IOUT X

FAULT BIT X

IDLIM

ILOAD

OFF

CSB

TSSA

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

OFF

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

OFF

Shorted Load/Short-to-VPWR

Gate X = Command Signal at the Gate of Driver X

Fault Bit X = Internal Fault Register Bit State

tREF X = First Refresh Time may be less than tREF

ILOAD = 20 mA

Fault Fault

tREF

tREF tREF tREF

tSSA tSSD

Normal

Operation

Shorted

Operation

Analog Integrated Circuit Device Data

Freescale Semiconductor 13

33882

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

Figure 7. Short Occurring While On, Ending During Retry (ILOAD = 20 mA)

GATE X = COMMAND SIGNAL AT THE GATE OF DRIVER X

FAULT BIT X = INTERNAL FAULT REGISTER BIT STATE

TREF x = FIRST REFRESH TIME MAY BE LESS THAN TREF

ILOA D = 20m A

NORMAL OPERATIO N

IN P UT X

GATE X

IO UT X

FAULT BIT X FAULT FAULT

ILOAD

0A TREFTREFTREF

TREF

IDLIM TSSD

OFF

SHORTED LOAD / SHORT - TO - VBAT

SHORT OCCURS W HILE O N, ENDS DURING RETRY

IN P UT X

GATE X

IO UT X

FAULT BIT X

IDLIM

ILOAD

OFF

CSB

TSSD

TSSA

Gate X = Command Signal at the Gate of Driver X

Fault Bit X = Internal Fault Register Bit State

tREF X = First Refresh Time may b e les s tha n tREF

ILOAD = 20 mA

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

OFF

Input X

Gate X

OUT

5.0 V

0 V

ILOAD

0 A

IO(LIM)

Fault Bit X

OFF

Fault Fault

tREF

tSSA tSSD tSSD

Shorted Load/Short-to-VPWR

Shorted

Operation

Normal

Operation

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

33882

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

Figure 8. Output RDS(ON) Versus Temperature Figure 9. Output Clamp Voltage Versus Temperature

0.37

0.38

AMBIENT TEMPERATURE (°C)

OHMS

55 70 11540 85 100 130

0.39

0.4

0.41

0.42

0.36

0.35

0.43

DS(ON)

AMBIENT TEMPERATURE (

VOLTS

-50 0 25 100-25 50 75 125

53.8

54.0

54.2

54.4

54.6

54.8

53.6

53.4

55.0 V

CLAMP

Table 5. Logi c Ta ble

Mode of Operation Command

Sent

Status

Transmitted

Status

Transmitted

Next SO Mode Pin IN0&IN1 IN4&IN5 Input Pins

5 4 3 2 1 0 Gates

5 4 3 2 1 0 Outputs

5 4 3 2 1 0

Normal Operation 00111111

001X1010

000101X1

00XXX000

00000000

00111111

001Y1010

000101Y1

00YYY000

X X X X X X

X H X L X L

L X L X H X

H H H L L L

H H H H H H

H H H L H L

L H L H H H

H H H L L L

L L L L L L

L L L H L H

H L H L L L

L L L H H H

Default Mode 00XXXXXX

00XXXXXX

11111111

X X H L X X

X X L H X X

X X H L X X

X X L H X X

H H H L H H

H H L H L L

L L H L H H

L L L H L L

L L H L H H

H H L H L L

H H H L H H

Over-voltage Shutdown 00XXXXXX 00XXXXXX 00XXXXXX X X X X X X X X X L L L L L L H H H H H H

Short-to-Battery /

Short-circuit Output 0 00XXXXX0

00XXXXX1 00000000

00000001 00YYYYY0

00YYYYY0 L

XX X X X X L

X X X X X X Y Y Y Y Y L

Y Y Y Y Y H Y Y Y Y Y H

Y Y Y Y Y H

Open Load /

Short-to-Ground Output 0 00XXXXX0

00XXXXX1 00000001

00000000 00YYYYY1

00YYYYY1 L

XX X X X X L

X X X X X X Y Y Y Y Y L

Y Y Y Y Y H Y Y Y Y Y L

Y Y Y Y Y L

Legend

0011XXYY = Serial (SPI) commands and status bytes (8-bit operation mode) MSB to LSB.

0 = Off command, SO OK status.

1 = On command, SO FAULT status.

X = Don’t care.

Y = Defined by state of X.

H = High-voltage level: Active state for inputs / gates, inactive state for outputs.

L = Low-voltage level: Inactive state for inputs / gates, active state for outputs.

Analog Integrated Circuit Device Data

Freescale Semiconductor 15

33882

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33882 incorporates six 1.0 A low side switches using

both Serial Peripheral Interface (SPI) I /O as well as o pti ona l

parallel input control to each output. There are also two low-

power (30 mA) low side switches with SPI diagnostic

feedback, but parallel-only inp ut control . T he 33882

incorporates SMARTMOS technology with CMOS logic,

bipolar / MOS analog circuitry, and DMOS power MOSFETs.

Designed to interface directly with a microcontrol ler, it

controls inductive or incandescent loads. Each output is

configured as an open drain transisto r wi th dynamic

clamping.

FUNCTIONAL PIN DESCRIPTION

VPWR PIN

The VPWR pin is connected to battery voltage. This supply

is provided for over-voltage shutdown protection and for

added gate drive capabilities. A decoupl ing capacitor is

required from VPWR to ground.

IN0 & IN1, IN2 & IN3, AND IN4 & IN5 PINS

These input pins control two output channels each when

the MODE pin is pulled high: IN0 & IN1 controls OUT0 and

OUT1, IN2 & IN3 controls OUT2 and OUT3, while IN4 & IN5

controls OUT4 and OUT5. These pins may be connected to

PWM outputs of the control IC and pulled high or pulled low

to control output channel states while the MODE pin is high.

The states of these pins are ignored during normal operation

(MODE pin low) and override the normal inputs (serial or

parallel) when the MODE pin is high. These pins have internal

active 25 μA pull-downs.

MODE PIN

The MODE pin is connected to the MODE pin of the control

IC. This pin has an internal active 25 μA pull-up. When pulled

high, the MODE pin does the following:

• Disables all serial control of the outputs while still reading

any serial input commands.

• Disables parallel inputs IN0, IN1, IN2, IN3, IN4, and IN5

control of the outputs.

• Selects IN0 & IN1, IN2 & IN3, and IN4 & IN5 input pins for

control of OUT0 and OUT1, OUT2 and OUT3, OUT4 and

OUT5, respectively.

• Turns off OUT6 and OUT7.

• Tri-states the SO pin.

IN0 TO IN7 PINS

These are parallel input pins connected to output pins of

the control IC. Each parallel input is logic high with the

corresponding SPI control bit to control each output channel.

These pins have internal 25 μA active pull-downs.

OUT0 TO OUT7 PINS

Each pin is one channel's low side switch output. OUT0 to

OUT5 are actively clamped to handle inductive loads.

SI PIN

The Serial Input pin is connected to the SPI Serial Data

Output pin of the control IC from where it receives output

command data. This input ha s an internal active 25 μA pull-

down and requires CMOS logic levels. The serial data

transmitted on this line is an 8- or 16-bit control command

sent MSB first, controlling the six output channels. Bits A5

through A0 control channels 5 through 0, respectively. Bits

A6 and A7 enable ON open load fault detection on channels

5 through 0. The control IC will ensure that data is available

on the rising edge of SCLK. Each channel has its serial

control bit high with its parallel input to determine its state.

SCLK PIN

The SCLK pin of the control IC is a bit (shift) clock for the

SPI port. It transitions one time per bit transferred when in

operation. It is idle between command transfers. It is 50%

duty cycle and has CMOS levels. This signal is used to shift

data to and from the device. For proper fault reporting

operation, the SCLK input must be low when CS transitions

from high to low.

CS PIN

The CS pin is connected to a chip select output of the

control IC. The control IC controls which device is addressed

by pulling the CS pin of the desired device low, enabling the

SPI communication with the device, while other devices on

the serial link keep their serial outputs tri-stated. This input

has an internal active 25 μA pull-up and requires CMOS logic

levels.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

33882

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

SO PIN

The Serial Output pin is connected to the SPI Serial Data

Input pin of the control IC or to the SI pin of the next device in

a daisy chain. This output will re main tri-stated unless the

device is selected by a low CS pin or the MODE pin goes low.

The output signal generated will have CMOS logic levels and

the output data will transition on the falling edges of SCLK.

The serial output da ta provides fault information for each

output and is returned MSB first when the device is

addressed. Fault bit assignments for return data are as

follows: MSB-0 through MSB-7 are output fault bits for OUT7

to OUT0, respectively. In 8-bit SPI mode, under normal

conditions, the SO pin (not daisy chained) returns all 0s,

representing no faults. If a fault is present, a 1 is returned for

the appropriate bit. In 16-bit SPI mode, sending a double

command byte will provide a command verification byte

following the fault status byte returned from the SO pin (non-

daisy chained). With the MODE pin high, the serial output pin

tri-states. If nothing is connected to the SO pin except an

external 10 kΩ pull-up resistor, data is read as all [1]s by the

control IC.

VDD PIN

This pin is connected to the 5.0 V power supply of the

system. A decoupling capacitor is required from VDD to

ground.

PERFORMANCE FEATURES

NORMAL OPERATION

OUT0 to OUT7 are independent during normal operation.

OUT0 to OUT5 may be driven serially or by their parallel input

pins. OUT6 and OUT7 can only be controlled by their parallel

input pins. Device operation is considered normal only if the

following conditions apply:

•V

PWR of 5.5 V to 24 V, and VDD voltage of 4.75 V to 5.25 V.

• Junction temperatures less than 150 °C.

• For each output, drain voltage exceeds the Open Load

OFF Detection Voltage, specified in the specification table,

while the output is OFF. For open load detection, an open

condition existing for less than the Open Loa d Detection

time, specified in the specification table, is not considered

a fault nor is it reported to the fault status register.

•The MODE pin is held at the logic low level, keeping the

serial channel / parallel input pins in control of the eight

outputs.

SERIAL / PARALLEL INPUT CONTROL

Input control is accomplished by th e serial control byte

sent via the SPI port from the control IC or by the parallel

control pins for each channel. For channels 0 to 5 with serial

and paralle l control the outp ut state is determ ined by the OR

of the serial bit and the parallel input pin state. Serial

communication is initiated by a low state on the CS pin and

timed by the SCLK signal . After CS switches low, the IC

initiates eight or 16 clock pulses with the control bi ts being

available on the SI pin at th e rising edge of SCLK.

The bits are transferred in descending bit-significant

order. Any fault or MODE indications on bits returned are logic

[1]s. The last six bits are the command signals to the six

outputs. Upon completion of the serial communication the CS

pin will switch high. This terminates the communication with

the slave device and loads the control bits just received to the

output channels. Upon device power-up, the serial register is

cleared.

In the appl ication for no n -daisy chain configurations, the

number of SPI devices available to be driven by the SO pin is

limited to eight devices.

SERIAL STATUS OUTPUT

Serial output information sent on the SPI port is a check on

the fault status of each output channel as well as a check for

MODE initiation. Serial command verification is also possible.

SO PIN OPERATION

The SO pin provides SPI status, allowing daisy chaining.

The status bits returned to the IC are the fault register bits

with logic [1]s indicating a fault on the designated output or

MODE if all bits return logic [1] (with a 10 kΩ pu l l -up resi stor

on the SO pin). A command verification is possible if the SPI

mode is switched to 16 bits. The first byte (8 bits) returned

would be the fault status, while the second byte returned

would be the first byte sent feeding through the 33882 IC.

The second command byte sent would be latched into the

33882 IC. The CS pin switching low indicates the device is

selected for serial communication with the IC. Once CS

switches low, the fault status register cannot receive new

fault information and serial communication begins. As the

control bits are clocked from the IC MSB first, they are

received on rising SCLK edges at the SI pin.

The fault status bits transition on the SO pin on falling

SCLK edges and are sampled on rising SCLK edges at the

input pin of the IC SPI device. When the command bit

transmissions for serial communication are complete, the CS

pin is switched high. This terminates communication with the

device. The SO pin tri-states, the fault status register is

opened to accept new fault information, and the transmitted

command data is loaded to the outputs. At the same time, the

IC can read the status byte it received.

DAISY CHAIN OPERATION (ONLY POSSIBLE WITH

SO PIN)

Daisy chain configurations can be used with the SO pin to

save CS outputs on the IC. Clocking and pin operations are

as defined in the SO Pin Operation paragraph. For daisy

chaining two 8-bit devices, a 16-bit SPI command is sent, the

first command byte for the second daisy chain device and the

second command byte for the first daisy chain device. A

command verification is possible if the SPI mode is switched

Analog Integrated Circuit Device Data

Freescale Semiconductor 17

33882

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

to 32 bits. The first word sent is command verification data

fed through the two 33882 ICs. Data returned in the 32 bits is

the two fault status bytes, followed by the first word sent. Bits

sent out are sampled on rising SCLK edges at the input pin

of the next IC in the da i sy cha i n.

Note Because SO pins of the 33882 ICs are tri-stated,

any device receiving its SPI data from a previous 33882 IC

SO pin in a daisy chain will not receive data if the MODE pin

is low. This prohibits setting SPI-controlled channels ON with

a SPI command while the MODE pin is low. Therefore, all

channels remain OFF when the MODE pin changes from low

to high at vehicle power-up.

MODE OPERATION

During normal operation output channels are controlled by

either the Serial Input control bits or the parallel input pins. If

the MODE pin is pulled high:

• Serial input control is disabled.

• Parallel input pins IN0 to IN5 are ignored.

• The SO pin is tri-stated.

OUT0 and OUT1, OUT2 and OUT3, and OUT4 and OUT5

are controlled by the IN0 & IN1, IN2 & IN3, and IN4 & IN5

pins, respectively. When a 10 kΩ pull-up resi st or i s use d, a

logic high o n th e MODE pin or an open serial output pin is

flagged by the SPI when all bits are returned as logic [1]s.

Although a logic high on the MODE pin disables serial

control of outputs, data can still be clocked into the serial

input register. This allows programming of a desired state for

the output s taking effect only when the MODE pin returns to a

logic low. For applications using the SO pin, daisy chaining is

permitted, but if the MODE pin is high, writing to other than the

first IC in a daisy chain is not possible because the serial

outputs are tri-stated.

OUTPUT DRIVERS

The high power OUT0 to OUT5 outputs are active

clamped, low side switches driving 1.0 A typical or less loads.

The low-power OUT6 and OUT7 outputs are unclamped low-

side switches driving 30 mA typical or less loads. All outputs

are individually protected from short circuit or short-to-battery

conditions and transient voltages. The outputs are also

protected by short-circuit device shutdown. Each output

individually detects and reports ope n load /short-to-ground

and short-circuit /short-to-battery faults.

FAULT SENSE / PROTECTION CIRCUITRY

Each output channel individuall y detects shorted loads /

short-to-battery while the output is ON and open load /short-

to-ground while the output is OFF. OUT0 to OUT5 may also

be programmed via SPI bits 6 and 7 to detect open loads and

shorts-to-ground while the output is ON. Whenever a short or

open fault condition is present on a particular output channel,

its fault bit in the internal fault register indicates the fault with

a logic [1].

When a fault ends, its fault bit remains set until the SPI

normal condition. When the CS pin is pulled low for serial

communication, the fault bits in the internal fault register

latch, preventing erroneous status transmissions and the

forthcoming communication reports this latched fault status.

The SO pin serial output data for 8-bit SPI mode are the fault

status register bi ts.

For 16-bit SPI mode and SO pin (non-daisy chained) use,

a transmitted double command provides the fault byte

followed by the first byte of the double command, becoming

a command verification. The status is sent back to the IC for

fault monitoring. Diagnostic interpretation of the followi ng

fault types can be accomplished using the procedure

described in the paragraph entitled Extensive Fault

Diagnostics:

• Communication error

• Open load /short-to-ground

• Short-to-battery or short-circuit

When serial communication is end ed, the CS pin returns

high, opening the fault status register to new fault information

and tri-stating the SO pin.

Two fault conditions initiate protective action by the device:

• A short-circuit or short-to-battery on a particular output will

cause that output to go into a low duty cycle operation until

the fault condition is removed or the input to that channel

turns OFF.

• A short-circuit condition causes all channels to shut down,

ignoring serial and parallel inputs to the device .

To be detected and reported as a fault, a fault cond ition

must last a specified time (fault sense time or fault mask

time). This prevents any normal switching transie nts from

causing inadvertent fault status indications.

Fault status information should be ignored for VBAT levels

outside the 9.0 V to 17 V range. The fault reporting may

appear to function properly but may not be 100 percent

reliable.

SHORT-CIRCUIT /SHORT-TO-BATTERY SENSING

AND PROTECTION

When an output is turned ON, if the drain current limit is

reached, the current remains at the limit until the short-circuit

sense time, tSS, has elapsed. At this time, the affected output

will shut down and its fault status bit switches to a logic [1].

The output goes into a low duty cycle operation as long as the

short-circuit condition exists and the input to th at channel is

ON.

This duty cycle is defined by the sense and refresh times.

If a short occurs after the output is ON, the fault sense time

indicates the fault and enters the low du ty cycle mode at

much less than t SS. The duty cycle is low enough to keep the

driver from exceeding its thermal capabilities. When the short

is removed, the driver resumes normal operation at the next

retry, but the fault status bit does not return to a normal

logic [0] state until it is read from the SPI. When the CS pin of

this device is pulled low, the fault status bits are latched, after

which any new fault information is not a part of this serial

communication even t.

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

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FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

The low duty cycle operation for a short-circuit condition is

required to protect the output. It is possible to override th is

duty cycle if the input signal (parallel or SPI) turns the channel

ON and OFF faster than 10 kH z. For this reason control

signals should not exce ed this frequency.

OPEN LOAD / SHORT-TO-GROUND WHILE OFF

SENSING

If the drain voltage falls bel ow the Open Load OFF

Detection Voltage at turn OFF for a period of time exceeding

the Open Load Sense Time, the fault status bit for this output

switches to a logic [1].

If a drain voltage falls below the Open Load OFF Detection

Voltage threshold when the output has been OFF, a fault is

indicated with a delay much less than the Open Load Sense

Time. When the fault is removed, normal operation resumes

and the fault status bit wil l return to a normal logic [0] state.

When the CS pin of this device is pulled low , the fa ult status

bits are latched, after which any new fault information is not

part of this serial communication event.

OVER-VOLTAGE SENSING AND PROTECTION

When VPWR exceeds the Over-voltage Shutdown

Threshold, all channels are shut down. Serial input data and

parallel inputs are ignored. The device resumes normal

operation when the VPWR voltage drops below the Over-

voltage Shutdown Hysteresis voltage. During over-voltage

shutdown, some faults may appear to report accurately;

however, fault sensing operation is only guaranteed for

battery voltage levels from 9.0 V to 17 V.

FAULT STATUS MONITORING REQUIREMENTS

FOR SERIALLY CONTROLLED OUTPUTS, SO PIN

Fault monitoring over the serial channel by the IC requires

a minimal amount of overhead for normal operation. Each

status byte received consists of all logic [0]s when faults are

not present. If any logic [1]s are returned, a communication

error occurred, an output fault occurred, or the MODE pin has

been set low. Upon receivin g any logic [1] bits, the IC must

resend the last command, verifying the returned logic [1]s, or

correct any communication error.

A 16-bit SPI transmission with a double command byte to

this 8-bit device allows verification of the command (second

byte returned) in addition to the fault byte (first byte returned).

The command (second) byte returned should mirror the bits

sent unless a communication error occurred, in which case

the command resent should accomplish the correction.

If the returned logic [1] validates, it may indicate a MODE

pin high or a confirmed output fault. If it was a confirmed

output fault, extensive diagnostics could be performed,

determining the fault type, especially if vehicle service is

being performed. If all bits return high and verify such, the IC

must verify sending a logic low to the MODE pin. It should

then resend the command, verifyin g the MODE pin is at a

logic low level, allowing resumption of a normal operation . If

all logic [1]s are again returned, there is an open SO line, an

open MODE line, or the SPI is not functioning.

If the fault does not verify on the command resend, normal

operation is resumed. The error could be a communication

mistake, a momentary output fault, or a fault condition no

longer sensed due to switching the state of the output. For the

first two cases, normal operation is resumed and the software

continues its normal functions. However in the third case,

additional commands are required for extensive diagnosis of

the fault type, if this information is mandatory.

EXTENSIVE FAULT DIAGNOSTICS

More extensive diagnosis may be required under the

following conditions:

• When the fault type of a confirmed fault is desired, the

following scenarios are possible:

– If MSB-2 to MSB-7 indicates a fault, it is an open

load / short-to-ground fault if the output is OFF when

the fault is reported because only open load / short-

to-ground sensing remains operable while an output

is OFF.

– If the output is ON when the fault is reported, the

fault is a short-circuit /short-to-battery if ON open

load detection is not enabled via SPI. If ON open

load detection is enab led, it must be disabled and

the fault status reread. If the fault remains, it is a

short-circuit / short-to-battery or it is an open load /

short-to-ground.

– If MSB-0 to MSB-2 indicates a fault, it is an open

load / short-to-ground fault if the output is OFF when

the fault is reported because only open load /short-

to-ground sensing remains operable while an output

is OFF.

– If the output is ON when the fault is reported, the

fault is a short-circuit /short-to-battery.

• When a fault did not confirm on resend, the fault could

either be an short-circuit /short-to-battery fault, not sensed

when turned OFF; an open load /short-to-ground fault, not

sensed when turned ON; or a corrected communication

error.

To determine if it is an output fault condition, the faulted

output must be turned back to its previous state with a new

command. This command should be sent twice to read the

status after the output is latched in this state, thus

confirming the fault and reporting it again.

Parallel control of outputs is a mode of control, potentially

requiring extensive diagnostics if a faul t is reported. This is

because parallel control signals are completely

asynchronous to the se rial commands. Status reports for

parallel controlled outputs could require additional

information exchange in software to:

• Avoid status reads when outputs are transitioned, thereby

avoiding fault masking times.

• Obtain the state of a faulted outp ut for determining fault

type (if required).

Analog Integrated Circuit Device Data

Freescale Semiconductor 19

33882

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

SYSTEM ACTUATOR ELECTRICAL

CHARACTERISTICS (AT ROOM TEMPERATURE)

All drains should have a 0.01 μF filter capacitor connected

to ground. Any unused output pin should not be energized. A

20 Ω resistor to the battery is required to prevent false open

load reporting. There must al so be a maximum of 100 Ω of

resistance from VPWR to ground, keeping battery-powered

loads OFF when the IC is powered down. However, all loads

should be powered by VPWR to protect the device from full

transient voltages on the battery voltage.

POWER-UP

The device is insensitive to power sequencing fo r VPWR

and VDD, as well as intolerant to latch-up on all I /O pins.

Upon power-up, an internal power-ON reset clears the serial

registers, allowing all outputs to power up in the off-state

when parallel control pins are also low. Althou gh the serial

initialize the outputs with an SPI command prior to changing

the MODE pin from a high to a low state. This assures known

output states when MODE is low.

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

33882

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. Dimensions

shown are provided for reference ONLY.

VW SUFFIX

30-PIN HSOP

98ASH70693A

ISSUE A

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

VW SUFFIX

30-PIN HSOP

98ASH70693A

ISSUE A

Analog Integrated Circuit Device Data

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33882

PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

VW SUFFIX

30-PIN HSOP

98ASH70693A

ISSUE A

Analog Integrated Circuit Device Data

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33882

PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EP SUFFIX (PB-FREE)

32-PIN QFN

98ARH99032A

ISSUE E

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EP SUFFIX (PB-FREE)

32-PIN QFN

98ARH99032A

ISSUE E

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EP SUFFIX (PB-FREE)

32-PIN QFN

98ARH99032A

ISSUE E

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EP SUFFIX (PB-FREE)

32-PIN QFN

98ARH99032A

ISSUE E

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EK SUFFIX (PB-FREE)

32-PIN SOIC-EP

98ARL10543D

ISSUE D

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EK SUFFIX (PB-FREE)

32-PIN SOIC-EP

98ARL10543D

ISSUE D

Analog Integrated Circuit Device Data

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PACKAGING

PACKAGE DIMENSIONS (CONTINUED)

EK SUFFIX (PB-FREE)

32-PIN SOIC-EP

98ARL10543D

ISSUE D

Analog Integrated Circuit Device Data

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REVISION HISTORY

PACKAGE DIMENSIONS (CONTINUED)

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

3.0 9/2005 • Implemented Revision History page

• Added Thermal Addendum

• Converted to Freescale format

4.0 5/2006 • Updated ordering information block on page 1

5.0 10/2006 • Updated data sheet format

• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter

from Maximum Ratings on page 5. Added note with instructions to obtain this information

from www.freescale.com.

6.0 6/2009 • Changed Supply Volta ge in Static Electrical Characteristics, Table 4, on page 9

7.0 3/2011 • New Fab transfer devices added. No electrica l parameter changes.

• Removed Part Numbers MC33882FC/R2, MC33882EK/R2, MC33882VW, and

MC33882EP, and replaced with part numbers MC33882PVW, MC33882PEP.

• Added EK package to the ordering information and supp orting data

• Removed all DH suffix information.

• Corrected HSOP 98A reference numb er and associated information

• Update the Packaging section 98A drawings

8.0 5/2012 •In 33882 Simplified Application Diagram on page 1, added OUT2, changed the direction

of arrow for the SI pin and connected the SO pin to MCU

•In Table 3, Static Electrical Characteristics on page 7, changed VDD Supply Current (All

Outputs ON) to VPWR Supply Current (All Outputs ON)

• Updated Freescale form and style

9.0 6/2012 • Updated part number PC33882EK to MC33882EK in the Ordering Information Table.

Document Number: MC33882

Rev.9.0

6/2012

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