▼= New type
Type Ordering Code Package
▼TDA 4862 Q67000-A8368-A205 P-DIP-8-1
▼TDA 4862 G Q67006-A8369-A703 P-DSO-8-1
Power-Factor Controller (PFC) TDA 4862
IC for High Power Factor
and Active Harmonic Filter
Advanced Information Bipolar IC
P-DIP-8-1
P-DSO-8-1
Features
• IC for sinusoidal line-current consumption
• Power factor approaching 1
• Controls boost converter as an active
harmonics filter
• Internal start-up with low current consumption
• Zero current detector for discontinuous
operation mode
• High current totem pole gate driver
• Trimmed ±1.4% internal reference
• Undervoltage lock-out with hysteresis
• Very low start-up current consumption
• Pin compatible to world standard
• Fast overvoltage regulator
• Current sense input with internal low pass filter
Semiconductor Group 1 1998-02-16
TDA 4862
Semiconductor Group 2 1998-02-16
Description
The TDA 4862 is excellent convenient for designing a preconverter in ballasts and
switched mode power supplies with sinusoidal line current consumption and a power
factor approaching unity.
The TDA 4862 controls a boost converter as an active harmonics filter in a discontinuous
mode (free oscillating triangular shaped current mode).
The TDA 4862 comprises an internal start-up timer, a high gain voltage amplifier, an one
quadrant multiplier for approaching unity power factor, a zero current detector, PWM and
logic circuitry, and totem pole MOSFET gate driver.
Protective features are: input undervoltage lockout with hysteresis, VCC zener clamp,
cycle-by-cycle current limiting, output voltage limiting for fast and slow load changes up
to open circuit, and a sinking gate driver current activated whenever undervoltage mode
occurs.
The output voltage of this preconverter is regulated with high accuracy. Therefore the
device can be used for world-wide line voltages without switches.
The TDA 4862 is the improved version of the TDA 4817 with a pinout equivalent to world
standard.
Figure 1 Pin Configuration (top view)
TDA 4862TDA 4862 G
MULTIN 4
3
2
1
IEP01748
5
6 GND
DETIN
7
8GTDRV
V
CC
AOUT
V
SENSE
V
SENSE
Ι
4
3
2
1
IEP01749
5
6
7
8
SENSE
Ι
MULTIN
AOUT
V
SENSE
V
CC
V
GTDRV
GND
DETIN
TDA 4862
Semiconductor Group 3 1998-02-16
Pin Definitions and Functions
Pin Symbol Function
1VSENSE Voltage Amplifier Inverting Input;
VSENSE is connected via a resistive divider to the boost converter output.
With a capacitor connected to VAOUT it forms an integrator.
2VAOUT Voltage Amplifier Output;
VAOUT is connected internally to the first multiplier input. To prevent
overshoot the input voltage will be clamped at 5 V. Input voltage less
than 2.2 V is inhibiting the gate driver. If the current flowing into this pin
is exceeding an internal defined margin the multiplier output voltage is
reduced to prevent the MOSFET from overvoltage damage.
3 MULTIN Multiplier Input;
MULTIN is the second multiplier input and connected via a resistive
divider to the rectifier output voltage.
4ISENSE Current Sense Minus;
ISENSE is connected to a sense resistor controlling the MOSFET source
current. The input is internally clamped at – 0.3 V to prevent negative
input voltage interaction. An internal low pass filter suppresses voltage
spikes when turning the MOSFET on.
5 DETIN Zero Current Detector Input;
DETIN is connected to an auxiliary winding monitoring the zero crossing
of the inductor current.
6 GND Ground;
All voltages are measured with respect to GND. VCC should be
bypassed directly to GND with a 0.1 µF or larger ceramic capacitor.
7 GTDRV Gate Drive Output;
GTDRV is the output of a totem-pole circuitry for direct driving a
MOSFET. A clamping network bypasses low state source current and
high state sink current.
8VCC Positive Supply Voltage;
VCC should be connected to a stable source slightly above the VCC
turn-ON threshold for normal operation. A 100 nF or lager ceramic
capacitor connected to VCC absorbs supply current spikes required to
charge external MOSFET gate capacitances.
TDA 4862
Semiconductor Group 4 1998-02-16
Functional Description
Introduction
Conventional electronic ballasts and switching power supplies are designed with a
bridge rectifier and bulk capacitor. Their disadvantage is that the circuit draws power
from the line when the instantaneous AC voltage exceeds the capacitor’s voltage. This
occurs near the line voltage peak and causes a high charge current spike with following
characteristics: the apparent power is higher than the real power that means low power
factor condition, the current spikes are non-sinusoidal with a high content of harmonics
causing line noise, the rectified voltage depends on load condition and requires a large
bulk capacitor, special efforts in noise suppression are necessary.
With the TDA 4862 preconverter a sinusoidal current is achieved which varies in direct
instantaneous proportion to the input voltage half sine wave and means a power factor
near 1. This is due to the appearance of almost any complex load like a resistive one at
the AC line. The harmonic distortions are reduced and comply with the IEC555 standard.
Operating Description
The TDA 4862 contains a wide bandwidth voltage amplifier used in a feedback loop, an
overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a
current sense comparator, zero current detector, a PWM and logic circuitry, a totem-pole
MOSFET driver, an internal trimmed voltage reference, a restart timer and an
undervoltage lockout circuitry. These functional blocks are described below.
Voltage Amplifier
The voltage amplifier is internally compensated and yields a gain bandwidth of 0.8 MHz
and a phase margin of 80 degrees. The non-inverting input is biased at 2.5 V and is not
pinned out. The inverting input is sensing the output voltage via a resitive devider. The
voltage amplifier output VAOUT and the inverting input VSENSE are connected in a simplest
way via an external capacitor. It forms an integrator which monitors the average output
voltage over several line cycles. Typically the bandwidth is set below 20 Hz. ln order to
keep the output voltage constant the voltage amplifier output is connected to the
multiplier input for regulation.
Overvoltage Regulator
Fast changes of the output voltage can’t be regulated by the integrator formed with the
voltage amplifier This occurs during initial start-up, sudden load removal, or output
arcing and leads to a current peak at the voltage amplifier input while the voltage
amplifier’s differential input voltages remains zero. The peak current is flowing through
the external capacitor into VAOUT. Exceeding an internal defined margin causes a
regulation circuitry to reduce the multiplier output voltage.
TDA 4862
Semiconductor Group 5 1998-02-16
Functional Description (cont’d)
MuItiplier
A one quadrant multiplier is the crucial circuitry that regulates the gate driver with respect
of the DC output voltage and the AC haversine input voltage of the preregulator. Both
inputs are designed for good linearity over a wide dynamic range, 0 V to 4.0 V for the
MULTIN and 2.5 V to 4.0 V for the VAOUT.
Current Sense Comparator and RS Latch
The multiplier output voltage is compared with the current sense voltage which
represents the current through the MOSFET. The current sense comparator in addition
with the logic ensures that only a single pulse appears at the drive output during a
given cycle. The multiplier output and the current sense threshold are internally clamped
at 1.3 V. So the gate drive MOSFET is protected against critical operating, as they occur
during start up. To prevent the input from negative pulses a special protection circuitry
is implemented. Switch-on current peaks are reduced by an internal RC-Filter.
Zero Current Detector
The zero current detector senses the inductor current via an auxiliary winding and
ensures that the next on-time is initiated immediately when the inductor current has
reached zero. This diminishes the reverse recovery losses of the boost converter diode.
Output switch conduction is terminated when the voltage drop of the shunt resistor
reaches the threshold level of the multiplier output. So the boost current waveform has
a triangular shape and there are no deadtime gaps between the cycles. This leads to a
continuous AC line current limiting the peak current to twice of the average current.
To prevent false tripping the zero current detector is designed as a Schmitt trigger with
a hysteresis of 0.6 V. An internal 5 V clamp protects the input from overvoltage
breakdown, a 0.6 V clamp prevents substrate injection. An external resistor must be
used in series with the auxiliary winding to limit the current through the clamps.
Timer
A restart timer function was added to the IC to eliminate the need for an oscillator when
used in stand-alone applications. The timer starts or restarts the TDA 4862 if the drive
output has been off for more than 15 µs after the inductor current reaches zero.
TDA 4862
Semiconductor Group 6 1998-02-16
Functional Description (cont’d)
Undervoltage Lockout
An undervoltage lockout circuitry enables the output stage when VCC reaches the upper
threshold VCC and terminates the output stage when VCC is falling below the lower
threshold VCCL. In the standby mode the supply current is typically 75 µA. An internal
clamp has been added from VCC to ground to protect the IC from an overvoltage
condition. The external circuitry is created with a start-up resistor connected from VCC to
the input supply voltage and a storage capacitor from VCC to ground. Bootstrap power
supply is created with the previous mentioned auxiliary winding and a diode.
Output
The TDA 4862 totem pole output stage is MOSFET compatible. An internal protection
circuitry is activated when VCC is within the stand by mode and ensures that the MOSFET
is turned-OFF. The totem pole output has been optimized to minimize cross conduction
current during high speed operation. The addition of two 4 Ωresistors, one in series with
the source output transistor and one in series with the sink output transistor, reduces the
cross conduction current.
TDA 4862
Semiconductor Group 7 1998-02-16
Figure 2 Block Diagram
Over-
Voltage
Regulation
Multi-
plier
4 V
0.9 V
1.3 V
30 k 10 pF
5 V
0.6 V
Driver
and
Logic
Reference
Voltage
Z-Clamp
V
CC-
REF
V
CC
V
Clamp
Clamp
Current
Comp
Voltage
Amplifier
Lockout
Undervoltage
Filter
Clamp Detector
+
11 V / 8.5 V
2.5 V / 1.9 V
+
TDA 4862; G
1
2
3
4
5
6
7
8
GND
GTDRV
CC
V
AOUT
V
MULTIN
DETIN
IEB01747
SENSE
V
SENSE
Ι
Ω
TDA 4862
Semiconductor Group 8 1998-02-16
Figure 3 Application Circuit with TDA 4862; G
0.22 F
C
1
Tr1
250 H
Detector
MULTIN
GND
GTDRV BUZ 334
Q1
C
470 F
6
DETIN
AOUT
V
Ref
V
2
6
3
4
1
7
85
V
IN
AC
90-270 V
V
TH
IES01750
RF-Filter
and
Rectifier
Multi-
pler
µ
µ
100 F
C
3
µ
C
100 nF
4
+
+
Voltage
OP
+
Current
OP
1.3 M
R
1
Ω
100 k
R
Ω
3
R
12 k
2
Ω
R
100
8
Ω
D1
1N4148
R
22 k
3
Ω
PWM
Logic
Driver
TDA 4862 G
1.6 M
R
Ω
5
10 k
R
6
Ω
R
7
Ω
0.1
V
SENSE
SENSE
Ι
BYP 101
D2
C
5
400 V
µ
OUT
V
470 nF
TDA 4862
Semiconductor Group 9 1998-02-16
Operating Range
1) VCCON means VCCH has been exceeded but the supply voltage is still above VCCL. The device has switched from
standby to active. For VCCH and VCCL values see Electrical Characteristics. If 0 V < VCC <VCCON, the device
is in standby and output GTDRV is active low.
Absolute Maximum Ratings
Parameter Symbol Limit Values Unit Notes
min. max.
Supply voltage at VCC Pin 8
supply + Z-current VCC-GND Pin 8
Current into GTDRV Pin 7
Clamping current into GTDRV Pin 7
Clamping current into GTDRV Pin 7
VCC
ICCZ
IGTDRV
IGTDCH
IGTDCL
– 0.3
0
– 400
–
– 100
–
70
500
100
–
V
mA
mA
mA
mA
–
observe Pmax
observe Pmax
VGTDRV >VCC
VGTDRV < – 0.3 V
Voltage at VSENSE Pin 1
Voltage at VAOUT Pin 2
Voltage at MULTIN Pin 3
Voltage at ISENSE Pin 4
Current into DETIN Pin 5
Current into DETIN Pin 5
VVSENSE
VVAOUT
VMULTIN
VISENSE
IDETINH
IDETINL
– 0.3
– 0.3
– 0.3
–10
–
–10
17
6
17
17
50
–
V
V
V
V
mA
mA
–
–
–
–
VDETIN >6 V
VDETIN < 0.9 V
Junction temperature Tj– 40 150 °C–
Storage temperature Tstg – 50 150 °C–
Thermal resistance system-air
TDA 4862
TDA 4862 G RthSA
RthSA
–
–100
180 K/W
K/W P-DIP-8-1
P-DSO-8-1
Parameter Symbol Limit Values Unit Notes
min. max.
Supply voltage VCC VCCON VZV1)
Z-current IZ0 50 mA observe Pmax
Junction temperature Tj– 40 150 °C–
Voltage at ISENSE VISENSE – 5 VZV–
TDA 4862
Semiconductor Group 10 1998-02-16
Electrical Characteristics
Unless otherwise stated, VCC = 12 V, – 40 °C < Tj < 150 °C.
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Overall
Supply current, OFF ICCL – 75 200 µA 0 V < VCC < VCCH
Supply current, ON ICCH – 4 6 mA Output low
Supply current, dynamic ICCDY – 4.2 8 mA fDETIN = 50 kHz,
CGTDRV = 1 nF
VCC turn-ON threshold VCCH – 11 11.5 V –
VCC turn-OFF threshold VCCL 8.0 8.5 – V –
VCC turn-ON/OFF
hysteresis VCCHY 1.8 2.3 3.0 V –
VCC clamp VZ15 17 19 V ICCZ = 50 mA
Voltage Amplifier
Voltage feedback
threshold VFB 2.465 2.5 2.53
5VTj= 25 °C,
Pin 1 to Pin 2
Voltage feedback
threshold VFB 2.45 – 2.55 V Pin 1 to Pin 2
Line regulation ∆VFBL –– 5mVVCC = 10 V to 15 V
Input bias current IBVSENSE –1 – – µA–
Open loop voltage gain1) GV– 80 – dB –
Unity gain bandwidth1) BW– 0.8 – MHz –
Phase margin1) ΦM– 80 – Degr –
Inhibit threshold voltage VVAOUTI – 2.2 – V –
Output current source IVAOUTH – – 12 – mA VVAOUT = 0 V,
VVSENSE = 2.3 V
Output current sink IVAOUTL –4 –mAVVAOUT = 4 V,
VVSENSE = 2.8 V
1) Guaranteed by design, not 100 % tested in production.
TDA 4862
Semiconductor Group 11 1998-02-16
Output voltage swing
high state VVAOUTH 3.8 4.3 5.0 V IVAOUT = – 0.2 mA
VVSENSE = 2.3 V
Output voltage swing
low state VVAOUTL – 0.9 – V IVAOUT = 0.5 A
VVSENSE = 2.8 V
Overvoltage Regulator
Regulation current IRVAOUT 20 30 45 µAVVAOUT =VMULTIN
= 4 V,
VISENSE = 0.5 V
Current Comparator
Input bias current IBISENSE –1 – – µA–
Input offset voltage VISENSEO –25 –mVVMULTIN = 0 V,
VVAOUT = 2.4 V
Max threshold voltage VISENSEM 1.05 1.25 1.5 V –
Delay to output1) tPHL – 250 – ns –
Detector
Upper threshold voltage
(VDETIN increasing) VDETINU – 2.5 2.75 V –
Lower threshold voltage
(VDETIN decreasing) VDETINL 1.5 1.9 – V –
Hysteresis VDETINHY – 0.6 – V –
Input current IBDETIN –1 – – µA 1.5 V < VDETIN
< 2.75 V
Input clamp voltage
High state
Low state VDETINHC
VDETINLC
4
–5
0.6 –
1V
VIDETIN = 5 mA
IDETIN = – 5 mA
1) Guaranteed by design, not 100 % tested in production.
Electrical Characteristics (cont’d)
Unless otherwise stated, VCC = 12 V, – 40 °C < Tj < 150 °C.
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
TDA 4862
Semiconductor Group 12 1998-02-16
1) K = VISENSE / (VMULTIN × (VVAOUT – VFB))
2) Guaranted by design, not 100% tested in production.
Multiplier
Input bias current IBMULTIN – 1 – – µA–
Dynamic voltage range
MULTIN
VAOUT
VMULTIN
VVAOUT
0 to 3
VFB to
VFB + 1
0 to 4
VFB to
VFB + 1.5
–
–V
VVVAOUT = 2.75 V
VMULTIN = 1.0 V
Multiplier gain 1) K0.45 0.65 0.85 1/V VMULTIN = 2 V
VVAOUT =VFB + 1 V
Restart Timer
Restart time delay tDLY 75 190 400 µs–
Gate Driver
Output voltage low state VGTDRVL – 0.8
1.8 –V
VIGTDRV = 20 mA
IGTDRV = 200 mA
Output voltage high
state VGTDRVH – 9.4
8.7 –VIGTDRV = – 20 mA
IGTDRV = – 200 mA
Output voltage active
shut down VGTDRVU – 2.0 2.6 V IGTDRV = 50 mA
VCC increasing:
0 < VCC < VCCH,
VCC decreasing:
0 < VCC < VCCL
Rise time 2) tr– 100 – – CGTDRV = 1 nF
Fall time 2) tf–40 ––CGTDRV = 1 nF
Electrical Characteristics (cont’d)
Unless otherwise stated, VCC = 12 V, – 40 °C < Tj < 150 °C.
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
TDA 4862
Semiconductor Group 13 1998-02-16
Supply Current ICC versus
Supply Voltage VCC
Turn-ON/-OFF Threshold Voltage VCC
versus Junction Temperature Tj
Supply Current ICC versus
Junction Temperature Tj
Open Loop Gain GV and Phase Φ
versus Frequency f
0
0510 15 V
V
CC
20
VSENSE
V
= 3 V
mA
Ι
CC
6
IED01751
5
4
3
2
1
= 3 V
VAOUT
V
= 1 V
MULTIN
V
= 0.5 V
ISENSE
V
= 2 V
DETIN
V
= 25 C
j
T
-50
7
8
9
10
0 50 100 C
T
j
CCL
V
V
11
12
CCH
V
IED01753
V
CC
150
-50
00 50 100 C
T
j
150
VSENSE
V
= 3 V
mA
Ι
CC
6
IED01752
5
4
3
2
1
= 3 V
VAOUT
V
= 1 V
MULTIN
V
= 0.5 V
ISENSE
V
= 2 V
DETIN
V
0
20
40
60
Φ
M
2
f
4
Φ
CC
100
G
V
A
dB
80
j
T
0
VV
VAOUT
IED01754
= 25 C
3.0 < < 3.5 V
= 12 V
kHz
10 10
0
30
60
90
120
150
Φ
deg
10
0
10
-1
10
-2 1
10
TDA 4862
Semiconductor Group 14 1998-02-16
Threshold Voltage Change ∆VFB versus
Junction Temperature Tj
Threshold Voltage VDETIN versus
Junction Temperature Tj
Threshold Voltage VISENSE versus
Regulation Current IRVAOUT
Current Sense Threshold VISENSE versus
Multiplier Input VMULTIN
-50
-15
-10
-5
0
0 50 100 C
T
j
mV
5
10 IED01755
V
FB
150
∆CC
V
= 12 V
Pin 1 connected to Pin 2
-50
00 50 100 C
T
j
150
1/V
3.00
IED01757
2.75
2.50
2.25
2.00
1.75
= 12 V
CC
V
= 1 V
MULTIN
V
= GND
VSENSE
V
= GND
ISENSE
V
DETIN
V
DETINupper
V
V
DETINlow
29
0.4
0.2
0
0.6
323130
0.8
1.0
1.4
RVAOUT
Ι
34
IED01756
33
µ
A
V
CC
=12 V
V
V
ISENSE
150 C
25 C
-40 C
0.8
0
0.4
0.2
0
0.6
3
21
1.0
1.4
5
IED01758
4V
V
V
ISENSE
MULTIN
V
4.0 V
3.5 V
3.0 V
2.75 V
VAOUT
V
= 2.5 V
Semiconductor Group 15 1998-02-16
Current Sense Threshold VISENSE versus
Voltage Amplifier Output VVAOUT
Restart Time Delay tDLY versus
Junction Temperature Tj
Multiplier Gain K versus
Junction Temperature Tj
Output Voltage Low/High State VSAT
versus Load Current IGTDRV
0.8
2.5
0.4
0.2
0
0.6
4.0
3.53.0
1.0
1.4
5.0
IED01759
4.5 V
V
V
ISENSE
VAOUT
V
MULTIN
V
= 3 V
2 V
1 V
0.5 V
-50
140 0 50 100 C
T
j
150
s
240
IED01761
180
200
160
t
DLY
220
µ
-50
00 50 100 C
T
j
150
CC
V
1/V
1.2
IED01760
0.6
MULTIN
V
VAOUT
V
0.9
0.3
K
= 12 V
= 2 V
= VFB + 1 V
0
0100 200 300 mA
V
SAT
400
CC
V
= 12 V
V
Ι
GTDRV
6
IED01762
5
4
3
2
1
= 10 ms
T
= 200 s
p
t
µ
CC
VV
GTDRVH
GTDRVL
V
GTDRVL
V
at
CC
V
= 7 V
TDA 4862
TDA 4862
Semiconductor Group 16 1998-02-16
Package Outlines
Plastic Package, P-DIP-8-1
(Plastic Dual In-line Package)
GPD05025
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
TDA 4862
Semiconductor Group 17 1998-02-16
GPS05121
Plastic Package, P-DSO-8-1
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
