1
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1999
1999 Integrated Device Technology, Inc. DSC-5439/-c
IDT54/74FCT16827AT/BT/CT/ET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS
20-BIT BUFFER
DESCRIPTION:
The FCT16827AT/BT/CT/ET 20-bit buffers are built using advanced
dual metal CMOS technology. These 20-bit bus drivers provide high-
performance bus interface buffering for wide data/address paths or buses
carrying parity. Two pair of NAND-ed output enable controls offer maximum
control flexibility and are organized to operate the device as two 10-bit
buffers or one 20-bit buffer. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT16827AT/BT/CT/ET are ideally suited for driving high capaci-
tance loads and low impedance backplanes. The output buffers are
designed with power off disable capability to allow "live insertion" of boards
when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
2Y1
TO NINE OTHER CHANNELS
2OE1
2OE2
2A1
1Y1
TO NINE OTHER CHANNELS
1OE1
1OE2
1A1
1
56
55
28
29
422 15
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP
and 25 mil pitch CERPACK packages
Extended commercial range of -40°C to +85°C
VCC = 5V ±10%
High drive outputs (-32mA IOH, 64mA IOL)
Power off disable outputs permit “live insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA =
25°C
2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other c onditions above t hose indicated in the operational s ections
of this specification is not implied. Exposure to absolute maximum
rating condit i ons for extended periods may affect reliability.
2. All dev i ce terminals exc ept FCT162XXXT Output and I/O t erminals.
3. Output and I/ O t erminals for FCT162XXXT.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
COUT Output Capacitance VOUT = 0V 3.5 8 pF
5v16-link
NOTE:
1. This paramet er i s measured at characterization but not test ed.
1Y1
GND
1Y3
VCC
1OE1
GND
1Y10
GND
1Y2
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
2Y3
VCC
GND
2Y4
2Y5
2Y7
2Y8
2Y6
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
1A7
1A8
1A9
1A10
GND
GND
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SO56-1
SO56-2
SO56-3
E56-1
2Y1
2Y2
2Y10
2Y9
2A3
2A4
VCC
2A5
2A7
2A8
2A6
GND
2A9
2A10
2OE2
29
30
31
3225
26
27
28
2A1
2A2
PIN DESCRIPTION
Pin Names Description
xOEx Output Enable Inputs (Active LOW)
xAx Data Inputs
xYx 3-State Outputs
FUNCTION TABLE(1)
Inputs Outputs
xOE1xOE2xAxxYx
LLL L
LLH H
HXX Z
XHX Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
3
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, VCC = 5.0V ±10%; Military: TA = -55°C to +125°C, VCC = 5.0V ±10%
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 V
VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V
IIH Input HIGH Current (Input pins)(5) VCC = Max. VI = VCC ——±A
Input HIGH Current (I/O pins)(5) ——±1
I
IL Input LOW Current (Input pins)(5) VI = GND ±1
Input LOW Current (I/O pins)(5) ——±1
I
OZH High Impedance Output Current VCC = Max. VO = 2.7V ±A
I
OZL (3-State Output pins)(5) VO = 0.5V ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA
VHInput Hysteresis 100 mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current VCC = Max.
VIN = GND or VCC 5 500 µA
5v16-link
NOTES:
1. For conditi ons shown as Max. or M i n. , use appropri ate value specified under Electrical Charac teristi cs for the applic abl e device t ype.
2. Typical values a re at V CC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one ti m e. Duration of t he test should not exceed one sec ond.
4. Duration of the condi tion can not exceed one second.
5. The test l i m i t for t hi s parameter is ±5µA at TA = -55°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
IOOutput Drive Current VCC = Max., VO = 2.5V(3) –50 –180 mA
VOH Output HIGH Voltage V CC = Min. IOH = –3mA 2.5 3.5 V
VIN = VIH or VIL IOH = –12mA MIL. 2.4 3.5 V
IOH = –15mA COM’L.
IOH = –24mA MIL. 2 3 V
IOH = –32mA COM’L.(4)
VOL Output LOW Voltage V CC = Min. IOH = 48mA MIL. 0.2 0.55 V
VIN = VIH or VIL IOH = 64mA COM’L
IOFF Input/Output Power Off Leakage(5) V CC = 0V, VIN or VO 4.5V ±1 µA
4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ICC Quiescent Power Supply Current
TTL Inputs HIGH VCC = Max.
VIN = 3.4V(3) —0.51.5mA
I
CCD Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
xOE1 = xOE2 = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND 60 100 µA/
MHz
ICTotal Power Supply Current(6) VCC = Max.
Outputs Open
fi = 10MHz
VIN = VCC
VIN = GND —0.61.5mA
50% Duty Cycle
xOE1 = xOE2 = GND
One Bit Toggling
VIN = 3.4V
VIN = GND —0.92.3
V
CC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND —35.5
(5)
50% Duty Cycle
xOE1 = xOE2 = GND
Twenty Bits Toggling
VIN = 3.4V
VIN = GND 8 20.5(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16827AT FCT16827BT
Com'l. Mil. Com'l. Mil.
Symbol
Parameter Condition(1) Min.(2) Max.Min.(2) Max.Min.(2) Max.Min.(2) Max.Unit
tPLH
tPHL Propagation Delay
xAx to xYx CL = 50pF
RL = 5001.5 8 1.5 9 1.5 5 1.5 6.5 ns
CL = 300pF(4)
RL = 5001.5 15 1.5 17 1.5 13 1.5 14
tPZH
tPZL Output Enable Time
xOEx to xYx CL = 50pF
RL = 5001.5 12 1.5 13 1.5 8 1.5 9 ns
CL = 300pF(4)
RL = 5001.5 23 1.5 25 1.5 15 1.5 16
tPHZ
tPLZ Output Disable Time
xOEx to xYx CL = 5pF(4)
RL = 5001.5 9 1.5 9 1.5 6 1.5 7 ns
CL = 50pF
RL = 5001.5 10 1.5 10 1.5 7 1.5 8
tSK(o) Output Skew(3) 0.5 0.5 0.5 0.5 ns
FCT16827CT FCT16827ET
Com'l. Mil. Com'l. Mil.
Symbol
Parameter Condition(1) Min.(2) Max.Min.(2) Max.Min.(2) Max.Min.(2) Max.Unit
tPLH
tPHL Propagation Delay
xAx to xYx CL = 50pF
RL = 5001.5 4.4 1.5 5 1.5 3.2 ns
CL = 300pF(4)
RL = 5001.5 10 1.5 11 1.5 7
tPZH
tPZL Output Enable Time
xOEx to xYx CL = 50pF
RL = 5001.5 7 1.5 8 1.5 4.8 ns
CL = 300pF(4)
RL = 5001.5 14 1.5 15 1.5 9
tPHZ
tPLZ Output Disable Time
xOEx to xYx CL = 5pF(4)
RL = 5001.5 5.7 1.5 6.7 1.5 4 ns
CL = 50pF
RL = 5001.5 6 1.5 7 1.5 4
tSK(o) Output Skew(3) 0.5 0.5 0.5 ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This condition is guaranteed but not tested.
6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMI NG
INPUT
ASYNCHRONO US CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOU S CONTROL
tSU tH
tREM
tSU tH
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
tPLZ
tPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES PULSE WIDTH
SWITCH POSITION
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
5v16-link
DEFINITIONS:
CL = Load capacit ance: i ncludes jig and probe capaci tance.
RT = Termination resistance: shoul d be equal t o ZOUT of the Pulse
Generator.
NOTES:
1. Diagram s hown for input Cont rol Enable-LOW and input Control
Disable-HIGH.
2. Puls e Generator for A l l Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
7
IDT54/74FCT16827AT/BT/CT/ET
FAST CMOS 20-BIT BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
ID T XX
Temp. Range XXXX
D evice Typ e X
Package X
Process
54
74 – 55 °C to +125°C
– 40 °C to +85°C
Blank
B
PV
PA
PF
E
827AT
827BT
827CT
827ET
Commercial
MIL-STD -883, Class B
Shrink Sm all Outline Package (SO5 6-1)
Thin Shrink Sm all O utline Pa ckage (SO56-2)
Thin Very Sm all Outline P ackage (SO 56-3)
CERPACK (E56-1)
20-Bit Buffer
FCT XX
Family
16 Doub le-Density 5 Volt High Drive