BS616UV4016AIP85 - Brilliance Semiconductor, Inc.

BSI Ultra Low Power/High Speed CMOS SRAM

256K X 16 bit BS616UV4016

R0201

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B

S616UV4016

1

Revision

1.

3

Sep

. 2005

n FEATURES

Ÿ Wide VCC operation voltage :

C-grade : 1.8V ~ 3.6V

I-grade : 1.9V ~ 3.6V

(VCC_min.=1.65V at 25OC)

Ÿ Ultra low power consumption :

V

CC = 2.0V C-grade : 10mA(Max.) operating current

I-grade : 12mA(Max.) operating current

0.3uA (Typ.) CMOS standby current

V

CC = 3.0V C-grade : 13mA(Max.) operating current

I-grade : 15mA(Max.) operating current

0.45uA (Typ.) CMOS standby current

Ÿ High speed access time :

-85 85ns (Max.)

-10 100ns (Max.)

Ÿ Automatic power down when chip is deselected

Ÿ Easy expansion with CE and OE options

Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.

Ÿ Three state outputs and TTL compatible

Ÿ Fully static operation

Ÿ Data retention supply voltage as low as 1.2V

n DESCRIPTION

The BS616UV4016 is a high performance, ultra low power CMOS Static

Random Access Memory organized as 262,144 words by 16 bits and

operates form a wide range of 1.8V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with typical CMOS standby current of

0.3uA at 2.0V/25OC and maximum access time of 85ns at 85OC.

Easy memory expansion is provided by an active LOW chip enable (CE)

and active LOW output enable (OE) and three-state output drivers.

The BS616UV4016 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS616UV4016 is available in DICE form, JEDEC standard 44-pin

TSOP Type II and 48-ball BGA package.

n PRODUCT FAMILY POWER DISSIPATION

SPEED

(ns) STANDBY

(ICCSB1, Max) Operating

(ICC, Max)

PRODUCT

FAMILY OPERATING

TEMPERATURE

VCC

RANGE C-grade : 1.8~3.6V

I-grade : 1.9~3.6V

VCC=3.0V

VCC=2.0V

VCC=3.0V

VCC=2.0V

PKG TYPE

BS616UV4016DC DICE

BS616UV4016EC TSOP2-44

BS616UV4016AC

+0OC to +70OC

1.8V ~ 3.6V 85/100 6.0uA

3.0uA

13mA

10mA

BGA-48-0608

BS616UV4016DI DICE

BS616UV4016EI TSOP2-44

BS616UV4016AI

-40OC to +85OC

1.9V ~ 3.6V 85/100 8.0uA

5.0uA

15mA

12mA

BGA-48-0608

n PIN CONFIGURATIONS

n BLOCK DIAGRAM

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

G

H

F

E

D

C

B

A

1

2

3

4

5

6

A9

A11

A10

NC

A12

A14

A13

A15

WE

IO13

IO5

IO7

IO6

A17

A16

A7

VSS

VCC

IO12

IO11

IO4

IO3

NC

A5

OE

A3

A0

A6

A4

A1

A2

NC

LB

IO10

IO1

CE

IO2

IO0

48-ball BGA top view

UB

IO8

IO9

VSS

VCC

IO14

IO15

NC

A8

A4

A3

A2

A1

A0

CE

IO0

IO1

IO2

IO3

VCC

GND

IO4

IO5

IO6

IO7

WE

A17

A16

A15

A14

A13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

BS616UV4016EC

BS616UV4016EI

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A5

A6

A7

OE

UB

LB

IO15

IO14

IO13

IO12

GND

VCC

IO11

IO10

IO9

IO8

NC

A8

A9

A10

A11

A12

Address

Input

Buffer

Row

Decoder

Memory Array

1024 x 4096

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

Data

Input

Buffer

Control

IO0

.

IO15

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

1

6

16

8

256

2048

1024

1

0

A13

Data

Output

Buffer

CE

WE

OE

UB

LB

VCC

GND

A1

4

.

A15A16A17A0

A2

A1

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R0201-BS616UV4016

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Sep. 2005

n PIN DESCRIPTIONS

Name Function

A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM

CE Chip Enable 1 Input CE is activ

e LOW. Chip enable must be active when data read form or write to the

device. If either chip enable is not active, the device is deselected and is in standby

power mode. The IO pins will be in the high impedance state when the device is

deselected.

WE Write Enable Input The write enable input is active LOW and controls read and write operations

. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the IO

pins; when WE is LOW, the data present on the IO pins will be writ

ten into the selected

memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the IO pins and they

will be enabled. The IO pins will be in the high impendence state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

IO0-IO15 Data Input/Output

Ports 16 bi-directional ports are used to read data from or write data into the RAM.

VCC Power Supply

GND Ground

n TRUTH TABLE

MODE CE WE OE LB UB IO0~IO7 IO8~IO15

VCC CURRENT

H X X X X High Z High Z ICCSB, ICCSB1

Chip De-selected

(Power Down) X X X H H High Z High Z ICCSB, ICCSB1

L H H L X High Z High Z ICC

Output Disabled L H H X L High Z High Z ICC

L L DOUT DOUT ICC

H L High Z DOUT ICC

Read L H L

L H DOUT High Z ICC

L L DIN DIN ICC

H L X DIN ICC

Write L L X

L H DIN X ICC

NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)

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Sep. 2005

n ABSOLUTE MAXIMUM RATINGS (1)

SYMBOL

PARAMETER RATING

UNITS

VTERM Terminal Voltage with

Respect to GND -0.5(2) to 4.6V

V

TBIAS Temperature Under

Bias -40 to +85

OC

TSTG Storage Temperature -60 to +150

OC

PT Power Dissipation 1.0 W

IOUT DC Output Current 20 MA

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

2. –2.0V in case of AC pulse width less than 30 ns

n OPERATING RANGE

RANG AMBIENT

TEMPERATURE Vcc

Commercial 0OC to + 70OC 1.8V ~ 3.6V

Industrial -40OC to + 85OC 1.9V ~ 3.6V

n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)

SYMBOL

PAMAMETER

CONDITIONS

MAX.

UNITS

CIN Input

Capacitance VIN = 0V 6 pF

CIO Input/Output

Capacitance VI/O = 0V 8 pF

1. This parameter is guaranteed and not 100% tested.

n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

PARAMETER

NAME PARAMETER TEST CONDITIONS MIN. TYP.(1)

MAX. UNITS

VCC Power Supply 1.9 -- 3.6 V

VCC=2.0V

0.6

VIL Input Low Voltage VCC=3.0V

-0.3(2) -- 0.8 V

VCC=2.0V

1.4

VIH Input High Voltage VCC=3.0V

2.0 -- VCC+0.3(3)

V

IIL Input Leakage Current VIN = 0V to VCC,

CE = VIH -- -- 1 uA

ILO Output Leakage Current VI/O = 0V to VCC

CE= VIH, or OE = VIH -- -- 1 uA

VCC = Max, IOL = 0.1mA VCC=2.0V

0.2

VOL Output Low Voltage VCC = Max, IOL = 2.0mA VCC=3.0V

-- -- 0.4 V

VCC = Min, IOH = -0.1mA VCC=2.0V

VCC-0.2

VOH Output High Voltage VCC = Min, IOH = -1.0mA VCC=3.0V

2.4 -- -- V

VCC=2.0V

12

ICC Operating Power Supply

Current

CE = VIL,

IIO = 0mA, f = FMAX(4) VCC=3.0V

-- -- 15 mA

VCC=2.0V

0.5

ICCSB Standby Current – TTL CE = VIH,

IIO = 0mA VCC=3.0V

-- -- 1.0 mA

VCC=2.0V

0.3 5.0

ICCSB1(5) Standby Current – CMOS CE≧VCC-0.2V,

VIN≧VCC-0.2V or VIN≦0.2V VCC=3.0V

-- 0.45 8.0 uA

1. Typical characteristics are at TA=25OC.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.

4. FMAX=1/tRC.

5. ICCSB1(MAX) is 3.0/6.0uA at VCC=2.0V/3.0V and TA=70OC.

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n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1)

MAX. UNITS

VDR VCC for Data Retention CE≧VCC-0.2V,

VIN≧VCC-0.2V or VIN≦0.2V 1.2 -- -- V

ICCDR(3) Data Retention Current CE≧VCC-0.2V,

VIN≧VCC-0.2V or VIN≦0.2V -- 0.15 1.7 uA

tCDR Chip Deselect to Data

Retention Time 0 -- -- ns

tR Operation Recovery Time See Retention Waveform tRC (2) -- -- ns

1. VCC=1.2V, TA=25OC.

2. tRC = Read Cycle Time.

3. ICCRD_Max. is 1.2uA at TA=70OC.

n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels Vcc / 0V

Input Rise and Fall Times 1V/ns

Input and Output Timing

Reference Level 0.5Vcc

tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL

Output Load

Others CL = 30pF+1TTL

1. Including jig and scope capacitance.

n KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE

STEADY MUST BE

STEADY

MAY CHANGE

FROM “H” TO “L” WILL BE CHANGE

FROM “H” TO “L”

MAY CHANGE

FROM “L” TO “H” WILL BE CHANGE

FROM “L” TO “H”

DON’T CARE

ANY CHANGE

PERMITTED

CHANGE :

STATE UNKNOW

DOES NOT

APPLY

CENTER LINE IS

HIGH INPEDANCE

“OFF” STATE

CL

(1)

1

TTL

Output

ALL INPUT PULSES

→

←

90%

V

CC

GND

Rise Time:

1V/ns Fall Time:

1V/ns

90%

→

←

10%

Data Retention Mode

V

CC

t

CDR

V

CC

tR

VIH

CE≧VCC - 0.2V

V

DR

≧1.0V

CE

VCC

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n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

READ CYCLE

JEDEC

PARAMETER

NAME

PARANETER

NAME DESCRIPTION CYCLE TIME : 85ns

(VCC=1.9~3.6V)

MIN. TYP. MAX.

CYCLE TIME : 100ns

(VCC=1.9~3.6V)

MIN. TYP. MAX.

UNITS

tAVAX tRC Read Cycle Time 85 -- -- 100

-- -- ns

tAVQX tAA Address Access Time -- -- 85 -- -- 100

ns

tELQV tACS Chip Select Access Time (CE)

-- -- 85 -- -- 100

ns

tBLQV tBA(1) Data Byte Control Access Time (LB, UB)

-- -- 40 -- -- 50 ns

tGLQV tOE Output Enable to Output Valid -- -- 40 -- -- 50 ns

tELQX tCLZ Chip Select to Output Low Z (CE)

15 -- -- 15 -- -- ns

tBLQX tBE Data Byte Control to Output Low Z (LB, UB)

15 -- -- 15 -- -- ns

tGLQX tOLZ Output Enable to Output Low Z 15 -- -- 15 -- -- ns

tEHQZ tCHZ Chip Select to Output High Z (CE)

-- -- 35 -- -- 40 ns

tBHQZ tBDO Data Byte Control to Output High Z (LB, UB)

-- -- 35 -- -- 40 ns

tGHQZ tOHZ Output Enable to Output High Z -- -- 35 -- -- 40 ns

tAVQX tOH Data Hold from Address Change 15 -- -- 15 -- -- ns

NOTE :

1. tBA is 40ns/50ns(@speed=85ns/100ns) with address toggle; tBA is 85ns/100ns(@speed=85ns/100ns) without address toggle

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1 (1,2,4)

READ CYCLE 2 (1,3,4)

tRC

t

OH

t

AA

DOUT

ADDRESS

tOH

tCLZ

(5)

tCHZ

(5)

DOUT

LB, UB

CE

t

BA

t

ACS

t

BE

t

BDO

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Sep. 2005

READ CYCLE 3 (1, 4)

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = VIL.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL.

5. Transition is measured ± 500mV from steady state with CL = 5pF.

The parameter is guaranteed but not 100% tested.

t

OH

t

RC

t

OE

tBE

tBDO

DOUT

CE

OE

ADDRESS

tCLZ

(5)

t

ACS

t

CHZ

(1,5)

tOHZ

(5)

t

OLZ

t

AA

LB, UB

t

BA

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Sep. 2005

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

WRITE CYCLE

JEDEC

PARAMETER

NAME

PARANETER

NAME DESCRIPTION CYCLE TIME : 85ns

(VCC=1.9~3.6V)

MIN. TYP. MAX.

CYCLE TIME : 100ns

(VCC=1.9~3.6V)

MIN. TYP. MAX.

UNITS

tAVAX tWC Write Cycle Time 85 -- -- 100

-- -- ns

tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns

tAVWH tAW Address Valid to End of Write 85 -- -- 100

-- -- ns

tELWH tCW Chip Select to End of Write (CE)

85 -- -- 100

-- -- ns

tBLWH tBW(1) Data Byte Control to End of Write (LB, UB)

35 -- -- 40 -- -- ns

tWLWH tWP Write Pulse Width 40 -- -- 50 -- -- ns

tWHAX tWR Write Recovery Time (CE, WE)

0 -- -- 0 -- -- ns

tWLQZ tWHZ Write to Output High Z -- -- 35 -- -- 40 ns

tDVWH tDW Data to Write Time Overlap 35 -- -- 40 -- -- ns

tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns

tGHQZ tOHZ Output Disable to Output in High Z -- -- 35 -- -- 40 ns

tWHQX tOW End of Write to Output Active 10 -- -- 10 -- -- ns

NOTE:

1. tBW is 35ns/40ns (@speed=85ns/100ns) with address toggle; tBW is 85ns/100ns (@speed=85ns/100ns) without address toggle.

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1 (1)

tWC

tCW

(11)

tWP

(2)

tAW

tOHZ

(4,10)

t

AS

tWR

(3)

t

DH

t

DW

DIN

DOUT

WE

LB, UB

CE

OE

ADDRESS

(5)

tBW

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Sep. 2005

WRITE CYCLE 2 (1,6)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be

active to initiate a write and any one signal can terminate a write by going inactive. The data input

setup and hold timing should be referenced to the second transition edge of the signal that terminates

the write.

3. t

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, IO pins are in the output state so that the input signals of opposite phase to the

outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition,

output remain in a high impedance state.

6. OE is continuously low (OE = VIL).

7. D

OUT is the same phase of write data of this write cycle.

8. D

OUT is the read data of next address.

9. If CE is low during this period, IO pins are in the output state. Then the data input signals of opposite

phase to the outputs must not be applied to them.

10. Transition is measured ± 500mV from steady state with CL = 5pF.

The parameter is guaranteed but not 100% tested.

11. t CW is measured from the later of CE going low to the end of write.

t

WC

tCW

(11)

tWP

(2)

tAW

tWHZ

(4,10)

t

AS

tWR

(3)

t

DH

t

DW

DIN

D

OUT

WE

LB, UB

CE

ADDRESS

(5)

t

OW

(7)

(8)

(8,9)

tBW

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Sep. 2005

n ORDERING INFORMATION

Note:

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not

authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in

significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

PACKAGE

D: DICE

E: TSOP 2-44

A

: BGA-48-0608

BS616UV4016 X X Z Y Y

GRADE

C : +0oC ~ +70oC

I : -40oC ~ +85oC

SPEED

85: 85ns

1

0:

10

0ns

PKG MATERIAL

-: Normal

G: Green

P: Pb free

48 mini-BGA (6 x 8mm)

D1

VIEW A

1.4

Max.

e

E1

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

D

8.0

6.0

E

N

48

3.75

E1

D1

5.25

NOTES

:

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Revision

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Sep. 2005

n PACKAGE DIMENSIONS (continued)

TSOP2-44