June 1999 4-21
STK11C68
8K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
•STORE to EEPROM Initiated by Software
•RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
DESCRIPTION
The Simtek STK11C68 is a fast static RAM with a
nonvolatile, electrically erasable PROM element
incorporated in each static memory cell. The SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
the EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation), or from EEPROM to
SRAM (the RECALL operation), take place using a
software sequence. Transfers from the EEPROM to
the SRAM (the RECALL operation) also take place
automatically on restoration of power.
The STK11C68 is pin-compatible with industry-
standard SRAMs. MIL-STD-883 device is also
available (STK11C68-M).
BLOCK DIAGRAM
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
128 x 512
ROW DECODER
INPUT BUFFERS
EEPROM ARRAY
128 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
A5
A6
A9
A11
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SOFTWARE
DETECT A0-A
12
G
E
W
A8
A7
A
10
A
3
A
2
A
0
A
1
A
4
PIN CONFIGURATIONS
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
NC
A8
A9
A11
G
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
28 - 300 PDIP
28 - 300 CDIP
28 - 350 SOIC
PIN NAMES
A0 - A12 Address Inputs
W Write Enable
DQ0 - DQ7Data In/Out
E Chip Enable
G Output Enable
VCC Power (+ 5V)
VSS Ground
STK11C68
June 1999 4-22
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration). . . . . . . .15mA
DC CHARACTERISTICS (VCC = 5.0V ± 10%)b
Note b: The STK11C68-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: ICC1and ICC3are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: ICC2 is the average current required for the duration of the STORE cycle (tSTORE).
Note e: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
CAPACITANCEf(TA = 25°C, f = 1.0MHz)
Note f: These parameters are guaranteed but not tested.
SYMBOL PARAMETER COMMERCIAL INDUSTRIAL UNITS NOTES
MIN MAX MIN MAX
ICC1cAverage VCC Current 100
90
75
65
N/A
90
75
65
mA
mA
mA
mA
tAVAV = 20ns
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
ICC2dAverage VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
ICC3cAverage VCC Current at tAVAV = 200ns
5V, 25˚C, Typical 10 10 mA W≥ (VCC– 0.2V)
All Others Cycling, CMOS Levels
ISB1eAverage VCC Current
(Standby, Cycling TTL Input Levels) 32
27
23
20
N/A
28
24
21
mA
mA
mA
mA
tAVAV = 20ns, E ≥ VIH
tAVAV = 25ns, E ≥ VIH
tAVAV = 35ns, E ≥ VIH
tAVAV = 45ns, E ≥ VIH
ISB2eVCC Standby Current
(Standby, Stable CMOS Input Levels) 750 750 µAE≥ (VCC - 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
IILK Input Leakage Current ±1±1µAVCC = max
VIN = VSS to VCC
IOLK Off-State Output Leakage Current ±5±5µAVCC = max
VIN = VSS to VCC,E or G ≥ VIH
VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
VOH Output Logic “1” Voltage 2.4 2.4 V IOUT =–4mA
VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 8mA
TAOperating Temperature 0 70 –40 85 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
CIN Input capacitance 8 pF ∆V = 0 to 3V
COUT Output Capacitance 7 pF ∆V = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
OUTPUT
SCOPE AND
FIXTURE
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
STK11C68
June 1999 4-23
SRAM READ CYCLES #1 & #2 (VCC = 5.0V + 10%)b
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
SRAM READ CYCLE #2: E Controlledg
NO.
SYMBOLS PARAMETER STK11C68-20 STK11C68-25 STK11C68-35 STK11C68-45 UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV tACS Chip Enable Access Time 20 25 35 45 ns
2t
AVAVgtRC Read Cycle Time 20 25 35 45 ns
3t
AVQVhtAA Address Access Time 22 25 35 45 ns
4t
GLQV tOE Output Enable to Data Valid 8 10 15 20 ns
5t
AXQXhtOH Output Hold after Address Change 5555ns
6t
ELQX tLZ Chip Enable to Output Active 5555ns
7t
EHQZitHZ Chip Disable to Output Inactive 7 10 13 15 ns
8t
GLQX tOLZ Output Enable to Output Active 0000ns
9t
GHQZitOHZ Output Disable to Output Inactive 7 10 13 15 ns
10 tELICCHftPA Chip Enable to Power Active 0000ns
11 tEHICCLe, f tPS Chip Disable to Power Standby 25 25 35 45 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
8
tGLQX
4
tGLQV
DQ (DATA OUT)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ
STK11C68
June 1999 4-24
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V + 10%)b
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1:W Controlledk
SRAM WRITE CYCLE #2:E Controlledk
NO. SYMBOLS PARAMETER STK11C68-20 STK11C68-25 STK11C68-35 STK11C68-45 UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
12 tAVAV tAVAV tWC Write Cycle Time 20 25 35 45 ns
13 tWLWH tWLEH tWP Write Pulse Width 15 20 25 30 ns
14 tELWH tELEH tCW Chip Enable to End of Write 15 20 25 30 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 8 10 12 15 ns
16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 15 20 25 30 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 0 ns
19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 0 ns
20 tWLQZi, j tWZ Write Enable to Output Disable 7 10 13 15 ns
21 tWHQX tOW Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA OUT
E
ADDRESS
12
tAVAV
W
DATA IN
13
tWLEH
17
tAVEH
DATA VALID
HIGH IMPEDANCE
14
tELEH
18
tAVEL
15
tDVEH
19
tEHAX
16
tEHDX
STK11C68
June 1999 4-25
STORE INHIBIT/POWER-UP RECALL (VCC = 5.0V + 10%)b
Note l: tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER-UP RECALL
NO. SYMBOLS PARAMETER STK11C68 UNITS NOTES
Standard MIN MAX
22 tRESTORE Power-up RECALL Duration 550 µsl
23 tSTORE STORE Cycle Duration 10 ms
24 VSWITCH Low Voltage Trigger Level 4.0 4.5 V
25 VRESET Low Voltage Reset Level 3.9 V
V
CC
V
SWITCH
V
RESET
OWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
22
tRESTORE
24
25
POWER-UP
RECALL BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
STK11C68
June 1999 4-26
SOFTWARE STORE/RECALL MODE SELECTION
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE STORE/RECALL CYCLEn, o (VCC = 5.0V ± 10%)b
Note n: The software sequence is clocked with E controlled reads.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
EWA
12 - A0 (hex) MODE I/O NOTES
LH
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m
LH
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m
NO. SYMBOLS PARAMETER STK11C68-20 STK11C68-25 STK11C68-35 STK11C68-45 UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
26 tAVAV STORE/RECALL Initiation Cycle Time 20 25 35 45 ns
27 tAVELnAddress Set-up Time 0000ns
28 tELEHnClock Pulse Width 15 20 25 30 ns
29 tELAXnAddress Hold Time 15 20 20 20 ns
30 tRECALLnRECALL Duration 20 20 20 20 µs
HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
26
tAVAV
DATA VALID
DQ (DATA OUT)
E
ADDRESS
23 30
tSTORE / tRECALL
26
tAVAV
27
tAVEL 28
tELEH
29
tELAX
STK11C68
June 1999 4-27
The STK11C68 is a versatile memory chip that pro-
vides several modes of operation. The STK11C68
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 EEPROM shadow to which the SRAM informa-
tion can be copied or from which the SRAM can be
updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between Vcc
and Vss, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK11C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-12 determines which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by EorG, the outputs will be valid at tELQV or
at tGLQV
, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until EorGis
brought high.
SRAM WRITE
AWRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either EorW goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
SOFTWARE NONVOLATILE STORE
The STK11C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initiated,
further input and output are disabled until the cycle
is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL cycle
DEVICE OPERATION
STK11C68
June 1999 4-28
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC <V
RESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH,aRECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
HARDWARE PROTECT
The STK11C68 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When VCC <V
SWITCH, software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READstoWRITEs; 5) the operating
temperature; 6) the Vcc level; and 7) I/O loading.
Figure 2: ICC (max) Reads
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
Figure 3: ICC (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
STK11C68
June 1999 4-29
ORDERING INFORMATION
Temperature Range
Blank = Commercial (0 to 70˚C)
I = Industrial (–40 to 85˚C)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
P = Plastic 28-pin 300 mil DIP
C = Ceramic 28-pin 300 mil DIP
S = Plastic 28-pin 350 mil SOIC
- P 25 I
STK11C68
STK11C68
June 1999 4-30
