X9C303S8IZ - Intersil Corporation

FN8223.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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X9C303

Logarithmic Digitally Controlled Potentiometer (XDCP™)

Terminal Voltage ±5V, 100 Taps, Log Ta per

Description

The Intersil X9C303 is a digitally controlled potenti ometer

(XDCP). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile me mory. The

wiper position is controlled by a three-wire interface.

The resistor array is composed of 99 resistive elements.

Between each element and at either end are tap points

accessible to the wiper terminal. The position of the wiper

element is controlled by the CS, U/D, and INC inputs. The

position of the wiper can be stored in nonvolatile memory

and then be recalled upon a subsequent power-up

operation.

The device can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide vari ety of

applications ranging from control, to signal processing, to

parameter adjustment. Digitally

controlled potentiometers

provide three powerful application advantages; (1) the

variability and reliability of a solid-state potentiometer , (2) the

flexibility of computer-based digital controls, and (3) the use

of nonvolatile memory for potentiometer settings retention.

Features

• Solid-state potentiometer

• Three-wire serial interface

• 100 wiper tap points

- Wiper position stored in nonvolatile memory and

recalled on power-up

• 99 resistive elements, log taper

- Temperature compensated

- End-to-end resistance, 32kΩ ±15%

- Terminal voltages, ±5V

• Low powe r CMOS

-V

CC = 5V

- Activ e current, 3mA max.

- Standby current, 750µA max.

• High reliabili ty

- Endurance, 100 ,000 data changes per bit

- Register data retention, 100 years

• Packages

- 8 Ld TSSOP

- 8 Ld SOIC

- 8 Ld PDIP

• Pb-free available (RoHS co mpliant)

Block Diagram

7-BIT

UP/DOWN

COUNTER

7-BIT

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

ONE

HUNDRED

DECODER RESISTOR

ARRAY

RL/VL

RW/VW

RH/VH

U/D

INC

TRANSFER

VCC

ONE-

GATES

VSS

Data Sheet January 30, 2009

2FN8223.2

January 30, 2009

Pin Descriptions

VH and VL

The high (VH) and low (VL) terminals of the device are

equivalent to the fixed te rminals of a mechanical

potentiometer. The minimum voltage is –5V and the

maximum is +5V. It should be noted that the terminology of

VL and VH references the relative position of th e terminal in

relation to wiper movement direction selected by the U/D

input and not the voltage potential on the terminal.

VW is the wiper terminal, equivalent to the movable terminal

of a mechanical potentiometer . The position of the wiper

within the array is determined by the control inputs. The

wiper terminal series resistance is typically 40Ω.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the counter

in the direction indicated by the logic level on the U/D input.

Chip Select (CS)

The device is selected when the CS input is LOW. The current

counter value is stored in nonvolatile memory when CS is

returned HIGH while the INC input is also HIGH. After the store

operation is complete, the device will be placed in the low

power standby mode until the device is selected once again.

Pinouts X9C303

(8 LD SOIC, 8 LD PDIP)

TOP VIEW

X9C303

(8 LD TSSOP)

TOP VIEW

Ordering Information

PART

NUMBER PART

MARKING TEMP. RANGE

(°C) PACKAGE PKG.

DWG. #

X9C303P X9C303P 0 to +70 8 Ld PDIP MDP0031

X9C303PI X9C303P I -40 to +85 8 Ld PDIP MDP0031

X9C303PIZ (Notes 1, 2) X9C303P ZI -40 to +85 8 Ld PDIP (300 mil) (Pb-free) MDP0031

X9C303PZ (Notes 1, 2) X9C303P Z 0 to +70 8 Ld PDIP (300 mil) (Pb-free) MDP0031

X9C303S8*, ** X9C303S 0 to +70 8 Ld SOIC (150 mil) MDP0027

X9C303S8I* X9C303S I -40 to +85 8 Ld SOIC (150 mil) MDP0027

X9C303S8IZ* (Note 1) X9C303S ZI -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027

X9C303S8Z* (Note 1) X9C303S Z 0 to +70 8 Ld SOIC (150 mil) (Pb-free) MDP0027

X9C303V8*, ** 9C303 0 to +70 8 Ld TSSOP (4.4mm) M8.173

X9C303V8I* C303 I -40 to +85 8 Ld TSSOP (4.4mm) M8.173

X9C303V8IZ* (Note 1) C303 IZ -40 to +85 8 Ld TSSOP (4.4mm) (Pb-free) M8.173

X9C303V8Z* (Note 1) 9C303 Z 0 to +70 8 Ld TSSOP (4.4mm) (Pb-free) M8.173

X9C303S8I-2.7 X9C303S G -40 to +85 8 Ld SOIC (150 mil) MDP0027

X9C303S8IZ-2.7 (Note 1) X9C303S ZG -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027

*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

**Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die att ach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

2. Pb-free PDIPs can be used for through hole wave solder processing only . They are not intended for use in Reflow solder processing applications.

VCC

INC

U/D

VSS

X9C303

VCC

INC

U/D

VSS

X9C303

3FN8223.2

January 30, 2009

Potentiometer Relationships

Principles of Operation

There are three sections of the X9C303: the input co ntrol,

counter and decode section; the nonvolatile memory; and the

resistor array. The input control se ction operates just l ike an

up/down counter. The output of thi s counter is decoded to turn

on a single electronic switch connecting a point on the resistor

array to the wiper output. Under the proper con ditions, the

contents of the counter can be sto red in nonvolatile memory

and retained fo r future use. The resisto r array is comprised of

99 individual resistors connected in series. At ei ther end of the

array and between each resistor is an electronic sw itch that

transfers the potential at that point to the wipe r.

The wiper, when at either fixed terminal, acts like its

mechanical equivalent and does not move beyond the last

position. That is, the counter does not wrap aroun d when

clocked to either extreme.

The electronic switches on the device operate in a “ma ke

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

connected to the wiper for tIW (INC to VW change). The

RTOTAL value for the device can temporarily be reduced by a

significant amount if the wiper is moved several positions.

When the device is powered-down, the last counter position

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled

and the counter is reset to the value last stored.

Instructions and Programming

The INC, U/D and CS input s control the movement of the

wiper along the resistor array. With CS set LOW, the device is

selected and enabled to respond to the U/D and INC input s.

HIGH to LOW transitions on INC will increment or decrement

(depending on the st ate of th e U/D in put) a seven-bit counter.

The output of this counter is decoded to select on e of

one-hundred wiper positions along the re sistive arra y.

The value of the counter is stored in no nvolatile memory

whenever CS transitions HIGH while the INC input is also

HIGH.

The system may select the X9C303, move the wiper, and

deselect the device without having to store the latest wiper

position in nonvolatile memory. The wiper movement is

performed as previously described ; once the new position is

reached, the system would the keep INC LOW while taking

CS HIGH. The new wiper position would be maintained until

changed by the system or until a power-down/up cycle

recalled the previously stored data.

This would allow the system to always power-up to a preset

value stored in nonvolatile memory; then during system

operation minor adjustments could be made. The

adjustments might be based on user preference: system

parameter changes due to temperature drift, etc.

The state of U/D may be changed while CS remains LOW.

This allows the host system to enable the device and then

move the wiper up and down until the proper trim is attained.

Pin Names

SYMBOL DESCRIPTION

VHHigh Terminal (Potentiometer)

VWWiper Terminal (Potentiometer)

VLLow Terminal (Potentiometer)

VSS Ground

VCC Supply Voltage

U/D Up/Down Control Input

INC Increment Control Input

CS Chip Select Control Input

NC No Connection

(VS)R99

R98

S100

S99

S98

Gi20LogR1R2. . . Ri

+++

RTOTAL

------------------------------------------------- VW

--------- V L0V=()==

R1R2. . . R99

+++ R

TOTAL

(REFER TEST CIRC UIT 1)

Mode Selection

CS INC U/D MODE

L H Wiper Up

L L Wiper Down

H X Store Wiper Position

H X X Standby Current

L X No Store, Return to Standby

L H Wiper Up (not recommended)

L L Wiper Down (not recommended)

X9C303

4FN8223.2

January 30, 2009

Symbol Table

Typical Electrical Taper

WAVEFORM INPUTS OUTPUTS

Must be

steady Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

100

% TOTAL RESISTANCE

TAP

R(VH - VW)

R(VW - VL)

Test Circuit #1

TEST POINT

Test Circuit #2

FORCE

TEST POINT

CURRENT

Circuit #3 SPICE Macro Model

RTOTAL

RHRL

10pF

25pF

X9C303

5FN8223.2

January 30, 2009

Absolute Maximum Ratings Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V

Voltage on VH and VL Referenced to VSS . . . . . . . . . . . . -8V to +8V

ΔV = |VH - VL| X9C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V

Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

Recommended Operating Conditions

Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C

Military Temperature Range. . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

Power Rating at +25°C X9C303 . . . . . . . . . . . . . . . . . . . . . . .10mW

Physical Characteristics

Marking Includes

Manufacturer’s Trademark

Resistance Value or Code

Date Code

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

Analog Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

SYMBOL PARAMETER TEST CONDITIONS

LIMITS

UNITMIN TYP

(Note 3) MAX

RTOTAL End-to-End Resistance 32 κΩ

End-to-End Resistance Tolerance -15 +15 %

VHVH Terminal Voltage -5 +5 V

VLVL Terminal Voltage -5 +5 V

RWWiper Resistance Max Wiper Current ±1mA 40 100 Ω

Tap Position Relative Step Size Err or Error = log (Vw(n)) - log (Vw(n - 1))

for tap n = 2 - 99, VH-VL = 10V 0.005 0.115 dB

Resistor Noise At 1kHz 23 nV(RMS)/

√Hz

Charge Pump Noise At 850kHz 20 mV(RMS)

End-to-End Resistance

Temperature Coefficient T = -40°C to +85°C ±400 ppm/°C

Ratiometric Temperature Coefficient Tap position 84 ±20 ppm/°C

CH/CL/CW

(Note 5) Potentiometer Capacitance See “Circuit #3 SPICE Macro Model” on

page 4 10/10/25 pF

X9C303

6FN8223.2

January 30, 2009

DC Electrical Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

SYMBOL PARAMETER TEST CONDITIONS

LIMITS

UNITMIN TYP

(Note 3) MAX

ICC Vcc Active Current CS = VIL, U/D = VIL or VIH and

INC = 0.4V to 2.4V @ Max tCYC 13mA

ISB Standby Supply Current CS = VCC - 0.3V , U/D and INC =V

SS or

VCC - 0.3V 200 750 µA

ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC -10 +10 µA

VIH CS, INC, U/D Input HIGH Voltage 2 V

VIL CS, INC, U/D Input LOW voltage 0.8 V

CIN (Note 5) CS, INC, U/D Input Capacitance VCC = 5V, VIN = VSS,

TA = +25°C, f = 1MHz 10 pF

EEPROM SPECS

EEPROM Endurance Wiper storage operations over

recommended operation conditions 100,000 Cycles

EEPROM Retention At +55°C 100 Years

NOTES:

3. Typical values are for TA = +25°C and nominal supply voltage.

Standard Parts

PART NUMBER MAXIMUM RESISTANCE WIPER INCREMENTS MINIMUM RESISTANCE

X9C303 32kΩLog Taper 40Ω Typical

AC Conditions of Test

Input Pulse Levels 0V to 3V

Input Rise and Fall Times 10ns

Input Reference Levels 1.5V

AC Electrical Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

SYMBOL PARAMETER

LIMITS

UNITMIN TYP

(Note 4) MAX

tCl CS to INC Set-up 100 ns

tlD INC HIGH to U/D Change 100 ns

tDI U/D to INC Set-up 2.9 µs

tlL INC LOW Period 1 µs

tlH INC HIGH Period 1 µs

tlC INC Inactive to CS Inactive 1 µs

tCPH CS Deselect Time 20 ms

tIW (Note 5) INC to VW Change 100 µs

tCYC INC Cycle Time 2 µs

X9C303

7FN8223.2

January 30, 2009

AC Timing Diagram

NOTES:

4. Typical values are for TA = +25°C and nominal supply voltage.

5. This parameter is not 100% tested.

6. MI in the “AC Timing Diagram” refers to the minimum incremental change in the VW output due to a change in the wiper position.

tR, tF (Note 5) INC Input Rise and Fall Time 500 ns

tPU (Note 5) Power-up to Wiper Stable 500 µs

tR VCC (Note 5) VCC Power-up Rate 0.2 50 mV/µs

AC Electrical Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested. ( Continued)

SYMBOL PARAMETER

LIMITS

UNITMIN TYP

(Note 4) MAX

INC

U/D

tCI tIL tIH

tCYC

tID tDI

tIW

tIC tCPH

tFtR

10%

90% 90%

(NOTE 6)

X9C303

8FN8223.2

January 30, 2009

X9C303

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

0.05(0.002)

M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N8 87

α0o8o0o8o-

Rev. 1 12/00

9FN8223.2

January 30, 2009

X9C303

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8223.2

January 30, 2009

X9C303

Plastic Dual-In-Line Packages (PDIP)

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL

INCHES

TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

Rev. C 2/07

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

NOTE 5

SEATING

PLANE

PIN #1

INDEX

12 N/2