CX28395-19 - Conexant Systems, Inc.

Data Sheet 100054E

June 2000

CX28394/28395/28398

Quad/x16/Octal—T1/E1/J1 Framers

The CX28394/28395/28398 is a family of multiple framers for T1/E1/J1 and Integrated

Service Digital Netw ork (ISDN) primary r ate interfaces operating at 1.544 Mbps o r 2.048

Mbps. All framers are totally independent, and each combines a sophisticated framing

synchronizer and transmit/receive slip buffers. Operations are controlled through a

series of memory-mapped registers accessible via a parallel microprocessor port.

Extensive register support is provided for alarm and error monitoring, signaling

supervision (including ISDN D-channel/SS7 process), per-channel trunk conditioning,

and Facility Data Link (FDL) maintenance. A flexible serial Time Division Multiplexed

(TDM) system interface that supports bus rates from 1.536 to 8.192 MHz is featured.

Extensive test and diagnostic functions include a full set of loopbacks, Pseudo Random

Bit Sequence (PRBS) test pattern generation, Bit Error Rate (BER) meter, and forced

error insertion.

Functional Block Diagram

Distinguishing Features

• Up to 16 T1/ E1/J1 Framers in one

package

• Extensive support of various

protocols

• T1: SF , ESF, SL C®9 6, T1 DM ,

TTC JT(J1)

• E1: PCM-30, G.704, G.706, G.732,

ISDN primary rate (ETS300 011,

INS 500)

• Extracts and inserts signalin g bits

• Dual HDLC contro llers pe r framer for

data link and LAPD/SS7 signaling

• T wo-fram e tran smit an d recei ve PCM

slip buffers

• Separate or multiplexed system bus

interfaces

• Paralle l 8-bit microprocessor port

supports Intel or Motorola buses

• BERT generation and c ounting

• B8ZS/ HDB3/B it 7 zero suppression

(CX28394 and CX28398 only)

• Operates from a single + 3. 3 Vdc

± 5% power supply

• Low -p ow e r CM OS t ech nology

Applications

• Multiline T1/E1 Channel Service

Unit/Data Service Unit (CSU/DSU)

• Digital Access Cr oss-Connect

System (DACS)

• T1/E 1 Mu ltiplexe r (MUX )

• PBXs and PC M channel bank

• ISDN Primary Rate Access (PRA)

• Frame Relay Switches and Access

Devices (FRADS)

• SONET/ SD H add/drop multipl exers

• T3/E3 channelized access

concentrators

ZCS*

Decode

Receive

Dual Rail or

NRZ

Receive

Dual Rail or

NRZ

Slip

Buffer

Slip

Buffer

T1/E1

Receive

Framer

ZCS*

Encode

T1/E1

Transmit

Framer

Overhead

Insertion

Control/Status

Registers

JTAG

Data Link Controllers

DL1+DL2

Motorola/Intel

Processor Bus

Test Por t

External Data Link

DL3*

Receive

System

Bus

Transmit

System

Bus

Framer #1

Framer #N

8394-8-5_019

F r amer #N

CX28394 - 4 F r ames

CX28398 - 8 F r ames

CX28395 - 16 F r ames

* CX28394 and CX28398 only.

100054E Conexant

Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are

provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no

responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at

any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for

conflicts or incompatibilities arising from future changes to its specifications and product descriptions.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as

provided in Conexant’s Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever.

THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING

TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A

PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY

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ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE

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DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE

OF THESE MATERIALS.

Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling

Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages

resulting from such improper use or sale.

The following are trademarks of Conexant Systems, Inc.: Conexant™, the Conexant C symbol, and “What’s Next in Communications

Technologies”™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of

third parties. Third-party brands and names are the property of their respective owners.

For additional disclaimer information, please consult Conexant’s Legal Information posted at www.conexant.com,whichis

incorporated by reference.

Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and

suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications

engineer.

CX28398EVM—Evaluation Module, Octal T1/E1 ISDN PRI Board

Local PCM Highway (i.e., 2 @ 8192 kbps)

Address

Data 12

Microprocessor

Bus

T1 or E1 Connection at DSX Levels

CX28398 (Octal T1/E1 Framer)

Bus

Quad T1/E1 LIU (CX28380) Quad T1/E1 LIU (CX28380)

8394-8-5_012

100054E Conexant

Typ ical Quad T1/E1 Application

Typ ical x16 T1/E1 Application

Ordering Information

Local PCM Highway (8192 kbps)

Address

Data

Microprocessor

Bus

T1 or E1 Connection at DSX Levels

CX28394 (Octal T1/E1 Framer)

Bus

CX28380 (Quad LIU)

8394-8-5_015

Local PCM Highways 32 at 1536 kbps to 8 at 8192 kbps)

Address

Data 12

Microprocessor

Bus

T1 or E1 Line Interfaces, SONET/SDH Mapper or M13/E13 Mux

CX28395 ( x16 T1/E1 Framer)

Bus CX28395 ( x16 T1/E1 Framer)

Chip

Selects

8394-8-5_014

Model Number Number of Framers Package Operating Temperature

CX28394-22 4 128-pin TQFP –40 to 85 °C

CX28398-22 8 208-pin PQFP –40 to 85 °C

CX28 398-23 8 272-pin BGA –40 to 85 °C

CX28395-19 16 318-pin BGA –40 to 85 °C

CX28395-18 16 318-pin BGA 0 to 70 °C

CX28398-24 8 208-pin CABGA –40 to 85 °C

BT00 -D 66 0- 001 CX28398/CX2 83 80 Ev a lu a t io n Mod ule

100054E Conexant

Detailed Feature Summary

Frame Alignment

• Framed formats:

– Indepen dent transmit and recei ve

framing modes

– T1: FT/SF/ESF/SLC/T1DM/TTC-JT(J1)

– E1: FAS/MFAS/FAS+CAS/MFAS+CAS

• Maximum Average Reframe Time

(MART) less than 50 ms

• Transmitter alignment modes:

– Align to system bus data

– Align to system bus sync

– Alig n to bu ffe r data (emb edd ed

framing)

• Unframed mode

Signaling

• T1: 2-, 4-, or 16-stat e robbed bit

ABCD signaling

• E1: Chan nel Associated Sig naling

(CAS)

• Com m on Ch a nnel Signalin g (CCS) in

any time slot

• Per-channel receiv e signaling stack

• Signaling st ate change int errupt

• Automatic and manual signaling

freeze

• Deboun ce signaling (2-bit

integration)

• UNICODE detection

• Signaling reinsertion on PCM system

bus

• S epa rat e I /O fo r sys te m bu s s ign al in g

• Per-c hannel t ransparent

Loopbacks

• Rem ote loop ba c k toward line

– Retains BPV transparency

(CX28394 and CX28398 only)

• Payload loopback

• Per- c hannel DS0 remote loopback

• Local loopback towards system

– Framer digital loopback

– Per- channel DS0 local loopback

• Inba nd loop ba c k code detec tio n/

generation

• Simultaneous local and remote line

loopbacks

Processor Interface

• Paral lel 8-bit bus

• Data strob es (Motorola) or add r ess

latch enable (Intel)

• Multiplexed or non-multiplexed

address /data bus

• Synchronous or asynchronous

data transfers

• Ope n dra in inte rr u pt ou tpu t w ith

maskable sources

Out-of -Service Testing

and Ma intenance

• Pseudo-Random Bit Sequence

(PRBS):

– Independent transmit an d receive

–2

11; 215; 220; 223 patterns

– Framed or unframed mode

– Optional 7/14 zero limit

– Bit Error Counter (BERR)

• Single error insertion:

– PRBS er ror

– Framing error

– CRC error

– BPV/ LCV error (CX28394 and

CX28398 onl y )

– COFA error

Syste m Bus Int erfa c e (SBI)

• Sys tem b u s data rates:

– 1536 kbps ( T1 without F-b i t s)

– 1544 kbps (T1)

– 2048 kbps (E1)

– 4096 kbps (2E1)

– 8192 kbps (4E1)

• Clock operation at 1x or 2x data rate

• Select able I/O clock edges

• Master, slave, or mixed bu s t iming

• Bit and time slot frame sync offsets

• DS0 drop/insert indicators for

external mux

• Embedded T1 framing transpor t

per G. 802

• Receive and transmit slip buffers

– Bypass, 2- frame, or 64-bit depth

– Slip detection with directional

status

– Slip buffer phase status

– Per-c hannel idle code insertion

– Processor accessible d a t a buffers

• Direct connection to upper layer

devices:

– Lin k la y er: Bt84 74

– ATM layer: CN8228

• Direct connection to physical line

interface

– CX28380

• Supported system bus formats:

– ATT Concen tration Highway

Interface (CHI)

– Multi-Vendor Integration Protocol

(MVIP)

–Mitel ST-bus

• Separate or internally multiplexed

bus modes

In-Service

Perfor mance Monitoring

• One-seco nd t imer I/O to synchronize

reporting

• Receive error det ectors with

accumulators:

– Bipolar/Line Cod e Violations

(LCV ) (CX283 94 and CX28398

only)

– Excessive Zeros (EXZ)

– Loss of Frame (RLOF)

– Framing Errors (FERR)

– CRC Errors (CERR)

– Far End Block Errors (FEBE)

– Severely Errored Fra mes (S EF)

– Change of Fra me Al ignment

(COFA)

• Transmit error detectors:

– Loss of Frame (TLOF)

– Framing Errors (TFERR)

– Multiframe Errors (TMERR)

– CRC Errors (TCERR)

– Loss of Tra nsmit Clock (TLOC)

• Receive alarm detectors:

– Alarm Indication Signal (AIS)

– Loss of Sig nal (RLOS)

– RAI/Ye l low Al arm (YEL )

– Multiframe Yellow (MYEL)

– Lost Frame Al ignment (FRED)

– Lost Multiframe Alignment

(MRED)

– Carrier Failure Alarm (CFA) with

8:1 dual slope integration

• Controlled Frame Slip (R FSLIP)

Uncontrol led Frame Slip (RUS LIP)

• Automatic and on-demand tr ansmit

alarms:

– AIS following RLOS and/or TLOC

– Automatic AIS clock switching

– YEL followi ng FRED

– YEL fol lowing 100ms reframe

timeout

– MYE L fol lowing MRE D

– FEB E followin g CERR

100054E Conexant

Data Links

• Two full-featured data link controllers

(DL1 and DL2):

– 64-octet transmit and receive

FIFOs

– HD LC Message Oriented P r otocol

(MOP)

– Unformatted data tran sfer

– Unformatted circular buffer

– End of message/buffer interrupt

– Near full/empty interrupts at

selecte d depth

• Access any bit combinat ion in any

time slot:

– ISDN D-channels at 16, 32, or 64

kbps

– National/spare bit s (SA-bits) in 4

kbps increm ents

– CCS/SS7

– T1DM R-bits

• Access T1 F-b it s in even, odd, or all

frames:

– Automatic Performance Report

Message (PRM) generator

– ESF Facility Data Link (FDL)

– Unformatted SLC-96 over head

– Bit-Oriented Protocol (BOP)

priority codeword gener ation and

detection

• Separate I/O for external data link

(DL3) on CX28394 and CX28398

devices

100054E Conexant

100054E Conexant vii

Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.1 External Datalink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.2 RINDO/TINDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1. 3 LIU S erial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.1.4 Transmit/Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2.0 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Functional Blo ck Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.1 ZCS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.2 In-Band Loopback Code Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.3 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.3.1 Frame Bit Error Count er. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.3.2 CRC Erro r Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.3.3 LCV Error Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.3.4 FEB E Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.4 Error Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2. 4.1 Frame Bit Err or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.4.2 MFAS Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2. 4.3 CAS Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.4.4 CRC Erro r. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.4.5 Pulse Density Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table of Cont ents CX28394/28395/28398

Quad/x16/Octal—T1/E1/J1 Framers

viii Conexant 100054E

2.2.5 Alarm Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.5.1 Loss of Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.5.2 Loss of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.5.3 Receive Analog Loss of Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.5.4 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2. 5.5 Yellow Alar m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2. 5.6 Multiframe YEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.5.7 Severely Errored Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.5.8 Change of Frame Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.5.9 Receive Multiframe AIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.6 Test Pattern Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.7 Receive Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.8 External Receive Data Link (CX28394 and CX28398 Only) . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.9 Sa-Byte Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.10 Receive Data Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.2.10.1 Data Link Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.2.10.2 RBOP Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3 System Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.3.1 Non-Multiplexed Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.3.2 Externally Multiplexed Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.3.3 Internally Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.3.4 Receive System Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.4.1 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.3. 4.2 Slip Buf f er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.3. 4.3 Signaling Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.3. 4.4 Signaling Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.3.4.5 Embedded Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.3.5 Transmit System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.3.5.1 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2.3. 5.2 Slip Buf f er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2.3. 5.3 Signaling Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2.3.5.4 Transmi t Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2.3.5.5 Embedded Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

2.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

2.4.1 External Transmit Data Link (CX28394 and CX28398 Only) . . . . . . . . . . . . . . . . . . . . . . 2-41

2.4.2 Transmit Data Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.4.2.1 Data Link Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.4.2.2 Circular Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.4.2.3 Time Slot and Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.4.2.4 Transmit Data Link FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.4.2.5 End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.4.2.6 Pro gramming th e Data Link Co ntroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.4.2.7 PRM Gener ator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

2.4.2.8 TBOP Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

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2.4.3 Sa-Byte Overwrite Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

2.4.4 Overhead Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

2.4.4.1 Framing Pat tern Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

2.4.4.2 Alarm Ge neration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

2.4.4.3 CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

2.4.4.4 Far-End Bloc k Error Gen eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

2.4.5 Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.4.6 Transmit Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.4.7 In-Band Loopback Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

2.4.8 ZCS Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

2.5 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

2.5.1 Address/Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

2.5. 2 Bus Co nt rol Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

2.5.3 Interrupt Request s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

2.5.4 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58

2.6 Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 9

2.6.1 Remote Line Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

2.6.2 Remote Payload Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

2.6.3 Remote Per-Channel Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

2.6.4 Local Framer Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

2.6.5 Local Per-Channel Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

2.7 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

2.8 Joint Test Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

2.8.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

2.8.2 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

000—Device Identification (DID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

080—Framer Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

081—Master Interrupt Request (MIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

082—Master Interrupt Enable (MIE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

083—Te st Co nfiguration (TE ST ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.3 Primary Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

001—Primary Control Register (CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.4 Interrupt Co ntrol R egis t er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

003—Interrupt Request Register (IRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

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3.5 Interrupt Status R egiste rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

004—Alarm 1 Interrupt Status (ISR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

005—Alarm 2 Interrupt Status (ISR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

006—Error Interrupt Status (ISR5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

007—Counter Overflow Interrupt Status (I SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

008—Timer Interrupt Status (ISR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

009—Data Link 1 Interrupt Status (ISR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

00A—Data Link 2 I nterrupt St atus (I SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

00B—Patter n Interrupt Status (ISR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.6 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

00C—Alarm 1 Interrupt Enable Register (IER7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

00D—Alarm 2 Interrupt Enable Register (IER6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

00E—Error Interrupt Enable Register (IER5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

00F—Count Overflow Interrupt Enable Register (IER4) . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

010—Timer Interrupt Enable Register (IER3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

011—Data Link 1 Interrupt Enable Register (IER2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

012—Data Link 2 Interrupt Enable Register (IER1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

013—Pattern Interrupt Enable Register (IER0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.7 Primary Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

014—Loopback Configuration Register (LOOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

015—External Data Link Time Slot (DL3_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

016—External Data Link Bit (DL3_BIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

017—Offline Framer Status (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

018—Programm abl e Inpu t/Output (PIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

019—Programmable Output Enable (POE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

01A—Clock Input Mux (CMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34

020—Receive Alarm Configuration (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34

021—Receive Line Code Status (RSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

3.8 Serial Interface Registe rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

022—Serial Control (SER_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

023—Serial Data (SER_DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

024—Serial Status (SER_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

025—Serial Config uration (SER_C ONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

026—RAM Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

3.9 Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

040—Receiver Configuration (RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

041—Receive Test Pattern Configuration (RPATT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

042—Receive Loopback Code Detector Configuration (RLB) . . . . . . . . . . . . . . . . . . . . . 3-40

043—Loopback Activate Code Pattern (LBA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

044—Loopback Deactivate Code Pattern (LBD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

045—Receive Alarm Signal Configuration (RALM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

046—Alarm/Error/C oun ter Latch Config urat i on (LATCH). . . . . . . . . . . . . . . . . . . . . . . . 3-44

047—Alarm 1 Status (ALM1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

048—Alarm 2 Status (ALM2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47

049—Alarm 3 Status (ALM3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48

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3.10 Performance Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

050—Framing Bit Error Counter LSB (FERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

051—Framing Bit Error Counter MSB (FERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

052—CRC Error Counter LSB (CERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

053—CR C Error Counter MSB (CERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

054—L ine Code Viol ation Counter LSB (LCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

055—L in e Code Violati on Counter MSB ( LCV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

056— Far En d Block Error Counte r LSB (FEBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

057— Far End Block Error Counter MSB (FEBE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

058—PRBS Bit Error Counter LSB (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

059—PRBS Bit Err or Counter MSB (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51

05A—SEF/FRED/CO FA Alarm Counter (AERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51

3.11 Receive Sa-Byte Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

05B—Receive Sa4 Byte Buffer (RSA4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

05C—Receive Sa5 Byte Buffer (RSA5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

05D—Receive Sa6 Byte Buffer (RSA6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

05E—Receive Sa7 Byte Buffer (RSA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

05F—Receive Sa8 Byte Buffer (RSA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54

3.12 Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55

070—Transmit Framer Configuration (TCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55

071—Transmitter Configuration (TCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

072—Transmit Frame Format (TFRM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61

073—Transmit Error Insert (TERROR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

074—Transmit Manual Sa-Byte/FEBE Configuration (TMAN) . . . . . . . . . . . . . . . . . . . . . 3-63

076—Transmit Test Pattern Configuration (TPATT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

077—Transmit Inband Loopback Code Configuration (TLB). . . . . . . . . . . . . . . . . . . . . . 3-66

078—Transmit Inband Loopback Code Pattern (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

3.13 Transmit Sa-Byte Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

07B—Transmit Sa4 Byte Buffer (TSA 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

07C—Transmit Sa5 Byte Buffer (TSA 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

07D—Transmit Sa6 Byte Buffer (TSA6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69

07E—Transmit Sa7 Byte Buffer (TSA7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69

07F—Transmit Sa8 Byte Buffer (TSA8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

3.14 Bit-Orien t ed Pro t ocol R egist er s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71

0A0—Bit Oriented Protocol Transceiver (BOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71

0A1— Tr ansmit BOP Code word (TBOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73

0A2—Receive BOP Codeword (RBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73

0A3— BOP Status (BOP_STAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74

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3.15 Data Link Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75

0A4—DL1 Time Slot Enable (DL1_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75

0A5—DL1 Bit Enable (DL1_BIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

0A6—DL1 Control (DL1_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

0A7—RDL #1 FIFO Fill Control (RDL1_FFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77

0A8—Receive Data Link FIFO #1 (RDL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79

0A9—RDL #1 Status ( RDL1_ STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

0AA—Performance Report Message (PRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81

0AB—TDL #1 FIFO Empty Co ntrol (TDL1_FEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82

0AC—TDL #1 End Of Message Control (TDL1_EOM). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

0AD—Transmit Data Link FIFO #1 (TDL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

0AE—TDL #1 Status (TDL1_STAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

0AF—DL2 Time Slot Enable (DL2_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84

0B0—DL2 Bit Enable (DL2_BIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85

0B1—DL2 Control (DL2_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85

0B2—RDL #2 FIFO Fill Control (RDL2_FFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87

0B3—Receive Data Link FIFO #2 (RDL2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88

0B4—RDL #2 Status ( RDL2_ STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89

0B6—TDL #2 FIFO Empty Contro l (TDL2_FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90

0B7—TDL #2 End Of Message Control (TDL2_EOM). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90

0B8—Transmi t Data Link FI FO #2 (TDL 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91

0B9—TDL #2 Status (TDL2_STAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91

0BA—DLINK Test Configuration (DL_TEST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92

0BB—DLIN K Test Status (DL_TEST2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92

0BC—DLIN K Test Status (DL_TEST3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92

0BD— DLINK Te st Cont rol #1 or Configurati on #2 (DL_TEST4) . . . . . . . . . . . . . . . . . . . 3-92

0BE—DLINK Test Control #2 or Confi gurat ion #2 (DL_TEST5). . . . . . . . . . . . . . . . . . . . 3-93

3.16 System Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

0D0—System Bus Interface Configuration (SBI_CR). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

0D1—Receive System Bus Configuration (RSB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96

0D2—RSB Sync Bit Offset (RSYNC_BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97

0D3—RSB Sync Time Slot Offset (R SYNC_TS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98

0D4—Transmit System Bus Configuration (TSB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99

0D5—TSB Sync Bit Offset (TSYNC_BIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

0D6—TSB Sync Time Slot Offset (TSYNC_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101

0D7—Receive Signaling Configuration (RSIG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

0D8—Signaling Reinsertion Frame Offset (RSYNC_FRM) . . . . . . . . . . . . . . . . . . . . . . 3-104

0D9—Slip Buffer Status (SSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105

0DA—Receive Signaling Stack (STACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

0DB—RSLIP Phase Status (RPHASE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108

0DC—TSLIP Phase Status (TPHASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108

0DD—RAM Parity Status (PERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109

0E0–0FF—System Bus Per-Channel Control (SBCn; n = 0 to 31) . . . . . . . . . . . . . . . . . 3-109

100–11F—Transmit Per-Channel Control (TPCn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . 3-110

120–13F—Transmit Signaling Buffer (TSIGn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . . . 3-112

CX28394/28395/28398 Table of Contents

Quad/x16/Octal—T1/E1/J1 Framers

100054E Conexant xiii

140–15F—Transmit PCM Slip Buffer (TSLIP_LOn; n = 0 to 31) . . . . . . . . . . . . . . . . . . 3-112

160–17F—Trans m it PCM Slip Buffer (TSLIP_HIn; n = 0 to 31). . . . . . . . . . . . . . . . . . . 3-113

180–19F—Receive Per-Channel Control (RPCn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . 3-113

1A0–1BF—Receive Signaling Buffer (RSIGn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . . . . 3-115

1C0–1DF—Receive PCM Slip Buffer (RSLIP_LOn; n = 0 to 31) . . . . . . . . . . . . . . . . . . 3-115

1E0–1FF—Receive PCM Slip Buffer (RSLIP_HIn; n = 0 to 31) . . . . . . . . . . . . . . . . . . . 3-116

3.17 Register Su mmary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117

4.0 Electrical/Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Absolute Maximum Rating s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Recomm ende d Operating Condition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.4 AC Char acteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.5 MPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.6 System Bus Interface (SBI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

4.7 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

4.8 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1 Superframe Format (SF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 T1DM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

A.3 SLC 96 Format (SLC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

A.4 Extended Superframe Format (ESF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

A.5 E1 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

A.6 IRSM CEPT Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Appendix C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.1 System Bus Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.1.1 AT&T Concentration Highway Interface (CHI):. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.1.2 CHI Programming Options:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

Appendix D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

D.1 Notation and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

D.1.1 Arithmetic Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1

D.2 Acronyms and A bbreviati ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

Appendix E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

E.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

Table of Cont ents CX28394/28395/28398

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xiv Conexant 100054E

CX28394/28395/28398 List of Figures

Quad/x16/Octal—T1/E1/J1 Framers

100054E Conexant xv

List of Figures

Figure 1-1. CX28395 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Figure 1-2. CX28394 128-pin TQFP Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 1-3. CX28395 318-pin BGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-4. CX28398 208-pin PQFP Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Figure 1-5. CX28398 208-pin CABGA Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Figure 1-6. CX28398 272-pin BGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Figure 1-7. CX28394 Logic Diagram (Non-Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 1-25

Figure 1-8. CX28394 Logic Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . . . . . 1-26

Figure 1-9. CX28398 Logic Diagram (Non-Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 1-27

Figure 1-10. CX28398 Logic Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . . . . . 1 -28

Figure 1-11. CX28395 Logic Diagram (Non-Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 1-29

Figure 1-12. CX28395 Logic Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . . . . . 1 -30

Figure 2-1. Detailed Framer Block Diagram (Multiplexed System Bus Mode) . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2. Detailed Framer Block Diagram (Non-multiplexed System Bus Mode) . . . . . . . . . . . . . . . . 2-3

Figure 2-3. RCVR Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4. Receive External Data Link Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Figure 2-5. Polled Receive Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Figure 2-6. Interrupt-Driven Receive Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Figure 2-7. Externally Multiplexed Configuration Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Figure 2-8. Internally Multiplexed Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

Figure 2-9. RSB Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Figure 2-10. RSB 4096K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

Figure 2-11. RSB 8192K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

Figure 2-12. RSB Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Figure 2-13. T1 Line to E1 System Bus Time Slot Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Figure 2-14. G.802 Embedded Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Figure 2-15. TSB Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

Figure 2-16. Transmit System Bus Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

Figure 2-17. TSB 4096K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Figure 2-18. TSB 8192K Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Figure 2-19. Transmit Framing and Timebase Alignment Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -37

Figure 2-20. XMTR Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -40

Figure 2-21. Transmit External Data Link Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

Figure 2-22. Pol led Transmit Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

Figure 2-23. Interrupt-Driven Transmit Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

Figure 2-24. Zero Code Substitution Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -52

Figure 2-25. Transmit Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Figure 2-26. NRZ Mode Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Figure 2-27. Microprocessor Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

List of Figures CX28394/28395/28398

Quad/x16/Octal—T1/E1/J1 Framers

xvi Conexant 100054E

Figure 2-28. Interrupt Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57

Figure 2-29. Seri al Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

Figure 2-30. Test Access Port (TAP) Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62

Figure 4-1. Minimum Clock Pulse Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-2. Input Data Setup/Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Figure 4-3. Output Data Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Figure 4-4. One-Second Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

Figure 4-5. Motorola Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Figure 4-6. Motorola Asynchronous Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Figure 4-7. Intel Asynchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10

Figure 4-8. Intel Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11

Figure 4-9. Motorola Synchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Figure 4-10. Motorola Synchronous Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Figure 4-11. Intel Synchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Figure 4-12. Intel Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -15

Figure 4-13. Serial Control Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Figure 4-14. Serial Control Port Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Figure 4-15. Serial Control Port Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Figure 4-16. SBI Timing—1536K Mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18

Figure 4-17. SBI Timing—1544K Mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19

Figure 4-18. SBI Timing—2048K Mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20

Figure 4-19. SBI Timing—4096K Mode(1),(5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -21

Figure 4-20. SBI Timing—8192K Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22

Figure 4-21. SBI Timing—Eight Clock Edge Combinations (Applicable to Any SBI Mode) . . . . . . . . . . 4-23

Figure 4-22. JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Figure 4-23. 318-Pin Ball Grid Array (BGA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -25

Figure 4-24. 272-Pin Ball Grid Array (BGA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -26

Figure 4-25. 208-Pin Ball Grid Array (CABGA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

Figure 4-26. 208-Pin Plastic Quad Flat Pack (PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

Figure 4-27. 128-Pin (TQFP) Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

Figure A-1. T1 Superframe PCM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Figure A-2. T1 Extended Superframe Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5

Figure A-3. E1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

CX28394/28395/28398 List of Tables

Quad/x16/Octal—T1/E1/J1 Framers

100054E Conexant xvii

List of Tables

Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -9

Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -11

Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Table 1-5. Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Table 1-6. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Table 2-1. Receive Framer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-2. Criteria for Loss/Recover y of Receive Framer Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Table 2-3. Commonly Used Data Link Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Table 2-4. RSB Interface Time Slot Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-27

Table 2-5. Commonly Used Data Link Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Table 2-6. Yellow Alarm Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

Table 2-7. Microprocessor Interface Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

Table 2-8. JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

Table 2-9. CX28394 Device Identification JTAG Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Table 2-10. CX28395 Device Identification JTAG Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Table 2-11. CX28398 Device Identification JTAG Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Table 3-1. Address Offset Map (CX28394). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3-2. Address Offset Map (CX28398). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3-3. Address Offset Map (CX28395). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-4. Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Table 3-5. Receive Framer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Table 3-6. Interrupt Status Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15

Table 3-7. Counter Overflow Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

Table 3-8. Maximum Average Reframe Time (MART) and Framer Timeout. . . . . . . . . . . . . . . . . . . . . 3-30

Table 3-9. System Bus Sync Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Table 3-10. Common TFSYNC and TMSYNC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Table 3-11. Common RFSYNC and RMSYNC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

Table 3-12. Receive PRBS Test Pattern Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

Table 3-13. Receive Yellow Alarm Set/Clear Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42

Table 3-14. Recei ve Yellow Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

Table 3-15. E1 Transmit Framer Modes (T1/E1N = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56

Table 3-16. T1 Transmit Framer Modes (T1/E1N = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

Table 3-17. Criteria for E1 Loss/Recovery of Transmit Frame Alignment. . . . . . . . . . . . . . . . . . . . . . . . 3-57

Table 3-18. Criteria for T1 Loss/Recovery of Transmit Frame Alignment. . . . . . . . . . . . . . . . . . . . . . . . 3-58

Table 3-19. Transmit Framer Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

Table 3-20. Transmit Zero Code Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

Table 3-21. Transmit PRBS Test Pattern Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66

Table 3-22. DLI Configuration for T1-ESF, FDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -71

List of Tables CX28394/28395/28398

Quad/x16/Octal—T1/E1/J1 Framers

xviii Conexant 100054E

Table 3-23. Remote DS0 Channel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111

Table 3-24. Signaling Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111

Table 3-25. Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-117

Table 3-26. Primary Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117

Table 3-27. Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117

Table 3-28. Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118

Table 3-29. Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118

Table 3-30. Primary Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119

Table 3-31. Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119

Table 3-32. Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120

Table 3-33. Performance Monitoring Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121

Table 3-34. Receive Sa-Byte Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121

Table 3-35. Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122

Table 3-36. Transmit Sa-Byte Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122

Table 3-37. Bit-Oriented Protocol Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123

Table 3-38. Data Link Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123

Table 3-39. System Bus Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-124

Table 4-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-2. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -2

Table 4-3. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table 4-4. Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-5. Input Data Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -5

Table 4-6. Output Data Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Table 4-7. One-Second Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Table 4-8. Motorola Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-9. Motorola Asynchronous Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

Table 4-10. Intel Asynchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 4-11. Intel Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Table 4-12. Motorola Synchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Table 4-13. Motorola Synchronous Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13

Table 4-14. Intel Synchronous Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Table 4-15. Intel Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Table 4-16. Host Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Table 4-17. Test and Diagnostic Interface Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Table 4-18. Test and Diagnostic Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Table A-1. Superframe Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Table A-2. T1DM Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Table A-3. SLC-96 Fs Bit Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

Table A-4. Extended Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

Table A-5. Performance Report Message Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

Table A-6. ITU–T CEPT Frame Format Time Slot 0 Bit Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

Table A-7. IRSM CEPT Frame Format Time Slot 0 Bit Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

Table A-8. CEPT (ITU–T and IRSM) Frame Format Time Slot 16 Bit Allocations . . . . . . . . . . . . . . . . . A-11

Table B-1. Applicable Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Table E-1. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

100054E Conexant 1-1

1.0 Product Description

1.1 Overview

The CX2839x devices each contain multiple T1/E1 framers which provide the

data access and framing portion of T1 and E1 physical layer interfaces:

While the framers are identical , there are minor dif ferences among the devices

due to the pins provided. These differences are summarized below.

1.1.1 External Datalink

The CX28394 and CX28398 devices include an External Datalink (DL3) which

provides signal access to any bit(s) in any time slot of all frames, odd frames, or

even frames, including T1 framing bits. Refer to Section 2.2.8, External Receive

Data Link (CX28394 and CX28398 Only), and 2.4.1, External Transmit Data

Link (CX28394 and CX28398 Only). The DL3 signals are not available on the

CX28395 device.

1.1.2 RINDO/TINDO

Receive and Transmit Time Slot Indicator signals are provided by each framer to

mark selected (pro grammabl e) recei ve an d transmit system bus time slots. On the

CX28394 and CX28398 de vices, these sig nals appear on d iff erent pins d epending

on w hether Mu ltiplexed System Bus mode o r Non-Multip lex ed Syst em Bus mode

is selected. On the CX28395, they are available only in Multiplexed Bus mode.

Device Number of Framers

CX28394 4

CX28398 8

CX28395 16

1.0 Product Description CX28394/28395/28398

1.1 Overv iew Quad/x16/Octal—T1/E1/J1 Framers

1-2 Conexant 100054E

1.1.3 LIU Serial Port

The CX28394 and CX28398 devices include a serial interface which allows a

microprocessor to indirectly communicate with a line interface unit such as the

CX28380 Quad T1/E1 LIU. This interface allows the microprocessor to control

and query the LIU status. This serial interface is not available on the CX28395.

1.1.4 Transmit/Receive Line Interface

The CX28394 and CX2839 8 devices inc lu de li ne in terfac es which can operat e in

either of two modes: bipolar NRZ or unipolar NRZ. In bipolar NRZ mode,

receiver signals RPOSI, RNEGI, and RCKI are used; and transmitter signals

TPOSO, TNEGO, and TCKO are used. In unipolar NRZ mode, receiver signals

RNRZ and RCKI are used, and transmitter signals TNRZO and TCKO are used.

The CX28395 device provides only unipolar NRZ operation and signals.

Figure 1-1 illustrates the CX28395 Functional Block Diagram (single framer).

Figure 1-1. CX28395 Functional Block Diagram

8394-8-5_011

Receive NRZ Clock

Transmit NRZ Clock

Receive NRZ Data

Transmit NRZ Data

T1/E1

Receive

Framer

T1/E1

Transmit

Framer

Overhead

Insertion

Slip

Buffer

Slip

Buffer

Data Link Controllers

DL1 + DL2

Receive

System

Bus

Transmit

System

Bus

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-3

1.2 Pin Assignme nts

The CX28394 is packaged in a 128-pi n Quad Flat P ac k (TQFP). The CX 28395 is

packaged in a 318-pin Ball Grid Array (BGA) multi-chip module (MCM). The

CX28398 has two package alternatives: a 208-pin Quad Flat Pack (MQFP) and a

272-pin BGA. Pinout diagrams are provided in Figures 1-2 through 1-6 and

Tables 1-1 through 1-4 summari ze pin assignments for syste m bus pins. Table 1-5

lists all other pin assignments.

Fi gures 1- 7 through 1-12 illustrate the devices’ logic, and Table 1-6 defines

the hardware signals.

The foll owing input pi ns co nt ain an i nt ernal pul lu p r esi sto r (>5 0 k Ω) and may

remain unconnected if the active high input state is desired:

A[7:0] Address lines unused in INTEL bus mode.

MOTO* Pullup selects INTEL bus mode if unconnected.

SYNCMD Pullup selects synchronous processor interface.

TDI (CX28394/28398) JTAG unused if not connected.

TDI1, TDI2 (CX28395) JTAG unused if not connected.

TMS JTAG unused if not connected.

TCK Disables JTAG if not conne ct e d.

TRST* Disables JTAG reset if no t c onnected.

RST* Disables hardware reset if not connected.

SERDI May be left unconnected if not used.

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-4 Conexant 100054E

Figure 1-2. CX 2839 4 128-pin TQFP Pinout Diagram

CX28394

VSS

VDD

VSS

TINDO[2] / TDLCKO[2]

TSIGI[2] / TDLI[2]

TSBCKI[2] / TPCMI

TPCMI[2] / TSIGI[2]

RINDO[2] / RDLCKO[2]

RSIGO[2] / RDLO[2]

SIGFRZ[2]

RPCMO[2] / RSIGO[2]

TFSYNC[2] / TMSYNC[2]

RSBCKI[2] / RPCMO

RFSYNC[2] / RMSYNC[2]

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

TINDO[1] / TDLCKO[1]

TSIGI[1] / TDLI[1]

TSBCKI[1] / TSBCKI

TFSYNC[1] / TMSYNC[1]

TPCMI[1] / TSIGI[1]

RINDO[1] / RDLCKO[1]

RSIGO[1] / RDLO[1]

SIGFRZ[1]

RSBCKI[1] / RSBCKI

RFSYNC[1] / RMSYNC[1]

RPCMO[1] / RSIGO[1]

XMTR4 / RCVR4

XMTR3 / RCVR3 XMTR1 / RCVR1

JTAG MPU

TSB4 / RSB4TSB3 / RSB3

CLKs

SERIO

TSB2 / RSB2 TSB1 / RSB1

VSS

VGG

TRST*

ONESEC

RST*

MOTO*

SYNCMD

MCLK

AS* / ALE

CS*

DS* / RD*

R/W* / WR*

DTACK*

INTR*

VDD

AD[5]

AD[6]

AD[7]

VDD

SERDI

SERCKO

SERDO

SERCS1*

TCK0[1]

TPOSO[1] / TNRZO[1]

TNEGO[1] / MSYNCO[1]

TCKI[1]

RCKI[1]

RPOSI[1]

RNEGI[1]

TCK0[2]

TCKI[2]

RCKI[2]

RPOSI[2]

RNEGI[2]

TPOSO[2] / TNRZO[2]

TNEGO[2] / MSYNCO[2]

TCK0[3]

TCKI[3]

RCKI[3]

RPOSI[3]

RNEGI[3]

TPOSO[3] / TNRZO[3]

TNEGO[3] / MSYNCO[3]

TCK0[4]

TCKI[4]

RCKI[4]

RPOSI[4]

RNEGI[4]

TPOSO[4] / TNRZO[4]

TNEGO[4] / MSYNCO[4]

VDD

T1ACKI

102

101

100

128

127

124

125

126

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

VSS

VDD

SYSCKI

EIACKI

VSS

VDD

TINDO[3] / TDLCKO[3]

TSIGI[3] / TDLI[3]

TSBCKI[3] / TINDO

TPCMI[3] / TSIGI[3]

RINDO[3] / RDLCKO[3]

RSIGO[3] / RDLO[3]

SIGFRZ[3]

RPCMO[3]/RSIGO[3]

TFSYNC[3] / TMSYNC[3]

RSBCKI[3] / RINDO

RFSYNC[3] / RMSYNC[3]

TCK

TMS

TDI

TDO

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

A[8]

A[9]

A[10]

TINDO[4] / TDLCKO[4]

TSIGI[4] / TDLI[4]

TSBCKI[4] / TFSYNC

TPCMI[4] / TSIGI[4]

RINDO[4] / RDLCKO[4]

RSIGO[4] / RDLO[4]

SIGFRZ[4]

RPCMO[4] / RSIGO[4]

TFSYNC[4] / TMSYNC[4]

RSBCKI[4] / RFSYNC

RFSYNC[4] / RMSYNC[4]

XMTR2 / RCVR2

8394-8-5_016

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-5

Figure 1-3. CX 2839 5 318-pin BGA Pinout Diagram

1 2 3 4 5 6 7 8 9 10111213141516 171819 20

8394-8-5_013

Top View

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-6 Conexant 100054E

Figure 1-4. CX28398 208-pin PQFP Pinout Diagram

208

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

100

101

102

103

104

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

207

VSS

VDD

VSS

TINDO[5] / TDLCKO[5]

TSIGI[5] / TDLI[5]

TSBCKI[5] / TSBCKI[B]

TPCMI[5] / TSIGI[5]

RINDO[5] / RDLCKO[5]

RSIGO[5] / RDLO[5]

SIGFRZ[5]

RPCMO[5] / RSIGO[5]

TFSYNC[5] / TMSYNC[5]

RSBCKI[5] / RSBCKI[B]

RFSYNC[5] / RMSYNC[5]

TINDO[2] / TDLCKO[2]

TSIGI[2] / TDLI[2]

TSBCKI[2] / TPCMI[A]

TPCMI[2] / TSIGI[2]

RINDO[2] / RDLCKO[2]

RSIGO[2] / RDLO[2]

SIGFRZ[2]

RPCMO[2] / RSIGO[2]

TFSYNC[2] / TMSYNC[2]

RSBCKI[2] / RPCMO[A]

RFSYNC[2] / RMSYNC[2]

TINDO[6] / TDLCKO[6]

TSIGI[6] / TDLI[6]

TSBCKI[6] / TPCMI[B]

TFSYNC[6] / TMSYNC[6]

TPCMI[6] / TSIGI[6]

RINDO[6] / RDLCKO[6]

RSIGO[6] / RDLO[6]

SIGFRZ[6]

RSBCKI[6] / RPCMO[B]

RFSYNC[6] / RMSYNC[6]

RPCMO[6] / RSIGO[6]

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

TINDO[1] / TDLCKO[1]

TSIGI[1] / TDLI[1]

TSBCKI[1] / TSBCKI[A]

TFSYNC[1] / TMSYNC[1]

TPCMI[1] / TSIGI[1]

RINDO[1] / RDLCKO[1]

RSIGO[1] / RDLO[1]

SIGFRZ[1]

RSBCKI[1] / RSBCKI[A]

RFSYNC[1] / RMSYNC[1]

RPCMO[1] / RSIGO[1]

MPU

XMTR4 / RCVR4

XMTR5 / RCVR5

XMTR6 / RCVR6

XMTR3 / RCVR3

XMTR2 / RCVR2

XMTR1 / RCVR1

JTAG

TSB8 / RSB8

TSB7 / RSB7

MPU

TSB8 / RSB8 TSB4 / RSB4TSB3 / RSB3 CLKsXMTR8 / RCVR8 XMTR7 / RCVR7

SERIO

TSB6 / RSB6 TSB5 / RSB5TSB2 / RSB2 TSB1 / RSB1

VSS

VDD

VGG

TCK

TMS

TRST*

TDI

TDO

TINDO[7] / TDLCKO[7]

TSIGI[7] / TDLI[7]

TSBCKI[7] / TINDO[B]

FSYNC[7] / TMSYNC[7]

TPCMI[7] / TSIGI[7]

RINDO[7] / RDLCKO[7]

RSIGO[7] / RDLO[7]

SIGFRZ[7]

RSBCKI[7] / RINDO[B]

FSYNC[7] / RMSYNC[7]

RPCMO[7] / RSIGO[7]

TINDO[8] / TDLCKO[8]

TSIGI[8] / TDLI[8]

TSBCKI[8] / TFSYNC[B]

FSYNC[8] / TMSYNC[8]

ONESEC

RST*

MOTO*

SYNCMD

MCLK

AS* / ALE

CS*

DS* / RD*

R/W* / WR*

DTACK*

INTR*

VDD

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

A[8]

A[9]

A[10]

A[11]

AD[5]

AD[6]

AD[7]

VDD

VSS

VDD

SERDI

SERCKO

SERDO

SERCS1*

SERCS2*

TCK0[1]

TPOSO[1] / TNRZO[1]

TNEGO[1] / MSYNCO

TCKI[1]

RCKI[1]

RPOSI[1]

RNEGI[1]

TCK0[2]

TCKI[2]

RCKI[2]

RPOSI[2]

RNEGI[2]

TPOSO[2] / TNRZO[2]

TNEGO[2] / MSYNCO

TCK0[3]

TCKI[3]

RCKI[3]

RPOSI[3]

RNEGI[3]

TPOSO[3] / TNRZO[3]

TNEGO[3] / MSYNCO

TCK0[4]

TCKI[4]

RCKI[4]

RPOSI[4]

RNEGI[4]

TPOSO[4] / TNRZO[4]

TNEGO[4] / MSYNCO

TCK0[5]

TCKI[5]

RCKI[5]

RPOSI[5]

RNEGI[5]

TPOSO[5] / TNRZO[5]

TNEGO[5] / MSYNCO

TCK0[6]

TCKI[6]

RCKI[6]

RPOSI[6]

RNEGI[6]

TPOSO[6] / TNRZO[6]

TNEGO[6] / MSYNCO

VDD

VSS

VDD

SYSCKI

T1ACKI

EIACKI

VSS

TCK0[7]

TCKI[7]

RCKI[7]

RPOSI[7]

RNEGI[7]

TPOSO[7] / TNRZO[7]

TNEGO[7] / MSYNCO[7]

TCK0[8]

TCKI[8]

RCKI[8]

RPOSI[8]

RNEGI[8]

TPOSO[8] / TNRZO[8]

TNEGO[8] / MSYNCO[8]

TINDO[4] / TDLCKO[4]

TSIGI[4] / TDLI[4]

TSBCKI[4] / TFSYNC[A]

TPCMI[4] / TSIGI[4]

RINDO[4] / RDLCKO[4]

RSIGO[4] / RDLO[4]

SIGFRZ[4]

RPCMO[4] / RSIGO[4]

TFSYNC[4] / TMSYNC[4]

RSBCKI[4] / RFSYNC[A]

RFSYNC[4] / RMSYNC[4

TINDO[3] / TDLCKO[3]

TSIGI[3] / TDLI[3]

TSBCKI[3] / TINDO[A]

TPCMI[3] / TSIGI[3]

RINDO[3] / RDLCKO[3]

RSIGO[3] / RDLO[3]

SIGFRZ[3]

RPCMO[3]/RSIGO[3]

TFSYNC[3] / TMSYNC[3]

RSBCKI[3] / RINDO[A]

RFSYNC[3] / RMSYNC[3

TPCMI[8] / TSIGI[8]

RINDO[8] / RDLCKO[8]

RSIGO[8] / RDLO[8]

SIGFRZ[8]

RSBCKI[8] / RFSYNC[B]

RFSYNC[8] / RMSYNC[8

RPCMO[8] / RSIGO[8]

CX28398

8394-8-5_023

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-7

Figure 1-5. CX28398 208-pin CABGA Pinout Diagram

Top View

2345678910111213141516117

100054_001

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-8 Conexant 100054E

Figure 1-6. CX 2839 8 272-pin BGA Pinout Diagram

1 2 3 4 5 6 7 8 9 10111213141516 171819 20

8394-8-5_005

Top View

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-9

Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4) (1 of 2)

Pin Number System Bus Interface Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208-pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMODE[0] = 0 [FCR; addr 080] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 080]

89 94 R12 V15 J3 RPCMO[1] RSIGO[1]

90 95 P11 W16 J4 RFSYNC[1]/RMSYNC[1] RMSYNC[1]

91 96 U14 Y17 J2 RSBCKI[1] RSBCKI[A]

92 97 T14 V16 — SIGFRZ[1] SIGFRZ[1]

93 98 R13 W17 — RSIG O[1] / RDLO[1 ] RDLO [1]

————J1RSIGO[1] TSTO[1]

94 99 P12 Y18 — RINDO[1] / RDLCK O[1 ] RDLC KO[1 ]

95 100 U15 V17 K4 TPCMI[1] TSIGI[1]

96 101 U16 W18 K1 TFSYNC[1]/TMSYNC[1] TMSYNC[1]

97 102 R14 Y19 K3 TSBCKI[1] TSBCKI[A]

98 103 P13 V18 — TSIG I[1] / TDLI[1] TDLI[ 1]

— — — — K2 TSIGI[1] TSTI[1]

99 104 T15 W19 — TIN DO [1] / TDLCKO[1] TDLCKO[1]

————K5TINDO[1] —

75 69 R6 W8 E4 RPCMO[2] RSIGO[2]

76 70 T6 Y8 E3 RFSYNC[2]/RMSYNC[2] RMSYNC[2]

77 71 U7 V9 E2 RSBCKI[2] RPCMO[A]

78 72 P7 W9 — SIGFRZ[2] SIGFRZ[2]

79 73 R7 Y9 — RSIGO[2] / RDLO[ 2 ] RDLO[ 2]

————F4RSIGO[2] TSTO[2]

80 74 T7 W10 — RINDO [2] / RDLCK O[2 ] RDLC KO[2 ]

81 75 U8 V10 F3 TPCMI[2] TSIGI[2]

82 76 P8 Y10 F2 TFSYNC[2]/TMSYNC[2] TMSYNC[2]

83 77 R8 Y11 E1 TSBCKI[2] TPCMI[A]

84 78 T8 W11 — TSIGI[2] / TDLI[2] TDLI[2]

— — — — F1 TSIGI[2] TSTI[2]

85 79 U9 V11 — TINDO[2] / TDLCKO[2] TDLCKO[2]

— — — — H5 TINDO[2] —

25 198 C6 C6 U9 RPCMO[3] RSIGO[3]

26 199 D6 B5 Y9 RFSYNC[3]/RMSYNC[3] RMSYNC[3]

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-10 Conexant 100054E

27 200 C5 A4 U10 RSBCKI[3] RINDO[A]

28 201 D5 C5 — SIGFRZ[3] SIGFRZ[3]

29 202 B5 B4 — RSIGO[3] / RDLO[3 ] RDLO [3]

————Y10RSIGO[3] TSTO[3]

30 203 A4 A3 — RINDO[3] / RDLCKO[3 ] RDLC KO[3 ]

31204A3C4V9TPCMI[3] TSIGI[3]

32 205 B3 B3 W10 TFSYNC[3]/TMSYNC[3] TMSYNC[3]

33 206 C4 B2 V10 TSBCKI[3] TINDO[A]

34 207 A2 A2 — TSIGI[3] / TDLI[3] TDLI[ 3]

— — — — W9 TSIGI[3] TSTI[3]

35 208 B4 C 3 — TINDO[3] / TDLCKO[3] TDLCKO[3]

————T10TINDO[3] —

13 178 A11 B11 U5 RPCMO[4] RSIGO[4]

14 179 B10 C11 W5 RFSYNC[4]/RMSYNC[4] RMSYNC[4]

15 180 C10 A11 V6 RSBCKI[4] RFSYNC[A]

16 181 D10 A10 — SIGFRZ[4] SIGFRZ[4]

17 182 A10 B10 — RSIGO[4] / RD LO[4 ] RDLO [4]

————Y5RSIGO[4] TSTO[4]

18 183 A9 C10 — RINDO[4] / RDLCK O[4 ] RDLCKO[4 ]

19 184 B9 A9 W6 TPCMI[4] TSIGI[4]

20 185 C9 B9 V5 TFSYNC[4]/TMSYNC[4] TMSYNC[4]

21 186 D9 C9 U6 TSBCKI[4] TFSYNC[A]

22 187 A8 A8 — TSIGI[4] / TDLI[4] TDLI[ 4]

— — — — Y6 TSIGI[4] TSTI[4]

23 188 C8 B 8 — TINDO[4] / TDLCKO[4] TDLCKO[4]

————T8TINDO[4] —

Table 1-1. Pin Assignments (SBI1, SBI2, SBI3, SBI4) (2 of 2)

Pin Number System Bus Interface Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMODE[0] = 0 [FCR; addr 080] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 080]

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-11

Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8) (1 of 2)

Pin Number System Bus Interface Pin Functions Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208-pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMODE[0] = 0 [FCR; addr 080] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 080]

— 81 U10 Y12 G4 RPCMO[5] RSIGO[5]

— 82 R9 W12 G2 RFSYNC[5] / RMS YNC[ 5] RMSYNC [5]

— 83 P9 V12 G3 RSBCKI[5] RSBCKI[B]

— 84 T10 Y13 — SIGFRZ[5] SIGFRZ[5]

— 85 R10 W13 — RSIGO[ 5] / RD LO[5 ] RDLO[ 5]

————G1RSIGO[5] TSTO[5]

— 86 U11 V13 — RINDO[5] / RDLCK O[5 ] RDLCKO[5 ]

— 87 T11 Y14 H3 TPCMI[5] TSIGI[5]

— 88 R11 W14 H4 TFSYNC[5] / TMSYNC[5] TMSYNC[5]

— 89 T12 Y15 H1 TSBCKI[5] TSBCKI[B]

— 90 U12 V14 — TSIG I[5] / TDLI[5] TDLI[ 5]

— — — — H2 TSIGI[5] TSTI[5]

— 91 P10 W 15 — TINDO[5] / TDLCKO[ 5] TD LCKO[5]

————J5TINDO[5] —

—58P4Y4C2RPCMO[6] RSIGO[6]

— 59 U3 V5 C4 RFSYNC[6] / RMSYNC[6] RMSYNC[6]

— 60 U4 W5 C1 RSBCKI[6] RPCMO[B]

— 61 R4 Y5 — SIGFRZ[6] SIGFRZ[6]

— 62 T4 V6 — RSIGO[6] / RDLO[6 ] RDLO[6]

————D4RSIGO[6] TSTO[6]

— 63 U5 W6 — RINDO[6] / RDLCKO[6] RDLC KO[6]

— 64 P5 Y6 D2 TPCMI[6] TSIGI[6]

— 65 R5 V7 D3 TFSYNC[6] / TMSYNC[6] TMSYNC[6]

— 66 T5 W7 D1 TSBCKI[6] TPCMI[B]

— 67 U6 Y7 — TSIGI[ 6] / TDLI[6] TDLI[6]

— — — — C3 TSIGI[6] TSTI[6]

— 68 P6 V8 — TINDO[6] / TDLCKO[ 6] TDLCKO[6 ]

— — — — G5 TINDO[6] —

— 25 J4 L1 U12 RPCMO[7] RSIGO[7]

— 26 H2 L2 Y11 RFSYNC [7] / RMS YNC[ 7] RMSYNC[7]

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-12 Conexant 100054E

— 27 H1 L3 Y12 RSBCKI[7] RINDO[B]

—28J1M1—SIGFRZ[7] SIGFRZ[7]

— 29 J3 M2 — RSIG O[7] / RDLO[7 ] RDLO[7]

————W11RSIGO[7] TSTO[7]

— 30 J2 M3 — RINDO[7] / RDLCK O[7 ] RDLC KO[7 ]

— 31 K4 N1 W12 TPCMI[7] TSIGI[7]

— 32 K1 N2 V11 TFSYNC[7] / TMSYNC[7] TMSYNC[7]

— 33 K2 N3 V12 TSBCKI[7] TINDO[B]

— 34 L1 P1 — TSIGI[7] / TDLI[7] TDLI [7]

————U11TSIGI[7] TSTI[7]

— 35 K3 P2 — TINDO[7] / TDLCKO[ 7] TDLCKO[7 ]

————T11TINDO[7] —

— 189 D8 C8 W7 RPCMO[8] RSIGO[8]

— 190 B8 A7 V7 RFSYNC [8] / RMSYNC[8] RMSYNC[ 8]

— 191 C7 B7 Y7 RSBCKI[8] RFSYNC[B]

— 192 A7 A6 — SIGFRZ[8] SIGFRZ[8]

— 193 D7 C7 — RSIGO[8] / RDLO[8] RDLO[8]

————V8RSIGO[8] TSTO[8]

— 194 B7 B6 — RINDO[8] / RDLCKO[8 ] RDLC KO[8 ]

— 195 A6 A5 Y8 TPCMI[8] TSIGI[8]

— 9 E4 E1 W8 TFSYNC[8] / TMSYNC[8] TMSYNC[8]

— 10 E3 F3 U8 TSBCKI[8] TFSYNC[B]

— 11 D2 F2 — TSIGI[8] / TDLI[8 ] TDLI [8]

— — — — U7 TSIGI[8] TSTI[8]

— 12 D1 F 1 — TINDO[8] / TDLCKO[8] TDLCKO[8]

————T9TINDO[8] —

Table 1-2. Pin Assignments (SBI5, SBI6, SBI7, SBI8) (2 of 2)

Pin Number System Bus Interface Pin Functions Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMODE[0] = 0 [FCR; addr 080] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 080]

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-13

Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12) (1 of 2)

Pin Number System Bus Interface Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208-pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMO D E[ 0] = [FCR; ad dr 001] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 001]

— — — — F20 RPCMO[9] RSIGO[9]

— — — — F18 RFSYNC[9]/RMSYNC[9] RMSYNC[9]

— — — — F19 RSBCKI[9] RSBCKI[C]

————F17RSIGO[9] TSTO[9]

————E20TPCMI[9] TSIGI[9]

— — — — E18 TFSYNC[9]/TMSYNC[9] TMSYNC[9]

— — — — E19 TSBCKI[9] TSBCKI[C]

————E17TSIGI[9] TSTI[9]

————F16TINDO[9] —

— — — — K17 RPCMO[10] RSIGO[10]

— — — — K19 RFSYNC[10]/RMSYNC[10] RMSYNC[10]

— — — — K18 RSBCKI[10] RPCMO[C]

————K20RSIGO[10] TSTO[10]

————J17TPCMI[10] TSIGI[10]

— — — — J20 TFSYNC[10]/TMSYNC[10] TMSYNC[10]

— — — — J18 TSBCKI[10] TPCMI[C]

— — — — J19 TSIGI[10] TSTI[10]

————H16TINDO[10] —

— — — — A4 RPCMO[11] RSIGO[11]

— — — — A3 RFSYNC[11]/RMSYNC[11] RMSYNC[11]

— — — — B4 RSBCKI[11] RINDO[C]

————B3RSIGO[11] TSTO[11]

————A2TPCMI[11] TSIGI[11]

— — — — A1 TFSYNC[11]/TMSYNC[11] TMSYNC[11]

— — — — B2 TSBCKI[11] TINDO[C]

— — — — B1 TSIGI[11] TSTI[11]

————E5TINDO[11] —

— — — — A10 RPCMO[12] RSIGO[12]

— — — — D10 RFSYNC[12]/RMSYNC[12] RMSYNC[12]

— — — — B10 RSBCKI[12] RFSYNC[C]

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-14 Conexant 100054E

— — — — D9 RSIGO[12] TSTO[12]

————A9TPCMI[12] TSIGI[12]

— — — — C9 TFSYNC[12]/TMSYNC[12] TMSYNC[12]

— — — — B9 TSBCKI[12] TFSYNC[C]

— — — — C10 TSIGI[12] TSTI[12]

————E7TINDO[12] —

Table 1-3. Pin Assignments (SBI9, SBI10, SBI11, SBI12) (2 of 2)

Pin Number System Bus Interface Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMO D E[ 0] = [FCR; ad dr 001] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 001]

Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16) (1 of 2)

Pin Number System Bus Interface Pin Functions

CX28394

128- pin TQFP

CX28398

208-pi n PQF P

CX28398

208-pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMO D E[ 0] = [FCR; ad dr 001] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 001]

— — — — H18 RPCMO[13] RSIGO[13]

— — — — H19 RFSYNC[13]/RMSYNC[13] RMSYNC[13]

— — — — H17 RSBCKI[13] RSBCKI[D]

————H20RSIGO[13] TSTO[13]

————G17TPCMI[13] TSIGI[13]

— — — — G20 TFSYNC[13]/TMSYNC[13] TMSYNC[13]

— — — — G18 TSBCKI[13] TSBCKI[D]

— — — — G19 TSIGI[13] TSTI[13]

————G16TINDO[13] —

— — — — M18 RPCMO[14] RSIGO[14]

— — — — M17 RFSYNC[14]/RMSYNC[14] RMSYNC[14]

— — — — M19 RSBCKI[14] RPCMO[D]

— — — — L19 RSIGO[14] TSTO[14]

— — — — L20 TPCMI[14] TSIGI[14]

— — — — L17 TFSYNC[14]/TMSYNC[14] TMSYNC[14]

— — — — M20 TSBCKI[14] TPCMI[D]

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-15

— — — — L18 TSIGI[14] TSTI[14]

————K16TINDO[14] —

— — — — B7 RPCMO[15] RSIGO[15]

— — — — B8 RFSYNC[15]/RMSYNC[15] RMSYNC[15]

— — — — D7 RSBCKI[15] RINDO[D]

————C8RSIGO[15] TSTO[15]

————A7TPCMI[15] TSIGI[15]

— — — — A8 TFSYNC[15]/TMSYNC[15] TMSYNC[15]

— — — — C7 TSBCKI[15] TINDO[D]

— — — — D8 TSIGI[15] TSTI[15]

————M16TINDO[15] —

— — — — A6 RPCMO[16] RSIGO[16]

— — — — A5 RFSYNC[16]/RMSYNC[16] RMSYNC[16]

— — — — B6 RSBCKI[16] RFSYNC[D]

— — — — D6 RSIGO[16] TSTO[16]

————C6TPCMI[16] TSIGI[16]

— — — — B5 TFSYNC[16]/TMSYNC[16] TMSYNC[16]

— — — — C5 TSBCKI[16] TFSYNC[D]

— — — — D5 TSIGI[16] TSTI[16]

————J16TINDO[16] —

Table 1-4. Pin Assignments (SBI13, SBI14, SBI15, SBI16) (2 of 2)

Pin Number System Bus Interface Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

Non-Multiplexed Mode

SBIMO D E[ 0] = [FCR; ad dr 001] Multiplexed Mode

SBIMODE[0] = 1 [FCR; addr 001]

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-16 Conexant 100054E

Tab le 1-5. Pi n Assi gnments (1 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208-pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

7 117 B2 A1 N6 VSS (GND)

9 140 G1 D4 N7 VSS (GND)

11 158 P3 D8 N8 VSS (GND)

37 160 T9 D13 P6 VSS (GND)

66 162 T13 D17 P7 VSS (GND)

86 196 N17 H4 P8 VSS (GND)

— 2 F17 H17 R6 VSS (GND)

— 24 B16 J9 R7 VSS (GND)

— 49 A16 J10 R8 VSS (GND)

— 80 D14 J11 F13 VSS (GND)

— 93 B6 J12 F14 VSS (GND)

— — — K9 F15 VSS (GND)

— — — K10 G13 VS S (GND)

— — — K11 G14 VS S (GND)

— — — K12 G15 VS S (GND)

———L9H13VSS (GND)

— — — L10 H14 VSS (GND)

— — — L11 H15 VSS (GND)

— — — L12 T13 VSS (GND)

———M9T14VSS (GND)

— — — M1 0 — VSS (GND)

— — — M1 1 — VSS (GND)

— — — M1 2 — VSS (GND)

— — — N4 — VSS (GND)

— — — N17 — VSS (GN D)

— — — U4 — VSS (GND)

— — — U8 — VSS (GND)

— — — U13 — VSS (GN D)

— — — U17 — VSS (GN D)

111 118 C1 D6 E6 VDD

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-17

119 141 P2 D11 F5 VDD

12 149 U13 D15 N20 VDD

24 163 M15 F4 R16 VDD

43 197 G15 F17 T15 VDD

87 8 F14 K4 Y20 VDD

—48C14L17—VDD

—92A5R4—VDD

———R17—VDD

— — — U6 — VDD

———U10—VDD

———U15—VDD

36 1 A1 B1 Y14 VGG

38 3 C3 D2 Y16 TRST*

39 4 B1 D3 W20 TMS

40 5 D4 C1 — TDI

————Y15TDI1

————T20TDI2

41 6 D3 D1 — TD0

————Y19TDO1

————P19TDO2

42 7 C2 E3 W17 TCK

6 157 A17 A19 P20 E1ACKI

8 159 B15 B17 N19 T1ACKI

10 161 C15 A18 U13 SYSCKI

44 13 F4 G3 — ONESEC

————V13ONESEC1

————Y13ONESEC2

45 14 F3 G2 — INTR*

————Y18INTR1*

————N17INTR2*

Tab le 1-5. Pi n Assi gnments (2 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-18 Conexant 100054E

46 15 E2 G1 — DTACK*

————W13DTACK1*

————T18DTACK2*

47 16 E1 H3 Y17 R/W*/WR*

48 17 G4 H2 W14 DS*/RD*

49 18 G3 H1 — CS*

————W19CSI*

————N18CS2*

50 19 F2 J3 V14 AS*/ALE

51 20 F1 J2 U14 MCLK

52 21 H4 J1 W15 SYNCMD

53 22 H3 K2 W18 MOTO*

54 23 G2 K3 W16 RST*

— 36 L3 R1 V15 A[11]

55 37 M2 P3 V18 A[10]

56 38 M1 R2 U15 A[9]

57 39 L4 T1 V16 A[8]

58 40 N2 R3 V20 A[7]

59 41 L2 T2 V19 A[6]

60 42 N1 U1 U20 A[5]

61 43 M4 T3 V17 A[4]

62 44 M3 U2 U16 A[3]

63 45 N4 V1 U19 A[2]

64 46 P1 U3 U17 A[1]

65 47 N3 V2 T17 A[0]

67 50 R2 V3 R17 AD[7]

68 51 R1 W2 U18 AD[6]

69 52 T1 Y1 R18 AD[5]

70 53 U1 W3 R20 AD[4]

71 54 T2 Y2 P18 AD[3]

Tab le 1-5. Pi n Assi gnments (3 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-19

72 55 U2 W4 R19 AD2]

73 56 T3 V4 P17 AD[1]

74 57 R3 Y3 T19 AD[0]

100 105 U17 W20 — SERCLKO

101 106 T16 V19 — SERDO

102 107 T17 U19 — SERDI

103 108 R16 U18 — SERCS1 * ( SE R CS *)

— 109 R17 V20 — SERCS2*

104 110 R15 U20 L3 TCKO[1]

107 113 P16 T20 M3 TCKI[1]

105 111 N15 T18 L4 TPOSO[1]/TNRZO[1]

106 112 P17 T19 L5 TNEGO[1]/MSYNCO[1]

108 114 P15 R18 L1 RCKI[1]

109 115 P14 R19 L2 RPOSI[1]/RNRZI[1]

110 116 N16 R20 — RNEGI[1]

112 126 K15 L19 N1 TCKO[2]

115 129 K16 K20 P3 TCKI[2]

113 127 K17 L18 N2 TPOSO[2]/TNRZO[2]

114 128 L14 L20 N5 TNEGO[2]/MSYNCO[2]

116 130 J16 K19 P1 RCKI[2]

117 131 J17 K18 P2 RPOSI[2]/RNRZI[2]

118 132 J15 J20 — RNEGI[2]

120 142 H14 F19 T1 TCKO[3]

123 145 G14 E19 T4 TCKI[3]

121 143 F16 E20 T3 TPOSO[3]/TNRZO[3]

122 144 E17 F18 R5 TNEGO[3]/MSYNCO[3]

124 146 F15 D20 T2 RCKI[3]

125 147 E16 E18 U1 RPOSI[3]/RNRZI[3]

126 148 D17 D19 — RNEGI[3]

127 150 E15 C20 U2 TCKO[4]

Tab le 1-5. Pi n Assi gnments (4 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-20 Conexant 100054E

2 153 E14 B20 U3 TCKI[4]

128 151 D16 D18 U4 TPOSO[4]/TNRZO[4]

1 152 C17 C19 T5 TNEGO[4]/MSYNCO[4]

3 154 D15 C18 V1 RCKI[4]

4 155 C16 B19 V2 RPOSI[4]/RNRZI[4]

5 156 B17 A20 — RNEGI[4]

— 119 N14 P20 M4 TCKO[5]

— 122 L15 N20 M2 TCKI[5]

— 120 M16 N18 M1 TPOSO[5]/TNRZO[5]

— 121 M17 N19 M5 TNEGO[5]/MSYNCO[5]

— 123 M14 M18 N3 RCKI[5]

— 124 L16 M19 N4 RPOSI[5]/RNRZI[5]

— 125 L17 M20 — RNEGI[5]

— 133 H17 J19 P4 TCKO[6]

— 136 H15 H19 R2 TCKI[6]

— 134 K14 J18 R1 TPOSO[6]/TNRZO[6]

— 135 H16 H20 P5 TNEGO[6]/MSYNCO[6]

— 137 G17 H18 R3 RCKI[6]

— 138 J14 G20 R4 RPOSI[6] /RNR ZI[6 ]

— 139 G16 G19 — RNEGI[6]

— 164 B14 B16 V3 TCKO[7]

— 167 C13 B15 Y1 TCKI[7]

— 165 A15 A16 W1 TPOSO[7]/TNRZO[7]

— 166 D13 C15 T6 TNEGO[7]/MSYNCO[7]

— 168 A14 A15 W2 RCKI[7]

— 169 B13 C14 Y2 RPOS I[7] /RNR ZI[7]

— 170 D12 B14 — RNEGI[7]

— 171 C12 A14 Y3 TCKO[8]

— 174 A12 A13 W3 TCKI[8]

— 172 A13 C13 V4 TPOSO[8]/TNRZO[8]

Tab le 1-5. Pi n Assi gnments (5 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-21

— 173 B12 B13 T7 TNEGO[8]/MSYNCO[8]

— 175 C11 C12 W4 RCKI[8]

— 176 B11 B12 Y4 RPOS I[8] /RNR ZI[8]

— 177 D11 A12 — RNEGI[8]

————D20TCKO[9]

————B20TCKI[9]

————C20TPOSO[9]/TNRZO[9]

————E16TNEGO[9]/MSYNCO[9]

————D19RCKI[9]

————C19RPOSI[9]/RNRZI[9]

————B18TCKO[10]

————D17TCKI[10]

————C17TPOSO[10]/TNRZO[10]

————E14TNEGO[10]/MSYNCO[10]

————A18RCKI[10]

————A17RPOSI[10]/RNRZI[10]

————A15TCKO[11]

————D15TCKI[11]

————C15TPOSO[11]/TNRZO[11]

————E12TNEGO[11]/MSYNCO[11]

————B15RCKI[11]

————A14RPOSI[11]/RNRZI[11]

————B14TCKO[12]

————D14TCKI[12]

————C14TPOSO[12]/TNRZO[12]

————E11TNEGO[12]/MSYNCO[12]

————A13RCKI[12]

————B13RPOSI[12]/RNRZI[12]

————B19TCKO[13]

————A19TCKI[13]

Tab le 1-5. Pi n Assi gnments (6 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-22 Conexant 100054E

————A20TPOSO[13]/TNRZO[13]

————E15TNEGO[13]/MSYNCO[13]

————C18RCKI[13]

————D18RPOSI[13]/RNRZI[13]

————B17TCKO[14]

————B16TCKI[14]

————A16TPOSO[14]/TNRZO[14]

————E13TNEGO[14]/MSYNCO[14]

————C16RCKI[14]

————D16RPOSI[14] /RNRZI[14]

————C12TCKO[15]

————A12TCKI[15]

————B12TPOSO[15]/TNRZO[15]

————E10TNEGO[15]/MSYNCO[15]

————C13RCKI[15]

————D13RPOSI[15] /RNRZI[15]

————B11TCKO[16]

————C11TCKI[16]

————D12TPOSO[16]/TNRZO[16]

————E8TNEGO[16]/MSYNCO[16]

————A11RCKI[16]

————D11RPOSI[16] /RNRZI[16]

———E2E9NC

———G4T12NC

———E4L16NC

———J4N16NC

———C2P16NC

———K1T16NC

———L4—NC

———M4—NC

Tab le 1-5. Pi n Assi gnments (7 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-23

———T4—NC

———P4—NC

———W1—NC

———U5—NC

———U7—NC

———U9—NC

— — — U11 — NC

— — — U12 — NC

———Y16—NC

— — — U14 — NC

— — — U16 — NC

———Y20—NC

———T17—NC

———P17—NC

———P18—NC

———P19—NC

———M17—NC

———F20—NC

———E17—NC

— — — G17 — NC

— — — G18 — NC

———B18—NC

———C17—NC

— — — D16 — NC

———A17—NC

———C16—NC

— — — D14 — NC

———K17—NC

———J17—NC

— — — D12 — NC

Tab le 1-5. Pi n Assi gnments (8 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-24 Conexant 100054E

— — — D10 — NC

———D9—NC

———D7—NC

———D5—NC

Tab le 1-5. Pi n Assi gnments (9 of 9)

Pin Number

Pin Functions

CX28394

128-pin TQFP

CX28398

208-pin PQFP

CX28398

208- pin CABGA

CX28398

272-pin BGA

CX28395

318-pin BGA

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-25

Figure 1-7. CX28394 Logic Diagram (Non-Multiplexed System Bus Mode)

Te st Data Out

PIO

Bused RSB PCM Data Out

Bused Time Slot Indicator

Bused RSB Frame Sync

Transmit Clock Out

Tr a nsm it Positive/Trans mi t NRZ Out

Transmit Negative/Transmit

PIO Bused Time Slot Indicator

Bused TSB Frame Sync

PIO

Receive Positi ve In

Receive Negative In

Bused TSB Cl oc k In

Bused TSB PCM Data In

I/O

Hardw ar e Reset

System Clock

Processor C lock

Synchronous Bus mode

Moto rol a Bu s mode

Address Strobe

Chip Select

Data or Read Strobe

Read/Write or Write Strobe

Address Bus

Serial Data In

Transmit Clock In

1544 KHz All Ones Clock

Receiv e Clock In

ITSB Signalling In

Bused RSB Cl ock In

2048 KHz All Ones Clock

RST*

SYSCKI

MCLK

SYNCMD

MOTO*

AS*(ALE*)

CS*

DS*(RD*)

R/W*(W*)

AD[7:0]

A[10:0]

SERDI

TCKI[4:1]

T1ACKI

E1ACKI

RCKI[4:1]

RPOSI[4:1]

RNEGI[4:1]

TSBCKI

TPCMI

TSIGI[4:1]

RSBCKI

TCK

TMS

TDI

TRST*

DTACK*

INTR*

ONESEC

SERCKO

SERDO

SERCS*

TCKO{4:1]

TPOSO[4:1]/TNRZO[4:1]

TNEGO[4:1]/MSYNCO[4:1]

TINDO

TFSYNC

RPCMO

RINDO

RFSYNC

RMSYNC

RSIGO

TDO

Boundary Scan

(JTAG)

Receiv e Sys t e m Bu s

(RSB)

Transmit System Bus

(TSB)

Receiver

(RCVR)

Transmitter

(XMTR)

LIU Serial

Port Interface

(SERIO)

Microprocessor Interface

and Control

(MPU)

Data or M ul tiplexed

Test Clock In

Test mode Select

Test Data In

Test Reset In

Data Transfer Acknowledge

Interru pt Request

One-Second Timer

Serial Clock Out

Serial Data Out

Serial Port Chip Select

Transmit Datalink Data In

PIO RSB Multiframe Sync

RSB Signalling

Multiframe Sync Out

Address/Data Bus

I= Input, O= Outp ut

PIO = Programmable I/O; controls located at PIO (address 018)

TDLI[4:1] PIO

OTSB Multiframe Sync

Transmi t D atalink Clock Out

TMSYNC[4:1]

TDLCKO[4:1]

Rece ive Dat al i nk Clock Out

RDLCKO

RDLO

SIGFRZ O

Receive Datalink Data Out

Signal li ng Fre eze

8394-8-5_017

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-26 Conexant 100054E

Figure 1-8. CX28394 Logic Diagram (Multiplexed System Bus Mode)

Test Data Out

PIO

Bused RSB PCM Data Out

Bused Time Slot Indicator

Bused RSB Frame Sync

OTransmit Clock Out

Tr a nsmi t Positive/Transmit NRZ Out

Transmit Negative/Transmit

PIO

OBused Time Slot Indicator

Bused TSB Frame Sync

PIO

OTSB MUltiframe Sync

Transmit Datalink Clock Out

PIO

Receive Positive In

Receive Negative In

Bused TSB Cloc k In

Bused TSB PCM Data In

I/O

Hard war e Reset

System Clock

Pro c esso r Clock

Synchro nous Bus mode

Moto rol a Bus mode

Address Strobe

Chip Select

Data or Re ad Strobe

Read/ Write or Write Strobe

Address Bus

Serial Data In

Transmit Cloc k In

1544 KHz All Ones Clock

Recei ve Clock In

TSB Sig na lling In/

Bused RSB C loc k In

2048 KHz All Ones Clock

RST*

SYSCKI

MCLK

SYNCMD

MOTO*

AS*(ALE*)

CS*

DS*(RD*)

R/W*(W*)

AD[7:0]

A[10:0]

SERDI

TCKI[4:1]

T1ACKI

E1ACKI

RCKI[4:1]

RPOSI[4:1]

RNEGI[4:1]

TSBCKI[A]

TPCMI[A]

TSIGI[4:1]

TDLI[4:1]

RSBCKI[8:1]

TCK

TMS

TDI

TRST*

DTACK*

INTR*

ONESEC

SERCKO

SERDO

SERCS*

TCKO[4:1]

TPOSO[8:1]/TNRZO[4:1]

TNEGO[8:1]/MSYNCO[4:1]

TINDO[A]

TFSYNC[A]

TMSYNC[4:1]

TDLCKO[4:1]

RPCMO[A]

RINDO[A]

RFSYNC[A] PIO RSB Multiframe Sync

RMSYNC[4:1] PIO RSB Signalling

RSIGO[4:1] OReceive Datalink Clock Out

RDLCKO[4:1] OReceive Datalink Data Out

RDLO[4:1] OSignalling Freeze

SIGFRZ[4:1]

TDO

Boundary Scan

(JTAG)

Receive System Bus

(RSB)

Transm it System Bus

(TSB)

Receiver

(RCVR)

Transmitter

(XMTR)

LIU Serial

Port Interface

(SERIO)

Microprocessor Interface

and Control

(MPU)

Data or Multiplexed

Te st Clock In

Test mode Select

Test Data In

Test Reset In

Data Transfer Acknowle dge

Interrupt Request

One-Second Timer

Seri al Clock Out

Serial Data Out

Serial Port Chip Select

Tr an smi t Datalink Data In

Mult iframe Sync Out

Address/Da t a Bu s

I= Input, O= Output

PIO = Programmable I/O; controls located at PIO (address 018)

8394-8-5_018a

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-27

Figure 1-9. CX28398 Logic Diagram (Non-Multiplexed System Bus Mode)

Test Data Out

PIO RSB PCM Data Out

RSB Frame/Multiframe Sync

Time Slot Indicator/Receive

OTransmit Clock Out

Tr ansmit Positi v e/Transmit NRZ Out

Transmit Negative/Transmit

PIO

OTSB Frame/Multiframe Sync

Time Slot Indicator/Transmit

PIO

Receive Positive In

Receive Negative In

TSB Cloc k In

TSB PCM Data In

I/O

Hard war e Reset

System Clock

Pro c esso r Clock

Synchro nous Bus mode

Moto rol a Bus mode

Address Strobe

Chip Select

Data or Re ad Strobe

Read/ Write or Write Strobe

Address Bus

Serial Data In

Transmit Cloc k In

1544 KHz All Ones Clock

Recei ve Clock In

TSB Sig nalling In/

RSB C loc k In

2048 KHz All Ones Clock

RST*

SYSCKI

MCLK

SYNCMD

MOTO*

AS*(ALE*)

CS*

DS*(RD*)

R/W*(W*)

AD[7:0]

A[11:0]

SERDI

TCKI[8:1]

T1ACKI

E1ACKI

RCKI[8:1]

RPOSI[8:1]

RNEGI[8:1]

TSBCKI[8:1]

TPCMI[8:1]

TSIGI[8:1]/TDLI[8:1]

RSBCKI[8:1]

TCK

TMS

TDI

TRST*

DTACK*

INTR*

ONESEC

SERCKO

SERDO

SERCS*[2:1]

TCKO[8:1]

TPOSO[8:1]/TNRZO[8:1]

TNEGO[8:1]/MSYNCO[8:1]

TFSYNC[8:1]/TMSYNC[8:1]

TINDO[8:1]/TDLCKO[8:1]

RPCMO[8:1]

RFSYNC[8:1]/RMSYNC[8:1]

RINDO[8:1]/RDLCKO[8:1]

RSIGO[8:1]/RDLO[8:1]

SIGFRZ[8:1]

TDO

Boundary Scan

(JTAG)

Receive System Bus

(RSB)

Transmit System Bus

(TSB)

Receiver

(RCVR)

Transmitter

(XMTR)

LIU Serial

Port Interface

(SERIO)

Microprocessor Interface

and Control

(MPU)

Data or Multiplexed

Te st Clock In

Test mode Select

Test Data In

Test Reset In

Data Transfer Acknowle dge

Interrupt Requ est

One-Second Timer

Seri al Clock Out

Serial Data Out

Serial Port Chip Select

Tr an smi t Datalink Data In Datalink Cl ock Out

PIO

RSB Signa ll ing/Rec e ive

Signal li ng Freeze

Mult iframe Sync Out

Address/Da t a Bu s

I= Input, O= Output

PIO = Programmable I/O; controls located at PIO (address 018)

Datalink Da ta Out

Datalink Cl ock Out

8394-8-5_020

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-28 Conexant 100054E

Figure 1-10. CX28398 Logic Diagram (Multiplexed System Bus Mode)

Test Data Out

PIO

Bused RSB PCM Data Out

Bused Time Slot Indicator

Bused RSB Frame Sync

OTransmit Clock Out

Tr a nsmi t Positive/Transmit NRZ Out

Transmit Negative/Transmit

PIO

OBused Time Slot Indicator

Bused TSB Frame Sync

PIO

OTSB MUltiframe Sync

Transmit Datalink Clock Out

PIO

Receive Positive In

Receive Negative In

Bused TSB Cloc k In

Bused TSB PCM Data In

I/O

Hard war e Reset

System Clock

Pro c esso r Clock

Synchro nous Bus mode

Moto rol a Bus mode

Address Strobe

Chip Select

Data or Re ad Strobe

Read/ Write or Write Strobe

Address Bus

Serial Data In

Transmit Cloc k In

1544 KHz All Ones Clock

Recei ve Clock In

TSB Sig na lling In/

Bused RSB C loc k In

2048 KHz All Ones Clock

RST*

SYSCKI

MCLK

SYNCMD

MOTO*

AS*(ALE*)

CS*

DS*(RD*)

R/W*(W*)

AD[7:0]

A[11:0]

SERDI

TCKI[8:1]

T1ACKI

E1ACKI

RCKI[8:1]

RPOSI[8:1]

RNEGI[8:1]

TSBCKI[A:B]

TPCMI[A:B]

TSIGI[8:1]

TDLI[8:1]

RSBCKI[A:B]

TCK

TMS

TDI

TRST*

DTACK*

INTR*

ONESEC

SERCKO

SERDO

SERCS*[2:1]

TCKO[8:1]

TPOSO[8:1]/TNRZO[8:1]

TNEGO[8:1]/MSYNCO[8:1]

TINDO[A:B]

TFSYNC[A:B]

TMSYNC[8:1]

TDLCKO[8:1]

RPCMO[A:B]

RINDO[A:B]

RFSYNC[A:B] PIO RSB Multiframe Sync

RMSYNC[8:1] PIO RSB Signalling

RSIGO[8:1] OReceive Datalink Clock Out

RDLCKO[8:1] OReceive Datalink Data Out

RDLO[8:1] OSignalling Freeze

SIGFRZ[8:1]

TDO

Boundary Scan

(JTAG)

Receive System Bus

(RSB)

Transm it System Bus

(TSB)

Receiver

(RCVR)

Transmitter

(XMTR)

LIU Serial

Port Interface

(SERIO)

Microprocessor Interface

and Control

(MPU)

Data or Multiplexed

Te st Clock In

Test mode Select

Test Data In

Test Reset In

Data Transfer Acknowle dge

Interrupt Request

One-Second Timer

Seri al Clock Out

Serial Data Out

Serial Port 1 and 2

Chip Selects

Tr an smi t Datalink Data In

Mult iframe Sync Out

Address/Da t a Bu s

I= Input, O= Output

PIO = Programmable I/O; controls located at PIO (address 018)

8394-8-5_021

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-29

Figure 1-11. CX28395 Logic Diagram (Non-Multiplexed System Bus M ode)

Test Data Out 1

PIO RSB Frame/Multiframe Sync

RSB PCM Data Out

OTransmit Clock Out

Tr a nsmi t Transmit NRZ Out

PIO TSB Frame/Multiframe Sync

PIO

Receive NRZ In

Receive Negative In

TSB Cloc k In

TSB PCM Data In

I/O

Hard war e Reset

System Clock

Pro c esso r Clock

Synchro nous Bus mode

Moto rol a Bus mode

Address Strobe

Chip Select 1

Data or Re ad Strobe

Read/ Write or Write Strobe

Address Bus

Transmit Cloc k In

1544 KHz All Ones Clock

Recei ve Clock In

TSB Sig na lling In/

RSB C loc k In

2048 KHz All Ones Clock

RST*

SYSCKI

MCLK

SYNCMD

MOTO*

AS*(ALE*)

CS1*

Chip Select 2 CS2*

R/W*(W*)

AD[7:0]

A[11:0]

TCKI[16:1]

T1ACKI

E1ACKI

RCKI[16:1]

RNRZ[16:1]

RNEGI[16:1]

TSBCKI[16:1]

TPCMI[16:1]

TSIGI[16:1]

RSBCKI[16:1]

TCK

TMS

TDI1

TRST*

DTACK*

INTR*

ONESEC

TCKO[16:1]

TNRZO[16:1]

TFSYNC[16:1]/TMSYNC[16:1]

RPCMO[16:1]

RFSYNC[16:1]/RMSYNC[16:1] RSB Signalling

RSIGO[16:1]

TDO1 Test Data Out 2

TDO2

Boundary Scan

(JTAG)

Receive System Bus

(RSB)

Transm it System Bus

(TSB)

Receiver

(RCVR)

Transmitter

(XMTR)

Microprocessor Interface

and Control

(MPU)

Data or Multiplexed

Te st Clock In

Test mode Select

Test Data In 1 ITDI2

Test Data In 2

Test Reset In

Data Transfer Acknowle dge

Interrupt Request

One-Second Timer

Address/Da t a Bu s

I= Input, O= Output

PIO = Programmable I/O; controls located at PIO (address 018)

8394-8-5_006

DS*(RD*)

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-30 Conexant 100054E

Figure 1-12. CX28395 Logic Diagram (Multiplexed System Bus Mode)

MCLK

SYNCMD

AS* (ALE*)

MOTO*

Processor Clock

Synchronous Bus Mode

Motorola Bus Mode

Address Strobe

RST* Hardware Reset

SYSCKI System Clock

Microprocessor

Interface and

Control

(MPU)

TCKI[16:1]

T1ACKI

TPCMI[A:D]

E1ACKI

RCKI[16:1]

RNRZ[16:1]

TSBCKI[A:D]

Transmit Clock In

1544 KHz All Ones Clock

2048 KHz All Ones Clock

Bused TSB PCM Data In

Receive Clock In

Receive NRZ In

Bused TSB Clock In

TCKO[16:1] Transmit Clock Out

TNRZO[16:1] Transmit Positive / Transmit NRZ Out

Transmitter

(XMTR)

Receiver

(RCVR)

Transmit System Bus

(TSB)

TSIGI[16:1]

RSBCKI[A:D]

TMSYNC[16:1]

TINDO[A:D]

TSB Multiframe Sync

Bused Timeslot Indicator

TSB Signalling In

Receive System Bus

(RSB)

Bused RSB Clock In RPCMO[A:D] Bused RSB PCM Data Out

RMSYNC[16:1] RSB Multiframe Sync

RINDO[A:D] Bused Timeslot Indicator

TDO1 Test Data Out 1

Boundary Scan

(JTAG)

TRST* Test Reset In

I = Input, O = Output

PIO = Programmable I/O; controls located at PIO (address 018)

RFSYNC[A:D] Bused RSB Frame Sync

RSIGO[16:1] RSB Signalling

TFSYNC[A:D] Bused TSB Frame Sync

CS1* Chip Select 1

TCK Test Clock In

TMS Test Mode Select

TDI2 Test Data In 2

TDI1 Test Data In 1

DS* (RD*)

R/W* (W*)

AD[7:0]

Data or Read Strobe

Read/Write or Write Strobe

Data or Multiplexed

Address/Data Bus

CS2* Chip Select 2

A[11:0] Address Bus

DTACK* Data Transfer Acknowledge

ONESEC1 One-Second Timer 1

INTR1* Interrupt Request 1

INTR2* Interrupt Request 2

ONESEC2 One-Second Timer 2

Test Data Out 2 TDO2

8394-8-5_022

I/O

PIO

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-31

Table 1-6. Hardware Signal Definitions (1 of 9)

Pin Label Signal Name Device(1) I/O Definition

Microprocessor Interface (MPU)

RST* Hardware Reset 4, 5, 8 I High-to-low-to-high cyc le forces registers to their

power-up state and all PIO pins to the input state. RST*

is not mandatory since power-on reset circuit perf orms

an identical fun ction. RST* must remain asserted for a

minimum of 2 processor clock cycles (MCLK or SYSCKI,

dep e nding on SYNCM D select ion).

SYSCKI System Clock 4, 5, 8 I Required 32.768 MHz clock for internal use. Supplied

from ext ernal source.

MCLK Processor Clock 4, 5, 8 I System applies MCLK in the ran ge of 8–36 MHz for use

with synchronous MPU applications. MC LK is used

when SYNCMD = 1 an d ignored when SYNC MD = 0.

SYNCMD Sync mode 4, 5, 8 I Selects synchronous or asynchronous read/ write ti ming

with respect to MCLK. Supports Intel- or Motorola-style

buses:

0 = Asynchronous Bus; read and write latches are

asyn chronously controlled by CS*, DS*, and R/W*

signals.

1 = Sy nchronous Bus; MCLK rising edge samples

CS*, DS*, and R/W* to determine valid read/write cycle

timing.

MOTO* Motorola Bus

Mode 4, 5, 8 I Selects Intel- or Motorola-sty le microprocessor

interface. DS*, R/W*, A[11:0], and AD[7:0] functions are

affected.

0 = Motorola; AD[7:0] i s data, A[11:0] is address,

DS* i s data strobe, and R/W* indicat es read (hi gh) or

write (low) data direction.

1 = Intel; AD[7:0] is multiplexed address/data, A[7:0]

is ignored, A[11:8] is address, DS* is read strobe (RD*),

and R/W* is writ e strobe ( WR*).

A[10:0] Address Bus 4 I Address used to identif y a re gister for subsequent

read/write data transfer cycle. In Motorola bus mode, all

eleven address bits (A[10:0]) are valid. In In tel bus

mode, only upper three bits (A[10:8]) are used.

A[11:0] Address Bus 5, 8 I Address used to identi fy a register for subsequent

read/wri te data transf er cycle. In Motorola bus mode, all

twelve address bits (A[1 1:0]) are valid. In Intel bus

mode, only upper four bits (A[11:8]) are used.

AD[7:0] Data Bus or

Address Data 4, 5, 8 I/O Multiplexed address/data (Intel) or data on ly(Motor ola).

Refer to MOTO* signal definition.

AS*(ALE) Address St robe 4, 5, 8 I For all processor bus modes, AS* falling edge

asynchronously l atches address from A[11:0]

(Motorola) or A[11:8], AD[7:0] (Intel) to identify one

CS1*, CS2* Chip Select 5 I Active-low enables read/write decoder . Active high ends

current read or write cycle and places data bus output in

high impedance. CS1* is the chip select pin fo r framers

1 to 8, CS2* is the chip select for framers 9 to 16.

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-32 Conexant 100054E

Microprocessor Interface (MPU) (Continued)

CS* Chip Select 4, 8 I Active-low enables read/write decoder. Active high ends

current read or write cycle and places data bus output in

high impedance.

DS*(RD*) Data Strobe or

Read Strobe 4, 5, 8 I Active-low read data str obe (RD* ) for MOTO* = 1, or

data strobe (DS*) for MOTO* = 0.

R/W*(WR*) Read/Write

Direction or

Write Str o be

4, 5, 8 I Active-low write data strobe (WR*) for MOTO* = 1, or

data select (R/W*) for MOTO* = 0.

ONESEC One Second

Timer 4, 8 PIO Cont rols or marks one-second interval used for statu s

reporting . When input, the t imer is a ligned to ONESEC

rising e dge. When output, rising edge indicates start of

each one-second interval.

ONESEC1

ONESEC2 One Second

Timer 5 PIO Controls or marks one-second interval used for status

reporting . When input, the t imer is a ligned to ONESEC

rising edge. When output, rising edge indicates start of

each one-second int erval . ONESEC1 is the one second

timer for framers 1 to 8, ONESEC2 is the one second

timer for framers 9 to 16.

INTR* Interrupt

Request 4, 8 O Open drain active low output signifies one or more

pending interrupt requests. INTR* goes to

high-impedance state with weak (>50 kΩ) internal pullup

resistance after processor has serviced all pending

interrupt requests.

INTR1*

INTR2* Interrupt

Request 5 O Open drain active lo w out put signifies one or more

pendin g in te rr up t req ue s ts . INTRn* goes to

high -im ped an ce st at e wi th we ak ( >50 k Ω) interna l pullu p

resistance after processor has serviced all pending

interrupt requests. INTR1* is the interrupt request for

framers 1 to 8, INTR2* is the interrupt request for

framers 9 t o 16.

DTACK* Data Transfer

Acknowledge 4, 8 O Op en drain active low output signifies in-progress data

transfer cycle. DTACK* remains assert ed (low) for as

long as AS * and CS* are both ac tive-low.

DTACK1*

DTACK2* Data Transfer

Acknowledge 5 O Open drain active lo w out put signifies in-progress data

transfer cycle. DTACKn* remains asserted (low) for as

long as AS * and CSn* are both active-low.

Table 1-6. Hardware Signal Definitions (2 of 9)

Pin Label Signal Name Device(1) I/O Definition

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-33

LIU Serial Interface

SERDI Serial Data Input 4, 8 I Serial data input from an LIU is sampled on rising edge

of SERCKO and written into Serial Dat a Register; addr

023.

SERCK O Serial Clock 4, 8 O Serial bit clock pro vided for transmitting and receiving

serial LIU data on SERDI and SERDO. SERCKO

freq uency is 1.024 MHz or 8 .192 MHz selectable.

SERDO Serial Data

Output 4, 8 O Address and da ta is output to an LIU ser ially on SERDO.

Data changes on fal ling edge of SERCKO.

SERCS* Serial Chip

Select 4 O Chip select li ne used to select an LIU’s serial port for

communication. SERCS is controlled in Serial

Configuration Register; addr 025.

SERCS1*

SERCS2* Serial Chip

Selects 8 O Chip select lines used to select an LIU’s serial port for

communication. SERCS1* and SERCS2* are

independently cont rolled in Serial Configuration

Transmitter (XMTR)

TCKI[4:1]

TCKI[8:1]

TCKI[16:1]

TX Clock Input 4

I Primary TX line rate cloc ks for transmitter si gnals:

TPOSO, TNEGO, TNRZO, MSYNCO, TDLI, and TDLCKO.

If TSLIP is bypassed, TCKI a lso clocks TSB signals.

T1ACKI T1 All Ones

Clock 4, 5, 8 I Syste m option ally applies T1ACKI to use for T1 AIS

transmission in case the selected primary transmit clock

source f a ils . T1ACK I i s ei t h er ma nuall y or au t o ma t ical ly

switched to replace TCKI (see [AISCLK; ad dr 075]).

Systems withou t a T 1 AI S clock should tie T1ACKI to

ground.

E1ACKI E1 All Ones

Clock 4, 5, 8 I Syste m option ally applies E1ACKI to use for E1 AIS

transmission in case the selected primary transmit clock

source f a ils . E1ACK I i s ei t h er ma nuall y or au t o ma t ical ly

switched to replace TCKI (see [AISCLK; ad dr 075]).

Systems without an E1 AIS cloc k should tie E1A CKI to

ground.

TPOSO[4:1]

TPOSO[8:1] TX Positive Rail

Output 4

8O Line rate data output from ZCS encoder changes on

rising edge of TCKO. Act ive-high ma rks transmis sion of

a positive AMI pulse.

TNEGO[4:1]

TNEGO[8:1] TX Negative Rai l

Output 4

8O Line- rate data output from ZCS encode r changes on

rising edge of TCKO. Active high marks transmission of a

negative AMI pulse.

TDLI[4:1]

TDLI[8:1] TX Data Link

Input 4

8I Selected tim e sl ot bits are sam pled on TDLCKO fallin g

edge for in sertio n into th e transm it outpu t stream d uring

external data link appl ications.

TDLCKO[4:1]

TDLCKO[8:1] TX Data Link

Clock 4

8O Gapped version of TCKI for external data link

appli cations. TD LCKO high clock pulse co incides wit h

low TCKI pulse interval during sel ected time slot b its,

else TD LCKO low (see [DL3_TS; addr 015]).

Table 1-6. Hardware Signal Definitions (3 of 9)

Pin Label Signal Name Device(1) I/O Definition

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-34 Conexant 100054E

Transm itter (XMTR) (Continu ed )

TCKO[4:1]

TCKO[8:1]

TCKO[16:1]

TX Clock Output 4

O Line rate clock. TCKO equals selected TCKI or T1 ACKI

(E1ACKI).

TNRZO[4:1]

TNRZO[8:1]

TNRZO[16:1]

TX Non Return

to Zero Data 4

O Line-rate data output from transmitter on rising edge of

TCKO. TNR ZO do e s no t inclu de ZCS enc od ed bipolar

violations.

MSYNCO[4:1]

MSYNCO[8:1]

MSYNCO[16:1]

TX Multifra m e

Sync 4

O Active high for one TCKI clock cycle to mark the first bit

of TX mult ifra m e co in c id en t with TNRZO. Outp ut on

risi ng edge of TCKO.

Receiver (RCVR)

RCKI[4:1]

RCKI[8:1]

RCKI[16:1]

RX Clock In put 4

I L ine rate clock samples RPOSI and RNEGI or RNRZ.

RNRZI[4:1]

RNRZI[8:1]

RNRZI[16:1]

RX Posi tive Rail

Input 4

I Line r a te data input on rising edge of RCKI. Non -return

to zero (NRZ) receive data.

RPOSI[4:1]

RPOSI[8:1] RX Positive Rail

Input 4

8I Line r a te data input on rising edge of RCKI. RPOSI and

RNEGI levels are interpreted as received AMI pulses,

encoded as follow s:

Unipolar. Non-return to zero (NRZ) data may be

connected to RPOSI or RNEGI in which case the other

input should be connected to ground. In this

conf ig ur a tio n RAM I [RCR0; addr 040] should b e s e t to 1

(receive AMI li ne f ormat) and DIS_LCV

[RALM; addr 045] sho uld be set to 1 (disable LCV

counting and reporting).

RNEGI[4:1]

RNEGI[8:1] RX N egativ e Rail

Input 4

8I Line ra te data input on rising edge of RCKI. See RPO SI

sig nal defi nition.

RDLO[4:1]

RDLO[8:1] RX Data Link

Output 4

8O Line rate NRZ data outpu t from receiver on falling ed ge

of RCKI. Al l receive data is represented at the RDLO pin.

However, selective RDLO bit positions are also marked

by RDLCKO for external data link applications.

RDLCKO[4:1]

RDLCKO[8:1] RX Data Link

Clock Output 4

8O Gapped versi on of RCKI for external data li nk

appli cations. RDLCKO high clock pulse coincides wit h

low RCKO pulse inte rval du ring selecte d time slot bits,

otherwise RDLCKO is lo w (see Figure 2-4, Receive

Extern al Data Link Wavefor ms).

Table 1-6. Hardware Signal Definitions (4 of 9)

Pin Label Signal Name Device(1) I/O Definition

RPOSI RNEGI RX Pulse Polarity

00 No pulse

0 1 Negative AMI pulse

1 0 Positive AMI pulse

1 1 In va lid (de c oded as a pul se)

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-35

Transmit System Bus (TSB)

TSBCKI[4:1]

TSBCKI[8:1]

TSBCKI[16:1]

TSBCKI[A]

TSBCKI[B]

TSBCKI[C]

TSBCKI[D}

TSB Clock Input

Bused TSB Clock

Inputs

4,5,8

5,8

I Bit clock and I/O signal t iming for TSB according to

system bus mode (see [SBI_C R; addr 0D0]). System

chooses from one of two differe nt clocks to act as TSB

clock so urce (see [CMUX; addr 01A]). Rising or falling

edge clocks are independently configurable for data

signa ls TPCM I, TSIGI, TINDO an d sy n c si gn a ls TFS YNC

and TMSYNC (see [TPCM_N EG and TSYN_NEG;

addr 0D4]). When configured to operate at twice the data

rate, TSB clock is in ternally divided by 2 before clocking

TSB data signals.

TPCMI[4:1]

TPCMI[8:1]

TPCMI[16:1]

TPCMI[A]

TPCMI[B]

TPCMI[C]

TPCMI[D]

TSB Data Input

Bused TS B Data

Input

4,5,8

5,8

I Serial data formatted into TSB frames consisting of DS0

chan nel time slots and optional F-bits . One grou p of 24

T1 time slots or 32 E1 ti me slots is selected from up to

four available groups; data from the group is sampled by

TSBCKI, then sent towards transmitter output. Time

slots are routed through transmit slip buffer (see

[TSLIPn; addr 140–17F]) according to TSLIP mode (see

[TSBI; addr 0D4]). F-bits are taken from the start of each

TSB frame or from within an embedded time slot (see

[EMBED; addr 0D0]) and optionally inserted into the

transmitter output (see [TFRM; addr 072] regis ter).

TSIGI[4:1]

TSIGI[8:1]

TSIGI[16:1]

TSB Signaling

Input 4

I Serial dat a formatted into TSB frames contai ning ABCD

signaling bits for each system bus time slot. Four bits of

TSIGI time slot carry signal ing state for eac h

accompanying TPCMI time sl ot. Signaling state of every

time slot is sampled during first frame of the TSB

multiframe and then transferred into transmit signaling

buffer [TSIGn; addr 120–13F].

TINDO[4:1]

TINDO[8:1]

TINDO[16:1]

TINDO[A]

TINDO[B]

TINDO[C]

TINDO[D]

TSB Time Slot

Indicator

Bused TS B Time

Slot Indicator

4,5,8

5,8

O Active-hig h output pulse marks selective transmit

system bus time slots as p r ogrammed by SBCn [addr

0E0-0FF], TINDO occurs on TSBCKI rising or falling

edges as selected by TPCM_NEG (see [TSBI; addr 0D4]).

TFSYNC[4:1]

TFSYNC[8:1]

TFSYNC[16:1]

TFSYNC[A]

TFSYNC[B]

TFSYNC[C]

TFSYNC[D]

TSB Frame Sync

Bused TS B

Frame Sync

4,5,8

5,8

PIO Input or output TSB frame sync (see [TFSYNC_IO; addr

018]). TFSYNC output is active high for one TSB clock

cycle at programmed offset bit location (see

[TSY NC_BIT; addr 0D 5]), marking offset bit position

within each TSB frame and repeating once every 125 µs.

When transmit framer is also enabled, TSB timebase and

TFSYNC output frame alig nment are established by

transmi t framer's exa mination of TPCMI serial data

input. When TFSYNC is programmed as an input, the

low-to-high signal transition is detected and is used to

align TSB timeb a se to program m e d offs e t bit value. TSB

timebase flywheels at 125 µs frame interval after the last

TFSYNC is applied.

Table 1-6. Hardware Signal Definitions (5 of 9)

Pin Label Signal Name Device(1) I/O Definition

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-36 Conexant 100054E

Transmit System Bus (TSB) (Continued)

TMSYNC[4:1]

TMSYNC[8:1]

TMSYNC[16:1]

TSB Multif rame

Sync 4

PIO Input or ou tp ut T SB m ul t ifr am e syn c ( s e e [T MS YNC _IO;

addr 018]). TMSYNC output is active high for one TSB

clock cycle at programmed offset bit locat ion (see

[TSY NC_BIT; addr 0D 5]), marking offset bit position

within each TSB multiframe and repeating once every 6

ms coincident with TFSYNC. Whe n t ransmit framer is

also enabled, TSB timebase and TMSYNC output

multiframe alignment are established by transmit

framer's examination of TPCMI serial data input . When

TMSYNC is programmed as an input, the low-to-high

signal transit ion is detected and is used to align TSB

timebase to programmed offset bi t value and first frame

of the multiframe. TSB timebase flywheels at 6 ms

multiframe intervals after t he last TMSYNC i s applied. If

system bus appli es TMSYNC input, TFSYNC input is not

needed.

Receive Sy stetm Bus (RSB)

RSBCKI[4:1]

RSBCKI[8:1]

RSBCKI[16:1]

RSBCKI[A]

RSBCKI[B]}

RSBCKI[C]}

RSBCKI[D]}

RSB Clock Inpu t

Bused RSB Data

Input

4,5,8

5,8

I Bit clock and I/O signal timing for RSB accordin g to

system bus mode (see [SBI_C R; addr 0D0]). System

chooses from one of two differe nt clocks to act as RSB

clock so urce (see [CMUX; addr 01A]). Rising or falling

edge clocks are independently configurable for data

signals RPCMO, RSIGO, RINDO and sync signals

RFSYNC, RMSYNC (see [RPCM_NEG and RSYN_NEG;

addr 0D1]) . Wh en con figu red t o ope rate at tw ice t he da ta

rate, RSB clock is inte rnally div ided by 2 b efore cl oc k in g

RSB data signals.

RPCMO[4:1]

RPCMO[8:1]

RPCMO[16:1]

RPCMO[A]

RPCMO[B]

RPCMO[C]

RPCMO[D]

RSB Data Output

Bused RSB Data

Output

4,5,8

5,8

O Serial data formatted in to RSB frames c ons is tin g of D S0

chann el time sl ots , op tio na l F-bits an d op tio nal ABCD

signal ing. Time slots are rout ed through receive slip

buffer (see [RSLIPn; addr 1C0–1FF]) according to RSLIP

mode (see [RSBI ; addr 0D1]). Data for each output time

slot is assigned sequentially from received time slot data

according to system bus channel programming (see

[ASSIGN; addr 0E0–0FF]). F-bits are output at the start

of each RSB frame or at the embedded time slot location

(see [ EMBED; ad dr 0D0]). ABCD signaling is optionally

inserted on a per-channel basi s (see [INSERT;

addr 0E0–0FF]) from the local signaling buffer (see

[RLOCAL; addr 1 80–19F]) or from the receive signaling

buffer [RSI Gn; addr 1A0–1BF]. When enabled, robbed

bit signaling or CAS reinsertion is performed accordin g

to T1/E1 mode: The eighth time slot bit of every sixth T1

frame is replaced, or th e 4-bit signa li ng value in the E1

time slot 16 is replaced.

RINDO[4:1]

RINDO[8:1]

RINDO[A]

RINDO[B]

RINDO[C]

RINDO[D]

RSB Tim e Sl ot

Indicator

Bused RSB Time

Slot Indicator

4,5,8

5,8

O Active high output pulse marks selective receive system

bus time sl ots as programmed by SB Cn [addr 0E0-0FF].

RINDO occurs on RSBCKI rising or falling edges as

selected by RPCM_NEG (see [RSBI; addr 0D 1]). Only

available in Multiplexed System Bus mode on CX28395

(see [FCR; addr 080]).

Table 1-6. Hardware Signal Definitions (6 of 9)

Pin Label Signal Name Device(1) I/O Definition

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-37

Receive Systetm Bus (RSB) (Continued)

RSIGO[4:1]

RSIGO[8:1]

RSIGO[16:1]

RSB Signal ing

Output 4

O Serial data formatted into RSB frames consisting of

ABCD si gnaling bits for each system bus time slot . Four

bits of RS IGO time slot carry signaling state f or each

accompanying RPCMO time slot. Local or through

signaling bits are output in every frame for each time slot

and updated once per RSB multiframe, regardless of

per-channel RPCMO signaling reinsertion.

RFSYNC[4:1]

RFSYNC[8:1]

RFSYNC[16:1]

RFSYNC[A]

RFSYNC[B]

RFSYNC[C]

RFSYNC[D]

RSB Frame Sync

Bused RSB

Frame Sync

4,8,5

5,8

PIO Input or outp ut RSB frame syn c (se e [RF S YNC_IO;

addr 018]). RFSYNC output is active high for one RSB

clock cycle at programmed offset bit locat ion (see

[RSYN C_BIT; addr 0D2 ]), marking offset bit within each

RSB frame and repeating once every 125 µs. RSB

timebase and RFSYNC output frame alignment begins at

an arbi trary position and changes alig nment according to

RSLIP mode (see [RSBI; addr 0D1]). When RFSYNC is

prog rammed as an input, the low-to-high signal

transition is detected and used to align RSB time base to

the programmed offset . RSB t imebase flywheels at

125 µs frame inter val after the last RFSYNC is applie d.

RMSYNC[4:1]

RMSYNC[8:1]

RMSYNC[16:1]

RSB Multifra m e

Sync 4

PIO Input or output R SB multifr ame syn c (see [R MSYNC_IO ;

addr 018]). RMSYNC output is active high for one RSB

clock cycle at programmed offset bit locat ion (see

[RSYN C_BIT; addr 0D2]), mar king offset bit within each

RSB multiframe and repeating once every 6 ms

coinci dent with RFS YNC. RSB timebase and RMSYN C

outp ut multiframe alignment begins at an arbitrary

position and changes align m ent according to RSLIP

mode (see [RSB I ; addr 0D1]). When RMSYNC is

prog rammed as an input, the low-to-high signal

transition is det ected and is used to align the RSB

timebase to programmed offset and first frame of the

multiframe. RSB timebase flywheels at 6 ms multiframe

interval aft er th e last RMSYNC is applied.

SIGFRZ[4:1]

SIGFRZ[8:1] Si gnaling Freeze 4

8O Active high indicat es that signaling bit up dates are

suspended for both receive signaling buffer [RSIGn;

addr 1A0–1BF ] and stack [STACK; addr 0DA] register.

SIGFRZ is clocked by RSB clock, goes hig h coincident

with receive loss of frame alignment (see RLOF;

addr 047) and returns low 6–9 ms after recovery of

frame alignment.

Table 1-6. Hardware Signal Definitions (7 of 9)

Pin Label Signal Name Device(1) I/O Definition

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-38 Conexant 100054E

Joint Test Access Group (JTAG)

TCK JT AG Clock 4, 5, 8 I Clock input samples TDI on rising edge and outputs TDO

on falling edge.

TDI1, TDI2 JTAG Test Data

Input 5 I Test data input pe r IEE E Std 11 49 .1 - 19 90 . Us ed for

loadin g all serial in structions and data into inte rn al tes t

logic. Sampled on the rising edge of TCK. TDI can be left

unconnected if it is not being used because it is pulled up

internally. TDI1 is the test data input for framers 1 to 8,

TDI2 is the test data inp ut for framers 9 to 16.

TDI JTAG Test Data

Input 4, 8 I Test data input per IEEE Std 1149.1-1990. Used for

loadin g all serial in structions and data into inte rn al tes t

logic. Sampled on the rising edge of TCK. TDI can be left

unconnected if it is not being used because it is pulled up

internally.

TMS JTAG Test mode

Select 4, 5, 8 I Active low test mode select input per I EEE Std

1149.1-1990. Int e rnally pulled-up input signal used to

control the test-logic state machine. Sampled on the

risi ng edge of TCK. TMS can be left unconnected if it is

not being us ed because it is pulled up internally.

TDO JTAG Test Data

Output 4, 8 O Test data output per IEEE Std 1149.1 -1990. TDO is a

three-state output used for reading all serial

confi guration and test da ta from int e rnal test logic.

Updat e d on the falling edge of TCK.

TDO1, TDO2 JTAG Test Data

Output 5 O Test data output per IEEE Std, 1149. 1-1990. TDO is a

three-state output used for reading all serial

confi guration and test da ta from int e rnal test logic.

Updated on the falling edge of TCK. TDO1 is the test data

output for fra mers1 to 8, TDO2 is the test data output for

framers 9 t o 16.

TRST* JTAG Reset 4, 5, 8 I Active low input to initialize Tap Controller.

Power Supply

VDD Power 4, 5, 8 I +3.3 Vdc ±5%.

VSS Ground 4, 5, 8 I 0 Vdc.

VGG High V o lta g e

Power 4, 5, 8 I +3.3 Vdc ±5%. Connect to +5 Vdc ±5% to ensure 5 V

toleran c e in ap p lic a tio ns whic h inc lude 5 V logic dri vi ng

signals.

Table 1-6. Hardware Signal Definitions (8 of 9)

Pin Label Signal Name Device(1) I/O Definition

CX28394/28395/28398 1.0 Product Description

Quad/x16/Octal—T1/E1/J1 Framers 1.2 P in Assignments

100054E Conexant 1-39

Test

TSTO[16:1] Test Output 5 O Test output. Leave disconnected for normal operation.

TSTI[16:1] Test Input 5 I Test input. Connect through 50k ohm pull-up resistor to

VDD for normal operation.

NOTE(S):

(1) 4 = CX28394

5 = CX28395

8 = CX28398

1. All RSB and TSB out puts can be pl aced in high-impeda nce state (see S BI _OE; addr 0D0).

2. I = Input, O = Output

3. PIO = Pro grammable I/O ; controls located at address 018.

4. Mult iple signal names show mut ually exclusive pin fu nctions.

Table 1-6. Hardware Signal Definitions (9 of 9)

Pin Label Signal Name Device(1) I/O Definition

1.0 Product Description CX28394/28395/28398

1.2 Pin Assignments Quad/x16/Octal—T1/E1/J1 Framers

1-40 Conexant 100054E

100054E Conexant 2-1

2.0 Circuit Description

2.1 Functional Block Diagram

Figures 2-1 and 2-2 i llustrate det aile d framer b lock di agrams for non-mult iple x ed

and multiplexed system bus mo des. To show the details of th ese circuits,

indi vidu al b lock diagrams of the functions listed bel o w have been created and are

placed, along with descriptions, throughout this section:

• Receiver (RCVR)

• Receive System Bus (RSB)

• Transmit System Bus (TSB)

• Transmitter (XMTR)

• Microprocessor Interface (MPU)

• Joint Test Access Group Por t (JTAG)

• Serial Port (SERIO)

2.0 Circuit Descrip tion CX28394/28395/28398

2.1 Func tional Block D iag ram Quad/x16/Octal—T1/E1/J1 Framers

2-2 Conexant 100054E

Figure 2-1. Detailed Framer Block Diagram (Multiplexed System Bus Mode)

NOTE(S):

(1) Not available on CX28395.

MCLK

SYNCMD

AS*

DS*

R/W*

AD[7:0]

A[11:0]

INTR*

ONESEC

RST*

CS*

SYSCKI

MOTO*

DTACK*

TCK

TMS

TDI

TDO

SERCS[1:0]

SERCLK

SERDO

SERI

RSIG

Stack

RSIG

Buffer

RZCS

Decoder

Clock

Monitor

TZCS

Encoder

External DLINK

PRBS/Inband LB

DLINK2 Buffer

DLINK1 Buffer

Sa-Byte/BOP

PDV Monito r

Error Counters

Alar m Monito r

Receiver Framer

Transmitter

Timebase

T1/E1 Frame Insert

External Dlink

DLINK1 Buffer

DLINK2 Buffer

Sa-Byte/BOP

PRBS Inband LB

Alarm/Error Insert

PDV Enforcer

TSIGI[1]

TPCMI[A]

RSIGO[1]

RPCMO[A]

SIGFRZ[1]

RINDO[A]

RFSYNC[A]

TCKI

TIACKI

TSBCKI[A]

TINDO[A]

RPHASE

TPHASE

TSLIP

Buffer

TSIG

Buffer

TSIG

Buffer

RMSYNC[1]

RSBCKI[A]

RSB

Timebase

TSB

Timebase

Transmit

Framer

AIS

RSIG

Local

RSLIP

Buffer

FRAMER 1

TPOSO[1]

RPOSI[1]

RNRZI[1]

RNEGI[1]

RCKI[1]

TCKO[1]

TNEGO[1]

TNRZO[1]

MSYNCO [1]

TDLCKO[1]

TDLI[1]

RDLCKO[1]RDLO[1]

Receive

Timebase

FRAMER 2

TMSYNC[1]

TFSYNC[A]

E1ACKI

Per-Channel

Local Loopback

Per-Channel

Remot e Loopbac k

Line Loopback

F ramer Loopback

8394-8-5_001

Microprocessor Port JTAG Port

TRST*

Serial Port

(1) (1)

(1)

(1) (1)

(1)

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.1 Functional Block Diagram

100054E Conexant 2-3

Figure 2-2. Detailed Framer Block Diagram (Non-multiplexed System Bus Mode)

NOTE(S):

(1) Not available on CX28395.

MCLK

SYNCMD

AS*

DS*

R/W*

AD[7:0]

A[11:0]

INTR*

ONESEC

RST*

CS*

SYSCKI

MOTO*

DTACK*

TCK

TMS

TDI

TDO

SERCS[1:0]

SERCLK

SERDO

SERI

RSIG

Stack

RSIG

Buffer

RZCS

Decoder

Clock

Monitor

TZCS

Encoder

External DLINK

PRBS/Inband LB

DLINK2 Buffer

DLINK1 Buffer

Sa-Byte/BOP

PDV Monito r

Error Counters

Alar m Monito r

Receiver Framer

Transmitter

Timebase

T1/E1 Frame Insert

External Dlink

DLINK1 Buffer

DLINK2 Buffer

Sa-Byte/BOP

PRBS Inband LB

Alarm/Error Insert

PDV Enforcer

TSIGI[1]

TPCMI[1]

RSIGO[1]

RPCMO[1]

SIGFRZ[1]

RINDO[1]

RFSYNC[1]

TCKI[1]

TIACKI

TSBCKI[1]

TINDO[1]

RPHASE

TPHASE

TSLIP

Buffer

TSIG

Buffer

TSIG

Buffer

RMSYNC[1]

RSBCKI[1]

RSB

Timebase

TSB

Timebase

Transmit

Framer

AIS

RSIG

Local

RSLIP

Buffer

FRAMER 1

TPOSO[1]

RPOSI[1]

RNEGI[1]

RCKI[1]

TCKO[1]

TNEGO[1]

TNRZO[1]

MSYNCO [1]

RDLCKO[1]RDLO[1]

Receive

Timebase

FRAMER N

TMSYNC[1]

TFSYNC[1]

E1ACKI

Per-Channel

Local Loopback

Per-Channel

Remot e Loopbac k

Line Loopback

F ramer Loopback

8394-8-5_001a

Microprocessor Port JTAG Port

TRST*

Serial Port

RNRZI[1]

(1)

TDLCKO[1]

TDLI[1]

(1) (1)

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-4 Conexant 100054E

2.2 Receiver

The Receiver (RCVR) inputs single rail NRZ data or decodes positive and

negative rail NRZ data into single rail NRZ data. The RCVR, illustrat ed in

Figure 2-3, consists of the following elements: Receive Zero Code Suppression

(RZCS) Decoder, In-Band Loopback Code Detector, Error Counters, Error

Monitor, Alar m Monitor, Test Pattern Receiver, Receive Framer, External

Receive Data Link, and Receive Data Links.

2.2.1 ZCS Decoder

The Receive Zero Code Suppression (RZCS) decoder is applicable only to the

CX28394 and CX28398. The decoder decodes the dual rail data (bipolar) into

single rail data (unipolar). The Receive AMI bit (RAMI) in the Receiver

Configuration register [RCR0; addr 040] controls whether the received signal is

B8ZS/HDB3 decoded, depending on T1/E1N [addr 001] line rate selection, or if

the RZCS decoder is bypassed. If the line code is unknown, the ZCSUB bit in

Receive Line Code Status [RSTAT; addr 021] indicates the RPOSI/RNEGI input

received one or more B8ZS/HDB3 substitution patterns. If the line code is

B8ZS/HDB3-encoded, the RZCS bit in RCR0 should be set to keep the LCV

counter from counting BPVs that are part of the B8ZS/HDB3 code.

Figure 2-3. RCVR Diagram

External DLINK

PRBS/Inband LB

Sa-Byte

RPDV Monitor

Error Monitor

Error Counters

Alarm Monitor

Receive Framer

Receiver Timebase

RCKI

RZCS

Decoder

Line

Loopback Framer

Loopback

RPOSI

RNEGI RNRZ

RDLO

RDLCKO

DLINK1

MOP/BOP

DLINK2

MOP

MPU

Registers

To RSB

RNRZI

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-5

2.2.2 In-Band Loopback Code Detection

The in-band loopback code detector circuitry detects receive data with in-band

codes of configurable value and length. These codes can be used to request

loopback of terminal equipment signals or other user specified applications. The

two codes are refer red to as loopback-activate and loopback-deactivate, although

the detectors need not be used only for loopback codes. Generally, any repeating

1–7 bit pattern can be selected. The loopback application is described in Section

9.3.1 of ANSI T1.403-1995. The loopback activate code is set in the Loopback

Acti v ate Code P att ern [LB A; addr 043]. The l oopback de activate code is set in the

Loopback Deactivate Code Pattern [LBD; addr 044].

The sequence length for the loopback activate and deactivate codes can be

prog rammed for 4, 5, 6, or 7 bits by setting the code length bits of the Receive

Loopback Code Detector Configuration register [RLB; addr 042]. Shorter codes

can be programmed by repeating the expected pattern (e.g. 3+3 bit code

programmed as 6-bit code).

T1 In-Band Loopback Codes

Activate 00001

Deactivate 001

When a loopback code is detected, the LOOPUP or LOOPDN status bit is set

in Alarm 2 register [ALM2; addr 048], and the corresponding LOOPUP or

LOOPDN bit in Alarm 2 Interrupt Status register (ISR6; addr 005] is set. The

loopback detection interrupt can be enabled using the Alarm 2 Interrupt Enable

re gist er [ I ER6; add r 00D] . Whe n enabled, a loop-up or loop-down code detect ion

causes the Alar m 2 Inter rupt bit [ALARM2] to be set in the Interrupt Request

automatically initiated, the processor must intercept and interpret th e interrupt

status con dit i on to determine w h en i t must en able or di sable the loopback con trol

mechanism (e.g., LLOOP; addr 014).

2.2.3 Error Counters

The following P erformance Monitorin g (PM) counters are availa b le in the RCVR:

• F raming Bit Errors (FERR)

• CRC Errors (CERR)

• Line Code Violations (LCV)

• Far End Block Errors (FEBE)

All PM count registers are reset on read unless LATCH_CNT is set in the

Alarm/Error/Counter Latch Configuration register [LATCH; addr 046].

LATCH_CNT enables the one-second latching of counts coincident with the

one-second timer interrupt [ISR6; addr 005]. One-second latching of PM counts

is required if AUTO_PRM responses are enabled. All PM counters can be

disabled during RLOF, RLOS, and RAIS, using the STOP_CNT bit in the

LATCH register.

Note that if STOP_ CNT is neg ated, error monitoring dur ing RLOF con ditions

will detect FERR, CERR, and FEBE according to the last known frame

alignment.

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-6 Conexant 100054E

2.2.3.1 Frame Bit Error

Counter The 12-bit Framing Bit Error Counter [FERR; addr 050 and 051] increments

every time a receive Ft, Fs, T1DM, FPS, or FAS error is detected. Fs (T1) and

NFAS (E1) errors can be included in the FERR count by setting FS_NFAS in

Recei ve Al arm Signal Configuration [RALM; addr 0 45]. An interrupt is avai lable

to indicate that the FERR counter overflowed in the Counter Overflow Interrupt

Status register [ISR4; addr 007].

2.2.3.2 CRC Error

Counter The 10-bit Cyclic Redundancy Check Error Counter [CERR; addr 052 and 053]

increments each time a receive CRC4 (E1) or CRC6 (T1) error is detected. An

interrupt is available to indicate that CERR counter overflowed in ISR4.

2.2.3.3 LCV Error

Counter The 16-bit Line Code Violation Error Counter [LCV; addr 054 and 055]

increments each time a receive Bipolar Violation (BPV)—not including line

coding—is detected. The LCV count can include EXZ if EXZ_LCV in the

Receive Alarm Signal Configuration register [RALM; addr 045] is set. EXZ can

be configured [RZCS; addr 040] to be 8 or 16 successive zeros, following a one.

An interr upt is available to indicate that the LCV counter overflowed in ISR4.

2.2.3.4 FEBE Counter The 10-bit Far End Block Error (FEBE) counter [FEBE; addr 056 and 057]

increments every time the RCVR encounters an E1 far-end block error. An

interrupt is available to indicate that the FEBE counter overflowed in ISR4.

2.2.4 Error Monitor

The follow ing signal errors are detected in the RCVR:

• F rame Bit Error (FERR)

• MFAS Error (MERR)

• CAS Erro r (SERR)

• CRC Error (CERR)

• Pulse Density Violation (PDV)

Each error type has an interrupt enable bit that enables an inter rupt to occur

marking the e ven t, and an interrupt register bi t that is read b y the interrupt service

routine to deter mine which event caused the interr upt. All error status registers

are reset on read unless the LATCH_ERR bit is set in the Alarm/Err or/Counter

Latch Configuration register [LATCH; addr 046]. LATCH_ERR enables the

one-second latching of alarms coincident with the one-second timer interrupt

[ISR6; addr 005]. With LATCH_ERR enabled, any error detected during the one

second interval is latched and held during the following one-second interval.

LATCH_ERR allows the processor to gather er ror statistics based on the

one-second interval.

2.2.4.1 Frame Bit Error FERR is reported for the receive d irection in the Error Interrupt Status register

[ISR5; addr 006] and for the transmi t di recti on i n P at tern Interrupt Status

[ISR0; addr 00B]. FERR indicates t hat o ne or more Ft/ Fs/F PS fr ame-bit errors or

FAS-pattern errors occurred since the last time the interrupt status was read. The

FERR type is det ermined b y the receive framer’s configuration [CR0; address 001].

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-7

2.2.4.2 MFAS Error When CRC4 framing is enab led , MERR is reported for the receiv e direction in the

Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in

Pattern Interrupt Status [ISR0; addr 00B]. MERR is applicable only in E1 mode,

and indicates that one or more MFAS pattern errors occurred since the interrupt

status was last read.

2.2.4.3 CAS Error When CAS framing is enabled, SERR is reported for the receive direction in the

Error Interrupt Status register [ISR5; addr 006] and for the transmit direction in

Pattern Interrupt Status [ISR0; addr 00B]. SERR is only applicable in E1 mode,

and indicates that one or more errors were received in the TS16 Multiframe

Alignment Signal (MAS) since the interrupt status was last read.

2.2.4.4 CRC Error CERR is reported for the receive direction in the Error Interr upt Status register

[ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status

[ISR0; addr 00B]. CERR is only appli cable in T1 ES F and E 1 MFAS modes, and

indicates t hat one or more bit errors were found in the CRC4/CRC6 patt ern block

since the interrupt status was last read.

2.2.4.5 Pulse Densit y

Violation PDV is reported when the receive signal does not meet the pulse density

requireme nts of ANSI T1.4 03- 19 95 (Sect i on 5.6). A PDV is declared when more

than 15 consecuti v e zeros or the a ver age ones density falls belo w 12.5 %. RPDV is

reported for the receive direction in the Alarm 1 Inter rupt Status register

[ISR7; addr 004].

2.2.5 Alarm Monitor

The follow ing signal alarms are detected in the RCVR:

• Loss Of Frame (LOF)

• Loss Of Signal (LOS)

• Receive Analog Loss Of Signal (RALOS)

• Alarm Indication Signal (AIS)

• Remote Alarm Indication (RAI) or Yellow Alarm (YEL)

• Multiframe Yellow Alarm (MYEL)

• Severely Errored Frame (SEF)

• Change Of Frame Alignment (COFA)

• Multiframe AIS (MAIS)

Each alarm has the following: a status register bit that reports the real-time

status of the event; an interrupt enable bit that enables an interrupt to mark the

even t; a nd an in terrupt regi st er bi t re a d by the int errupt service routi ne t o identif y

the event that caused the interrupt. All alarm st atus registers are reset on read

unless the LATCH_ALM bit is set in the Alarm/Error/Counter Latch

Configuration register [LATCH; addr 046]. LATCH_ALM enables the

one-second latching of alarms coincident with the one-second timer interrupt

[ISR6; addr 005]. With LATCH_ALM enabled, any alarm detected during the

one-second interval is latched and held during the following one-second interval.

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-8 Conexant 100054E

2.2.5.1 Loss of Frame Receiv e Loss Of F rame (RLOF) is d eclared w hen the recei ve data stream does not

meet the framing criteria specifi ed in the Receiver Configuration register

[RCR0; addr 040].

If the line rate is E1 [T1/E1N; addr 001], RLOF is the logically OR'ed status

of FAS, MFAS, and CAS alignment. These alignments, FRED, MRED and

SRED, respectively, are available separately in the Alarm 3 Status register

[ALM3; addr 049]. Once RLOF is declared t he LOF[1: 0] bits in ALM3 report the

reason for E1 loss of frame alignment. In T1 mode, RLOF is equal to FRED.

The RLOF real-time status is available in Alarm 1 Status register

[ALM1; addr 047], and the interrupt status is set in th e Alarm 1 Interrupt Status

Alarm 1 Interrupt Enable register [IER7; addr 00C].

An FRED count [FRED[3:0]; addr 05A] is also available in the

SEF/LOF/COFA Alarm Counter [AERR; addr 05A]. An inter rupt in Counter

Overflow Interrupt Status [ISR4; addr 007] indicates that the FRED counter

overflowed.

While T1 framing mode is enabled, the RLOF status and RLOF interrupt

status are integrated over 2.0 to 2.5 seconds if the RLOF_INTEG bit is set in the

Receive Alarm Signal Configuration register [RALM; addr 045]. The FRED

count is unaffected by RLOF_INTEG.

2.2.5.2 Loss of Signal If the line ra te is T1, the criteria for Receive Loss Of Si gnal (RLOS) is 100

contiguous zeros (consistent with the standard requirement of 175 ±75 zeros). If

the line rate is E1, the criteria for RLOS is 32 con tiguous zeros. RLOS is c le a re d

upon detecting an average pulse density of at least 12.5% (occurring during a

period of 175 ± 75 bits starting with the receipt of a pulse, and where no

occurrences of 100/32 cont iguous zer os are detect ed). The RLOS rea l-time status

is availa ble in ALM1 , and the interrupt is available in ISR7. The X MTR can be

configured to automatically generate an Alarm Indication Signal (AIS) in the

transmit direction when RLOS is declared (see AUTO_AIS [TALM; addr 075]).

2.2.5.3 Receive Analog

Loss of Signal RALOS [ALM1; addr 047] can be configured to report loss of receive clock

(RCKI) or loss of receive signal [RLOS; addr 047] for 1 msec depending on the

RALOS configuration bit [RAL_CON; addr 020]. RALOS status is provided for

compatib ili ty with ANSI T1. 431 loss of signa l det ection r equir ements; and works

in conjunction with LIUs which detect loss of signal if the received signal level

falls below a cer tain threshold and which have a signal ‘squelch’ feature. If

RAL_CON is set for loss of signal, RALOS indicates that all zeros have been

received for at least 1 msec (RLOS is active for 1 msec). If RAL_CON is set for

loss of clock, RALOS becomes active (1) if the receive clock on the RCKI pin is

not present, and inactive (0) if the clock is present.

2.2.5.4 Alarm

Indication Signal If the line rate is T 1 [T1/E1N; addr 001], th e criteria for Recei ve Al arm Indic ation

Signal (RAIS) is the reception of four or fewer zeros in a period of 3 ms (4632

bits) and assertion of RLOF. If the line rate is E1, RAIS is set if two consecutive

double frames e ach contain t wo or fewer zeros out of 512 bi t s and FAS ali gn ment

is lost [FRED; addr 049]. The RAIS real-time status is available in ALM1. The

RAIS interrupt is available in ISR7.

2.2.5.5 Yellow Alarm The criteria for Yel low Alarm (YEL) is describe d in Table 3-13, Recei ve Yellow

Alarm Set/Clear Criteria. YEL real-time status is available in ALM1; YEL

interrupt is available i n ISR7.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-9

2.2.5.6 Multiframe YEL The criteria for Mu ltiframe Yellow Alarm is described in Table 3-13, Receive

Yellow Alarm Set/Clear Criteria. The MYEL real-time status is available in

ALM1, and the interrupt is available in IS R7.

2.2.5.7 Severely Errored

Frame A SEF is reported when the receive signal does not meet the requirements of

ANSI T1.231. SEF real-time status is available in ALM3. A 2-bit counter is also

available [SEF; addr 05A]. An interrupt is available in ISR4 to indicate that the

SEF counter overflowed .

2.2.5.8 Change of

Frame

Alignment

Each COFA increments a 2-bit counter [COFA; addr 05A]. An interrupt is

available in ISR4 to indicate that the COFA counter overflowed.

2.2.5.9 Receive

Multiframe AIS Receive Multiframe AIS (RMA IS) is reported when the receive TS16 signal

contains three or fewer zeros out of 128 bits in each multiframe over two

consecutive multiframes, according to the requirements of ITU–T

Recommendation G.775. RMAIS is only checked in E1 CAS mode. RMAIS

real-time status is available in ALM3 [addr 049].

2.2.6 Test Pattern Receiver

The test pattern recei ver circuitry can sync on framed or unframed PRBS patterns

and count bit errors. This feature is particularly useful for system diagnostics,

producti on test ing, and test equipment appl icat ions. The PRBS patterns a vaila ble

include 2E11-1, 2E15- 1, 2E20-1, and 2E23 -1. Each pattern can opti onall y include

Zero Code Suppression (ZCS).

The Receive Test Pattern Configuration register [RPATT; addr 041] controls

the test patter n receiver circuit. The BSTART control bit (in RPATT) m ust be

active to enable the test pattern receiver and to begin counting bit errors. RPATT

control s the PRBS pattern, ZCS setting (ZLIMIT), and T1/E1 framing

(FRAMED). RPATT selects which PRBS pattern the receiver should hunt for

pattern sync. ZLIMIT selects the maximum number of consecutive zeros the

pattern is all owed to contain. FRAME D mode i nf orms the PRBS patt ern receiver

not to search for the pattern in the frame bit in T1 mode or search for the pattern

in time slot 0 (and time slot 16 if CAS framing is selected) in E1 mode. CAS

framing is selected by setting RFRAME[3] to 1 in the Primary Control register

[CR0; addr 001]. If FRAMED is disabled, the PRBS pattern receiver searches all

time slots for the test pat tern.

The RESEED bit in RPATT infor ms the receive PRBS sync circuit to begin a

PRBS pattern search. Once the search begins, any additional writes to RESEED

restarts the pattern sync search at a d if feren t point in th e pattern. The time to sy nc

depends on the pattern and number of bit errors in the pattern.

Pattern sync is reported (when found) in PSYNC status of the Pattern

Interrupt Status register [ISR0; addr 00B]. Next, the PRBS Pattern Error counter

[BERR; addr 058 and 059] counts bit errors detected on the incoming pattern,

provided that BSTART remains active. Error counting stops if th e BSTART bit is

cleared. The BERR counter is reset to zero after every read, or latched on every

ONESEC in terrupt as selected by LATCH_CNT [addr 046]. An in terrupt is

available to indicate the BERR counter overflowed in ISR4.

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-10 Conexant 100054E

2.2.7 Receive Framing

Two framers are in the receive data stream: an offline framer and an online frame

status monitor. The offline framer recovers receive frame alignment; the online

framer monitors frame alignment patterns and recovers multiframe alignment in

E1 modes. Table 2-1 lists suppor ted RCVR framing modes. Frame and

multiframe synchronizat ion criteria used b y the framers, as w ell as the monitoring

criteria of the online framer, are selected in RFRAME[3:0] of the Primary

Control register [CR0; addr 001]. Table 2-2 details framing loss/recovery c riteria.

Recei ve frame synchronizati on is initiat ed by the online framer’s acti vation of

the Receive Loss Of Frame (RLOF) status bit in the Alarm 1 Status register

[ALM1; add r 04 7]. The RLOF criteria is set in the RLOFA, RLOFB, RLOFC,

and RLOFD bits of the Receiver Configuration register [RCR01; addr 040]. The

online framer suppor t s the following LOF criteria for T1: 2 out of 4, 2 out of 5,

and 2 out of 6. For E1, the online framer supports 3 out of 3, with or without 915

out of 1000 CRC errors.

When RLOF is asserted, the offline framer automatically starts searching the

receive data stream for a new frame alignment, provided that receive framing is

enabled [RABORT; addr 040]. If receive framing is disabled, the offline framer

doe s not automatic ally se arch for t he frame alignment, but waits for a r eframe

command [RFORCE; addr 040] to star t a frame alignment search. If RLOF

integration is enabled [RLOF_INTEG; addr 045] the RLOF status [ALM1; addr

047] and RLOF interrupt status [ISR7; addr 004] is integrated for 2.0 to 2.5

seconds.

The online framer continuously monitors for loss of frame (RLOF) condition

[ALM1; addr 047] and searches for E1 multiframe alignment after basic frame

alignment is recovered by the offline framer. Receive multiframe alignment is

declared when multiframe alignment criteria are met. The receive online framer

reports multiframe errors, as well as frame errors and CRC errors in the Error

Interrupt Status [ISR5; addr 006].

The offline framer is shared between the RCVR and XMTR and can search

only in one direction at any time. Consequently, the processor arbitrates wh ich

direction is searched by enabling the reframe request (RLOF and TLOF) for that

direction.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-11

Tab le 2-1. R eceive Frame r Modes

T1/E1N RFRAME[3:0] Rec eiv e Fr am er Mode

0000XFAS Only

0 001X FAS Only + BSLIP

0010XFAS + CRC

0 011X FAS + CRC + BSLIP

0100XFAS + CAS

0 101X FAS + CAS + BSLIP

0 110X FAS + CRC + CAS

0 111X FAS + CRC + CAS + BSLIP

10000FT Only

1 0001 ESF + No CRC (FPS only)

10100SF

1 0101 SF + JYEL

1 0110 SF + T1 DM

1 1000 SLC + FSLOF

11001SLC

1 1100 ESF + Mimi c CRC

1 1101 ESF + Force CRC

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-12 Conexant 100054E

Tab le 2-2. Criteria for Loss/Recovery of Receive Fram er Alignment

Mode Description

FAS Basic Frame Al ignment (BFA) is recovered when the following search criteria are sat isfied:

• FAS pattern (0011011) is found in frame N.

• Frame N+1 co ntains bit 2 equal to 1.

• Frame N+2 al so contains FAS pa ttern (0011011).

During FAS-only modes, BFA is recovered when the following search criteria are sat isfied:

• FAS pattern (0011011) is found in frame N.

• No mimics of the FAS pattern are present in frame N+ 1.

• FAS pattern (0011011) is found in frame N+2.

NOTE(S): If FAS pattern is not found in frame N+2, or if FAS mimic is found in frame N+1, the search restarts in

frame N+2.

Loss of FAS frame alig nment (FRED) is declared when o ne of the following criteri a is met:

• Three consecutive F AS pattern errors are detected when the FAS pattern consists of a 7-bit (x0011011)

pattern in FAS frames and—if FS_NFAS is also active [addr 045]—the FAS pattern includes bit 2 of

NFAS frames.

• Loss of MFAS (MR ED) is due to 915 or more CRC errors out of 100 0.

• Failure to locate two valid MFAS patterns within 8 ms after BFA.

NOTE(S): In all cases, FRED causes next search for FAS alignment to begi n 1 bit after the current FAS location.

BSLIP FAS Bit Sli p Enable. A pplicable only for Dutc h PTT national applications. If BSLIP is enabled, the online fr amer

is allowed to change RX timebase by ±1 bit when a 1-bit F AS pa ttern slip is de tected. BSL IP doe s not affect the

offline framer's search criteria.

MFAS CRC4 Multiframe Alignment is recovered when the following search criteria are satisfied :

• BFA is recovered, identifying FAS and NFA S frames.

• Wit hin 8 ms after BFA, bit 1 of NFAS frames contains two MFAS patte rn s (001011xx). The second

MFAS must be aligned with respect to first MFAS, but the second MFAS pattern is not nec essarily

receive d in consecutive frames.

• Within 8 ms after BF A, bit 1 of NF A S frames contains the second MFAS pattern (001011xx), aligned to

first MFAS.

Loss of MFAS alignment (MRED) decl ared when one of the follow ing criteria is met:

• 915 or more CRC4 errors out of 1000 (submultifr ame) blocks.

• Loss of FAS (FRED).

NOTE(S): If Disable 915 CRC Reframe is set [RLOFD; a ddr 040], then MRED is activated only by FRED.

CAS CAS Multifram e Al ignment is recovered when the followi ng search criteria are satisfied:

• BFA is recovered, identifying TS0 through TS31.

• MAS ( 0000xxxx) multiframe alignment signa l pattern is found in the fi rst 4 bits of TS16, and 8 bits of

TS16 in preceding f rame contains nonzero value.

Loss of CAS alignment (SRED) is declared when one of the following crite ria is met:

• Two consecutive MA S pattern errors are det ected.

• TS16 contains all zeros in two multiframes (32 consecutive frames).

• Loss of FAS (FRED).

FT Only Terminal frame ali gnment is recovered when:

The first valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ms), where F-bits are separated by

193 bits.

During Ft-o nly mode, lo ss of frame alignment (FRED) is declared when:

Number of Ft bit errors detected meets selected los s of frame criteria [RLOFA–RLOFC ; ad dr 040].

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-13

SF Superframe alignment is recovered when:

• Terminal frame al ignment is recovered, ident ify ing Ft bits.

• Depends on SF submode:

If JYEL, onl y Ft bits are used, Fs bits are ignored.

If no JYEL, SF pattern (001110) f ound in Fs bits.

During any SF mode, loss of frame alignment (FRED) is declared when:

Number of frame errors detected—ei t her Ft or Fs bit errors—meets selected loss of frame criteri a

[RLOFA–RLOFC; addr 040]. FS _NFAS [addr 045] det ermines wheth er Fs bits are included in error count.

SLC Superframe alignment is recovered when:

Terminal frame alignment is recovered, identifying Ft bits.

SLC pattern (refer to Table A-3, SLC-96 Fs Bit Contents) is found in 16 of 36 Fs bits, according to Bellcore

TR-TSY-000008.

During SLC modes without FSLOF, lo ss of frame alignment (FRED) is declared when:

Number of Ft bi t erro rs detected meets selected refra me criteria [RLOFA–RLOFC; addr 040].

FSLOF FSLOF inst ructs the online framer to monitor 16 of 36 F s bits (SLC multiframe patte rn) for loss of fr ame

alignment criter ia. FS_NFAS [addr 045] must also be set to include Fs bits in loss of frame. FSLOF does not

affect the of fline fr amer's search criteria.

ESF Extended Superframe a lignment is recovere d w hen:

A valid FPS candidate is located (001011). Candidate bits are each separated by 772 digits and are received

without pattern errors.

If ther e is only one valid FPS can didate and the mode is one of the following :

No CRC mode—align to FPS, regardless of CRC6 comparison.

Mimic CRC mode—align to FPS, regardless of CRC6 comparison.

Force CRC mode—align to FPS, only if CRC6 is correct.

If there are two or more valid FPS candidates and the mode is one of the fo llowing:

No CRC mode—do not align (INVALID status).

Mimic CRC mode—align to first FPS with correct CRC6.

Force CRC mode—align to first FPS with correct CRC6.

During any ESF mode, loss of frame alignment (FRED) is declared when:

Number of FP S pattern errors det ected meets selected loss of fr ame criteria [R LOFA–RLOFC; addr 040].

T1DM During T1DM mode, frame alignment is recovered in two steps:

1. A 6-bit T1DM pa ttern (10111xx0) is fou nd.

2. A valid F-bit pa ttern (Ft, Fs, or FPS) is found in the first six consecutive frames of the 12-frame cycle

aligned to th e T1DM pattern.

During T1DM mode, loss of frame alignment (FRED) is declared when:

Number of frame errors detected, either Ft, Fs, or T1DM errors, meets selected lo ss of frame criteria

[RLOFA–RLOFC; addr 040]. FS_NFAS [addr 046] does not af fect T1DM mode.

NOTE(S): To be compatible with Bellcore TA-TSY-000278, the processor must select SF + T1 DM framer mode

and reframe criteria = 2 out of 6 F- bit errors [ RLOFA–RLOFC; addr 040].

Tab le 2-2. Criteria for Loss/Recovery of Receive Fram er Alignment

Mode Description

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-14 Conexant 100054E

The offline framer waits until the current search is complete (see [FSTAT;

addr 017]) before checking for pending LOF reframe requests. If both online

framers have pending reframe requests, the offline framer aligns to the direction

opposite from that which was most recently searched. For example, if TLOF is

pending at the conclusion of a receive search which timed out without finding

alignme nt, the offline framer switches to searc h in the tran sm it direction. The

TLOF switchover is prevented in the preceding example if the processor asserts

TABORT to mask the transmit reframe request. TABORT does not affect TLOF

status reporting. For applications that frame in only one direction, the opposite

direction sho uld be masked . If, at the concl usion of a recei v e search, TLOF status

is asserted but masked by TABORT, the offline framer continues to search in the

recei v e di recti on. For applic ation s that frame in both di recti ons, the processor c an

allow the offline framer to automatically arbitrate among pending reframe

requests, or may elect to manually control reframe precedence. An example of

manual c ontrol follows:

The status of the offline framer can be monitored for diagnostic purposes

using the Offline Framer Status register [FSTAT; addr 017]. The register reports

the following: whether the offli ne framer is looking at th e recei v e or transmit dat a

streams (RX/TXN); whether the framer is actively searching for a frame

alignment (ACTIVE); whether the framer found multiple framing candidates

(TIMEOUT); whether the framer found frame sync (FOUND); and whether the

framer found no frame alignment candidates (INVALID). Note that these status

bits are update d in real time and might be acti ve for onl y very short (1-b it) periods

of time. Table 2-1 lists the receive framer modes.

1 Initialize RABORT = 1 and TABORT = 1

2 Enable RLOF and TLOF interrupts

3 Read clear pending ISR interrupts

4 Release RABORT = 0

5 Cal l LOF Ser vice Routine if either RLOF or TL OF interrupt;

{(ch e ck cu rr e nt LOF sta tus [ALM1 , 2; ad dr 047, 048 ]

If RLOF recovered and TLOF lost

—Assert RABORT = 1

—Release TABORT = 0

If RLOF lost or TLOF recovered

—Assert T ABOR T = 1

—Release RAB O RT = 0

}

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-15

2.2.8 External Receive Data Link (CX28394 and CX28398 Only)

The External Data Link ( DL3) provides signal access to any b it(s) in a ny ti me slot

of all fr ames, odd frames, o r ev en frames, i ncludin g T1 framin g bits. Pin ac cess to

the DL3 recei v er is provided through RDLCKO and RDLO. These two pins serve

as the DL3 clock outpu t (RDLCK O) and data outpu t (RDLO). The data link mode

of the pins is selected using the RDL_IO bit in the Programmable Input/Output

Control of DL3 is provided in two registers: External Data Link Channel

[DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016]. RDL3 is

set up by selecting the bit(s) (DL3_BIT) and time slot [TS[4:0]; addr 015] to be

monitored, and then enablin g th e data link [DL3EN; add r 015], which starts the

RDLCKO and TDLCKO gapped clock outputs that mark the selected bits, as

shown in Figure 2-4.

NOTE: DL3 signals are not provided on the CX28395. Therefore, DL3_TS must

be written to 00 to disable the DL3 transmitter and prevent transmit data

corruption.

2.2.9 Sa-Byte Receive Buffers

The Sa-Byte buffers give read access to the odd frame Sa bits in E1 mode. Five

receive Sa-Byte buffers [RSA4 to RSA8; addr 05B to 05F] are available. As a

group, the buffers are updated every multiframe from Sa-bits received in TS0.

This gives the processor up to 2 ms after the receive multiframe interrupt [RMF;

addr 008] occurs to read any Sa-Byte buffer before the buffer content changes.

Figure 2-4. Receive External Data Link Waveforms

NOTE(S): This waveform represents ESF FDL extraction; any combi nat ion of bits can alternatively be selected.

24 F12 2324 1 2F

Frame 1

24 F 1 2 23 24 12

23 F23 24 1FF12 23 2

Frame 2 Frame 3 Frame 4 Frame 5

TS24 TS1

RCKi

RDLO

RDLCKO

RDLO

RDLCKO

(T1: ESF)

8394-8-5_074

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-16 Conexant 100054E

2.2.10 Receive Data Link

The RCVR contains two independent data link controllers (DL1 and DL2) and a

Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to

send and receive HDLC formatted messages in the Message-Oriented Protocol

(MOP) mode. Alternativ el y, unformatted serial data can be sent and receiv ed over

any combination of bits within a selected time slot or F-bit channel. The BOP

transceiver can preemptively receive and transmit BOP messages, such as ESF

Yellow Alarm.

2.2.10.1 Data Link

Controllers DL1 an d DL2 con trol two serial data channels operat ing at multi ples of 4 kbps up

to the full 64 kbps time slot rate by selecting a combination of bits from odd,

even, or all frames. Both DL1 and DL2 support ESF Facilities Data Link (FDL),

SLC-96 Data Link, Sa Data Link, Common Channel Signaling (CCS), Signaling

System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI)

Signaling in TS24, as well as the latest ETSI V.51 and V.52 signaling channels.

DL1 and DL2 each contain a 64-byte receive FIFO buffer.

Both data link controllers are configured identically, except for their offset in

the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address

range i s 0AF to 0B9. F r om thi s p oin t on, DL 1 i s used t o desc ri be th e operation of

both data link controllers.

DL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6]. DL1

will not function unt il it is enabled. DL1_CTL also controls the format of the

data. The following data formats [DL1[1:0]; addr 0A6] are supported on the data

link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and

non-FCS are HDLC formatted messages. Pack8 and Pack6 are unformatted

messages with 8 bits per FIFO access, or 6 bi ts per FIFO access, respective l y (see

Table 2-3).

The time slot and bit selection are performed through the DL1 Time Slot

Enabl e re gi ster [DL1_TS; add r 0A4] and t he DL1 Bit Enab l e re g ister [DL1_BIT;

addr 0A5]. The DL1 Time Slot Enable regi ster sele cts the frames and time slot to

extract the data link. The frame select tells the receiver to extract the time slot in

all frames, odd frames, or even frames. The time slot enable is a value between 0

and 31 that selects which time slot t o extract. The DL1 Bit E nable reg ister sel ects

which bits will be extracted in the selected tim e slot. Refer to Table 2-3 for the

common frame, time slot, time slot bits, and modes used.

Table 2-3. Commonly Used Data Link Settings

Data Link Frame Time Slot Time Slot Bits Mode

ESF FDL Odd 0 (F-bits) Don’t Care FCS

T1DM R Bit All 24 00000010 FCS

SLC-9 6 Even 0 (F-bits) Don’t Care Pac k6

ISD N LAPD All N 11111111 F CS

Sa4 Odd 1 00001000 FCS

NOTE(S): N represen ts any T1/E1 time slot.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-17

The Receive Data Link FIFO #1 [RDL1; addr 0A8] is 64 bytes. The Receive

FIFO buffer is formatted differently than the transmit FIFO buffer. The Receive

buffer contains not only received messages, but also a status by te preceding each

message that specifies the size of the received message and the status of that

message. The message status reports if the message was aborted, received with a

correct or incorrect FCS, or continued. A continued message means the byte

count represents a partial message. When all message bytes are read, the buffer

contains another status byte. Message bytes can be differentiated from status

bytes i n th e buffer by readin g the RSTAT1 bit in th e RDL #1 Statu s regis te r

[RDL1_STAT; addr 0A9]. RSTAT1 reports whether the next by te read from the

buffer will be a status byte or some number of message bytes.

The receive data link controller has a versatile microprocessor interface that

can be tu ned to the system’s CPU ban dwidth. For system s with one dedicated

CPU, the data link status can be polled. For systems where a single CPU controls

multiple devices, the data link can be interrupt-driven. See Figures 2-5 and 2-6

for a high-level description of polling and interrupt driven Receive Data Link

Controller software.

Using the Receive FIFO buffer, an entire block of data can be received with

very little microprocesso r interrupt o verhead. Block tran sfers from the buffer can

be controlled by the Near Full Threshold in the FIFO Fill Control register

[RDL1_FFC; addr 0A7]. The Near Full Threshold is a user programmable value

between 0 and 63. This value represents the maximum number of bytes that can

be placed in the Receive buffer without the near full being declared. Once the

threshold is set, the Near Full S tatus (RNEAR1) in RDL #1 Status [RDL1_S TAT;

addr 0A9] is asserted when the Near Full Threshold is reached. An interrupt,

RNEAR, in Data Link 1 Interrupt Status [ISR2; addr 009], is also available to

mark thi s event.

The de v ice uses a hierarchical in terrupt structure, with one top-lev el int errupt

request register directing software to the lower levels (see Master Interrupt

Request register; addr 081 and Interr upt Request register; addr 003). Of all the

interrupt sources, the two most significant bandwidth requirements are signaling

and data link interrupts. Each data link controller has a top-level interrupt status

registers [ISR2, ISR1; addr 009 and 00A). The processor uses a three-step

interrupt scheme for the data link:

1. Read the Master Interrupt Request register to determine which framer

interrupted.

2. Read the Interrupt Request register for that framer.

3. Use that register value to read the corr esponding Data Link Interrupt

Status register.

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-18 Conexant 100054E

Figure 2-5. Polled Receive Data Link Processing

NOTE(S): Message status contains num ber of message bytes (X) in FIFO.

Receive Message

Read Data Link Status

FIFO EMPTY

Message Status

on FIFO

Read Message Status from FIFO

Yes

Read X Message Bytes from FIFO

Message Status

is Continue

Yes

Message Status

is Good

Yes

Error Receiving Message

Return

Read Message Byte from FIFO

Wait N Milliseconds

Yes

Wait N Milliseconds

Return

and Discard

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.2 R eceiver

100054E Conexant 2-19

Figure 2-6. Interrupt-Driven Receive Data Link Processing

NOTE(S): Message status contains num ber of message bytes (X) in FIFO.

Interrupt Occurred

Read Interrupt Status

Read Message Status from FIFO

Read X Message Bytes from FIFO

Message Status

is Good or

Yes

Error Receiving Message

Return

Process Other Interrupt

Yes

Return

Read Data Link Status

Message Status

on FIFO

Yes

Read Message Byte from FIFO

Return

Continue

Interrupt Service Routine

Complete MSG

or Near Full

Interrupt

and Discard

2.0 Circuit Descrip tion CX28394/28395/28398

2.2 Rece iv er Quad/x16/Octal—T1/E1/J1 Framers

2-20 Conexant 100054E

2.2.10.2 RBOP Receiver The Receive Bit-Oriented Protocol (RBOP) receiver receives BOP messages,

including the ESF Yellow Alarm, which consists of repeated 16-bit patterns with

an embedded 6-bit codeword as shown in this example:

0xxxxxx0 11111111 (received right to left)

[543210] RBOP = 6-bit codeword

The BOP message channel is configured to operate over the same channel

selected by Data Link #1 [DL1_TS; addr 0A4]. It must be configured to operate

over the FDL channel so RBOP can detect priority, command, and response

codewo rd messages according to ANSI T1.403, Section 9.4.1.

RBOP i s enabled using the RBOP_START bit in Bit Oriented Protocol

Transceiver register [BOP; address 0A0]. BOP codewords are received in the

Receive BOP Codeword register [RBOP; addr 0A2], which contains the 6-bit

code w ord, a v alid flag (RBOP_VALID), and a lost flag (RBOP_LOST). The val id

flag is set each time a new code word is put in RBOP, and is cleared on reading the

codewo rd. The lost flag indicates a new codeword overwrote a valid codeword

before being read by the processor.

The BOP receiver can be configured to update RBOP using a message length

filter and integration filter. The receive BOP message length filter [RBOP_LEN;

addr 0A40] sets the number of successive identical messages required before

RBOP is updated. RBOP_LEN can be set to 1, 10, or 25 messages. When

enabled, the RBOP integration filter [RBOP_INTEG; add 0A0] requires receipt

of two identical consecutive 16-bit patterns, without gaps or errors between

patterns, to validate the first codeword. RBOP integration is needed to meet the

codeword detection criteria while receiving 1/1000 bit error ratio.

The real-time status of the codeword reception can be monitored using the

RBOP_ACTIVE bit in the BOP Status register [BOP_STAT; addr 0A3]. Each

time a message is put in RBOP register, an interrupt is generated, and the RBOP

bit is set in the Data Link 2 Interrupt Statu s regi ster [ISR1; addr 00A].

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-21

2.3 System Bus

Each framer provides high-speed, transmit and receive serial TDM interfaces.

These interfaces can be configured as non-multiplexed, individual system buses,

or they can be multiplexed internally or externally to provide 2xE1 (4096 Mbps)

and 4xE1 (8192 Mbps) buses. The system bus is compatible with the Mitel

ST-Bus, the Siemens PEB Bus, and the AT&T CHI Bus and directly connects to

other Conexant serial TDM bus devices without the need for any external

circuitry. The following five bus rates are supported:

• 1.536 MHz—T1 rate, 24 time slots, without framing bit

• 1.544 MHz—T1 rate with framing bit

• 2.048 MHz—E1 rate, 32 time slots

• 4.096 MHz—twice the E1 rate, 64 time slots

• 8.192 MHz—four times the E1 rate, 128 time slots

2.3.1 Non-Multiplexed Mode

In Non-Multiplexed mode, each framer has a separate system bus interface

consisting of the following pin functions:

The signal available on dual function pins is controlled using register PIO

[addr 018].

To use Non-Multiplexed mode, SBIMODE[0] and/or SBIMODE[1] in the

Framer Control register [FCR; addr 080] must be zero to disable Internally

Multiplexed mode. The system bus rate is indep endent of the line rate and must

be selected using SBI[3:0] in the System Bus Interface Configuration register

[SBI_CR; addr 0D0]. Register bit SBI_OE [SBI_CR; addr 0D0] must also be set

to 1 to enable system bus outputs.

Receive System Bus (RSB) Transmit S y stem Bus (TSB)

RSBCKI TSBCKI

RPCMO TPCMI

RFSYNC/RMSYNC TFSYNC/TMSYNC

RINDO/RDLCKO TINDO/TDLCKO

RSIGO/RDLO TSIGI/TDLI

SIGFRZ —

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-22 Conexant 100054E

2.3.2 Externally Multiplexed Mode

Externally Multiplexed mode allows any two, three, or four framers (in the same

or different devices) to share a common high speed system bus (see Figure 2-7).

The 4.096 and 8.192 MHz bus modes contain multiple bus members (bus g roups

A, B, C, D) which allow multiple T1/E1 si gnals to share the same system bus .

This is done by interleaving the time slots from up to four framers (see

Figures 2-10 and 2-11).

To use Externally Multiplexed mode, SBIMODE[0] and/or SBIMODE [1 ] in

the Framer Control register [FCR; addr 080] must be zero to disable Internally

Multiplexed mode. The system bus rate is indep endent of the line rate and must

be selected using SBI[3:0] in the System Bus Interface Configuration register

[SBI_CR; addr 0D0]. SBI[3:0] is also used to assign each framer to a different

bus group. Register bits SBI_OE [SBI_CR; addr 0D0], BUS_RSB [RSB_CR;

addr 0D1], and B US_ TS B [TS B_CR; addr 0D4] must be set to 1 t o allow system

bus outputs to share common connections.

Figure 2-7. Externally Multiplexed Configuration Examples

Possible Externally Multiplexed

Configurations

4.096 Mbps

8.192 Mbps

CX28398

Framer 1

Framer 2

Framer 3

Framer 4

Framer 5

Framer 6

Framer 7

Framer 8

4.096 Mbps

8.192 Mbps

CX28398

Framer 1

Framer 2

8394-8-5_003

Framer 3

Framer 4

Framer 5

Framer 6

Framer 7

Framer 8

2.048 Mbps

1.544 Mbps

Any 2, 3, or 4 framers from a

device (or from different

devices) can be externally

multiplexed with no additional

circuitry.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-23

2.3.3 Internally Multiplexed Mode

Internally Multiplexed mode operation is very sim ilar to Exte rnal ly Multiplexed

mode. The framers in each device are internally grouped into four-framer groups

to allow an internally multiplexed mode (see Figure 2-8). In the CX28398,

framers 1 through 4 form a group (l o w er group or group A) and framers 5 through

8 form another (up per group or group B). The CX28 395 supports fou r groups: A,

B , C, and D. The CX28394’s four framer s are also grouped in th e same manner. In

this mode, system bus signals from all four framers are internally connected and

the interface pin functions are redefined. The advantage of this mode is that all

system bus signals which are normally available on dual function pins, are now

available on separate pins. In Internally Multiplexed mode, the following signals

are available for each four-framer group (lower group shown):

To use Internally Multiplexed mode, SBIMODE[0] and/or SBIMODE[1] in

the F ramer Control re gister [FCR; ad dr 080] must b e set to 1. The system bus rate

is independent of the line rate and must be selected using SBI[3:0] in the System

Bus Interface Configuration register [SBI_CR; addr 0D0]. SBI[3:0] is also used

to assign each framer to a different bus group. Register bits SBI_OE [SBI_CR;

addr 0D0], BUS_RSB [RSB_CR; addr 0D1], and BUS_TSB [TSB_CR; addr

0D4] must be set to 1 to allow system bus outputs to share common connections.

Because RFSYNC (and TFSYNC) signals are bused, all four framers’ RFSYNC

(and TFSYNC) signals must be configured as inputs and driven externally or,

alternatively, three framers’ sync signals can be configured as inputs and one as

an output [PIO; addr 018].

Receive System Bus (RSB) Transmit System Bus (TSB)

RSBCKI[A] TSBCKI[A] Common, internally

connected to all four

framers.

RPCMO[A] TPCMI[A]

RFSYNC[A] TFSYNC[A]

RINDO[A] TINDO[A]

RSIGO[1:4] TSIGI[1:4]

Separate sign al s.

RMSYNC[1:4] TMSYNC[1:4]

RDLCKO[1:4](1) TDLCKO[1:4](1)

RDLO[1:4](1) TDLI[1:4](1)

SIGFRZ[1:4] —

NOTE(S):

(1) These signals are not provide d on the CX28395.

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-24 Conexant 100054E

2.3.4 Receive System Bus

The Receive System Bus (RSB) provides a high-speed, serial interface between

the RCVR and the system bus. The RSB has the following pins:

Figure 2-8. Internally Multiplexed Configuration Examples

Framer 1

Framer 2

Framer 3

Framer 4

Framer 5

Framer 6

Framer 7

Framer 8

CX28398

Possible Internally Multiplexed

Configurations

8.192 Mbps

Two separte 8.192

Mbps buses is the

typical application for

Internally Multiplexed

mode.

Framer 1

Framer 2

Framer 3

Framer 4

Framer 5

Framer 6

Framer 7

Framer 8

CX28398

4.096 Mbps

In this application, Framers 3 and 4

are used as back-up line interfaces

and are connected to the system bus;

but are disabled.

8.192 Mbps

In this application, Framer 8 is used as

a back-up line interface and is

connected to the system bus; but is

disabled.

8394-8-5_004

Pin Name Function

RSBCKI Receive System Bus Cloc k

RPCMO Receive PCM Data

RFSYNC/RMSYNC Receive Frame Sync or

Receive Multiframe Sync

RINDO/RDLCKO Receive Time Slot Indicator or

Receive Datalink Clock

RSIGO/RD LO Rece iv e Signa li ng Da ta or

Receive Datalink Data

SIGFRZ Signaling Freeze

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-25

Figure 2-9 illu strates the rela tionship betw een these signals. Signal definitions

are provid ed in Table 1-6, Hardw a re Signal Definiti ons. R SB dat a out put s can be

configured to output on the rising or falling edge of RSBCKI (see the Receive

System Bus Configuration register [RSB_CR; addr 0D1]).

The RSB supports five different system bus rates (MHz):

• 1.536 MHz—T1 rate, 24 time slots, without framing bit

• 1.544 MHz—T1 rate with framing bit

• 2.048 MHz—E1 rate, 32 time slots

• 4.096 MHz—twice the E1 rate, 64 time slots

• 8.192 MHz—four times the E1 rate, 128 time slots

Figure 2-9. RSB Waveforms

NOTE(S): The R eceive Multiframe Sync (RMSYNC) occurs every 6 ms, 48 T1 or 48 E1 frames.

RSBCKI

123456781234567812

ABCDABCDABCDABCDAB

12345678F123456781

ABCDABCDXABCDABCDA

RPCMO

RINDO

RSIGO

RPCMO

RINDO

RSIGO

SIGFRZ

RFSYNC

RMSYNC

Frame48TS31 Frame1TS0

Frame48TS24 Frame1TS1

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-26 Conexant 100054E

The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B,

C, D) which allow multiple T1 /E1 signals to share the same syste m bus. This is

done by interleaving the time slots from up to four framers, without external

circuitry (see Figures 2-10 and 2-11). The system bus rate is independent of the

line rate and must be selected using the System Bus Interface Configuration

Figure 2-10. RSB 4096K Bus Mode Time Slot Interleaving

NOTE(S): A and B time s lot comes from different f ramers. Output dat a on rising edge clock, RCPM_ NEG = 0 [add r 0D1].

Output sync on rising edge clock, RSY N_ NEG = 0 [addr 0D1]. RSBCKI operat es at 1 times the data rate.

RSBCKI

TS31A TS31B TS0A TS0B

RPCMO

RFSYNC

SIG31A SIG31B SIG0A SIG0B

RSIGO

Figure 2-11. RSB 8192K Bus Mode Time Slot Interleaving

NOTE(S): A, B , C, and D data comes fro m different framers. Outpu t data on rising edge clock, RCP M_NEG = 0 [addr 0D1].

Output sync on rising ed ge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI oper ates at 1 times the data rate. RSB.O FFSET equal s

zero.

SIG31A SIG31B SIG31C SIG31D SIG0A SIG0B SIG0C SIG0D

RSBCKI

RSIGO

RFSYNC

TS31A TS31B TS31C TS31D TS0A TS0B TS0C TS0D

RPCMO

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-27

The RSB maps line rate tim e slots to system bus time s lots. The 24 (DS1 ) or

32 (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus

time slots as listed in Table 2-4. The system bus rate must be greater than or equ al

to the line rate, except for 1536K bus mode.

The RSB, Figure 2-12, consists of a timebase, slip buffer, a signaling buffer,

and a signaling stack.

Tab le 2-4. R SB Interface Time Slot Mappin g

Line Rate (MHz) Source

Channels System Bus Rate

(MHz) Destination Time

Slots

1.544 24 1.536 24

24 1.544 24

24 2.048 32

24 4.096 64

24 8.192 128

2.048 32 2.048 32

32 4.096 64

32 8.192 128

Figure 2-12. RSB Diagram

RSIGO

RPCMO

SIGFRZ

RINDO

RFSYNC

RMSYNC

RSBCKI

TSBCKI

RSIG

STACK

RSLIP

Buffer

RSIG

Local

RSIG

Buffer

RPHASE

I/O From Pins

RSB

Timebase

Remote

Channel

Loopback

Local

Channel

Loopback

From

Receive

RNRZ AIS

Timebase

}

RSBCK

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-28 Conexant 100054E

2.3.4.1 Timebase The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the

Receive System Bus Clock (RSBCKI). The RSBCK can be slaved to two

dif f erent c lo ck so urces: Receive System Bus Clock Inp ut (RSBCKI), or Transmit

System B us Clock In put (TSBCKI). The RSB clo ck selection is made thro ugh the

Clock Input Mux register [CMUX; addr 01A]. The system bus clock can also be

configured to run a t twice the data rate by setting the X2CLK bit in the System

Bus Interface Configuration register [SBI_CR; addr 0D0].

In Non-Multiplexed mode, the RFSYNC/RMSYNC dual function pin is

configured for either RFSYNC or RMSYNC usi ng the RMSYNC_EN regi ster bit

[PIO; addr 018]. RFSYNC and RMSYNC can be con figured as inputs or out pu ts

[PIO; addr 018]. RFSYNC and RMSYNC should be configured as inputs when

the RSB timebase i s slaved to the system bus [SBI_OE; addr 0D 0]. RFSYNC an d

RMSYNC should be configured as outputs when the RSB timebase is master of

the system bus. RFSYNC and RMSYNC can be also configured as rising or

falling edge outputs [RSB_CR; addr 0D1]. In addition to having RFSYNC and

RMSYNC active on the frame boundary, a programmable offset is available to

select the time slot and bit offset in the frame. See the Receive System Bus Sync

Time Slot Offset [RSYNC_TS; addr 0D3] and the Receive System Bus Sync Bit

Offset [RSYNC_BIT; addr 0D2].

2.3.4.2 Slip Buffer The 64-byte Receive PCM Slip Buffer [RSLIP; addr 1C0 to 1FF] resynchronizes

the Receiver Clock (RCKI) and data (RNRZ), to the Receive System Bus Clock

(RSBCK) and data (RPCMO). RSLIP acts lik e an elastic store by clo cking RNRZ

data in with RCKI and clocking PCM data out on RPCMO with RSBCK.

If the system bus rate is g reater than the line rate (i.e., T1 line rate and E1

system bu s ra te), there will be a mismatched num ber of time slots. Th e m apping

of line rate time slots to system bus time slots is done by time slot assignments

with the ASSIGN bit in the System Bus Per-Channel Control register [SBC0 to

SBC31; addr 0E0 to 0FF]. ASSIGN selects which system bus time slots are used

to transport line rate time slots. Time slot mapping is done by mapping the first

line rate time slot to the first assigned system bus time slot. F or example, T1 to E1

mapping might make every fourth time slot unassigned (i.e., 3, 7, 11, 15, 19, 23,

27, 31); see Figure 2-13. This distribution of unassigned time slots averages out

the idle tim e slots and optimizes the use of th e slip buffer.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-29

RSLIP has four modes of operation: Two Frame Normal, 64-bit Elastic,

Two-Frame Short, and Bypass. RSLIP mode is set in the Receive System Bus

Configuration register [RSB_CR; addr 0D1]. RSLIP is organized as a two-frame

buffer. This allows MPU access to frame data, regardless of the RSLIP mode

selected. Each byte offset into the frame buffer is a different time slot: offset 0 in

RSLIP is always time slot 0 (TS0), offset 1 is always TS1, and so on. The slip

buffer has processor read/write access.

Two- Frame Nor mal In Normal mode, the slip buffer total depth is two 193-bit frames (T1) or two

256-bit frames (E1). Data is written to the slip buffer using RXCLK, and read

from the slip buffer using RSBCK. If a slight rate difference between the clocks

occurs, the slip buffer changes from its initial condition—approximately half

full—by either adding or re moving frames. If RXCLK write s to the slip buffer

faster than RSBCK reads the data, the buffer will fill up. When the slip buffer in

Normal mode is full, an entire frame of data is deleted. Conversely, if RSBCK

reads the slip buffer faster than RXCLK writes the data, the buffer will become

empty. When the slip buffer in Normal mode is empty, an entire frame of data is

duplicated. When an entire frame is deleted or duplicated it is known as a Frame

Slip (FS LIP), w hich is al w a ys one f ull frame of data. The FSLIP stat us is reported

in the Slip Buffer Status register [SSTAT; addr 0D9]. In T1 mo de, the F-bit is

treated as par t of the frame and can slip accordingly.

Figure 2-13 . T1 Line to E1 System Bus Time Slot Mapping

NOTE(S):

(1) u = unassigned time slots

(2) FA = T1 frame bit, frame A

(3) FB = T1 fram e bi t, fr am e B

FA2 3 4 5 24 FB1 2 41233

0 2 3 4 516 28 30 31 0 129 2

RNRZ

RPCMO

Frame A Frame B

u27

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-30 Conexant 100054E

64-Bit Elastic In 64-bit Elastic mode, the slip buffer total depth is 64 bits, and the initial

throughput delay is 32 bits, one-half of the total depth. Similar to Normal mode,

Elastic mode allows the system bus to operate at any of the programmable rates,

independe nt of t he li ne rate. T he adv a ntage of thi s mode over t he Normal mode is

that throughput delay is reduced from one frame to an average of 32 bits, and the

output multiframe always retains its alignment with respect to the ou tput data.

The disadv antage of th is mode is handling t he full and empty buf fer conditions. In

Elastic mode, an empty or full buffer condition causes an Uncontrolled Slip

(USLIP). Unlike an FSLIP, a USLIP is of unknown size within the range of 1 to

256 bits of data. The USLIP status is reported in SSTAT.

Two- Frame Short The Two- Frame Short mode c ombi nes t he dep th of t he Normal mode wit h th e

throughput delay of the Elastic mode. The Two-Frame Short mode begins in the

Elastic mode with a 32-bit initial throughput delay, and switches to the Normal

mode wh en the buf fer becomes empty or full; th ereafter the Tw o-Frame Sh ort and

normal mode perform identically. If the slip buffer is full (two frames) in the

Two-Frame Short mode, an FSLIP is reported, after which the slip buffer and

Two-Frame mode perform identically.

Bypass In Bypass mode, d ata is immediat ely clocked through RSLIP from t he R CVR

to RSB, and RCKI internally replaces the system bus clock.

2.3.4.3 Signaling Buffer The 32-byte Receive Signaling Buffer [RSIG; addr 1A0 to 1BF] stores a single

multiframe of signaling data. Each byte offset into RSIG contains signaling data

for a different time slot: offset 0 stores TS0 signaling data, offset 1 stores TS1

signaling data an d so on. The signali ng data is stored in th e least si gnificant 4 bit s

of RSIG. The output signaling data is stored in the most significant 4 bits of

RSIG. Similar to RSLIP, the RSIG buffer has read/write processor access to read

or overwrite signaling information. RMSYNC extracts robbed-bit signaling from

RSIG onto RPCMO; RFSYNC extracts ABCD signaling from RSIG onto

RSIGO.

The RSIG buffer has the following confi gurable features: transparent,

robbed-bit signaling; signaling freeze; debounce signaling; and unicode

detection. Each feature is available in the Receive Signaling Configuration

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-31

2.3.4.4 Signaling Stack The Receive Signaling Stack (RSTACK) allows the processor to quickly extract

signaling changes without polling every channel. RSTACK is activated on a

per -channel basis by set ting the Receiv ed Si gnal ing St ack (SIG_STK) control bit

in the Receive Per-Channel Control register [RPC0 to RPC31; addr 180 to 19F].

The signaling stack stores the channel and the A, B, C , and D signaling bits that

changed in the last multiframe. The stack has the capacity to store signaling

changes for all 24 (T1) or 30 (E1) PCM channels.

At the end of any mul tiframe where one or more ABCD sign aling values have

changed, an interr upt occurs with RSIG set in the Timer Interrupt Status register

[ISR3; addr 008]. The processo r then reads the Recei ve Si gnaling Stack [STACK;

addr 0DA] twi ce to retrieve the chan nel number (WORD = 0) and the ne w ABCD

value (WORD = 1), and continues to read from STACK until the MORE bit in

STACK is cleared, indicating the RSIG stack is empty.

Optionally, the processo r can select RSIG interrupt (SET_RSI G; addr 0D7) t o

occur at each multiframe boundary in T1 modes, regardless of signaling change.

This mode provides an interrup t a ligned to the m ultiframe to read the RSIG

buffer, rather than to read RSTACK.

2.3.4.5 Embedded

Framing Embedded framing mode bit (EMBED; addr 0D0) instructs the RSB to embed

framing bits in RPCMO while in T1 mode.

The Embedded mode supports ITU-T Recommendation G.802, which

describes how 24 T1 time slots and one framing bit (193 bits) are mapped to 32

E1 time slots (256 bits). This mapping is done by leaving TS0 and TS16

unassigned; by storing the 24 T1 time slots in TS1 to TS15, and TS17 to TS25;

and by storing the frame bit in bit 1 of TS26 (see Figure 2-14). TS26 through

TS31 are also unassigned.

Figure 2-14. G.802 Embedded Framing

NOTE(S):

(1) X = unuse d bit s

(2) u = unassi gned time slot (see ASSIGN bi t [addr 0E0 to 0FF])

(3) FA = T1 frame bit, frame A

(4) FB = T1 fram e bi t, fr am e B

(5) FC = T1 fram e bi t, fr am e C

FA214 24 FB1 2 23 24 1 2123F

0 2 14115 24 26 27 3125 0

RNRZ

Frame A

uu uuu

15 16 17

16 17 18 1 2

Frame B

E1 Framing E1 Multiframe/Signalling

Time Slot

X X X X X XX

Time Slot

RPCMO

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-32 Conexant 100054E

2.3.5 Transmit System Bus

The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling

buffer, and transmit framer (Figure 2-15). It provides a high-spe ed serial inte rface

between the XMTR and the system bus.

The TSB contain s the fo llowing five pins:

Figur e 2-15. TSB Interface Bl ock Dia gram

8394-8-5_035

TINDO

TFSYNC

TMSYNC

RSBCKI

TSBCKI

TSIG

Local

TSIG

Local

TSLIP

Buffer

TPHASE

Transmit

Framer

TSB

Timebase

TPCMI

TSIGI

Remote

Channel

Loopback

Local

Channel

Loopback

TNRZ

From

Transmit

TXDATA

Timebase

Pin Name Function

TSBCKI Transmit S y stem Bus Clock

TPCMI Trans m it PCM Data

TFSYNC/TMSYNC Transmit Frame Sync or

Tran sm it Multiframe Sync

TINDO/TDLCKO Transmit Time Slot Indicator or

Transmit Datalink Clock

TSIGI/TDLI Transmit Signaling Data or

Transmit Datalink Data

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-33

Refer to Figure 2-16 for the relationship between these signals. Signal

definitions are provided in Table 1-6, Hardware Signal Definitions. TSB data

outputs can be configured to input data on the rising or falling edge of TSBCKI

(see the Transmit System Bus Configuration register [TSB_CR; addr 0D4].

The TSB supports five different system bus rates (MHz):

• 1.536 MHz—T1 rate, 24 time slots, without framing bits

• 1.544 MHz—T1 rate with framing bits

• 2.048 MHz—E1 rate, 32 time slots

• 4.096 MHz—twice the E1 rate, 64 time slots

• 8.192 MHz—four times the E1 rate, 128 time slots.

Figure 2-16. Transmit System Bus Waveforms

TSBCKI

123456781234567812

XXXXABCDXXXXABCDXX

12345678F123456781

XXXXABCDXXXXXABCDX

TPCMO

TINDO

TSIGI

TPCMI

TINDO

TSIGI

TFSYNC

TMSYNC

Frame48TS31 Frame1TS0

Frame48TS24 Frame0TS1

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-34 Conexant 100054E

The 4.096 an d 8.192 MHz bus mo des contain mu lti ple bus members (A, B, C,

and D) of which one bus member is selected by the SBI [3:0] bits in the System

Bus Interface Configuration register [SBI_CR; 0D0] (see Figures 2-17 and 2-18).

The system bus r at e i s in dependent of th e l in e rat e and must be selected using the

System Bus Interface Configuration register.

Figure 2-17. TSB 4096K Bus Mode Time Slot Interleaving

NOTE(S): A and B ti me slot data comes from different framers. TSBCKI can be operat ed at 1 or 2 times t he data rate.

TSBCKI

TS31A TS31B TS0A TS0B

TPCMI

TFSYNC

SIG31A SIG31B SIG0A SIG0B

TSIGI

Figure 2-18. TSB 8192K Bus Mode Time Slot Interleaving

NOTE(S): A, B, C, and D time slot d ata comes from d if ferent framers. TSBCKI can be o perat ed at 1 or 2 times t he data rate.

SIG31A SIG31B SIG31C SIG31D SIG0A SIG0B SIG0C SIG0D

TSBCKI

TSIGI

TFSYNC

TS31A TS31B TS31C TS31D TS0A TS0B TS0C TS0D

TPCMI

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-35

2.3.5.1 Timebase The TSB timebase sync hronizes TPCMI, TFSYNC, TMSYNC, and T INDO with

the Transmit System Bus Clock (TSBCK). The TSBCK can be slaved to three

different clock sources: Transmit Clock Input (TCKI), Transmit System Bus

Clock Input (TSBCKI), and Receive System Bus Clock Input (RSBCKI). The

TSB clock selection is ma de t hrou gh t he C l ock In put Mu x register [ C MUX; a ddr

01A]. TCKI is autom a tically selected when the tra nsmit slip buffer is bypassed.

The system bus clock can also be configured to run at twice the data rate by

setting the X2CLK bit in the System Bus Interface Configuration register

[SBI_CR; addr 0D0] when TSLIP is not in Bypass mode.

In Non-Multiplexed mode, the TFSYNC/TMSYNC dual function pin is

configu red for either TFSYNC or TMSYNC using t he TMSYNC_EN reg ister bit

[PIO; addr 018]. TFSYNC and TMSYNC can be individually configured as

inputs or outputs, [PIO; addr 018]. TFSYNC and TMSYNC should b e configured

as inputs when the TSB timebase is slaved to the system bus, the transmit framer

is disabled [TABORT; addr 071], or TSB carries embedded T1 framing.

TFSYNC and TMS YNC should be c onfigur ed as outputs w hen the T SB timebase

is master of the system bus, or the transmit framer is enabled. TFSYNC and

TMSYNC can be also configured as rising or falling edge outputs [TSB_CR;

addr 0D4]. In addition to having TFSYNC and TMSYNC active on the frame

boundary, a prog rammable offset is available to select the time slot and bit offset

in the frame (see Transmit System Bus Sync Time Slot Of fset [TSYNC_TS; ad dr

0D6] and Transmit System Bus Sync Bit Offset [TSYNC_BIT; addr 0D5]).

2.3.5.2 Slip Buffer The 64-byte T ra nsmit PCM S li p Buffer [TSLIP; addr 140 to 17F] resync hroni zes

the Transm it System Bus Clock (TSBCK) and data (TPCMI) to the Transmit

Clock (TXCLK) and data (TNRZ). TSLIP acts like an elastic store by clocking

PCM data in on T PCMI wi th TS BCK and cl ocking TNRZ dat a out with T XCLK.

TPCMI ca n be con figure d to sa mple on the r ising or fall ing ed ge of TSBCKI (see

the Transmit System Bus Configuration register [TSB_CR; addr 0D4]).

TSLIP has four modes of operation: Two Frame Normal, 64-bit Elastic, Two

Frame Short, and Bypass. TSLIP mode is set in the Transmit System Bus

Configuration register [TSB_CR; addr 0D4]. It is organized as a two-frame

buffer, with high frame and low frame buffers. This allows MPU access to frame

data, regardless of the TSLIP mode selected. Each byte offset into the frame

buf fer is a different t i me sl ot, offset 0 in TSLIP i s always ti me slot 0 ( TS0) ; offset

1 is always TS1, and so on. The slip buffer has processor read/write access.

Two- Frame Nor mal In Normal mode, the slip buffer total depth is two 193-bit frames (T1), or two

256-bi t frames (E 1). Data is written t o the sl ip buf fer u sing TSB CK and read from

the slip buffer using TXCLK. If there is a slight rate difference between the two

clocks, the slip buffer changes from its initial condition—approximately half

full—by either ad ding or removing frames. If TSBCK writes to the slip buffer

faster than TXCLK reads the data, the buffer becomes full. When the slip buffer

in Normal mode is full, an entire frame of data is deleted. Conversely, if TXCLK

is reading the slip buffer at a faster rate than TSBCK is writing the data, the buffer

will eventually empty, and an entire frame of data is duplicated. When an entire

frame is deleted or duplicated, it is known as a Frame Slip (FSLIP). An FSLIP is

always one full frame of data. The FSLIP status is reported in the Slip Buffer

Status register [SSTAT; addr 0D9].

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-36 Conexant 100054E

64-Bit Elastic In 64-bit Elastic mode, the slip buffer total depth is 64 bits and the initial

throughput delay is 32 bits, or one-half of the total depth. Similar to Normal

mode, Elastic mode allow s the system bus to operate at any of the programmable

bus rate s, independent of the line rate. The advantage of th is mode over the

tw o-frame mod e is that t hroughput del a y is reduced from on e frame to an average

of 32 bits, and the transmit multiframe can retain its alignment with respect to the

transmit data. The di sadva ntage of t his mode is handling the full an d empty buf fer

conditions. In 64-bit Elastic mode, an empty or full buffer condition causes an

Uncontrolled Slip (USLIP). Unlike an FSLIP, a USLIP is of unknown size,

ranging from 1 to 256 bits of data. The USLIP status is reported in SSTAT.

Two- Frame Short The Two- Frame Short mode c ombi nes t he dep th of t he Normal mode wit h th e

throughput delay of the Elastic mode. This mode begins in Elastic mode with a

32-bit initial throughput delay, and switches to Normal modes when the buffer is

empty or full; thereafter, the Two-Frame Short and Normal modes perform

identically. If the slip buffer is full (two frames) in the Two-Frame Short and

normal modes, an FSLIP is repor ted; thereafter, the slip buffer performs exactly

like Normal mode.

Bypass In Bypass mode, data is clocked through TSLIP from the TSB to the XMTR

using TXCLK as selected by the TXCLK input clock mux.

2.3.5.3 Signaling Buffer The 32-byte Transmit Signaling Buffer [TSIG; addr 120–13F] stores a single

multiframe of signaling data input from TSIGI pin and is updated as each time

slot is recei v ed in e v ery TSB frame. Each b yte of fset into TSIG is a dif ferent time

slot’s signaling data: offs et 0 stores TS0 signaling data, offset 1 stores TS1

signaling d ata, etc. T he signaling d ata is stor ed in the least sign ificant 4 bits of the

signaling buffer. Similar to TSLIP, TSIG has read/write processor access for

accessing or overwriting signal ing information. T FSYNC is us ed b y the sign aling

buffer to identify the frame boundaries in the TSIGI data stream.

2.3.5.4 Transmi t

Framing A transmit framin g option is provided to allow the transmitter to autom a tically

align to the transmit P CM data on TPCMI. In this mode, the Transmit Framer

searches transmit data for a valid E1 or T1 framing pattern. The transmit data

stream has tw o framing functions: offline framer and an onl ine framer . The of fline

framer recovers the transmit frame alignment (TFSYNC). The online framer

monitors the frame alignment found by the offline framer and recovers

multiframe alignment (TMSYNC).

Transmit Fr a m e Alig nm en t Transmit frame resynchronizati on is initiated by activating the Transmit Loss

Of Frame (TLOF) status bit in the Alarm 2 status [ALM2; addr 048] register by

the online framer. The TLOF criteria is set in the TLOFA, TLOFB, and TLOFC

bits of the Transmitter Configuration register [TCR1; addr 071]. The online

framer suppor ts the following LOF criteria for T1: 2 frame bit e rrors out of 4, 2

out of 5, or 2 out of 6; for E1, it supports 3 out of 3. Figure 2-19 illustrates

transmit framing and timebase alignment options.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-37

When TLOF is asserted, the offline framer searches the transmit data stream

for a new frame alignment, provided that transmit framing is enabled [TABORT;

addr 071]. If embedded framing is enabled [EMBED; addr 0D0], the offline

framer examines the TSLIP buffer output—TNRZ—for transmit frame

alignment. If embedded framing is disabled, the offline framer examines the slip

buffer input (TPCMI) for transmit frame alignment. This case (EMBED = 0) is

only applicable if TPCMI is configured to operate at the line rate—2,048 kbps

E1, or 1,544 kbps T1. If transmit framing is disabled, the offline framer waits for

a reframe command [TFORCE; addr 071] before beginning a frame alignment

search.

Transmit Multiframe

Alignment After the offline framer recovers frame alignment, the online framer monitors

TLOF and searches for m ul tiframe al ignment using criteria defined by the

Transmit Frame mode [TFRAME; addr 070]. The online framer conducts a

multiframe alignme nt search each time the of flin e framer recovers transmit frame

alignment—as reported by high-to-low transition of transmit loss of frame status

[TLOF; a ddr 0 48]. After TLOF recovery, the online fr amer searc hes cont inuou sl y

for multiframe alignment until the correct pattern seq uence is located, or u ntil

basic fram e alignment is lost (TLOF goes active-high). After m ultiframe

alignment recovery, the online framer checks subsequent multiframes for errored

alignment patterns, but does not use those errors as part of the criteria for loss of

basic frame alignment.

Figure 2-19. Transmit Framing and Timebase Alignment Options

NOTE(S):

(1) EMBE D locate d in SBI_CR (addr 0D0).

(2) TSB_ALIGN a nd TX_AL IGN locat ed in TSB_CR (a ddr 0D4) .

TPCMI

Off-Line

Framer

Pass

TSLIP

Buffer

A01 C

FSYNC MSYNC

TSB Timebase

TFSYNCI

TMSYNCI

TMSYNCO

TFSYNCO

ATSB Aligns to TPCMI (EMBED = 0)

BTSBAlignstoTX(TSB_ALIGN=1)

CTSB Aligns to TNRZ (EMBED = 1)

DTX Aligns to TSB (TX_ALIGN = 1)

TPHASE

Recenter

(TUSLIP)

CAS

On-Line MFAS

On-Line

TNRZ

TX Timebase

FSYNC MSYNCFAS CAS

TSB

Offset B

2.0 Circuit Descrip tion CX28394/28395/28398

2.3 Sys t em Bus Quad/x16/Octal—T1/E1/J1 Framers

2-38 Conexant 100054E

Note that th e online frame r' s m ultiframe se arch status is not directly reporte d

to the processor , but instead is monitored by e xamination of transmit error status:

TMERR, TSERR, and TCERR [addr 00B]. If the system incorporates a certain

number of m ultiframe pattern e rrors (or a certain error ra tio) into th e loss of

transmit frame alignment criteria, the processor must count multiframe pattern

errors to determine when to force a transmit reframe [TFORCE ; addr 071].

Transmit Fr a m e Alig nm en t

Criteria The frame synchronization criteria used by the offline framer is set in the

TFRAME[3:0] of the Transmit Framer Configuration register [TCR0; addr 070].

(Tables 3-15 and 3-16 illustrate supported transmit framing formats. Also, see

Tables 3-17 and 3-18, Criteria for Loss/Recovery of Transmit Frame Alignment.)

Transmit/Receive Framer

Arbitration The offline framer is shared between the RCVR and XMTR and can only

search in one direction at a time. Consequently, the host processor can manually

arbitrate between RCVR and XMTR reframe requests by manipulating the

ABORT and FORCE controls, or by allowing the framer to automatically

arbitrate LOF requests.

The offline framer waits until the current search is complete [FSTAT;

addr 017] before checking for pending LOF reframe requests. If both online

framers have pending reframe requests, the offline framer aligns to the opposite

direction of that most recently searched. For example, if TLOF is pending at the

conclusion of a receive search which timed out without finding alignment, the

offline framer switches to search in the transmit direction. The TLOF switchover

is prevented in the preceding example if the processor asserts TABORT to mask

the transmit reframe request. TABOR T does not affect TLOF status reporting. F or

applications that frame in only one direction, framing in the opposite direction

must be masked. If, at the conclusion of a receive search timeout, TLOF status is

asserted but masked by TABORT, the offli ne framer continues to search in the

receive direction.

For applications that frame in both directions, the processor can manually

arbitrate among pending reframe requests by controlling the reframe precedence.

An example of manual control follows:

1 Initialize RABORT = 1 and TABORT = 1.

2 Enable RL OF and TLOF interrupts.

3 Read clear pending ISR interrupts.

4 Release RABORT = 0.

5 Cal l LOF Ser vice Routine if either RLOF or TL OF interrupt;

{(check current LOF status (A LMI, 2; addr 047, 048)

If RLOF recovered and TLOF lost

—Assert RABORT = 1

—Release TABORT = 0

If RLOF lost or TLOF recovered

—Assert T ABOR T = 1

—Release RAB O RT = 0

}

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.3 System Bus

100054E Conexant 2-39

The status of the offline framer can be monitored using the Offline Framer

Status re gi ster [F STAT; ad dr 017]. The re gi ster re ports the following: w hether the

offline framer is looking at the receive or transmit data streams (RX/TXN);

w hether the frame r is a ctiv ely searching for frame a lignme nt (ACTIVE); whether

the framer found multiple framing candi dates (T IMEOUT); whether the framer

found frame sync (FOUND); and whether the framer found no frame alignment

candidates (INVALID).

2.3.5.5 Embedded

Framing Embedded framing mode [EMBED; addr 0D0] instructs the transmit framer to

search TSLIP buffer output (TNRZ) for framing bits while in T1 mode, or for

MFAS and CAS in E1 mode. Embedded framing allows the transmit timebase to

align with the transmit framer mul tiframe alignment of th e PCM signa l

transported across the system bus.

The Embedded mode supports ITU-T Recommendation G.802, which

describes how 24 T1 time slo ts and framing bit (193 bits) are mapped to the 32 E1

time slots (256 bits): by leaving TS0 and TS16 unassigned; by storing the 24 T1

time slots in TS1 t o TS15, and in TS17 to TS25; and by storing the frame bit in

Bit 1 of TS26 (see Figure 2-14, G.802 Embedded Framing).

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-40 Conexant 100054E

2.4 Transmitter

The Transmitter (XMTR) inserts T1/E1 overhea d data and ou tputs single ra il

NRZ data from the TSB or ZCS-encoded P and N rail NRZ data. The CX28395

only provi des single rail NRZ transmit signals.

The XMTR, Figure 2-20, consists of the followi ng elements: two Transmit

Data Links, Test Pa ttern Generat or , In-Band Loop back Code Generator , Overhead

Pattern Generator, Alarm Generator, Zero Code Suppression (ZCS) Encoder,

External Transmit Data Link (CX28394 and CX28398 only), CRC Generation,

Framing Pattern Insert ion, an d Far End Blo ck Error Gener ator.

Figure 2-20. XMTR Diagram

TPDV Enforcer

Alarm/Error Insert

PRBS/Inband LB

Sa-Byte/BOP

Data Link 1 Buffer

Data Link 2 Buffer

External DL3

T1/E1 Frame Insert

Transmitter

Timebase

TXCLK

To TSBI

TNRZ

ZCS

Encoder

AIS

Generator

Line

Loopback Framer

Loopback

TPOSO/TNRZO

TNEGO/MSYNCO

TDLI

TDLCKO

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-41

2.4.1 External Transmit Data Link (CX28394 and CX28398 Only)

The Exte rnal Data Link (DL3) all o ws the system to e xternall y suppl y an y bit (s) in

an y t i me sl ot in all frame s, odd frames or even frames, including T1 framin g bit s.

Pin access to the DL3 transmitter is provided through TDLCKO and TDLI. These

two pins serve as the TDL3 clock output (TDLCKO) and data input (TDLI). The

mode of the pins is sel ected using the TDL_IO bit in the Program m able

Input/Output register [PIO; addr 018].

Control of DL3 format is prov ided in two registers: External Data Link

Channel [DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016].

Transmit DL3 is set up by selecting the bit(s) [DL3_BIT], time slot [TS[4:0];

addr 015], and frames [EVEN/ODD; addr 015] to be overwritten, then enabling

the data link [DL3EN; addr 015]. Enabling the data link will start TDLCKO

gating the NR Z dat a provided on TDLI (see Figure 2-21).

NOTE: DL3 signals are not provided on the CX28395. Therefore, DL3_TS must

be written to 00 to disable the DL3 transmitter and prevent transmit data

corruption.

2.4.2 Transmit Data Links

The XMTR contains two independent data link controllers (DL1, DL2), a

Performance Report Message (PRM) generator, and a Bit-Oriented Protocol

(BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC

formatted messages in the Message Oriented Protocol (MOP) mode or

unformatted serial data over an y combina tion of bi ts with in a selected time slot or

F-bit channel. The PRM message generator can immediately or automatically

send one-second performance reports. The BOP transceiver can preemptively

transmit BOP messages, such as ESF Yellow Alarm.

2.4.2.1 Data Link

Controllers DL1 and DL2 control serial data channels operating at multiples of 4 kbps up to

the full 64 kbps time slot rate by selecting a combination of bits from odd, even,

or all frames. Both data link controllers support ESF Facilities Data Link (FDL),

SLC-96 data link, Sa data link, Common Channel Signaling (CCS), Signaling

System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI)

signaling in TS24, as well as the latest ETSI V.51 and V.52 signaling channels.

DL1 and DL2 each contain a 64-byte transmit buffer which function either as

prog rammable length circular buffers in transparent (unformatted) mode, or as

full-length data FIF O s in formatted (HDL C) mode.

Figure 2-21. Transmit External Data Link Waveforms

NOTE(S): This example shows bits 1, 2, 7, and 8 of TS9 selected. A ny combination of time slot bits can be select ed.

TDLI

TDLCKO

1 2 7 8

TS8 TS9 TS10

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-42 Conexant 100054E

DL1 and DL2 are configured identically, except for their offset in the register

map. The DL1 address range is 0A4 to 0AE, and the DL2 address ra nge is 0AF to

0B9. From this point on, the DL1 is used to describe the operation of both data

link controllers. Transmit Data Link 1 (TDL1) can be viewed as having a higher

priority than Transmit Data Link 2 (TDL2) because TDL1 overwrites the primary

rate channel after TDL2. Thus, any data tha t TDL2 writes t o the primary rate

channel can be overwritten by TDL1, if TDL1 is configure d to transmit in the

same time slot as TDL2.

The TDL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6].

TDL1 will not o verwrite time slot data until it is enabled. DL1_CTL also controls

the data format and the circular buffer/FIFO mode.

The following data formats [DL1[1,0]; addr 0A6] are supported on the data

link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and

non-FCS are HDLC-formatted messages. Pack8 and Pack6 are unformatted

messages with 8 bits per FIFO access, and 6 bits per FIFO access, respectively.

2.4.2.2 Circular Buffer The Circular Buffer/ FIFO cont rol bit [TDL1_RPT; addr 0A6] al lows the FIFO to

act as a circular buffer; in this mode, a message can be transmitted repeatedly.

This feature i s available only for unformatted transmit da ta link applications . The

processor can repeatedly send fixed patterns on the selected channel by writing a

1- to 64-byte message into the circular buffer. The programmed message length

repeats until the processor writes a new message. The first byte of each

unformatted message is output automatically, aligned to the first frame of a

24-, or 16-frame transmit multiframe (SF/ESF/MFAS). This allows the processor

to source overhead or data elements aligned to the TX timebase. In both SF and

ESF T1 modes, unformatted messages are aligned on 24-frame boundaries.

Therefore, i n SF applica tions the repeat ing message must be desi gned to span two

SF multiframes.

Each unformatted message written is output-aligned only after the preceding

message complet es transmission. T herefore, data continui ty is reta ined during t he

linkage of consecutive messages, provided that the contents of each message

consists o f a mu ltiple of th e mu ltiframe len gth.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-43

2.4.2.3 Time Slot and

Bit Selection Time slot and bit selection is done through the DL1 Time Slot Enable [DL1_TS;

addr 0A4] and DL1 Bit Enable [DL1_BIT; addr 0A5] registers. DL1_TS selects

which frames and which time slot will be overwritten. The fram e select allows

TDL1 to overwrite the time slot in either all frames, odd frames, even frames, or

in a special 2 kbps mode. The time slot word enable is a value between 0 and 31

that selec ts which time slot will be filled wit h data from the transmit data link

buffer. DL1_BIT selects which bits will be overwritten in the time slot selected.

Table 2-5 lists commonly used data link settings.

2.4.2.4 Transmit Data

Link FIFO Buffer The T ransmit Dat a Link F IFO #1 [T DL1; addr 0AD] is a v e rsatile, 64- b yt e buf fer

that can be used as a single-byte transmit buffer or for any number of bytes up to

64. As a single-byte FIFO, the Transmit FIFO Empty Status (TMPTY1) in TDL

#1 Status [TDL1_STAT; addr 0AE] and Transmit FIFO Empty Interrupt

(TEMPTY) in Data Link 1 Interrupt Status (ISR2; addr 009] can be used to do

byte-by-byte transmissions.

Using the Transmit Data FIFO , an entire block of data can be transmitted with

very lit tle microprocesso r interrupt overhead. Block tran sfers to the FIFO can be

controlled by the Near Empty Threshold in the FIFO Empty Control register

[TDL1_FEC; addr 0AB]. The Near Empty Threshold is a user-programmable

value between 0 and 64 that represents the minimum number of bytes that can be

left in the transmit FIF O before near empty is de cla red. Once t he threshol d is set,

the Near Empty Status (TNEAR1) in TDL #1 Status [TDL1_STAT; addr 0AE]

will be asserted whenever the Near Empty Threshold is reached. An interrupt,

TNEAR in the Data Link 1 Interr upt Status register [ISR2; addr 009], is also

available to mark this event.

2.4.2.5 End of Message Once an entire message is written to the tran sm it FIFO or circular buffer, the

processor must indicate the end of message by writing any value to the TDL #1

End Of Message (EOM) Control [TDL1_EOM; addr 0AC]. In FCS mode, the

EOM indicates that the FCS is to be calculated and transmitted following the last

byte in the FIFO. In the circular buffer mode, the EOM indicates the end of the

transmit circular buf fe r.

Table 2-5. Commonly Used Data Link Settings

Data Link Frame Time Slot Time Slot Bits Mode

ESF F DL Odd 0 (F-bi ts) Don’t Care FCS

T1DM R Bit All 24 00000010 FCS

SLC-96 Even 0 (F-bits) D on’t Care Pack6

ISD N LAPD All N 111 11111 FCS

CEPT Sa4 Odd 1 0000100 0 FCS

NOTE(S): N represen ts any T1/E1 time slot.

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-44 Conexant 100054E

2.4.2.6 Programming

the Data Link Controller The Transmit Data Link Controller can be prog rammed according to the system

CPU bandwidth. For systems with sufficient CPU bandwidth, the data l i nk stat us

can be polled, and the 64-byte transmit FIFO buffer can be used as a single-byte

transmit buffer. For systems with limited CPU ban dwidth, the data link can be

interrupt-dri ven, and the entire 64-b y te transmit FIFO buf fe r can be used to store

entire messages. See Figures 2-22 and 2-23 for a hi gh l ev el description o f pol l in g

and interrupt-driven Transmit Data Link Controller software.

The de v ice uses a hierarchical in terrupt structure, with one top-lev el int errupt

request register directing software to the lower levels (see Master Interrupt

Request register; addr 081 and Interr upt Request register; addr 003). Of all the

interrupt sources, the two most significant bandwidth requirements are signaling

and data link interrupts. Each data link controller has a top-level interrupt status

registers [ISR2; addr 009, and ISR1; 00A]). The processor uses a three-step

interrupt scheme for the data link:

1. Read the Master Interrupt Request register to determine which framer is

interrupted.

2. Read the Interrupt Request register for that framer.

3. Use that register value to read the corr esponding Data Link Interrupt

Status register.

Figure 2-22. Polled Transmit Data Link Processing

Transmit Message

WriteBlock/BytetoFIFO

Yes

Read FIFO Status

Write End of Message Register

Yes

Return

Wait N Milliseconds

End of

Message

FIFO Empty

Message

Block 1

Block 2

Block 3

0x00

0x20

0x40

or Near

Empty

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-45

Figure 2-23. Interrupt-Driven Transmit Data Link Processing

Transmit Message

WriteBlock/BytetoFIFO

Process Other Interrupt

Yes

Return

WriteBlock/BytetoFIFO

End of

Message

Yes

Message

Block 1

Block 2

Block 3

0x00

0x20

0x40

Main Line Code

Return

Interrupt Service Routine

Interrupt Occurred

Read Interrupt Status

Transmit Data

Link Near Empty

Interrupt

Return

Write End of Message Register

Return

Block 4

0x60

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-46 Conexant 100054E

2.4.2.7 PRM Generator In T1 applications, Performance Report Messages (PRMs) are HDLC messages

containing path identification and performance monitoring information. If

automatic perfor mance repor t insertion is selected [AUTO_PRM; addr 0AA], a

performance report is generated each second and begins transmitting coincident

with the one-second timer interrupt [ONESEC; addr 005]. The PRM is sent

immediately if the processor sets SEND_PRM bit in the Performance Report

Message register [PRM; addr 0AA]. All performance monitoring fields of the

message are automatically filled in when a PRM is generated. The remaining

PRM bit fields are application-specific and can be configured using the

Performance Report Message register.

For limited systems, the automatic PRM generation off-loads a signific ant

portion of CPU bandwidth.

2.4.2.8 TBOP

Transceiver The Transmit Bit-Oriented Protocol (TBOP) transceiver sends BOP messages in

T1 applicati ons, inc lu di ng ESF Yell ow Alarm. These messages consist of

repeated 16-bit patterns with an embedded 6-bit codeword, as shown in this

example:

0xxxxxx0 11111111 (transmitted right to left)

[543210] TBOP = 6-bit codeword

The TBOP is configured to operate over the same channel selected by Data

Link #1 [DL1_TS; addr 0A4]. The TBOP channel must be configured to operate

over the FDL channel in order for TBOP to convey Priorit y, Command, and

Response codeword messages according to ANSI T1.403, Section 9.4.1. The

precedence of transmitted BOP messages with respect to current DL1 transmit

activity is configurable using the Transmit BOP mode bits [TBOP_MODE[1 ,0];

addr 0A0]. BOP messages can also be transmitted during E1 mode, although the

16-bit codeword pattern has not currently been adopted as an E1 standard. The

length of the BOP message [TBOP_LEN[1,0]; addr 0A0] can be set to a single

pattern, 10 patterns, 25 patterns, or continuous.

BOP codewords are tran smitted by writing to the Transm it BOP Codeword

[TBOP; addr 0A1]. The real-time status of the codeword transmission can be

monitored using TBOP_ACTIVE in the BOP Status register [BOP_STAT;

addr 0A3]. A TBOP Transmit interrupt is available in the Data Link 1 Interr upt

Status register [ISR2; addr 009] to indicate that a codeword has begun

transmission and the next codeword may be written to TBOP.

2.4.3 Sa-Byte Overwrite Buffer

There are five transmit Sa-Byte buffers [TSA4 to TSA8; addr 07B to 07F]. The

Sa-Byte buffers insert Sa-bits into the odd frames of TS0. The entire group of 40

bits is sampled every 1 6 frames coincide nt with the Transmi t Multiframe bit

interrupt boundar y [TMF; addr 008]. Bit 0 from each TSA register is then

inserted during fra me 1, bit 1 is i nserted during frame 3, bi t 2 duri ng frame 5, and

so on, which gives the processor up to 2 ms after TMF interrupt to write new

Sa-By te buffer values . Transmit Sa-bits maintain a fixed relationship to the

transmit CRC multiframe. Each of the 5 Sa-Byte transmit buffers can be

individually enabled using the Manual Sa-Byte Transmit Enable in Transmit

Manual Sa-Byte/FEBE Configuration register [TMAN; addr 074].

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-47

2.4.4 Overhead Pattern Generation

The transmit overhead generation circuitry provides the ability to insert all of the

overhead associated with the Primary Rate Channel. The following types of

overhead pattern generation are supported: Framing patter n s, Alarm patterns,

Cyclic Redundancy Check (CRC), and Far-End Block Error (FEBE).

2.4.4.1 F raming Pattern

Generation The framing pattern generation circuitry inserts the 2-bit terminal framing (Ft)

pattern, the 6-bit signaling frame (Fs) pattern, the 6-bit FPS pattern, the 8-bit

FAS/NFAS pattern, and the 6-bit MFAS pattern into the transmit data stream.

The Ft pattern in SF, SLC-96, and T1DM is in serted into the tra nsmit data

stream b y enab li ng the INS_FBIT in the T ra nsmit F rame Format regi ster [TFRM;

addr 072]. The Fs pattern in SF is inserted by enabling the INS_MF bit. The FPS

pattern in T1-ESF and the FAS/NFAS pattern in E1 mode are inserted b y enab ling

the INS_FBIT bit. The M FAS pattern is inserted by enabling the INS_MF bit.

2.4.4.2 Alarm

Generation The Transmit Alarm Generation circuitry generates Alarm Indication Signal

(AIS) and Remote Alarm Indication (RAI/Yellow Alarm).

AIS Generation AIS is an unframed all-ones pattern and is nor mally transmitted when the data

source is lost. AIS transmission can be enabled:

1. manually,

2. automatically upon detection of transmit loss of clock, and

3. automatically upon loss of received signal.

Typical applications require transmission of AIS toward the line when DTE

transmit dat a or clock is not p resent. In most applicat ions, DTE data and cl ock are

isolated from the transmitter requiring manual AIS transmission under software

control. Manual insertion of AIS is controlled by the TAIS bit in T ransmit Alarm

Signal Configuration register [TALM; addr 075]. Set ting this bit overwrites the

currentl y transmitted data with the AIS pattern. If AISC LK [TLIU_CR; addr 068]

is also set, AIS is tra nsmitted usi ng an alternate transmit line rate clock supplied

on E1ACKI (for E1 ) or T1ACKI (for T1) pins.

Automatic transmi ssion of AIS can be control led b y detect ion of tran smit loss

of clock [TLOC; addr 048]. This mode is enabled by setting AISCLK and

providing an alternate transmit line rate clock on the E1ACKI or T1ACKI pin. If

no transitions are detected on the TCKI pin for eight cycles of E1ACKI or

T1ACKI, TLOC is set a nd AIS is transmitte d. AIS is ter minated and TLOC

cleared when TCKI returns.

By setting AUTO_AIS in the TALM register, automatic transmission of AIS

can also be c ontrolled b y detection of Recei v er Loss Of Signal [RLOS; addr 047].

This mod e is typically used to tra nsmit AIS (keep-alive) during line lo opback if

the received signal is lost . Setting AUTO_AIS sim ultaneously with setting

LLOOP [LOOP; addr 014] enables this operation.

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-48 Conexant 100054E

Yellow Alarm Generation Yello w Alarm, also referred to as RAI (Remote Alarm Indication), is a bit patt ern

inserted into the transmit stream to alert far-end equ ipment that the local receiver

cannot recover data. Yellow Alarm/RAI is typically transmitted during receive

loss of frame and is defined dif ferentl y depending upon t he transmit frame f ormat

configured [TFRAME; addr 070]. Table 2-6 describes the Yellow Alarm/RAI

transmitted for each frame format.

Transmission of Yellow Alar m/R AI is controlled by these register bits:

Insertion of Yellow Alarm/RAI into the transmit stream is controlled by

INS_YEL. Yellow Alarm/RAI is inserted only when INS_YEL is set, otherwise

these bit positions are supplied by data from TPCMI. Yellow Alarm/RAI

generation can be done manually or automatically.

Manual generation of Yellow Alarm/RAI is cont rolled by TYEL. Setti ng this

bit will immediately and unconditionally overwrite the Yellow Alarm/RAI signal

bit(s) in the transmitted data stream with the appropriate pattern.

Automatic generation of Yellow Alarm/RAI is controlled by AUTO_YEL ,

RLOF, and RLOF_INTEG. If AUT O_YEL is set, Yellow Alarm/RAI is generated

during a receive loss of frame alignment (RLOF = 1). Optionally, RLOF

integra tion can be enabled by setting RLOF_ I NTEG. In this ca s e , both RLOF

indication and Yellow Alarm/RAI generation are delayed for approximately 2.5

seconds if a continuous out-of-frame condition exists. Yellow Alarm/RAI

generation continues for at least 1 second after RLOF clears.

Table 2-6. Yellow Alarm Generation

Frame For m at Yellow Alarm Transmitted Mode

SF Bit 2 of every time slot set to zero YB2

ESF(1) Bit 2 of every time slot set to zero YB2

SLC-96 Bit 2 of every time slot set to zero YB2

SF/JYEL F-bit 12 of ev ery superf r a me set t o one Y J

T1DM Y bit of the sync byte set to zero Y24

E1 The A bit of TS0 set to one Y0

NOTE(S):

(1) Yellow Alarm/RAI for T1-ESF framing is defined as a BOP priority codeword in the FDL

channel. T1-ESF Yell ow Alarm/RA I is not tran smitted using the procedur e described

below. Instead, T1- ESF Yellow Alarm/RAI is generated by configuring DL1 to

continuously tr ansmit an all zeros BOP prio rit y codeword. Refer to Section 2.4.2,

Transmit Data Links.

Bit Name Register

INS_YEL TFRM; addr 072]

TYEL TALM; addr 075]

AUTO_YEL TALM; addr 075]

RLOF ALM1; addr 047]

RLOF_INTEG RALM; addr 045]

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-49

Multiframe Yellow Alarm

Generation In E1 CAS framing modes, Multiframe Yellow Alarm is inserted into the transmit

stream to alert far-end equipment that local received multiframe alignment is not

reco vered. E1 Multiframe Yello w Alarm is transmitted by setting the Y bit in time

slot 16, frame 0.

Transmission of Multiframe Yellow Alarm is controlled by these register bits:

Insertion of E1 Mu ltiframe Yellow Alarm is c ontrolled by INS_MYEL a nd

inserted only when INS_MYEL is set. Multiframe Yellow Alarm generation can

be initiated manually or automatically.

Manual in se rtion of Multifra m e Yellow Alarm is controlled by TMYEL.

Setting this bit will uncond itionally overwrite the Mul tiframe Yell ow Alarm

signal bit in the transmitted data stream.

Automatic inser tion of Multifra me Yellow Alarm is controlled by

AUTO_MYEL in the TALM register. When set, the AUTO_MYEL m ode will

send y ellow alarm for the duration of a receive loss of CAS multiframe al ignment

[SRED; addr 049]

2.4.4.3 CRC Generation The CRC generation circuitr y computes the value of the CRC6 code in T1 mode

or the CRC4 code in E1 mode. Once computed, it is inser ted into the appropriate

position of the transmitted dat a stream. CRC overwrite is enabled by INS_CRC

[TFRM; addr 072]. In T1 mode, CRC6 may be computed on only the payload

data or on all data including the F-bit. Setting TINCF [TCR0; addr 070] selects

CRC6 computation on all data.

If the transmit frame format is configured as ESF and INS_CRC is active, the

2 kbps CRC sequence is inserted. The position of the CRC-6 bits is shown in

Table A-4, Extended Superframe Format.

If the transmit frame format is configured as E1, and INS_CRC is active, the

4 kbps CRC sequence is inserted. The position of the CRC-4 bits is shown in

Table A-6, ITU–T CEPT Frame Format Time Slot 0 Bit Allocations.

2.4.4.4 Far-End Block

Error

Generation

The register bits that control FEBE are INS_FE [TFRM; addr 072], TFEBE

[TMAN; addr 074], FEBE_I [TMAN; addr 074], and FEBE_II [TMAN; addr

074]. The Far-End Block Error (FEBE) generation circuitry inserts FEBE bits

automa ti cally or manuall y. Automatic FE BE generation i s enabled by INS_F E. I f

the transmit frame format is configured as E1 and INS_FE bit is set, a FEBE is

generated in response to an incoming CRC-4 error by setting an E-bit of TS0 to

zero. Refer to Table A-6, ITU– T CEPT Fr ame Format T ime Sl ot 0 Bit Allocati ons,

for the location of the E-bits within the E1 frame.

Manual FEBE gene ration is en abled by TFEBE. If the tran sm it frame format

is configured as E1 and TFEBE is set, the FEBE bits are supplied by the

processor in FEBE_I and FEBE_II.

Bit Name Register

INS_MYEL [TFRM; addr 072]

TMYEL [TALM; addr 075]

AUTO_MYEL [TALM; addr 075]

SRED [ ALM3; addr 049]

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-50 Conexant 100054E

2.4.5 Test Pattern Generation

The transmit test pattern generation circuitry overwrites the transmit data with

various test patterns and permits logical and frame-bit er ror insertion. This

feature is particularly useful for system diagnostics, production testing, and test

equipment applications. The test pattern can be a framed or unframed PRBS

pattern. The PRBS patterns available include 2E11-1, 2E15-1, 2E20-1, and

2E23-1 . Each pattern can optionall y incl ude Zero Code Suppr ession (ZCS). Error

insertion includes LCV, BPV, Ft, CRC4, CRC6, COFA, PRBS, Fs, MFAS, and

CAS.

The Transmit Test Patter n Configuration register [TPATT; addr 076] controls

the test patter n insertion circuit. TPATT controls the P RBS pattern (TPATT[1:0])

bits), ZCS se tting (ZLIM I T bit), T1/E1 fra ming (FRA MED bit), and starti ng and

stopping transmission (TPSTART bit).

Patterns are generated in accordance with ITU–T O.150 (10/92), O.151

(10/92), and O.152 (10/92). Enabling ZLIMIT modifies the inserted pattern by

limiting the number of consecutive zeros. For the 2E11-1 or 2E15-1 PRBS

patterns, eigh t or more zeros will not occur with ZLIMIT enab led. F or the 2E 20-1

or 2E23-1 PRBS patterns, 15 or more zeros will not occur with ZLIMIT enabled.

Note that the QRSS patt ern is a 2E20-1 PRBS with ZLIMIT enabled. This

function is performed according to ANSI T1.403 and ITU–T O.151 (10/92).

Frame bit positions can be preserved in the output pattern by enabling

FRAMED. In T1 mode, this p r events the test patte rn fro m overwriting the frame

bit which occurs every 193 bits. In E1 mode with FRAMED enabled, the test

pattern does not overwrite time slot 0 data (FAS and NFAS words) and time slot

16 (CAS signalling word) if CAS framing is also selected. CAS framing is

selected by setting TF RAME[3] to 1 in the Transmit Configura tion register

[TCR0; addr 070]. The test pattern is stopped during these bit periods according

to ITU-T O .151, ( 10/92). If FRAMED is disab led , the te st pattern is transmitted in

all time slots.

2.4.6 Transmit Error Insertion

The Transmit Error Insert register [TERROR; addr 073] controls error insertion

during pattern generation. Writing one to a TERROR bit injects a single

occurrence of the respective error on TPOSO/TNEGO and XTIP/XRING

outputs; writing a zero has no effect. Multiple transmit errors can be generated

simultaneously. Periodic or random bit error rates can also be emulated by

software control of the error control bit. Note that injected errors affect the data

sent during a Framer or Analog Loopback [FLOOP or ALOOP; addr 014].

Line Code Violations (LCV) are inser t ed via the TVERR bit of the TERROR

ones. TVERR is latche d until the BPV is inserted into the transmit data stream,

and then cleared. In E1 mode with HDB3 selected, two consecutive BPVs of the

same polarity are inserted. This is registered as a single LCV for the receiving E1

equipment.

Ft, FPS, and FAS bit errors are inserted using the TFERR bit in the TERROR

CRC4 (E1) and CRC6 (T1) bit errors are inserted using the TCERR bit in the

TERROR register. TCERR c ommands a logical inversion of the next CRC bit

transmitted.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-51

Change Of Frame Alignments (COFAs) are controlled by the TCOFA and

BSLIP bits in the TERROR register. TCOFA command s a 1-bit shift in the

location of t he tr ansmit f rame align ment b y delet ing (o r in serting) a 1-bit posit ion

from the tra nsmit frame. During E1 mode s, BSLIP dete rmin es which direction

the bit slip occurs. In T1 modes, only 1-bit deletion is pro vided. Note that TCOFA

alters extraction rate of data from transmit slip buffer; thus, repeated TCOFAs

eventually cause a controlled frame slip where one frame of data is repeated

(T1/BSLIP = 0), or where one frame of data is deleted (BSLIP = 1).

PRBS test pattern errors are inserted by TBERR in the TERROR register.

TBERR commands a single PRBS error by logically inverting the next PRBS

generator output bit.

Fs and MFAS errors are controlled by the TMERR bit in the TERROR

by logically inverting the next multifram e bit transmitted.

CAS Multiframe (MAS ) errors are controlled by the TSERR bit in the

TERROR register. TSERR commands a single MAS pattern error by logically

inver ting the first MAS bit transmitted.

2.4.7 In-Band Loopback Code Generation

The in-band loopback code generator circuitry overwrites the transmit data with

in-band codes of configurable value and length. These codes are sequences with

periods of 1 to 7 bits and may, in some applications, overwrite the framing bit.

The Transmit Inband Loopback Code Configuration register [TLB; addr 077]

controls the functions required for this operation.

A loopback code is gene ra ted in the tra nsmit data strea m by writing the

loopback co de to the T ransmit Inban d Loopback Code Patte rn registe r [LBP; addr

078], and then setting the Start Inband Loopback (LBSTART) and Loopback

Length (LB_LEN) bits in the Transmit Inband Loopback Code Configuration

to overwrite framing bits using the UNFRAMED bit. The LB_LEN provides

loopback code patt ern lengths of 4 t o 7 bits. Patt erns of 2 or 3 bits can b e achie ve d

b y repeating t he pattern in 4- or 6-bi t modes, respect i vel y. Framed or unframed all

ones or all zeros can also be ach ie ved b y setti ng the pattern to all zeros or all ones.

2.4.8 ZCS Encoder

The ZCS encoder encodes the single rail clock and data (unipolar) into dual rail

data (bipolar). The Transmit Zero Code Suppression Bits (TZCS[1,0]) in the

Transmitter Configuration register [TCR1; addr 071] selects ZCS and Pulse

Density Violation (PDV) enforcement options for TPOSO/TNEGO output pins.

TZCS supports the following: Alternate Mark Inversion (AMI); High Density

Bipolar of order 3 (HDB3); Bipolar with 8 Zero Suppression (B8ZS); Pulse

Density Violation (PDV); Unassigned Mux Code (UMC); and Bipolar with 7

Zero Suppression (B7ZS). Note that ZCS encoding, which alters data content, is

performed prior to the CRC calculation so the outgoing CRC is always correct.

The AMI line code requires at least 12.5 percent average ones density and no

more than 15 consecutive zeros. A one is encoded as either a positive or negative

pulse; a zero is the absence of a pulse. Two consecutive pulses of the same

polarity are referred to as a Bipolar Violation (BPV).

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-52 Conexant 100054E

The HDB3 line code replaces four consecutive zeros by 000V or B00V code,

where B is an AMI pulse and V is a bipolar violation (see Figure 2-24). ZCS

encoder selects the code that will force the BPV output polarity opposite to the

prior BPV.

UMC forces DS0 channels containing 8 zeros to be replaced with the

10011000 code, per Bellcore TA-TSY-000278. Note that RCVR's ZCS decoder

cannot recover original data content from a UMC or B7ZS encoded signal, or

from a PDV-enforced one.

Figure 2-24. Zero Code Substitution Formats

BPV

BPV BPV

110000000011

Octet

AMI

B8ZS

HDB3

B7ZS

UMC

Zero Code Substitution Formats

BPV

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.4 Transmitter

100054E Conexant 2-53

The outpu t on TP OSO/TNEGO can b e chang ed from dual rail b ipola r to NRZ

unipolar data (TNRZO) and to multiframe sync clock (MSYNCO), using the

Transmit NRZ Data (TNRZ) bit in TCR1[addr 071]. Figures 2-25 and 2-26

illustrate transmit signal timing for both bipolar and unipolar operation.

Figure 2-25. Transmit Signals

11 11 1000

TCKO

TPOSO

(Bipolar)

TNEGO

(Bipolar)

TNRZO

(Unipolar)

8394-8-5_077

2.0 Circuit Descrip tion CX28394/28395/28398

2.4 Tran s mi tter Quad/x16/Octal—T1/E1/J1 Framers

2-54 Conexant 100054E

Figure 2-26. NRZ Mode Transmit Signals

8394-8-5_078

In E1 mode, MSYNCO is output during bit 7 of

time slot 31 in frame 15 of the multiframe.

Bit 8 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6F-bit

Bit 6 Bit 8 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5Bit 7

Time Slot 24,

Frame 12 (SF) or

Frame 24 (ESF)

Time Slot 1,

Frame 1

Time Slot 0,

Frame 0

Time Slot 31,

Frame 15

MSYNCO

TCKO

TNRZO

MSYNCO

TCKO

TNRZO

T1 Mode

E1 Mode

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.5 Mi croproc essor Interface

100054E Conexant 2-55

2.5 Microprocessor Interface

The Microprocessor Interface (MPU) provides the capability to configure the

device, read status registers and counters, and respond to interrupts (see

Figure 2-27). The in terface supports both the Int el 8051 and Motorola 680 00-type

processors. In the Intel mode , the address and d ata are multip lexed; in the

Motorola mode, the address and data are separate pins. Both synchronous and

asynchronous Read and Write modes are supported. The synchronous mode is

optimized for Motorola 68000-type processors with a maximum clock rate of 36

MHz. The asynchronous mode runs intern ally at 32 MHz, which limits the

processor speed to 30 MHz for 68302 processors, and 16 MHz for 8051

processors.

The microprocessor interface is made up of the following pins: MCLK,

MOTO*, SYNCMD, CS*, AS*/ALE, DS*/RD*, R/W*/W R*, DTACK*,

AD[7:0], A[11:0], INTR*, ONESEC, RST*. A detailed description of the MPU

signals is provided in Table 1-6, Hardware Signal Definitions.

Figure 2-27. Micropro c essor In terface Block D iagram

Microprocessor Interface

MCLK

MOTO*

SYNCMD

CS*

AS*/ALE

DS*/RD*

R/W*(WR*)

DTACK*

AD[7:0]

A[11:0]

INTR*

ONESEC

RST*

2.0 Circuit Descrip tion CX28394/28395/28398

2.5 Microprocessor Interface Quad/x16/Octal—T1/E1/J1 Framers

2-56 Conexant 100054E

2.5.1 Address/Data Bus

In Non-Multi ple x ed Address Mode, A[11: 0] (A[10: 0] for CX283 94) provides the

address for the register access. In Multiplexed Address Mode, A[11:8] (A[10:8]

for CX28394) and AD[7:0] provide the address. In both modes, the data bytes

flow over the shared bidirectional, byte-wide bus, AD[7:0].

2.5.2 Bus Control Signals

Four signals control operation of the interface por t . The control signals are

AS*/ALE, CS *, DS*/RD*, an d R/W*(WR*). An addit ional pi n, MOT O*, selects

whether the interface signals are of a Motorola or Intel style.

When MOT O* is lo w, indicating a Motorola-style interface, CS*, AS*, R/W*,

and DS* signals are expected. When MOTO* is high, indicating an Intel-style

interface, CS*, ALE, RD*, and WR* signals are expected.

When MOTO * is high, the a ddress lines are multiplexed with the data . This

pin should usually be tied high for Intel devices and tied low for Motorola

devices. SYNCMD puts the interface into the Synchronous Processor Interface

Mode. Motorol a 68000 processor s typical ly ha v e SYNCMD tied high if MC LK is

connected to the MPU clock source; Intel 8051 processors have SYNCMD tied

low (see Table 2-7).

2.5.3 Interrupt Requests

Figure 2-28, In terrupt Generation Blo ck Diagram, details t he interrupt gener ation

process. The INTR* output pin is an active low, open-drain type output which

provides a common interrupt request for all eight framers and the LIU serial

interface.

Each framer includes interr upt status registers (ISR[7:0]), interr upt enable

registers (IER[7:0]), an d an interrupt request re gister (IRR). Ev ents such as alarm

status changes and sync signals are latched in ISR registers until read by the

microprocessor. Each ISR bit has a corresponding IER bit used to enable or

disable interrupt gen eration. If enabled, an ISR event is reported in the

appropriate IRR bit.

Table 2-7. Microprocessor Interface Operating Modes

MOTO* SYNCMD Description

0 0 Asynchronous Motorola, internal clock

0 1 Synchronous Motorola, external clock

1 0 Asynchronous Intel, internal clock

1 1 Synchronous Intel, external cl ock

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.5 Mi croproc essor Interface

100054E Conexant 2-57

The IRR bits from each framer are gated with the corresponding enable bit in

the master interrupt enable register [MIE; addr 01E] and are routed to the master

interrupt register [MIR; addr 01D]. MIE provides a convenient location t o enable

or disable inter rupts for an entire framer. The serial done bit [SER_STAT;

addr 024] is gated with the serial inter rupt enable bit [SER_CONFIG; addr 025]

to prod uce an additional interr upt reque st. Finally, MIR bits and the LIU serial

interface interr upt request are combined to generate a single interrupt request

signal on th e INT R * pin.

Using these registers, the microprocessor can process interrupts as follows:

Interrupt se rv ice routine

1. Read MIR and SER_STAT registers to determine which framer or framers

caused the interrupt or whether LIU serial operation occurred.

2. For each interrupting framer, read IRR to determine which ISR contains

the inte rrupt event or events.

3. Read the ISR and mask t he interrupt e v ent bit using the corresponding IER

to determine which event or events caused the interrupt.

4. Enter the appropriate service routine.

Figure 2-28. Interrupt Generation Block Diagram

NOTE(S):

(1) In CX2 8395, IN TR1* is pro v ided for Framers 1-8, and INTR2* is provided for Framers 9-16.

SER_DONE Framer 8

IER

Registers

ISR

Latches

Framer 7

Framer 6

Framer 5

Framer 4

Framer 3

Framer 2

Framer 1

Events

MIE

INTR*

IRR

SER_IER

MIR

2.0 Circuit Descrip tion CX28394/28395/28398

2.5 Microprocessor Interface Quad/x16/Octal—T1/E1/J1 Framers

2-58 Conexant 100054E

2.5.4 Device Reset

The device contains four reset methods:

1. Inter nal Power-On Reset (POR),

2. Hardware Reset which uses the RST* pin,

3. Global Software Reset which uses the GRESET bit in register FCR [addr

080], and

4. Software Reset which uses the RESET bit in register CR0 [addr 001].

All four methods resul t in de vice outputs plac ed in a high- impedance st ate and

configuration registers set to default values as shown in Table 3-4, A d dress Map.

In all reset met hod s, SYSC KI must be present during th e reset process for proper

operat ion . M CL K ( i nternal or external) per f orms the actual r egister initi ali zat i on.

Therefore, if the SYNCMD pin is connected high to enable external MCLK, the

external MCLK must be applied during reset, and if the SYNCMD pin is low

during reset, the internal clock (33 MHz) is used and external MCLK is not

required. After hardware reset, software reset, or internal power-on reset, the

microprocessor must initialize the configuration registers to the desired state.

An internal POR process is initiated during power-up. When V DD has

reached approximately 2.0 V, the internal reset process begins and continues for

100 SYSCKI cycles if SYSCKI is applied. If SYSCKI is not present, the device

remains in the reset state and does not terminate until detecting 100 SYSCKI

cycles. GRESET or RESET can be monitored to determi ne when POR is

complete. MCLK (internal or external) must be present during the POR

concurr ent with SYSCKI to allow register initial iz ation.

Hardware reset is initiated by bringing the RST* pin active (low ) for a

minimum of 4 µs. If SYNCMD is high (using external MCLK), external MCLK

must be prese nt while RST* is low to allow register initialization. After RST* is

deactivated, the internal reset process continues for 5 µs and register access

should be avoided. GRESET can be monitored to determine when the reset

process is complete.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.6 Loopbacks

100054E Conexant 2-59

2.6 Loopbacks

The device provides a complete set of loopbacks for diagnostics, maintenance,

and troubleshooting for each framer. All loopbacks perform clock and data

switching, if necessary.

2.6.1 Remote Line Loopback

The line loopback loops the RCVR inputs to the XMTR outputs. The loopback

provides BPV transparency and the ability to override the lo oped data with AIS.

The RCVR data path is not affected by the activation of this loopback. Remote

line loopback is activated by setting the Remote Line Loopback (LLOOP) bit in

the Loopback Configuration register [LOOP; addr 014]. It is possible to operate

the remote line loopback simultaneously with the local framer loopback.

2.6.2 Remote Payload Loopback

The pa yl oad loo pback loop s all DS0 c hannels f rom the RCVR i nput t o the XMT R

output. Payload loopback retains time slot integrity, so that numbered time slots

from each receive frame are transferred to the same numbered time slots in the

transmit frame. Transmit overhead bits—F-bits in T1 mode or TS0 in E1

mode—are supplied by transmit frame formatter or by TSB according to TFRM

[addr 072] settings. Existing transmit frame alignment and clock timing are not

altered by [PLOOP; addr 014] activation or deactivation, allowing system

operation with independent receive and transmit timing. Controlled frame slips

are perfor med in the payload loopback path if receive and transmit clocks are

asynchronous, alt hough t hese slips are not reported to the proce ssor as slip buf fer

errors. Multiframe integrity is not maintained during PLOOP; therefore, DS0 and

signaling channel loopbacks [TPCn; addr 100–11F] must be used to implement

payload loopback if transparent or forced signaling is desired. PLOOP overrides

transmit per-channel remote loopback selection (TLOOP bit in TPCn).

2.6.3 Remote Per-Channel Loopback

The remote per-channel loopback loops the RCVR input DS0 channel to the

XMTR output DS0 channel. The remote per-channel loopback is activated by

setting TLOOP in the Transmit Per-Channel Control register [TPC0 to TPC31;

addr 100 to 11F].

2.0 Circuit Descrip tion CX28394/28395/28398

2.6 Lo op backs Quad/x16/Octal—T1/E1/J1 Framers

2-60 Conexant 100054E

2.6.4 Local Framer Loopback

The local framer loopback loops the transmit line encoder outputs to the receive

line decoder inputs. Transmitter output is not affected by the activation of this

loopback. The local framer loopback is activated by setting the Local Framer

Loopback (FLOOP) bit in the Loopback Configuration register [LOOP;

addr 014]. It is possible t o operate the local f ramer loo pback simultaneo usly with

the remote line loopback.

2.6.5 Local Per-Channel Loopback

The local per-channel loopback loops the TSB PCM and signaling inputs to the

RSB PCM and signaling outputs on a per-channel basis. The local per-channel

PCM loopback is activated by setting RL OOP in the System Bus Per-Channel

Control registers [SBC0 to SBC31; addr 0E0 to 0FF]. The local per-channel

signaling loopback is a ctivated by setti ng SIG_LP in System Bus Per-Channel

Control registers.

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.7 Seri al Interface

100054E Conexant 2-61

2.7 Serial Interface

The device provides a serial interface that allows the microprocessor to indirectly

communicate with an at tac hed LI U (such as t he Con e xan t CX283 80 Quad T1/E 1

LIU). This interface allows the microprocessor to control and query the LIU

status. One 8-bit register in the LIU can be written via the SERDO pin or read

from the SERDI pin at the clock rate determined by the SERCKO clock output.

The serial interface suppor ts a glueless interface to two quad LIUs by supplying

two independently controlled external chip select lines on the CX28398:

SERCS1* and SERCS2*. The CX28394 provides a single SERCS* chip select

line. On the CX28395, the serial interface is not accessable.

The serial interface uses a 16-bit process for each write or read operation.

During a write operation, a 16-bit word—consisting of [SER_CTRL; addr 022]

and [SER_DAT; addr 023]—is transmitted to the LIU. The SER_ CTL register

contains the LIU register address for the current operation and a read/write

contro l bi t. Du rin g a r ead operat ion , SER _C TL i s t ra nsmitt e d a nd 8 -b it d ata from

the LIU is received and placed in SER_DAT register. Writing to SER_CTL

initiates a serial interface read or write operation.

The Data regist er contains either write or read da ta. F or the write operat ion, its

content is written to the SERDO serial port on the eight SERCKO cycles

immediately following the Address/Command byte. Likewise, for the read

operation, data on the SERDI serial port is input immediately on the eight

SERCKO clock cycles following the Address/Command byte.

Figure 2-29 illustrates serial interface timing.

Figure 2-29. Serial Interface Timing Diagram

Read Timing

SERCS*

SERCLK

SERDO

SERDI

;

;;

;;;

R/W A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

Write Timing

;;;;;;

SERCS*

SERCLK

SERDO

SERDI

;

;;

R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7

2.0 Circuit Descrip tion CX28394/28395/28398

2.8 Joint Test Access Group Quad/x16/Octal—T1/E1/J1 Framers

2-62 Conexant 100054E

2.8 Joint Test Access Group

The device incorporates printed circuit board testability circuits in compliance

with IEEE Std. P1149.1a–1993, IEEE Standard Test Access Port and

Boundary–Scan Architecture, commonly known as JTAG (Joint Test Action

Group).

The JTAG includes a Test Access Port (TAP) and several data registers. The

TAP provides a standard interface through which instructions and test data are

communicated (see Figure 2-30). A Boundary Scan Description Language

(BSDL) file is available from Conexant upon request.

The test access port consists of TDI, TCK, TMS, TDO and TRST* pins.

2.8.1 Instructions

In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST

instructions, IDCODE instruction is supported. There is also one private

instruction. Table 2-8 lists the JTAG instructions along with their codes.

Figure 2-30. Test Access Port (TAP) Diagram

100054_003

TCK

TMS

TRST*

TDI

(CX28394, CX28398) TDO

JTAG Port

TDO1 (CX28395)

TDO2

Tab le 2-8. JTAG Instr uctions

Instruction Code

BYPASS 111

SAMPLE/PRELOAD 001

EXTEST 000

IDCODE 010

Private xxx

CX28394/28395/28398 2.0 Circuit Description

Quad/x16/Octal—T1/E1/J1 Framers 2.8 Join t Test Access Group

100054E Conexant 2-63

2.8.2 Device Identification Register

JTAG ID register consists of a 4-bit version, 16-bit part number, and 11-bit

manufacturer number (see Tables 2-11 and 2-9).

Table 2-9. CX28394 Device Identification JTAG Register

Version(1) Part Number Manufacturer ID

00001000001110010100000000100 1 1 1

0x0 0x8394 0X013

4 bits 16 bits 11 bi ts

NOTE(S):

(1) Consult factory for current version number.

TDO

Table 2-10. CX28395 Device Identification JTAG Register

Version(1) Part Number Manufacturer ID

00001000001110010101000000100 1 1 1

0x0 0x8395 0X013

4 bits 16 bits 11 bi ts

NOTE(S):

(1) Consult factory for current version number.

TDO1

TDO2

Table 2-11. CX28398 Device Identification JTAG Register

Version(1) Part Number Manufacturer ID

00001000001110011000000000100 1 1 1

0x0 0x8398 0X013

4 bits 16 bits 11 bi ts

NOTE(S):

(1) Consult factory for current version number.

TDO

2.0 Circuit Descrip tion CX28394/28395/28398

2.8 Joint Test Access Group Quad/x16/Octal—T1/E1/J1 Framers

2-64 Conexant 100054E

100054E Conexant 3-1

3.0 Registers

3.1 Address Map

Registers shown with a default setting are reset to the indicated value following power up, software RESET

(CRO; addr 001), GRESET (FCR; addr 080), or hardware reset (RST* pin).

Addresses 000 (hex) to 1FF (hex) are offset by the upper 3 bits of address lines A[11:0] and chip selects as

listed in Tables 3-1 through 3-3.

Tab le 3-1. Address Of fset Map (CX28394)

Framer Chip Select

CS*

Offset

Address A[10:0]

(hex)

10000

20200

30400

40600

NOTE(S):

1. Global registers at 000 and 080–083 may be accessed at any offsets.

Tab le 3-2. Address Of fset Map (CX28398)

Framer Chip Select

CS*

Offset

Address A[11:0]

(hex)

10000

20200

30400

40600

50800

60A00

70C00

80E00

NOTE(S):

1. Global registers at 000 and 080–083 may be accessed at any offsets.

3.0 Registers CX28394/28395/28398

3.1 Ad dress Map Quad/x16/Octal—T1/E1/J1 Framers

3-2 Conexant 100054E

Tab le 3-3. Address Of fset Map (CX28395)

Framer Chip Select Offset

Address A[11:0]

(hex)

CS1* CS2*

101000

201200

301400

401600

501800

601A00

701C00

801E00

910000

10 1 0 200

11 1 0 400

12 1 0 600

13 1 0 800

14 1 0 A00

15 1 0 C00

16 1 0 E00

NOTE(S):

1. Global registers at 000 and 080–083 for framers 1–8 may be accessed at any of th e fi rst 8 off sets.

2. Global registers at 000 and 080–083 for framers 9–16 may be accessed at any of the second 8 offsets.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.1 Address Map

100054E Conexant 3-3

Tab le 3-4. Address Map (1 of 5)

Block Address

(Hex) Acronym R/W Description Default

Setting (Hex)

Global

000 DID R Device Identification 28

080 FCR R/W Framer Control Register 00

081 MIR R Master Interrupt Request 00

082 MIE R/W Master Interrupt Enable 00

083 TEST R/W Test Configuration 00

Primary

Control

001 CR0 R/W Primary Control Register 00

003 IRR R Interrupt R equest Regi ster —

Interrupt Status

004 ISR7 R Alarm 1 Interrupt Status —

005 ISR6 R Alarm 2 Interrupt Status —

006 ISR5 R Error Interrupt Status —

007 ISR4 R Counter Overflow Interrupt Status —

008 ISR3 R Timer Interrupt Status —

009 ISR2 R Data Link 1 Interrupt Status —

00A IS R1 R Data Li nk 2 Int e rrupt Status —

00B ISR0 R Pattern Interrupt Status 00

Interrupt Enable

00C IER7 R/W Alarm 1 Interrupt Enable Register 00

00D IER6 R/W Alarm 2 Interrupt Enable Register 00

00E IER5 R/W Error Interru pt Enable Regis te r 0 0

00F IER4 R/W Count Overflow Int e rrupt Enable Register 00

010 IER3 R/W Timer Interr upt Enable Register 00

011 IER2 R/W Data Lin k 1 Inter ru pt Enable Reg ist e r 00

012 IER1 R/W Data Lin k 2 Inter ru pt Enable Reg ist e r 00

013 IER0 R/W Pattern Interrupt Enable Register 00

Primary

014 LOOP R/W Loopback Confi guratio n Register —

015 DL3_TS R/W External Data Link Channel —

016 DL3_BIT R/W External Data Link Bit —

017 FSTAT R Of fline Framer Status —

018 PIO R/W Programmable Input/Output 00

019 POE R/W Programmable Output Enable 3C

01A CMUX R/W Clock Input Mux 00

020 RAC R/W Receive Alarm Configurat ion —

021 RSTAT R/W Receive Line Code Status —

3.0 Registers CX28394/28395/28398

3.1 Ad dress Map Quad/x16/Octal—T1/E1/J1 Framers

3-4 Conexant 100054E

Serial Interface

022 SER_CTL R/W Serial Control —

023 SER_DAT R/W Serial Data —

024 SER_STAT R/W Serial Status —

025 SER_CONFIG R/W Serial Configuration 00

026 RAM TEST R/W Ram Test —

Digital Receiver (RCVR)

040 RCR0 R/W Receiver Configuration —

041 RPATT R/W Receive Test Pattern Configuration —

042 RLB R/W Receive Loopback Cod e Detector Con fi guration —

043 LBA R/W Loopba ck Activate Code Pattern —

044 LBD R/W Loopback D eactivate Cod e Pattern —

045 RALM R/W Receive Alarm Signal Co nfigurat ion —

046 LATCH R/W Alarm/Error/Counter Latch Configuration —

047 ALM1 R Alarm 1 Status —

048 ALM2 R Alarm 2 Status —

049 ALM3 R Alarm 3 Status —

Error/Alarm Counters

050 FERR R Framing Bit Error Counter LSB —

051 FERR R Framing Bit Error Counter MSB —

052 CERR R CRC Error Counter LSB —

053 CERR R CRC Error Counter MSB —

054 LCV R Line Code Viola tion Counter LSB —

055 LCV R Line Code Viola tion Counter MSB —

056 FEBE R Far End Block Error Counter LSB —

057 FEBE R Far End Block Error Counter MSB —

058 BERR R PRBS Bit Error Counter LSB —

059 BERR R PRBS Bit Error Counter MSB —

05A AERR R SEF/LOF/COFA Alarm Count —

Receive Sa-B yte

05B RSA4 R Receive Sa4 Byte Buf fer —

05C RSA5 R Receive Sa5 Byte Buf fer —

05D RSA6 R Receive Sa6 Byte Buf fer —

05E RSA7 R Rece ive Sa7 Byte Buffer —

05F RSA8 R Receive Sa8 Byte Buf fer —

Tab le 3-4. Address Map (2 of 5)

Block Address

(Hex) Acronym R/W Description Default

Setting (Hex)

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.1 Address Map

100054E Conexant 3-5

Digital Transmitter (XMTR)

070 TCR0 R/W Transmit Framer Configuration —

071 TCR1 R/W Transmitter Configuration —

072 TFRM R/W Transmit Frame Format —

073 TERROR R/W Transm it Erro r Insert 00

074 TMAN R/W Transmit Manual Sa-Byte/FEBE Configuration —

075 TALM R/W Transmit Alarm Signal Conf iguratio n —

076 TP ATT R/W Trans m it Test Patte r n Configuratio n —

077 TLB R/W Transmit Inband Loopbac k Code Configuration —

078 LBP R/W Transmit In-Band Loopback Code Pattern —

Transmit Sa-Byte

07B TSA4 R/W Transmit Sa 4 By te Buffer —

07C TSA5 R/W Transmit Sa 5 By te Buffer —

07D TSA6 R/W Trans mit Sa 6 By te Buffer —

07E TSA7 R/W Transm it Sa 7 By te Buffer —

07F TSA 8 R/W Tra nsm it Sa 8 By te Buffe r —

BOP

0A0 BOP R /W Bit Oriented Protocol Tr ansceiver 00

0A1 TBOP R/W Transmit BOP Code Word 00

0A2 RBOP R Receive BOP Code Word —

0A3 BOP_STAT R BOP Status —

Data Link #1

0A4 DL 1_TS R/W DL1 Time Slot Enable 00

0A5 DL1_BIT R/W DL1 Bit Enable 00

0A6 DL1_CTL R/W DL1 Control 00

0A7 RDL1_FFC R/W RDL #1 FIFO Fi ll Control 00

0A8 RDL1 R Receive Data Lin k FIFO #1 —

0A9 RDL1_STAT R RDL #1 Status —

0AA PRM R/W Performance Repo rt Message 00

0AB TD L1_FEC R/W TDL #1 FIFO Empty Control 00

0AC TDL1_EOM W TDL #1 End Of Message Con trol —

0AD T DL1 R/W Transmit Data Link FIFO #1 —

0AE TDL1_STAT R TDL #1 Stat us —

Tab le 3-4. Address Map (3 of 5)

Block Address

(Hex) Acronym R/W Description Default

Setting (Hex)

3.0 Registers CX28394/28395/28398

3.1 Ad dress Map Quad/x16/Octal—T1/E1/J1 Framers

3-6 Conexant 100054E

Data Link #2

0AF DL2_TS R/W DL2 Time-Slot Enable 00

0B0 DL2_BIT R/W DL2 Bit Enable 00

0B1 DL2_CTL R/W DL2 Control 00

0B2 RDL2_FFC R/W RDL #2 FIFO Fi ll Control 00

0B3 RDL2 R Receive Data Lin k FIFO #2 —

0B4 RDL2_STAT R RDL #2 Status —

0B6 TD L2_FEC R/W TDL #2 FIFO Empty Control 00

0B7 TDL2_EOM W TDL #2 End Of Message Con trol —

0B8 TDL2 R/W Transmi t Data Link FI FO #2 —

0B9 TDL2_STAT R TDL #2 S tatus —

Test

0BA DL_TEST1 R/W DL I NK Test Co nfigurat io n 00

0BB DL_TEST2 R/W DLINK Test Status 00

0BC DL_TEST3 R/W DLINK Test Status 00

0BD DL_TEST4 R/W DL INK Test Control #1 or Conf igu r a tio n #2 00

0BE DL_TEST 5 R/W DLINK Test Control #2 or Configu ra t io n #2 00

System Bus Int erfa ce (SBI)

0D0 SBI_CR R/W System Bus Interface Configuration 00

0D1 RSB_CR R/W Receive Sys tem Bus Configuration 00

0D2 RSYNC_BIT R/W Receive System Bus Sync Bit Offset —

0D3 RSYNC_TS R/W Receive System Bus Sync Time Slot Offset —

0D4 TS B_CR R/W Transmit System Bus Configuration 00

0D5 TSYNC_BIT R/W Transmit System Bus Sync Bit Offset —

0D6 TSYN C_TS R/W Tran smit System Bus Sync Time Slot Off set —

0D7 RSIG_CR R/W Receiv e Signaling Configuratio n —

0D8 RSYNC_FRM R/W Sig naling Reinsert ion Frame Offset —

0D9 SSTAT R Slip Buffer Status —

0DA S TACK R R eceive Si gnaling St ack —

0DB RPHASE R RSLIP Phase Statu s —

0DC TPHASE R TSLIP Phase Status —

0DD PERR R RAM Pa rity Status —

0E0–0FF SBCn:

n = 0 to 31 R/W System Bus Per-Channel Contro l —

Tab le 3-4. Address Map (4 of 5)

Block Address

(Hex) Acronym R/W Description Default

Setting (Hex)

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.1 Address Map

100054E Conexant 3-7

Buffer Me m ory

100–11F TPCn:

n = 0 to 31 R/W Transmit Per-Ch anne l Co ntro l —

120–13F TSIGn:

n = 0 to 31 R/W Transmit Signa l in g Buffer —

140–15F TSLIP_LOn:

n = 0 to 31 R/W Transmit PCM Slip Buffer —

160–17F TSLIP_HIn:

n = 0 to 31 R/W Transmit PCM Slip Buffer —

180–19F RPCn:

n = 0 to 31 R/W Receive Per-Channel Control —

1A0–1BF RSIGn:

n = 0 to 31 R/W Receive Signaling Buffer —

1C0–1DF RSLIP_LOn:

n = 0 to 31 R/W Receive PC M Sl ip Buffer —

1E0–1FF RSLIP_HIn:

n = 0 to 31 R/W Receive PC M Sl ip Buffer —

Tab le 3-4. Address Map (5 of 5)

Block Address

(Hex) Acronym R/W Description Default

Setting (Hex)

3.0 Registers CX28394/28395/28398

3.2 Global Control and Stat us Registers Quad/x16/Octal—T1/E1/J1 Framers

3-8 Conexant 100054E

3.2 Global Control and Status Registers

Global registers are applicable to all framers in the CX28394 and CX28398. There are two sets of global

registers for the CX28395, one for each 8-framer group.

000—Device Identification (DID)

Read only v al ue.

DID[7:4] Device Revision—A value of 0x4 indicates the current revision.

DID[3:0] Device ID—A value of 0x8 indicates the CX28398 or CX28395. A value of 0x4 indicates the

CX28394.

080—Framer Control Register (FCR)

Unused bits are reser ved and should be written to 0.

GRESET Global Reset —When written to 1 by the microprocessor, GRESET initiates an internal global

reset process which initializes all global control registers and certain control registers for all

framers to their default settings (see Table 3-4). The internal reset proc ess tak es a maxi mum of

15 µsec.

The processor must not write to the control registers until the reset process is complete.

GRESET remains active (1) during the reset process to allow the microprocessor to detect

reset completion. GRESET also indicates a reset operation triggered by power-up or by an

active low RST* pin. After GRESET initializatio n, the following is true:

• System bus outputs (RSIGO, RPCMO, and SIGFRZ) for all framers are three-stated.

• Programmable I/O pins are configured as inputs.

• Global control and framer control registers are set to their default values.

ONESEC_I O Bidirectional ONESEC Input/Output Mode—Selects input or output mode for ONESEC

signal pi n and controls the internal timer int erv al used for one-second stat us latching [L ATCH;

addr 046]. When ONESEC is an output, SYSCLK is used to develop the one-second timer

interval output with an arbitrarily defined initial starting location. When ONESEC is an input,

the timer/latch interval is aligned to rising edge of ONESEC input. The system can apply

ONESEC input to define any length timer/latch inter val up to 1 second, but not greater than 1

second.

0 = ONESEC input

1 = ONESEC output

7 6 5 4 3 2 1 0

DID[7] DID[6] DID[5] DID[4] DID[3] DID[2] DID[1] DID[0]

7 6 5 4 3 2 1 0

GRESET – – – – ONESEC_IO SBIMODE[1] SBIMODE[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.2 Global Control and Status Registers

100054E Conexant 3-9

SBIMODE[1:0] The processor writes FCR at power-up to configure the system bus interface mode. Each

group of four framers can be configured as separate system bus interfaces or as an internally

multiplexed group. The group consisting of framers 1 through 4 (9 through 12) can be

configured to share a common system bus interface, SBI Bus A. The group consisting of

framers 5 through 8 (13 through 16) can also be configured to share a common system bus

interface, SBI Bus B .

081—Master Interrupt Request (MIR)

CX28394

CX28398 and CX28395

MIR[7:0] An active MIR bit indica te s which fram er has active interrupt s . An MIR bit is latched active

(high) whenever any bit in the Interrupt Request Register (IRR[7:0]; addr 003–0B) is set to

report an interrupt event.

SBIMODE[1]: 0 = Separate system bus interface mode for framer group 5–8 (13–16).

1 = Common, multiplexed system bus interface mode.

SBIMODE[0]: 0 = Separate system bus interface mode for framer group 1–4 (9–12).

1 = Common, multiplexed system bus interface mode.

7 6 5 4 3 2 1 0

— — — — MIR[3] MIR[2] MIR[1] MIR[0]

7 6 5 4 3 2 1 0

MIR[7] MIR[6] MIR[5] MIR[4] MIR[3] MIR[2] MIR[1] MIR[0]

MIR0: 0 = no interrupt event in framer 0

1 = active interrup t event in framer 0

MIR1: 0 = no interrupt event in framer 1

1 = active interrup t event in framer 1

MIR2: 0 = no interrupt event in framer 2

1 = active interrup t event in framer 2

MIR3: 0 = no interrupt event in framer 3

1 = active interrup t event in framer 3

MIR4: 0 = no interrupt event in framer 4

1 = active interrup t event in framer 4

MIR5: 0 = no interrupt event in framer 5

1 = active interrup t event in framer 5

MIR6: 0 = no interrupt event in framer 6

1 = active interrup t event in framer 6

MIR7: 0 = no interrupt event in framer 7

1 = active interrup t event in framer 7

3.0 Registers CX28394/28395/28398

3.2 Global Control and Stat us Registers Quad/x16/Octal—T1/E1/J1 Framers

3-10 Conexant 100054E

082—Master Interrupt Enable (MIE)

CX28394

CX28398 and CX28395

MIE[7:0] MIE is a global interrupt enable for each framer. Writing a one to an MIE bit enables the

corresponding framer’s IRR bit to be latched in MIR (addr 081) and to activate the INTR*

output.

083—Test Configuration (TEST)

Unused bits are reser ved and should be written to 0.

TEST Global Test Enable—Reserved for Conexant production test.

7 6 5 4 3 2 1 0

— — — — MIE[3] MIE[2] MIE[1] MIE[0]

7 6 5 4 3 2 1 0

MIE[7] MIE[6] MIE[5] MIE[4] MIE[3] MIE[2] MIE[1] MIE[0]

MIE0: 0 = Disable framer 0 IRR int errupt

1 = Enable framer 0 IRR in terrupt

MIE1: 0 = Disable framer 1 IRR int errupt

1 = Enable framer 1 IRR in terrupt

MIE2: 0 = Disable framer 2 IRR int errupt

1 = Enable framer 2 IRR in terrupt

MIE3: 0 = Disable framer 3 IRR int errupt

1 = Enable framer 3 IRR in terrupt

MIE4: 0 = Disable framer 4 IRR int errupt

1 = Enable framer 4 IRR in terrupt

MIE5: 0 = Disable framer 5 IRR int errupt

1 = Enable framer 5 IRR in terrupt

MIE6: 0 = Disable framer 6 IRR int errupt

1 = Enable framer 6 IRR in terrupt

MIE7: 0 = Disable framer 7 IRR int errupt

1 = Enable framer 7 IRR in terrupt

7 6 5 4 3 2 1 0

——————TEST—

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.3 Primar y Control and Stat us Register

100054E Conexant 3-11

3.3 Primary Control and Status Register

001—Primary Control Register (CR0)

Unused bits are reser ved and should be written to 0.

RESET Framer Reset—Whe n wr itten to 1 by the microprocessor, RESET initiates an inter nal reset

process which initializes certain control registers to their default settin gs (see Table 3-4). The

internal reset process ta kes a maximum of 15 µsec.

The processor must not write to the control registers until the reset process is complete.

RESET remains active (1) during the reset process to allow the microprocessor to detect reset

completion. RESET also indicates a reset operation triggered by power-up, GRESET [FCR;

addr 080], or by an active low RST* pin. After RESE T initialization, the following is true:

• System bus outputs (RSIGO, RPCMO, and SIGFRZ) are three-stated.

• Programmable I/O pins are configured as inputs.

• Framer control registers are set to their default values.

RINCF Receiver Framer CRC6 include F-bit—Deter mines if the F-bit is included in the CRC6

remaind er calcul ati on in T1 mo de (T1 /E 1N = 1) . T his b it i s ig nor ed in E 1 mod e (T1 /E 1N = 0).

7 6 5 4 3 2 1 0

RESET — RINCF RFRAME[3] RFRAME[2] RFRAME[1] RFRAME[0] T1/E1N

0 = T1 ESF CRC6 calculation is performed on the

receive data including a 1 in place of the F-bit.

1 = TI ESF CRC6 tran sm it calculati on is performed on

receive data including the F-bit.

3.0 Registers CX28394/28395/28398

3.3 Primary Control and St atus Register Quad/x16/Octal—T1/E1/J1 Framers

3-12 Conexant 100054E

RFRAME[3:0] Receiver Framer Mode—Establishes the offline framer's search criteria for recovery of frame

alignment (reframe). Also works in conjunction with the RLOFA–RLOFD bits [addr 040] to

establish the online fram er's criteria fo r loss of frame al ignment. R efer to Tables A-1 through

A-6 to find which frame bits are monitored and Table 2-2, Criteria for Loss/Recovery of

Receive Framer A lignment, for frame alignment loss/recovery criteria during the selected

mode. Mode descriptions are given in Table 3-5. Online framer’s SF, SLC, CAS and MFAS

criteria for loss/recovery of multiframe alignment are also selected by RFRAME[3:0].

T1/E1N Global T1/E1 Select—Af fects all functions b y ena bling recei ve and t ransmit circuits to o perate

at either the T1 or E1 line rate. The pro cessor should reinitializ e all control regi ste r settings

after ch anging the T1/E1N control bit. T1/E1N selec ts the nomina l line rate (s hown below)

while the exact receive and transmit line rate frequencies are independently determined by

their respective input clock or input data references. The actual receive and transmit line

frequency can vary within defined tolerances.

0 = 2.048 MHz line rate (E1)

1 = 1.544 MHz line rate (T1)

Tab le 3-5. R eceive Frame r Modes

RFRAME[3:0] T1/E1N Receive Fram er Mode

000X 0 FAS Only

001X 0 FAS Only + BSLIP

010X 0 FAS + CRC

011X 0 FAS + CRC + BSLIP

100X 0 FAS + CAS

101X 0 FAS + CAS + BSLIP

110X 0 FAS + CRC + CAS

111X 0 FAS + CRC + CAS + BSLIP

0000 1 FT Only

0001 1 ESF + No CRC (FPS only)

0100 1 SF

0101 1 SF + JYEL

0110 1 SF + T1D M

1000 1 SLC + FSLOF

1001 1 SLC

1100 1 ESF + Mimic CRC

1101 1 ESF + Force C RC

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.4 Interrupt Control Regi ster

100054E Conexant 3-13

3.4 Interrupt Control Register

003—Interrupt Request Register (IRR)

An IRR bit is latched active (high) whenever an enabled interrupt source reports an interrupt event in the

corresponding Interrupt Status Register [ISR7–ISR0; addr 004–00B]. IRR is latched until the corresponding

ISR register is read by the processor. Reading ISR clears the respective IRR bit, independent of clearing ISR

bits. Therefore, persis tent ly active ISR bits won't affect INTR* deactivation. All IRR bits are l ogically OR'ed to

activate a corresponding MIR bit and INTR*, so the processor must read IRR = 00 before exiting its interrupt

service routine in order to confirm the MIR bit has been deasserted.

ALARM1 Alarm 1 Interrupt Request—Indicates one or more rece iv er errors. Processor reads ISR7 [addr

004] to locate specific source.

0 = no event

1 = active interrupt request

ALARM2 Alarm 2 Interrupt Request—Indicates one-second timer expiry, or detection of one or more

transmitter errors, or det ection of inb and lo opback co de word. Processor rea ds ISR6 [a ddr 00 5]

to locate specific source.

0 = no event

1 = active interrupt request

ERROR Error Interrupt—Indicates one or more errors detected by receive framer, RSLIP, or TSLIP

circuits. Processor reads ISR5 [addr 006] to locate specific source.

0 = no event

1 = active interrupt request

COUNT Counter Overflow Interrupt—Indicates one or more error counts [addr 050–05A] have issued

an overflow interrupt. Processor reads ISR4 [addr 007] to locate specific source.

0 = no event

1 = active interrupt request

TIMER Timer Interrupt Request—Indicates that the transmit, receive, or system bus timebase has

reached a frame count terminus or that the receive signaling stack [STACK; addr 0DA] has

been updated with ne w signaling during t he prior multiframe. Pr ocessor reads ISR3 [addr 008]

to locate specific source.

0 = no event

1 = active interrupt request

DL1 Data Link Controller 1 or BOP Transmit—Indicates that a transmit or receive interrupt issued

by DL1 or BOP transceiver has begun transmitting a priority codeword from TBOP

[addr 0A1]. Processor reads ISR2 [addr 009] to locate specific source.

0 = no event

1 = active interrupt request

7 6 5 4 3 2 1 0

ALARM1 ALARM2 ERROR COUNT TIMER DL1 DL2 PATT

3.0 Registers CX28394/28395/28398

3.4 Interrupt Control Register Quad/x16/Octal—T1/E1/J1 Framers

3-14 Conexant 100054E

DL2 Data Link Controller 2 or BOP Receive—Indicates that a transmit or receive interrupt issued

by DL2 or BOP transceiver has received a valid priority codeword and updated RBOP

[addr 0A2]. Processor reads ISR1 [addr 00A] to locate specific source.

0 = no event

1 = active interrupt request

PATT PRBS Pattern or Transmit Framer Error—Indicates detection of PRBS test patter n sync or

detection of one or more transmit frame alignment pattern errors. Processor reads ISR0

[addr 00B] to locate specific source.

0 = no event

1 = active interrupt request

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.5 Interrupt Status Registers

100054E Conexant 3-15

3.5 Interrupt Status Registers

An Interrupt Status Register (ISR) bit is latched active (high) whenever its corresponding interrupt source

reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt

enab le is acti v e (high), each interrupt e vent forces the associ ated IRR bit acti v e (high). Interrupt sources fall into

tw o categories:

• Rising-edge source reports an interr upt event when status changes from inactive to active state. Unless

specifically noted otherwise, all ISR bits are rising-edge sources.

• Dual-edge source repor ts an interrupt event when status changes from inactive to active (rising edge), or

from acti ve to inact i ve (falling ed ge). The pro cessor must read t he associated real -time status to d etermine

which edge occurred.

Interrupt events are rep orted in re al t im e in t he MIR r e gi st er a nd on t he IN TR* output pin if in terrupt enabl e

is active (high) . Otherwise, the interrupt status is la tched and re porte d according to the selected la tching mo de

[LATCH; addr 046] without asserting the MI R bit or th e INTR* out put pi n. Table 3-6 summarizes t he interrupt

status registers.

Tab le 3-6. Interrupt Status Regi s ter Summary

Bit 004

ISR7

ALARM1

005

ISR6

ALARM2

006

ISR5

ERROR

007

ISR4

COUNT

008

ISR3

TIMER

009

ISR2

DL1

00A

ISR1

DL2

00B

ISR0

PATT

0 SIGFRZ ONESEC FERR FERR[12] RFRAME TMSG TMSG TFERR

1 RLOF TLOF MERR CRC[10] RMF TNEAR TNEAR TMERR

2 RLOS — SERR LCV[16] RMSYNC TEMPTY TEMPTY TSERR

3 RALOS TLOC CERR FEBE[10] RSIG TDLERR TDLERR TCERR

4 RAIS — — BERR[12] TFRAME RMSG RMSG PSYNC

5 RPDV TPDV — SEF[2] TMF RNEAR RNEAR BSLIP

6 RYEL LOOPUP RSLIP COFA[2] TMSYNC RFULL RFULL —

7 RMYEL LOOPDN TSLIP FRED[4] TSIG TBOP RBOP —

3.0 Registers CX28394/28395/28398

3.5 Interrupt Status Registers Quad/x16/Octal—T1/E1/J1 Framers

3-16 Conexant 100054E

004—Alarm 1 Interrupt Status (ISR7)

All events reported in ISR7 are from dual-edge sources, except Receive Pulse Density Violation [RPDV]. Any

transit ion of real-time sta tus in Alarm 1 Status Re gister [ALM1; addr 047] forces the corresponding ISR7 sta tus

bit active (high). Active high status is latched and held according to the LATCH_ALM bit [addr 046]. Each

event triggers an interrupt if the corresponding IER7 bit is enabled [addr 00C].

RMYEL Loss/Recovery of Multiframe Yellow Alar m—Reports any change in real-time status of

Multiframe Yellow (E1) or ESF Yellow (T1) alarm detector.

0 = no event

1 = multiframe yellow alarm transition

RYEL Loss/Recovery of Yellow Alar m—Reports any change in real-time status of Remote Alarm

Indication (RAI), also referred to as yellow alarm.

0 = no event

1 = yellow alarm transition

RPDV Receive Pulse Density Violation—Reports each occurrence of a receive pulse density

violation according to ANSI T1.403 sliding window criteria. RPDV is latched active upon

detec tion of an y window of 8 (N+1) bits w hic h does not contai n at least N pul ses. F or exampl e,

RPDV reports each occur rence of 16 consecutive zeros.

0 = no error

1 = receive pulse density violation

RAIS Loss/Rec overy of Alarm Indication Signal—Reports any chang e in real-time status of the AIS

detector.

0 = no event

1 = AIS transition

RALOS Loss/Recovery of Receive Signal or Clock—Reports any change in RALOS [ALM1;

addr 047] status. RALOS can be configur ed to report recei ve loss of cl ock or a continuou s loss

of signal for 1 msec.

RLOS Loss/Recovery of Receive Signal—Reports any change in real-time status of digital receive

signal detector.

0 = no event

1 = receive signal transition

RLOF Loss/Recovery of Frame Alignment—Reports any change in real-time or integr ated status of

receive onli ne frame status monitor.

0 = no event

1 = receive frame status transition

SIGFRZ Loss/Recovery of Signaling Freeze—Reports any change in real-time status of the SIGFRZ

receiver status, which is also available on the SIGFRZ output pin.

0 = no event

1 = SIGFRZ transition

7 6 5 4 3 2 1 0

RMYEL RYEL RPDV RAIS RALOS RLOS RLOF SIGFRZ

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.5 Interrupt Status Registers

100054E Conexant 3-17

005—Alarm 2 Interrupt Status (ISR6)

All events reported in ISR6 are from dual-edge sources, except the one-second timer [ONESEC] and Transmit

Pulse Density Violation [TPDV]. Any transition of real-time status in the Alarm 2 Status Register [ALM2;

addr 048] forces the corresponding ISR6 status bit active (high). Active-high status is latched and held

accordi ng t o the LATCH_ALM bit [addr 046]. Each e vent tri gger s an interrupt if th e corresponding IER6 bi t i s

enabled [addr 00D].

LOOPDN Loss/Recovery of Inband Loopback Deactivate Code—Reports any change in real-time status

of inband loopback deactivate code detector.

0 = no event

1 = LOOPDN code transition

LOOPUP Loss/Recovery of Inband Loop back Acti vate Code —Reports any chan ge in real-time status of

inband loopback activate code detector.

0 = no event

1 = LOOPUP code transition

TPDV Transmit PDV Monitor/Enforcer—Applicable only if TZCS [addr 071] enables PDV

enforcement. When enabled, TPDV is latched active if one or more PDV-enforced ones were

output in order to meet ANSI T1.403 minimum pulse density requirements.

0 = no error

1 = PDV-enforced one

TLOC Loss/Recovery of Transmit Clock—Reports any change in real-time status of TCKI clock

monitor.

0 = No alarm

1 = cloc k monitor transition

TLOF Loss/Recovery of Transmit Frame Alignment—Reports any change in real-time status of

transmit framer's basic alignment.

0 = no alarm

1 = transmit framer transition

ONESEC One Second Ti mer Event—ONESEC is derived from the internal 1-second timer or the rising

edge of ONESEC input signal according to the selected I/O mode [PIO; addr 018].

0 = no timer event

1 = ONESEC timer expired or rising edge of ONESEC input

7 6 5 4 3 2 1 0

LOOPDN LOOPUP TPDV — TLOC — TLOF ONESEC

3.0 Registers CX28394/28395/28398

3.5 Interrupt Status Registers Quad/x16/Octal—T1/E1/J1 Framers

3-18 Conexant 100054E

006—Error Interrupt Status (ISR5)

All events in ISR5 are from rising edge sources. Each event is latched active high and held according to the

LATCH_ERR bit [addr 046] and triggers an interrupt if the corresponding IER5 bit is enabled [addr 00E].

TSLIP Transmit Slip Error—Two types of TSLIP buffer errors are reported: TFSLIP or TUSLIP.

Error type is reported separately in slip status [SSTAT; 0D9].

0 = no error

1 = TSLIP error

RSLIP Recei v e Slip Error—Two typ es of RSLIP buffer errors are reported: RFSLIP or R USLIP. Error

type is reported separately in slip status [SSTAT; 0D9].

0 = no error

1 = RSLIP error

CERR CRC6/CRC4 Block Error—Applicable to ESF and MFAS modes only, read zero in other

modes. CERR indicates one or more bit errors found in received CRC-6 or CRC-4 checksum

block pattern.

0 = no error

1 = CRC error

SERR CAS Patter n Error—Applicable only in E1 mode, read zero in T1 mode. SERR indicates one

or more bit errors in received TS16 Multiframe Alignment Signal (MAS).

0 = no error

1 = CAS error

MERR MFAS Pattern Error—Applicable only in E1 mode (read zero in T1 mode)—Indicates one or

more bit errors in received MFAS alignment patter n .

0 = no error

1 = MFAS error

FERR Frame Error—Ft/Fs/T1DM/FPS/FAS Pattern Error—Indicates one or more Ft/Fs/F PS frame

bit errors or FAS p attern errors. Refer to Tables A-1 through A-6 for a description of which

frame bits are monitored according to the selected receive framer mode.

0 = no error

1 = frame er ro r

7 6 5 4 3 2 1 0

TSLIP RSLIP — — CERR SERR MERR FERR

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.5 Interrupt Status Registers

100054E Conexant 3-19

007—Counter Overflow Interrupt Status (ISR4)

All count overflow events in ISR4 are from rising edge sources. Each event is latched active high when the

respective err or counte r [addr 050–05A] reaches its maximum count value, but only while the respective IER4

[addr 00F] interrupt enable bit is active. If the corresponding interrupt is masked, then no overflow status is

reported. Active overflow status bits are held until the processor read clears ISR4. Each event triggers an

interrupt if the corr esponding IER4 bit is enabled.

FRED[4] Out of Frame Error Count Overflow

COFA[2] Change of Alignment Count Overflow

SEF[2] Severely Errored Frame Count Overflow

BERR[12 ] Test Pattern Bit Error Count Overflow

FEBE[10] FEBE Error Cou nt O verflow

LCV[16] LCV (BPV+EXZ) Error Count Overflow

CRC[10] CRC6/CRC4 Error Count O verflow

FERR[12] Ft/Fs/FPS/FAS Error Count Overflow

008—Timer Interrupt Status (ISR3)

All events in ISR3 are from rising edge sources. Each event is latched active high and held until the processor

read clears ISR3. Each event triggers an interrupt if corresponding IER3 bit is enabled [addr 010].

TSIG Transmit Signaling Multiframe—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms

(CAS) coincident w ith the first bi t of a transmit signaling multiframe.

0 = no timer event

1 = transm it signaling multifra me

TMSYNC TX System Bus MF Sync—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (CAS)

coincident with the first bit of transmit system bus multiframe input on TPCMI.

0 = no timer event

1 = TSB multiframe

TMF T ransmi t Multif rame—TMF is act ivated ev ery 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms (MFAS)

coincident with the first bit of a transmit multiframe.

0 = no timer event

1 = transmit multiframe

TFRAME Transmit Frame—Activated every 193 bits (T1) or 256 bits (E1) coincident with first bit of a

transmit frame. Processor may read TPHASE [addr ODC] to determine which TSLIP buffer

half can be accessed.

0 = no timer event

1 = transmit frame

7 6 5 4 3 2 1 0

FRED[4] COFA[2] SEF[2] BERR[12] FEBE[10] LCV[16] CRC[10] FERR[12]

7 6 5 4 3 2 1 0

TSIG TMSYNC TMF TFRAME RSIG RMSYNC RMF RFRAME

3.0 Registers CX28394/28395/28398

3.5 Interrupt Status Registers Quad/x16/Octal—T1/E1/J1 Framers

3-20 Conexant 100054E

RSIG Receive Signaling Stack—Indicates that one or more signaling bit changes were detected

during the prior receive multiframe, and that new ABCD (robbed bit or CAS) signaling is

available on the Receive Signaling Stack Register [addr 0DA]. RSIG is cleared by processor

read of ISR3, independent of STACK contents.

0 = no stack update

1 = new ABCD signaling

RMSYNC Receive System Bus MF Sync—Activated every 3 ms (SF/SLC/ESF), or 2 ms (CAS)

coincident with the first bit of receive system bus multiframe output on RPCMO.

0 = no timer event

1 = RSB mult iframe

RMF Receive Multiframe Boundary—RMF is activated every 1.5 ms (SF/SLC), 3 ms (ESF), or

2 ms (MFAS ) coincident with the first bit of a received mu ltiframe. If MAS is not included in

the receive framer criteria, then RMF is activated at 2 ms interval.

0 = no timer event

1 = receive multiframe

RFRAME Receive Frame Boundary—Activated every 193 bits (T1) or 256 bits (E1) coincident with the

first bit of a received frame. Processor m ay read RPHASE [addr 0DB] to determine which

RSLIP buffer half can be accessed.

0 = no timer event

1 = receive frame

009—Data Link 1 Interru pt Status (ISR2 )

All events in ISR2 are from rising edge sources. Each event is latched active high and held until the processor

read clears ISR2. Each event triggers an interrupt if the corresponding IER2 bit is enabled [addr 011].

TBOP BOP Codeword Transmitted—Set when a valid Bit Oriented Codeword has been tra nsmitted

and a new TBOP value can be written [TBOP; addr 0A1].

RFULL1 Receive FIFO Full—In HDLC mo d es, RFULL is set when the data lin k receiver attempts to

write received data to a full FIFO causing the receive data link FIFO to overrun. In

unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the

MSG_FILL Limit selected in register RDL1_FFC [addr 0A7].

RNEAR1 Receive FIFO Near Full—Set when the receive FIFO fill level reaches the near full threshold

selected in re gi st er RDL1_F FC [addr 0A7].

RMSG1 Message Received—Set when a complete message or a partial message is received and

available in the receiver FIFO.

TDLERR 1 T rans mi t FIFO Error—Set when the FIFO underr u ns as a result of the inter nal logic emptying

the FIFO without encountering an end of message [TDL1_EOM; addr 0AC]. The underrun

condition also forces transmission of an HDLC abort code.

TEMPTY1 Transmit FIFO Empty—Set when the FIFO overflo ws as a result of the processor at tempting to

write to a full FIFO. Overflow data is ignored by the transmit FIF O.

TNEAR1 Transmit FIFO Near Empty —Set when the transm it FIFO level falls below the threshold

selected in re gi st er TDL1_FE C [addr 0AB].

TMSG1 Message T ransmitted—Set wh en a complete message ha s been transmit ted and the closin g flag

is just beginn ing transmission.

7 6 5 4 3 2 1 0

TBOP RFULL1 RNEAR1 RMSG1 TDLERR1 TEMPTY1 TNEAR1 TMSG1

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.5 Interrupt Status Registers

100054E Conexant 3-21

00A—Data Link 2 Interrupt Status (ISR1)

All events in ISR1 are from rising edge sources. Each event is latched active high and held until the processor

read clears ISR1. Each event triggers an interrupt if the corresponding IER1 bit is enabled [addr 012].

RBOP BOP Codeword Received—Set when a valid Bit Oriented Codeword is received and available

in the RBOP regi ste r [addr 0 A2].

RFULL2 Receive FIFO Full—In HDLC mo d es, RFULL is set when the data lin k receiver attempts to

write received data to a full FIFO causing the receive data link FIFO to overrun. In

unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the

MSG_FILL limit selected in register RDL2_FFC [addr 0B2].

RNEAR2 Receive FIFO Near Full—Set when the receive FIFO fill level reaches the near full threshold

selected in re gi st er RDL2_FFC [addr 0B2].

RMSG2 Message Received—Set when a complete message or a partial message is received and

available in the receiver FIFO.

TDLERR 2 T rans mi t FIFO Error—Set when the FIFO underr u ns as a result of the inter nal logic emptying

the FIFO without encountering an end of message [TDL2_EOM; addr 0B7]. The underrun

condition also forces transmission of an HDLC abort code.

TEMPTY2 Transmit FIFO Empty—Set when the FIFO overflo ws as a result of the processor at tempting to

write to a full FIFO. Overflow data is ignored by the transmit FIF O.

TNEAR2 Transmit FIFO Near Empty—Set when the transmit FI FO level falls below the threshold

selected in re gi st er TDL2_FE C [addr 0B6].

TMSG2 Message T ransmitted—Set wh en a complete message ha s been transmit ted and the closin g flag

is just beginn ing transmission.

7 6 5 4 3 2 1 0

RBOP RFULL2 RNEAR2 RMSG2 TDLERR2 TEMPTY2 TNEAR2 TMSG2

3.0 Registers CX28394/28395/28398

3.5 Interrupt Status Registers Quad/x16/Octal—T1/E1/J1 Framers

3-22 Conexant 100054E

00B—Patt ern Inter ru pt Statu s (ISR0 )

All events in ISR0 are from rising edge sources. Each event is latched active high and held until the processor

read clears ISR0. Each event triggers an interrupt if the corresponding IER0 bit is enabled [addr 013].

BSLIP Online Framer Bit Slip—Active high, indicates receive online framer adjusted receive frame

sync by ±1 bit. When BSLIP occurs, the apparent FAS error is not reported elsewhere (not to

FERR count, RLOF circuit, or SEF circuit). Applicable only to receive framer modes with

BSLIP enabled (see Table 3-5).

0 = no error

1 = frame bit slip

PSYNC Recei ve PRBS Test Pattern Sync—Forced to inactive (low) status when the processor request s

RESEED [addr 041] of the PRBS sync detector and remains low while the detector searches

for test pat te rn sync. PRBS bi t errors [BERR; addr 058, 059] are not cou nt ed while P SYNC is

low. PSYNC remai ns low for a minimum of 1 28 bits foll o wi ng RESE ED and for as lo ng a s the

received bit error ratio (BER) exceeds 10E-2. PSYNC is latched active (high) and the PRBS

sync detector stops searching when no bit errors are found for a period of 96 bits. The sync

detector remains disabled until the processor requests another RESEED. Therefore, any range

of BER can be measured after initial pattern sync. The processor must determine criteria for

loss of pattern sync based on its accumulation of bit errors over the desired time interval.

0 = no sync

1 = PRBS test pattern sync

TCERR Transmit CRC Er ror—Reports occurrences of CRC-6 or CRC-4 errors detected on TPCMI

data according to the selected T1/E1 mode.

0 = no error

1 = CRC error

TSERR Transmit CAS Error—Reports occurrences of MAS pattern errors detected on TPCMI data if

CAS transmit framer mode is selected.

0 = no error

1 = CAS error

TMERR Transmit Multiframe Error—Reports occurrences of Fs or MFAS errors detected on TPCMI

data according to the selected transmit framer mode.

0 = no error

1 = transmit multiframe e rror

TFERR Transmit Frame Error—Reports occurrences of Ft, FPS, or FAS errors detected on TPCMI

data according to the selected transmit framer mode.

0 = no error

1 = transmit frame error

7 6 5 4 3 2 1 0

— — BSLIP PSYNC TCERR TSERR TMERR TFERR

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.6 Interrupt Enable Registers

100054E Conexant 3-23

3.6 Interrupt Enable Registers

Writing a one to an IER bit all ows that specific interrupt source to activ a te it s respectiv e ISR bit, t he associat ed

MIR bit. While cleared, each IER bit al l ows that source to acti vate its respective ISR bit , but prevents acti vation

of the MIR bit.

00C—Alarm 1 Interrupt Enable Register (IER7)

RMYEL Enable RMYEL In terrupt

RYEL Enable RYEL Interrupt

RPDV Enable RPDV In terr upt

RAIS Enable RAIS Interrupt

RALOS Enable RALOS Interrupt

RLOS Enable RLOS Interrupt

RLOF Enable RLOF Interr upt

SIGFRZ Enable SIGFRZ Interrupt

00D—Alarm 2 Interrupt Enable Register (IER6)

Unused bits are reser ved and should be written to 0.

LOOPDN Enable LOOPDN Interru pt

LOOPUP Enable LOOPUP Interrupt

TPDV Enable TPDV Interrupt

TLOC Enable TLOC Interrupt

TLOF Enable TLOF Inte rrupt

ONESEC Ena ble ONESEC Interrupt

7 6 5 4 3 2 1 0

RMYEL RYEL RPDV RAIS RALOS RLOS RLOF SIGFRZ

7 6 5 4 3 2 1 0

LOOPDN LOOPUP TPDV — TLOC — TLOF ONESEC

3.0 Registers CX28394/28395/28398

3.6 Interrupt Enable Registers Quad/x16/Octal—T1/E1/J1 Framers

3-24 Conexant 100054E

00E—Error Interrupt Enable Register (IER5)

Unused bits are reser ved and should be written to 0.

TSLIP Enable TSLI P Interrupt

RSLIP Enable RSLIP Interrupt

CERR Enable CERR Interru pt

SERR Enable SERR Interrupt

MERR Enable MERR Interrupt

FERR Enable FERR Interrupt

00F—Count Overflow Interrupt Enable Register (IER4)

LOF Enable LOF Count Overflow Interrupt

COF A Enable COFA Count Overflow Interrupt

SEF Enable SEF Count Overflow Interrupt

BERR Enable BERR Count Overflow Interrupt

FEBE Enable FEBE Count Overflow In terrupt

LCV Enable LCV Count Overflow Interrupt

CRC Enable CRC Cou nt Overflow Interrupt

FERR Ena ble FERR Count Overflow Interrupt

7 6 5 4 3 2 1 0

TSLIP RSLIP — — CERR SERR MERR FERR

7 6 5 4 3 2 1 0

LOF COFA SEF BERR FEBE LCV CRC FERR

Tab le 3-7. Counter Overf low Behavior

IER4 LATCH_CNT Count (addr 050–05A) MIR*

Addr 00F Addr 046 Saturate Latch Clear Active

0 0 Hold al l One s hi @ rd_ LSB hi @rd_M SB None

1 0 Rollover hi @rd_LS B hi @rd_MSB @rollove r

0 1 Hold all Ones onesec None None

1 1 Rollover onesec none @rollover

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.6 Interrupt Enable Registers

100054E Conexant 3-25

010—Timer Interrupt Enable Register (IER3)

TSIG Enable TSIG Interrupt

TMSYNC Enable TMSYNC Interru pt

TMF Enable TMF Interr upt

TFRAME En able TFRAME Interrup t

RSIG Enable RSIG Interr upt

RMSYNC En able RMSYNC Interrupt

RMF Enable RMF Interrupt

RFRAME En able RFRAME Int e rrupt

011—Data Link 1 Interrupt Enable Register (IER2)

TBOP Ena ble TBOP Interrupt

RFULL1 Enable RFULL Interrupt

RNEAR1 Enable RNEAR Interru pt

RMSG1 Enable RMSG Inter rupt

TDLERR 1 Enable TDLERR Interrupt

TEMPTY1 Enable TEMPTY In terrup t

TNEAR1 Enable TNEAR In terrupt

TMSG1 Enable TMSG Interru pt

7 6 5 4 3 2 1 0

TSIG TMSYNC TMF TFRAME RSIG RMSYNC RMF RFRAME

7 6 5 4 3 2 1 0

TBOP RFULL1 RNEAR1 RMSG1 TDLERR1 TEMPTY1 TNEAR1 TMSG1

3.0 Registers CX28394/28395/28398

3.6 Interrupt Enable Registers Quad/x16/Octal—T1/E1/J1 Framers

3-26 Conexant 100054E

012—Data Link 2 Interrupt Enable Register (IER1)

RBOP Enable RBOP Interrupt

RFULL2 Enable RFULL Interrupt

RNEAR2 Enable RNEAR Interru pt

RMSG2 Enable RMSG Interrupt

TDLERR2 Enable TDLERR Interrupt

TEMPTY2 Enable TEMPTY In terrup t

TNEAR2 Ena ble TNEA R Interrupt

TMSG2 Enable TMSG Interrupt

013—Pattern Interrupt Enable Register (IER0)

Unused bits are reser ved and should be written to 0.

BSLIP Ena ble BSLIP Interrupt

PSYNC Enable PSYNC Interrupt

TCERR En able TCERR Interrupt

TSERR En able TSERR Interrupt

TMERR Enable TMERR Interrupt

TFERR Enable TFERR In terr upt

7 6 5 4 3 2 1 0

RBOP RFULL2 RNEAR2 RMSG2 TDLERR2 TEMPTY2 TNEAR2 TMSG2

7 6 5 4 3 2 1 0

— — BSLIP PSYNC TCERR TSERR TMERR TFERR

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.7 Pr imary Cont rol and St atus Registers

100054E Conexant 3-27

3.7 Primary Control and Status Registers

014—Loopback Configuration Register (LOOP)

Unused bits are reser ved and should be written to 0.

PLOOP Enable Remote Payload Loopback—Payload from receiver replaces payload on transmitter

output. Loopback payload retains time slot and frame integrity, such that numbered time slots

from each recei v e frame are t ransferred to the same numbered time slots in the transmit frame.

Transmit overhead bits, Fbits in T1 mode or TS0 in E1 mode, are supplied by transmit frame

formatter or by tran smit system bus according to TFR M [addr 072] set ting s. Existi ng transmi t

frame alignment and clock timing is not altered by PLOOP activation or deactivation, thus

allowing system operation with independent receive and transmit timing. Controlled frame

slips are performed in the payload loopback path if receive and transmit clocks are

asynchronous, although these slips are not reported to the processor as slip buffer errors.

Multiframe integrity is not maintained during PLOOP. This means that DS0 channel loopbacks

[TPCn; addr 100–11F] must be used to implement payload loopbacks when transparent or

forced signaling is desired. Note that TIDLE (in TPCn) overrides PLOOP.

0 = no loopback

1 = payload loopback

LLOOP Enable Remote Line Loopback—Received dual-rail unipolar data (RPOSI, RNEGI) is

internally connected to transmit dual-rail unipolar data (TPOSO, TNEGO). The receive clock

must also be looped when LLOP is selected in CMUX [addr 01A]; TXCLK must be set to 01

to select RCKI as the transmit clock. Loopback data retains BPV transparency. Data input

from transmit system bus continues to pass through the transmitter, but is ignored at ZCS

encoder out puts. Received da ta to RSB bloc k i s u naffected. LLOOP and FLOOP can be act ive

simultaneously to support both line and network loopbacks at the same time.

0 = no loopback

1 = line loopback

FLOOP Enable Local Framer Loopback—Dual-rail unipolar data from transmit ZCS encoder is

internally connected to receive ZCS decoder inputs. Clock switching is automatic during

FLOOP loopback mode.

0 = no loopback

1 = framer loopback

7 6 5 4 3 2 1 0

————PLOOPLLOOPFLOOP—

3.0 Registers CX28394/28395/28398

3.7 Primary Control and St atus Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-28 Conexant 100054E

015—External Data Link Time Slot (DL3_TS)

DL3_TS works in conjunct ion with t he DL3_BIT R egister [addr 016] to determine w hich tr ansmit time slots are

supplied from the TDLI pins and which receive and transmit time slots are accompanied by a gated RDLCKO

and TDLCKO output. Refer to Figure 2-21, Transmit External Data Link Waveforms. Note that RDLO outputs

the entire receive data bit stream, and only selective time slots are marked by RDLCKO. DL3 is not accessible

on the CX28395 device, therefore, DL3_TS must be written to 00.

CX28394, CX28398

CX28395

DL3EN Enable External Data Link—Active high enables data inser tion from TDLI and clock gating

on TDLCKO and RDLCKO outputs according to the selected external data link mode. PIO

[addr 018] must select TDL_IO and/or RDL_IO to enable external data link signals.

0 = external data link pins inactive

1 = TDLI/TDLC KO and RDLO/RDLCKO active

ODD/EVEN Odd/Even Frame Select—The external data link is prog rammed to source and sink data bits

during all frames or odd or even frames only. ODD/EVEN also controls gating of RDLCKO

and TDLC KO external dat a link c locks. F rames are counted f rom 0 thr ough 15 in E1 mode and

1 through 24 in T1 mode, where frames 1, 3, 5 etc., are always considered ODD frames.

ODD/EVEN is ignored if T1 Fbits are selected in DL3_TS.

TS[4:0] External Data Link Time Slot Select—Picks one 8-bit time slot for input and output over the

external data link pins. Any time slot can be chosen from TS0 to TS31 in E1 mode, or TS1 to

TS24 in T1 mode. In T1 mode, TS0 selects Fbits instead of a channel time slot.

7 6 5 4 3 2 1 0

DL3EN ODD EVEN TS[4] TS[3] TS[2] TS[1] TS[0]

7 6 5 4 3 2 1 0

00000000

ODD EVEN Frame Select

0 0 None. Equivalent to disabling external data link.

0 1 Ev en frames only. Frame 0, 2, 4, 6, etc.

1 0 Odd frames on ly. Frame 1, 3, 5, 7, etc.

1 1 All f ram es

00000 T1 Fbits or E1 Time Slot 0

00001 Time Slot 1

| |

11110 Time Slot 30

11111 Time Slot 31

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.7 Pr imary Cont rol and St atus Registers

100054E Conexant 3-29

016—External Data Link Bit (DL3_BIT)

DL3_BIT[7:0] External Data Link Bit Select—Enables receive (RDLCKO) and transmit (TDLCKO) clock

pulse outp uts during the sel ected time slot bit s. DL3_BIT and the DL3_TS Register [addr 015]

select any combination of bits fo r input and out put on the e xternal data link pins b y writ ing the

corresponding DL3_BIT active (high). LSB enables clock pulses coincident with the first bit

transmitted or recei ved. Ful l T1/E 1 dat a st ream is output on RDLO as long as t he R DL_IO bi t

[addr 018] is active and regardless of which bits are accompanied by RDLCKO clock pulses.

The selected transmit data link bits are sampled from the TDLI pin on the falling edge of

TDLCKO to replace normal transmitted data. DL3_BIT has no effect when DL3_TS selects

T1 Fbits or when the DL3EN bit is inactive. DL3 is not accessible on the CX28395 device.

0 = disable DL3 bit

1 = enable DL3 bit

017—Offline Framer Status (FSTAT)

Each framer contains a single offline framer that acts as a shared resource for both receive and transmit

channels. Current alignment status for receive and transmit channels are reported separately in Alarm Status

Registers (ALM1, ALM2; addr 047, 048). FSTAT is thus used primarily for diagnostic purposes to monitor the

prog ress of an alignment search or to verify acknowledgment of a processor-generated forced reframe request.

These status bits may only be repor ted for a very short period of time (i.e., 1 clock cycle) since the RLOF and

TLOF reframe requests may immediately request another offline framer search.

INVALID No Candidate—Active high at the conclusion of a search during which no frame alignment

candidates were located.

0 = search active, aborted, timed out, or found

1 = alignment not found (no candidate)

FOUND Frame Search Successful—Active high indicates the offline framer located frame alignment

according to the selected receive or transmit framer mode. Refer to Table 3-8 for Maximum

Average Reframe Time. Upon detection of frame alignment, the following occurs: FOUND

goes active high, RLOF or TLOF is cleared by the online framer (depending on RX/TX

direction), offline framer goes inactive (if no pending reframe requests), and RX, TX, or TSB

timebase is realigned (depending on RX/TX direction and the embedd ed framing mode). If the

reframe pulse causes the receive timebase to align to a position that differs from its existing

alignment, the change of frame alignment error counter [COFA; addr 05A] will increment.

Changes of the transmit frame alignment are not detected.

0 = no candidate: search active, aborted, or timed out

1 = frame alignment found (one and only one candidate)

NOTE: In E1 receive framer modes, th e offline f ra mer also reports interme diate FRED,

MRED, and SRED status [ALM3; addr 049] while searching for FAS/MFAS/CAS

alignment, respectively.

7 6 5 4 3 2 1 0

DL3_BIT[7] DL3_BIT[6] DL3_BIT[5] DL3_BIT[4] DL3_BIT[3] DL3_BIT[2] DL3_BIT[1] DL3_BIT[0]

7 6 5 4 3 2 1 0

— — — INVALID FOUND TIMEOUT ACTIVE RX/TXN

3.0 Registers CX28394/28395/28398

3.7 Primary Control and St atus Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-30 Conexant 100054E

TIMEO UT Framer Search Timeout—Cleared when the offline framer transitions to its ACTIVE state. If

multiple frame candidates exist over the entire mode-dependent timeout interval (refer to

Table 3-8), TIME OUT is lat ched act i v e hi gh. Processo r -gener ated refr ame re quests (RFOR CE

or TFORC E) in itiate a singl e s earc h that extends for up to 24 ms before TIMEOUT. After

reporting TIMEOUT, the offline framer starts another search if the reframe request (RLOF or

TLOF) is active.

0 = no candidate; search active, abor ted, or found

1 = framer search timeout (multiple candidates)

ACTIVE Framer Active—Offline framer transitions to its ACTIVE state in response to RFORCE or

TFORCE reframe request from the processor or in response to RLOF or TLOF reframe

request from an online framer. Offline framer remains ACTIVE until alignment is found

(FOUND), search is aborted [see RABORT, addr 040; or TABORT, addr 071], search reaches

its timeout interval (TIMEOUT), or all possible frame cand idates are eliminated (INVALID).

0 = offline framer inactive; search completed, aborted or timed out

1 = offline framer actively searching for alignment

NOTE: RFORCE or TFORCE don’t change current RLOF or TLOF status. RFORCE or

TFORCE is cleared by framer transition to ACTIVE.

RX/TXN RX/TX Reframe Operation—Indicates which direct ion the of fline framer is acti v ely searching

or most recentl y sea rched for frame alignment. RX/TXN status i s updated w hen of fline framer

transitions to its ACTIVE state in response to a reframe request.

0 = search data from Transmit System Bus PCM Input (TPCMI)

1 = search data from receive line interface unit

Table 3-8. Maximum Average Reframe Time (MART) and Framer Timeout

Framer Mode MART TIMEOUT (addr 017)

Ft 3.5 ms 12 ms ±1 bit

Ft + T1DM 1.0 ms 12 ms ±1 bit

SF 3.5 ms 12 ms ±1 bit

SF + JYEL 4.5 ms 12 ms ±1 bit

SF + TIDM 2.0 ms 12 ms ±1 bit

SLC 15.0 ms 24 ms ±1 bit

ESF 10.0 ms 24 ms ±1 bit

ESF + CRC 15.0 ms 24 ms ±1 bit

ESF + MI MIC 15.0 ms 24 ms ±1 bit

FAS 0.5 ms 8 ms ±125 µs

CAS 2.0 ms 8 ms ±125 µs

MFAS 10.0 ms 8 ms ±125 µs

NOTE(S): MART is defin e d (per Bel lcore TA-0278) as the diffe rence be tween the time that

known good pseudo-random DS1 input is applied and the time that a valid DS0 signal is

observed at the output.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.7 Pr imary Cont rol and St atus Registers

100054E Conexant 3-31

018—Programmable Input/Output (PIO)

RMSYNC_EN Enable RMSYNC—Select which signal is present on bimodal pin, RFSYNC/RMSYNC.

When acti ve, recei v er multiframe sync (RMSYNC) is enabled. Otherwise, recei ver frame sync

RFSYNC is enabled.

RDL_IO Enable Receiver Data Link—Select which signals are present on bimodal RDLCKO and

RDLO. When active Receiver Data Link Clock Out (RDLCKO) and Receive Data Link Data

Out (RDLO) are enabled. Otherwise RINDO and RSIGO are as follows:

0 = select RINDO and RSIGO

1 = select Receive Data Link

TMSYNC _EN Enable TMSYNC—Select which si gnal is present on bimodal pin, TFSYNC/TMS YNC. When

active, transmit multiframe sync (TMSYNC) is enabled. Otherwise, receiver frame sync

TFSYNC is enabled.

TDL_IO Enable Transmit Data Link—Select which signals are present on bimodal TDLCKO and

TDLI. When active Transmit Data Link Clock Out (TDLCKO) and Transmit Data Link Data

Out (TDLO) are enab led. On the CX28395 de v ice, TDL3 is not a v ailab le and TDL_IO must b e

written to 0.

0 = select TINDO and TSIGI

1 = select Transmit Data Link

RFSYNC_IO Bidirectional RFSYNC Input/Output Mode—Refer to the system bus sync mode summary in

Tables 3-9 and 3-11. When RFSY NC is an input, i ts low to high transition aligns the RS B

timebase to the programmed RSB.OFFS ET. Refer to RSYNC_BIT, RSYNC_TS, and

RSYNC_FRM offset registers [addr 0D2, 0D3, and 0D8] for a complete description of the

RSB Sync Bits Tim e Slot and Frame Offset. Once aligned, the RSB timebase internally

flywheels at a 125 µs interval (8 kHz) until a new RFSYNC pulse is applied. When RFSYNC

is programmed as an output, it operates continuously at a 8 kHz frame rate, marking the RSB

sync bits and time slot offset position of each fram e. Initial RFSYNC align ment and

subsequent realignment depends upon RSB Mode [RSBI; addr 0D1] and RSB manual center

[RSB_CTR ; addr 0D1]. RFSYNC must be programmed as an output when RSLIP i s in bypass

mode. RFSYNC and RMSYNC are supplied either by the RSB timebase (output) or receive

system bus (input) at a programmable RSB sync bit offset, time slot location and frame offset

location.

0 = RFSYNC input

1 = RFSYNC output

RMSYNC_IO Bidir ec tion al RMSYNC Inpu t/ Output M ode— Refe r to t he syst em bus sync mode su mmary in

Table 3-9. When RMSYNC is an input, its low-to-high transition aligns the RSB timebase to

the pro grammed RSB .OFFSET. Once aligned , the RSB timebase internall y fl ywheel s at a 3 ms

(T1) or 2 ms (E1) interval until a new RMSYNC pulse is applied. Note that RMSYNC input

signal must always coincide with RFSYNC. When RMSYNC is an output, it operates

continuously at the 6 ms multiframe rate, marking the RSB.OFFSET position of ever y second

multifra me (T1) or every thir d multiframe (E1). Initia l RMSYNC alignment and subsequent

realignment depends upon RSB mode [RSBI; addr 0D1] and RSB manual center [RSB_CTR;

addr 0D1]. RMSYNC must be programmed as an output when RSLIP is in bypass mode or

transparent signaling mode [THRU; addr 0D7].

0 = RMSYNC input

1 = RMSYNC output

7 6 5 4 3 2 1 0

RMSYNC_EN RDL_IO TMSYNC_EN TDL_IO RFSYNC_IO RMSYNC_IO TFSYNC_IO TMSYNC_IO

3.0 Registers CX28394/28395/28398

3.7 Primary Control and St atus Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-32 Conexant 100054E

TFSYN C_I O Bidirectional TFSYNC Input/Output Mode—TFSYNC_IO programming is dependent on

transmit framer and system bus modes as shown in Tables 3-9 and 3-10.

0 = TFSYNC input

1 = TFSYNC output

TMSYNC _I O Bidirectional TMSYNC Input/Output mode—TMSYNC_IO programming is dependent on

transmit framer and system bus modes as shown in Tables 3-9 and 3-10.

0 = TMSYNC input

1 = TMSYNC output

Tab le 3-9. System Bus Sync Mode Summary

FSYNC MSYNC SBI Alignment Mode

IN IN SBI supplies multiframe and 8 kHz frame alignment. FSYNC must be aligned with

MSYNC if both are provided .

IN IN-GND SBI supplies 8 kHz frame alignment. Multiframe alignment is arbitrary and MSYNC is

unused.

IN OUT SBI supplies 8 kHz frame alignment. Multiframe alignment is supplied by the framer.

IN-GND OUT Framer supplies multiframe ali gnment. FSYNC is unused.

OUT IN SBI supplies multiframe and frame alignment.

OUT OUT Framer supplies frame and multiframe alignment.

Table 3-10. Common TFSYNC and TMSYNC Configurations

Conditions TFSYNC TMSYNC Explanation

Transmit framer disable d.

(TABORT = 1) IN IN TSB timebase slaved to system bus TFSYN C or TMSYNC.

IN-GND IN TSB time base slaved to system bus TMSYNC. TFSYNC i s unused.

IN IN-GND TSB ti mebase slaved to system b us TFSYNC. TMSY NC is unuse d

and mult iframe alignment is arbit r ary.

IN OUT SB timebase slaved to system bus TFSYNC. TMSYNC alignment is

arbitrary.

OUT OUT TSB ti mebase alignment is arb itrary.

OUT IN TSB timebase slaved to s ystem bus TMSYN C. TFSYNC aligns to

TMSYNC in pu t.

T ransmit framer enabled to

search TPCMI for

embedded framing.

(EMBED = 0, TABORT = 0)

OUT OUT TSB timebase is aligne d to embed ded framing on TP CMI. TPCMI

must be configured to l ine rate for this case .

T ransmit framer enabled to

search TNRZ (after TSLIP

buffer) for embedded

fram ing. (EMB ED = 1,

TABORT = 0)

OUT IN-GND T SB time base is aligned to embedded framing on TNRZ data.

TMSYNC is unus e d. TPCMI m ay b e co nfigure d for 1 ,544 kbp s or a

multi ple of 2,048 kbps .

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.7 Pr imary Cont rol and St atus Registers

100054E Conexant 3-33

019—Programmable Output Enable (POE)

Unused bits are reser ved and should be written to 0.

TDL_OE TDLCKO Output Buffer Control—When enabled, TDLCKO is output according to DL3_TS

and DL3_BIT [addr 015, 016]. TDL_OE should be written to 1 on the CX28395 device.

0 = TDLCKO output enabled

1 = TDLCKO output three-stated

RDL_OE RDLCKO and RDLO Out put B uffer Co nt rol— When enabled, bo th bi modal signal s a re output

by their respective internal circuits. Otherwise, both outputs are placed in high impedance

state. RDL_OE should be written to 1 on the CX28395 device.

0 = RDLCKO and RDLO outputs enabled

1 = RDLCKO and RDLO outputs three-stated

INDY_OE RINDO and TINDO Output Buffer Control—When enabled, both bimodal signals are output by

their respective internal circuits. Otherwise, both outputs are forced into high impedance state.

0 = RINDO outputs enabled

1 = RINDO outputs three-stated

TCKO_O E TCKO Output Buffer Control—Allows the system to connect multiple devices to a comm on

clock bus by providing programmable three-state control over the TCKO output buffer.

0 = TCKO output enabled

1 = TCKO output three-stated

Table 3-11. Common RFSYNC and RMSYNC Configurations

Conditions RFSYNC RMSYNC Explanation

Thru = 0 [RSIG_CR;

addr 0D7] IN IN RSB timebase slave d to system bus RFS YNC or RMSYNC .

IN OUT RSB timebase slaved t o system bus RFS YNC. RMSYNC alignment

is arbitr ary.

OUT IN RSB timebase slaved t o syst em bus RMSYNC. RFSYN C aligns to

TMSYNC in pu t.

OUT OUT RFSYNC and RMSYNC alignment is arbitrary.

Thru = 1 [RSIG_CR;

addr 0D7] IN OUT RSB timebase slaved t o system bus RFS YNC. RMSYNC is aligned

with the RX ti mebase and can follow a change of RX multiframe

align ment without generating an alarm indi cation.

OUT OUT RMSYNC is aligned with the RX timebase and can follo w a change

of RX mult ifra m e al ig nm e nt w ith ou t ge ne ra tin g an alarm

indication. RFSYNC is aligned to RMSYNC.

7 6 5 4 3 2 1 0

— — TDL_OE RDL_OE INDY_OE TCKO_OE — —

3.0 Registers CX28394/28395/28398

3.7 Primary Control and St atus Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-34 Conexant 100054E

01A—Clock Input Mux (CMUX)

Unused bits are reser ved and should be written to 0.

RSBCK RSBCK Source Select—Internal clock mux selects from one of two clock signals for

application to the RSB timebase. The RSBCKI input pin is ignored if TSBCKI is selected.

TSBCK TSBCK Source Select—Internal clock mux selects from one of three clock signals for

applica tion to t he TSB time base. If TSL IP is b ypasse d [TSB_CR; addr 0D4], TCKI is select ed.

The TSBCKI input pin is ignored if TCKI or RSBCKI is selected.

TXCLK[1:0] TXCLK Source Select—Internal transmit clock mux selects from one of three clock signals.

The selected clock signal is applied to tr ansmit clock moni tor , acts as a timing reference for the

transmitter block, and must operate at the T1/E1 line rate. The selected clock signal also

appears on TCKO pin. The TCKI input pin is ignored whenever a clock source other than

TCKI is selected.

020—Receive Alarm Configuration (RAC)

Unused bits are reser ved and should be written to 0.

RAL_CON RALOS Alarm Configuration – Determines whether RALOS [ALM1; addr 047] reports loss

of receive clock (RCKI) or loss of receive signal for 1 msec.

0 = RALOS reports that RLOS [ALM1; addr 047] has been active for 1 msec

1 = RALOS reports loss of clock on RCKI pin

7 6 5 4 3 2 1 0

— RSBCK — TSBCK — — TXCLK[1] TXCLK[0]

RSBCK RSBCK Source Notes

0 RSBCKI pin Normal RSB timebase

1 TSBCKI pin RSB slaved to TSB

TSBCK TSBCK Source Notes

0 TSBCKI pin Normal TSB timebase

1 RSBCKI pin TSB slaved to RSB

x TCKI pin TSLIP is bypassed

TXCLK[1:0] TXCLK Source Notes

00 TCKI Normal transmit (With TSLIP)

01 RCKI Transmit slaved to receiver (Loop Timed)

10 RSBCKI Transmit slaved to RSB

7 6 5 4 3 2 1 0

———RAL_CON————

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.7 Pr imary Cont rol and St atus Registers

100054E Conexant 3-35

021—Receive Line Code Status (RSTAT)

ZCSUB Zero Code Substitution—Indicates one or more B8ZS/HDB3 substitution patterns have been

detected on receiver input data, depending on T1/E1N line rate selection. ZCSUB is reported

regardless of whether ZCS decoding is enabled [RAMI; addr 040]. ZCSUB is latched active

high upon detection of the first ZCS pattern. The active high hold interval is defined by

LATCH_ERR [addr 046].

EXZ Excessive Zeros—Reports one or more long strings of zeros detected on the receiver data

inputs. Depending on bits RZCS [addr 040] and T1/E1N [addr 001], occurrences of 8, 10, or

16 consecutive zeros are detected. EXZ is latched active high upon detection of the first error.

The active high ho ld in terval is defined b y LATCH_ERR [addr 046] . I f EXZ _L CV [add r 0 45]

is enabled, EXZ errors are also accumulated in LCV count [addr 054, 055].

BPV Bipolar Violation—Repor t s one or more bipolar violations detected on the receiver data

inputs. Depending on RZCS [addr 040], BPV may or may not include bipolar violations

received as part of a B8ZS or HDB3 zero code substitu tion. Detectio n of BPV or LCV erro rs

can be selected regardless of whether receive ZCS decoding is enabled [RAMI; addr 040].

BPV is latched active high upon detection of the first error. The active high hold interval is

defined by LATCH_ERR [addr 046]. BPV er rors are also accumulated in LCV count [addr

054, 055].

7 6 5 4 3 2 1 0

— — ZCSUB EXZ BPV — — —

ZCSUB T1/E1N ZCSUB Status

0XNo ZCS patterns detected

10HDB3 pattern detected

11B8ZS pattern detected

EXZ T1/E1N. RZCS EXZ Status

0X XNo error

10X10 consecutive zeros

11 016 consecutive zeros

11 18 consecutive zeros

BPV T1/E1N RZCS BPV Status

0XXNo error

100All BPVs, including HDB3 coded BPV

101Code violation per ITU 0.162 (two consecutive BPVs of

same polarity)

110All BPVs, including B8ZS coded BPV

111Only BPVs that are not part of B8ZS

3.0 Registers CX28394/28395/28398

3.8 Se rial Interfac e Reg i s te r s Quad/x16/Octal—T1/E1/J1 Framers

3-36 Conexant 100054E

3.8 Serial Interface Registers

These registers are not used on the CX28395 device.

022—Serial Control (SER_CTL)

Writing to SER_CTL initiates a seria l interface read or write operation. During a write operation, a 16-bit word,

consisting of SER_CTL and SER_DAT, is transmitted to the LIU. During a read operation, SER_CTL is

transmitted and 8-bit data from the LIU is received and placed in SER_DAT register. SER_RW is transmitted

fir st and SER_DAT[0] is transmitted or received first.

SER_RW Serial Read/Write – Selects the current serial interface operation type.

0 = Write

1 = Read

SER_A[6:0] Serial Interface Register Address – Identifies the LIU register address for the current read or

write operati on.

023—Serial Data (SER_DAT)

SER_DAT[7:0] Serial Interface Data

024—Serial Status (SER_STAT)

SER_DONE Serial Interface Done–During a read or write serial interface operati on, SER_ DONE is cleared

indicati ng tha t an op erat ion i s in progress. After t he operat ion is comple te, this bi t is se t a nd an

interrupt request is generated if enabled by SER_IER [addr 025]. SER_DONE is also cleared

if read by the MPU. When the SER_DONE is cleared, the inter rupt request is deactivated to

allow the INTR* pin to also be deactivated if all other interrupt sources have been serviced.

7 6 5 4 3 2 1 0

SER_A[6] SER_A[5] SER_A[4] SER_A[3] SER_A[2] SER_A[1] SER_A[0] SER_RW

7 6 5 4 3 2 1 0

SER_DAT[7] SER_DAT[6] SER_DAT[5] SER_DAT[4] SER_DAT[3] SER_DAT[2] SER_DAT[1] SER_DAT[0]

7 6 5 4 3 2 1 0

———————SER_DONE

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.8 Serial Interface Registers

100054E Conexant 3-37

025—Serial Configuration (SER_CONFIG)

Unused bits are reser ved and should be written to 0.

SER_CS Serial Interface Chip Select 1

0 = sets external SERCS1* signal low

1 = sets external SERCS2* signal low

SER_CLK Serial Interf ace Cloc k

0 =1.024 MHz

1 = 8.192 MHz

SER_IER Serial Interface Interrupt Enable

0 = interrupt disabled

1 = interrup t enabled

026—RAM Test

Reserved for Conexant Production test.

7 6 5 4 3 2 1 0

SER_CS SER_CLK — — — — — SER_IER

7 6 5 4 3 2 1 0

RT[7] RT[6] RT[5] RT[4] RT[3] RT[2] RT[1] RT[0]

3.0 Registers CX28394/28395/28398

3.9 Receiver Registers Quad/x16/Octal—T1/E1/J1 Framers

3-38 Conexant 100054E

3.9 Receiver Registers

040—Receiver Configuration (RCR0)

RAMI Receive AMI Encoded Inputs—Disables B8ZS/HDB3 decoding for AMI formatted receive

signals. Otherwise, ZCS decoder replaces 000VB0VB code (B8ZS) with 8 zeros in T1 mode

or replaces X00V code (HDB3) with 4 zeros in E1 mode : wh ere B is a normal AMI pulse, V i s

a bipolar violation, and X is a “don't- care.” Regardless of RAMI setting, receipt of a ZCS

signature is always detected and reported in ZCSUB status [RSTAT; addr 021].

0 = receive B8ZS/HDB3 line format

1 = receive AMI line format

RABORT Abort/Disable RX Offline Framer—When set, the offline framer ignores reframe requests

from the online framer (RLOF) and aborts any in-progress RLOF reframe request. Loss of

frame status [RLOF; addr 047] is not affected. While RABORT remains set, offline framer

responds only to pr oce ssor forced reframes (R FORCE) . Thi s al lows the processo r t o man ual ly

control reframe criteria and prevent changes i n the cu rrent receive frame a lignmen t. RABORT

is typically set only during unframed operation.

0 = normal framer operation

1 = framer disabled

RFORCE Force RX Reframe—Forces the offline framer to perform a single reframe according to

selected receive framer mode. RFORCE is automatically cleared when offline framer

acknowledges the request [FSTAT; addr 017]. The processor does not typically need to force

reframe since the online framer reframe request (RLOF) is active whenever reframe criteria

(RLOFD–A) is met. However, the processor may force reframe if frame or CRC error ratios

indicate that the framer might have aligned to a duplicated frame alignment pattern.

0 = no effect

1 = force RX reframe

RLOFD– RLOFA RX R eframe Criteria—Determines the number of frame errors that the online framer must

detect before declaring loss of frame alignment [ALM1; addr 047]. Refer to receive framer

mode [RFRAME; addr 001] Table 2-1, Receive Framer Modes, to find which frame bits are

monitored.

7 6 5 4 3 2 1 0

RAMI RABORT RFORCE RLOFD RLOFC RLOFB RLOFA RZCS

T1/E1N RLOFD–A Reframe Criteria

0 0100 3 consecutive FAS or 915 CRC errors

0 110 0 3 consecutive FAS errors

1 0001 2 out of 4 F-bit errors

1 0010 2 out of 5 F-bit errors

1 0100 2 out of 6 F-bit errors

NOTE(S): Other RL OFD–RLOFA combinations are invalid. RA IS and RLOF st atus is disabled if

RLOFD–RLOF A equa l s all zeros.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.9 Receiver Registers

100054E Conexant 3-39

RZCS Receiv e B8ZS/HDB3 Zero Code Substitut ion (af fects onl y BPV/LCV/EXZ counting)—When

set, the ZCS decoder does not include bipolar violations received as part of a B8ZS/HDB3

code in the LCV er ror count [addr 054, 055]. Otherwise, all bipolar violations are counted.

EXZ detection criteria is either 8 or 16 consecutive zeros, depending on RZCS configuration.

0 = ZCS decoder reports all occurrences of BPV; also selects EXZ = 16 zeros

1 = ZCS decoder does not report BPVs received as part of ZCS; also selects EXZ = 8 zeros

041—Receive Test Pattern Configuration (RPATT)

RESEED Reseed PRBS Sync Detector (auto clear)—If BSTART is active high, writing a one to

RESEED forces the PRBS sync detector to reseed and search for test pattern sync [PSYNC;

addr 00B]. The reseed and search algorithm remains active until test pattern sync is found.

0 = no effect

1 = reseed and search for test pattern sync

BSTART Enab le PRBS Detecto r and St art Counting PR BS Bit Errors— BERR [add r 058, 059 ] counti ng

is enabled when BSTART is active high, and pattern sync is found [PSYNC=1; addr 00B].

Otherwise, BERR counter holds its present value until cleared by a processor read.

0 = PRBS detector disabled and BERR stops counting

1 = enable PRBS detector and BERR counter

FRAMED PRBS Framed—When set, PRBS test pattern bits are not checked during F-bit locations in T1

mode or TS0 locations in E1 mode. Otherwise, test patterns are checked in all T1/E1 bit

locations. FRAMED, ZLIMIT, and RPATT establish the test pattern measurement type as

listed in Table 3-12.

7 6 5 4 3 2 1 0

— — RESEED BSTART FRAMED ZLIMIT RPATT[1] RPATT[0]

Table 3-12. Receive PRBS Test Pattern Measurements (1 of 2)

FRAMED ZLIMIT RPATT T es t Pattern Measurements Inversion

0000

Unframed 211 No

0001

Unframed 215 Yes

0010

Unframed 220 No

0011

Unframed 223 Yes

0100

Unframed 211 with 7 zero limit No

0101

Unframed 215 with 7 zero limit (non-std) No

0110

Unframed 220 with 14 zero limit (QRSS/QRS/QRTS) No

0111

Unframed 223 with 14 zero limit (non-std) No

1000

Framed 211 No

1001

Framed 215 Yes

3.0 Registers CX28394/28395/28398

3.9 Receiver Registers Quad/x16/Octal—T1/E1/J1 Framers

3-40 Conexant 100054E

ZLIMIT PRBS Zero Limit—Deter mines the number of consecutive zeros allowed within the selected

PRBS te st pattern. Refer to Table 3-12 for test pattern measurement options.

RPATT[1: 0] P RBS Test Pat tern—Selects one o f four PR BS test pa ttern lengths used to measur e recei ved bit

err or ratio during out of ser vice testing. Refer to Table 3-12 for test pattern measurement

options. PRBS test patterns used by RPATT [addr 041] and TPATT [addr 076] are defined in

the ITU standards O.151 and O.152 to use either inverted or non-inverted data. Standard data

inversion is used for selected PRBS test patterns unless ZLIMIT is enabled, in which case the

test patter n always uses non-inverted data.

042—Receive Loopback Code Detector Configuration (RLB)

Unused bits are reser ved and should be written to 0.

DN_LEN[1:0] Loopback Deactivate Code Length—Selects the number of loopback pattern bits from LBD

[addr 044] that are compared to received data. This is done in order to deter mine whether a

Loopback Deact ivate Code [LOOPDN; addr 04 8] has been detected. LOOPDN i s recovered if

the received data pattern contains fewer than 63 bit errors in a 24 ms period, or lost if 64 or

more bit errors are detected in a subsequent 24 ms period. F-bits that overwrite or are inserted

into the loopback pattern are not counted as bit errors. Accurate code detection is provided on

lines wit h up to 1E-3 BER.

1010

Framed 220 No

1011

Framed 223 Yes

1100

Framed 211 with 7 zero limit No

1101

Framed 215 with 7 zero limit (non-std) No

1110

Framed 220 with 14 zero limit (QRSS/QRS/QRTS) No

1111

Framed 223 with 14 zero limit (non-std) No

Table 3-12. Receive PRBS Test Pattern Measurements (2 of 2)

FRAMED ZLIMIT RPATT T es t Pattern Measurements Inversion

7 6 5 4 3 2 1 0

— — — — DN_LEN[1] DN_LEN[0] UP_LEN[1] UP_LEN[0]

DN_LEN LBD Le ngth

00 4 bits

01 5 bits

10 6 bits

11 7 bits

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.9 Receiver Registers

100054E Conexant 3-41

UP_LEN[1:0] Loopback Activate Code Length—Selects the number of loopback pattern bits from LBA

[addr 043] that are compared to received data. This is done in order to deter mine whether a

Loopback Acti v ate Code [LOOPUP; addr 048 ] has been detected. LOOPUP is reco v ered if the

received data patter n contains fewer than 63 bit errors in a 24 ms period, or lost if 64 or more

bit errors are detected in a subsequent 24 ms period. F-bits that overwrite or are inserted into

the loopback pattern are not coun ted as bit errors. Accurate code det ection is provided on lines

with up to 1E-3 BER.

043—Loopback Activate Code Pattern (LBA)

Unused bits are reser ved and should be written to 0.

LBA[1] First bit expected of LOOPUP pattern

LBA[2] Second bit expected of LOOPUP pattern

LBA[3] Third bit expected of LOOPUP pattern

LBA[4] Fourth bit expected—Last bit if UP_LEN selects a 4-bit pattern

LBA[5] Fifth bit expected—Las t bit if UP_L EN selects a 5-b it pattern

LBA[6] Sixth bit expected—Last bit if UP_LEN selects a 6-bit pattern

LBA[7] Seventh bit expe cted—Last bit if UP_LEN selects a 7-bit pattern

044—Loopback Deactivate Code Pattern (LBD)

Unused bits are reser ved and should be written to 0.

LBD[1 ] First bit expected of LOOPDN pattern

LBD[2 ] Second bit expected of LOOPDN pattern

LBD[3] Third bit expected of LOOPDN pattern

LBD[4 ] Fourth bit expected—Last bit if DN_LEN selects a 4-bit pattern

LBD[5] Fifth bit expected—Last bit if DN_LEN selects a 5-bit pattern

LBD[6 ] Sixth bit expected—Last bit if DN_LEN selects a 6-bit pattern

LBD[7 ] Seventh bit expected—Last bit if DN_LEN selects a 7-bit pattern

UP_LEN LBA Length

00 4 bits

01 5 bits

10 6 bits

11 7 bits

7 6 5 4 3 2 1 0

LBA[1] LBA[2] LBA[3] LBA[4] LBA[5] LBA[6] LBA[7] —

7 6 5 4 3 2 1 0

LBD[1] LBD[2] LBD[3] LBD[4] LBD[5] LBD[6] LBD[7] —

3.0 Registers CX28394/28395/28398

3.9 Receiver Registers Quad/x16/Octal—T1/E1/J1 Framers

3-42 Conexant 100054E

045—Receive Alarm Signal Configuration (RALM)

Unused bits are reser ved and should be written to 0.

DIS_LCV Disable LCV indication and counting. Primarily used in configurations where receive data is

unipolar NRZ. If AUTO_PRM is enabled (PRM; addr 0AA) LV is transmitted with a default

value of 0 .

0 = LCV counting and indication enabled

1 = LCV counting and indication disabled

FS_NFAS Include FS/NFAS in FERR and FRED—Selects whether Fs bit err ors (T1) or NFAS Bit2

errors ( E 1) ar e co unt ed as frame errors [FERR; a ddr 050, 051]. Further select s whether loss of

frame alignment [FRED; addr 049] includes Fs or NFAS bit errors as part of the detection

criteria. Note that t he nu mber of Fs bi t locat ions checked also dep ends o n JYEL framer mo de.

0 = FERR and FRED do not include FS/NFAS

1 = FERR and FRED include FS/NFAS

EXZ_LCV Excess Zeros Included in LCV—Whether line code violation error count [LCV; addr 054,

055] includes EXZ errors depends on the EXZ_LCV control setting. Depending on RZCS bit

setting [addr 040], each EXZ is equal to either 8 or 16 consecutive zeros.

0 = LCV does not include EXZ

1 = LCV includes EXZ

YEL_INT EG Enable Yellow Alarm Integration—When set, both the receive frame and multiframe yellow

alarms [RYEL and RMYEL; addr 047] are integrated, as described in Table 3-13 (per t he

selected framer mode). RYEL and RMYEL interrupt status [ISR7; addr 004] are similarly

affected.

0 = normal RYEL and RMYEL status

1 = integ r ated RYEL and RMYEL status

7 6 5 4 3 2 1 0

— DIS_LCV FS_NFAS EXZ_LCV YEL_INTEG RLOF_INTEG RPCM_YEL RPCM_AIS

Table 3-13. Receive Yellow Alarm Set/Clear Criteria (1 of 2)

Mode Set/Clear Criteria

Y0 Set for 4 frames (50 0 µs) if 2 consecutive NF AS frames each contain TS0 bit 3 = 1. Cleared for 4 frames if 2

consecutive NFAS frames each contain TS0 bit 3 = 0.

Y0_INT Set for 16 multiframes (24 ms) if every NFAS frame contains TS0 bit 3 = 1. Cleared for 16 multiframes if 1 or

more N FAS frames contain TS0 bit 3 = 0.

Y16 Set for 2 multiframes (4 ms) if frame 0 in 2 consecutive mul ti frames contains TS16 bi t 6 = 1. Cleared for 2

mult iframes if fr ame 0 in 2 consecutive multiframes con tains TS1 6 bit 6 = 0.

Y16_INT Set for 16 mul tiframes (24 ms ) if every frame 0 contai ns TS16 bit 6 = 1. Cleared for 16 mul tiframes if at

lea s t 1 frame 0 contains TS16 bit 6 = 0.

YB2 Set for 1 frame (125 µs) if all 24 time slots contain bit 2 = 0. Cleared for 1 frame if 1 or more time slots

cont ain bit 2 = 1.

YB2_INT Set for 192 frames (24 ms) if less than 15 time slots contain bit 2 = 0. Cleared for 192 frames if 15 or more

time slots contain bit 2 = 1.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.9 Receiver Registers

100054E Conexant 3-43

RLOF_INTEG Enable RLOF Integration—When set, the receive loss of frame status [RLOF; addr 047] is

inte grated for 2.0 to 2.5 seco nds during T1 fra me r modes ( not ap pl ica ble t o E 1 mo des). R LOF

inter rupt status [ISR7; addr 004] is also integrated. However, receive framer status in ALM3

[addr 049], loss of frame count [FRED[3:0]; addr 05A], and RLOF counter overflow [ISR4;

addr 007] are unaffected.

0 = normal RLOF status

1 = integrated RLOF [addr 047] status

RPCM_YEL Send Bit2 Yellow Alarm on RPCMO Output Pin—Similar to RPCM_AIS, exce pt all RPCMO

time slot Bit2 locations are replaced by all zeros. Bit2 yellow alarms are applicable only to T1

mode. E1 modes do not require yellow alarm forwarding.

0 = normal RPCMO data

1 = RPCMO includes Bit2 yellow alarm

RPCM_AIS Send AIS on RPCMO Output Pin—Replaces RPCMO data with a continuous series of all

ones. RPCM_AIS is useful in CSU or digital section applications, where the local interface

must be able to forward an AIS to the opposing interface. RPCM_AIS has a higher priority

than RPCM_YEL.

0 = normal RPCMO data

1 = RPCMO replaced with all ones

YJ Set for 1 multiframe (1. 5 ms) if frame 12 contains Fs bit = 1. Clea red for 1 multif rame if frame 12 cont ains

Fs bit = 0.

YJ_INT Set for 16 multiframes (24 ms) if every frame 12 contains Fs bit = 1. Cleared for 16 multiframes (24 ms) if at

least 1 frame 12 contains Fs bit = 0.

Y24 Set for 1 frame (125 µs) if TS24 contains bit 6 = 0. Clear ed for 1 frame if TS24 cont ains bit 6 = 1.

Y24_INT Set for 192 fr ames (24 ms) if every TS24 b it 6 = 0. Cle ared for 1 92 frames if at least 1 TS24 bit 6 = 1.

YF Set for 32 frames (4 ms) if 16 FDL bits contain ye llow alarm priority codeword pattern (00F Fh). Cleared for

32 frames if 16 FDL bits do not contain a yellow alarm priority codeword pattern.

YF_INT Set upon recep ti on of 16 FDL bi ts matching yel low alarm pri ority codeword and remains set as long as the

codeword patt ern is not interrupted for greater than 100 ms. Cleared when the yellow alarm priority

code word is not present for more than 100 ms (26 missing codewords = 104 ms).

Table 3-13. Receive Yellow Alarm Set/Clear Criteria (2 of 2)

Mode Set/Clear Criteria

3.0 Registers CX28394/28395/28398

3.9 Receiver Registers Quad/x16/Octal—T1/E1/J1 Framers

3-44 Conexant 100054E

046—Alarm/Error/Counter Latch Configuration (LATCH)

Unused bits are reser ved and should be written to 0.

STOP_CNT Stop Error Count du ring RLOF/RLOS/RAI S—If enabl ed , error count regi sters [addr 050–057]

are suspended at their present values during any receive loss of frame (RLOF), loss of signal

(RLOS), or all ones (RAIS) alarm condition. STOP_CNT does not affect counting of test

pattern errors [BERR; addr 058, 059] or alarm ev ent s [AERR; addr 05A]. The occurrence of a

red or AIS CGA will inhibit further processi ng of all other performance parameters (i.e., BER ,

errored seconds, SLIPS, etc.). However, a CGA caused by a yellow alarm will not inhibit

further alarm or performance monitoring

0 = continue error count during alar ms

1 = stop error count during alarms

LATCH_C NT Enable ONESEC Latching o f Counters—Deter m ines interval for which error counts re main

held i n al l co unt re gisters [addr 05 0–05 7] . L ATCH_CNT must be act ive in T1 mode whenev er

automatic one-second performance repor t messaging [AUTO_PRM; addr 0AA] is enabled.

Note that LATCH_CNT active during E1 mode prevents the processor from using RLOF

counter overflow [addr 007] as a 128 ms MFAS timeout.

When LATCH_CNT is inactive, the processor read of the LSB register reports current LSB

error coun t, it lat ches c urrent MSB error count to MSB register, and clears LSB . Subsequen tly,

reading MSB register reports current latched MSB error count and then clears MSB.

LATCH_ERR Enable ONESEC Latching of Errors—D etermines the interval for which latched active errors

are held in error inter rupt [ISR5; addr 006] and patter n interrupt [ISR0; addr 00B] status.

LATCH_A LM Enable ONESEC Latching of Alarms—Determines interval for which latched active alarms

remain held in alarm interrupt status [ISR7, ISR6; addr 004, 005].

7 6 5 4 3 2 1 0

— — — — STOP_CNT LATCH_CNT LATCH_ERR LATCH_ALM

LATCH_CNT Count Latched Count Hold Time

0 Never Until read clear

1 ONESEC interval ONESEC interval

IER LATCH_ERR ISR Latched ISR Hold Time

0 0 Rising edge event Until read clear

0 1 Rising edge event ONESEC interval

1 X Rising edge ev ent Until read clear

IER LATCH_ALM ISR Latch e d ISR Hold Time

0 0 Rising edge or transition Until read clear

0 1 Rising edge or transition ONESEC interval

1 X Rising edge or transition Until read clear

NOTE(S): Interrupt t ype determines rising edge or t ransition event.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.9 Receiver Registers

100054E Conexant 3-45

047—Alarm 1 Status (ALM1)

ALM1 reports current status of receive alar ms. Any change in the current status activates the corresponding

interrupt status bit [ISR7; addr 004].

RMYEL Receive Multiframe Yellow Alarm—Real-time or integrated RMYEL status depends on the

selected framer mode and the yellow alarm integration mode [YEL_INTEG; addr 045]. Refer

to Table 2-1, Receive Framer Modes, for mode summary and Table 3-13 for set/c le ar criteria.

0 = no alarm

1 = receive multiframe yellow alarm

RYEL Receive Yellow Alarm—Real-time or integrated RYEL status depends on selected receive

framer mode and yellow alarm integration mode [YEL_INTEG; addr 045]. Refer to

Table 3-14 for mode summary and Table 3-13 for set/clear criteria.

0 = no alarm

1 = receive Yellow Alarm

7 6 5 4 3 2 1 0

RMYEL RYEL — RAIS RALOS RLOS RLOF SIGFRZ

Table 3-14. Receive Yell ow Alarm

Recei v e Fr am er

Mode

YEL_I N TE G = 0 YEL_INTE G = 1

RYEL RMYEL RYEL RMYEL

FT/SF/SLC YB2 — YB2_INT —

JYEL YJ — YJ_INT —

T1DM Y24 — Y24_INT —

ESF YB2 YF YB2_INT YF_INT

FAS Y0 — Y0_INT —

CAS Y0 Y16 Y0_INT Y16_INT

NOTE(S): Last known frame alignment is used to locate and monitor yell ow alarms.

Therefore, RYEL and RMYEL will not accurately rep ort alarms during receive loss of frame

alignment [RL OF; addr 047].

3.0 Registers CX28394/28395/28398

3.9 Receiver Registers Quad/x16/Octal—T1/E1/J1 Framers

3-46 Conexant 100054E

RAIS Recei v e Alarm Indication Signa l—Criteria for detection and clearan ce of RAIS per ITU G.775

and ANSI T1.231.

RALOS Receive Loss of Signal or Receive Clock—Reports loss of receive clock (RCKI) or loss of

receive signal [RLOS; addr 047] for 1 msec depending on the RALOS configuration bit

[RAL_CON; addr 020].

When set for loss of clock, RALOS beco mes activ e (1) i f the receive clock on the RCKI pin

is not present, and inactive (0) if the clock is present.

When set for loss of signal, RALOS indicates that all zeros have been recei v ed for at least 1

msec (RLOS is active for 1 msec). This status is provided for compatibility with ITU-I.431

loss of signal det ect io n requi r ement s; an d works in conjunction wit h LIUs which det ect loss of

signal if the received signal level falls below a certain threshold and which have a signal

‘squelch’ feature. Operation is as follows:

• The LIU detects receive loss of signal if the receive level falls below:

– 30 dB below nominal for T1.

– 20 dB below nominal for E1

• The LIU squelches (turns off) the signal to the framer so all zeros are received.

• RLOS is reported after 100 continuous zeros are detected.

• RALOS is report ed after RLOS is active for 1 msec.

RLOS Receive Loss of Signal—Criteria for detection and clearance of RLOS per ITU G.775 and

ANSI T1.231.

Mode RAIS Set/Clear Criteria

E1 0 Cleared if 2 consecutive double frames (500 µs) each

contain 3 or more zeros out of 512 bits or FAS

alignment is recovered [FRED = 0; addr 049].

E1 1 Set if 2 consecutive double frames each contain 2 or

fewer zeros out of 512 bits and FAS alignment is lost

[FRED = 1; addr 049].

T1 0 Cleared if data received for a period of 3 ms contains

5 or more zeros out of 4632 bits or frame alignment is

recovered [FRED = 0; addr 049].

T1 1 Set if data received for a period of 3 ms contains 4 or

fewer zeros out of 4632 bits and frame alignment is

lost [FRED = 1; addr 049].

Mode RLOS Set/Clear Criteria

T1 0 Cleared if received data sustains an average pulse

density of 12.5% over a period of 114 bits starting

with the receipt of a pulse, and no occurrence of 100

consecutive zeros.

T1 1 Set if 100 consecutive zeros received.

E1 0 Cleared upon reception of 193 bits in which no

interval of 32 consecutive zeros appear, where the

193-bit window begins with receipt of a pulse.

E1 1 Set upon reception of 32 consecutive zeros.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.9 Receiver Registers

100054E Conexant 3-47

RLOF Receive Loss of Frame Alignment—Real-ti me or integrated RLOF status depends on select ed

recei v e fra mer mode, out of f rame criter ia [RLOFA–RLOFD; addr 040], and int egration mode

[RLOF_INTEG; addr 045]. Refer to Tables A-1 through A-6 in Appendix A to find which

frame bits are monitored. Refer to Table 2-2, Criteria for Loss/Recovery of Receive Framer

Alignment, for the loss/recovery criteria. During E1 mode, RLOF indicates logically OR'ed

status of FAS/MFAS/CAS alignment machines from which individual alignment status is

reported separately in FRED/MRED/SRED [addr 049].

0 = no alarm

1 = receive loss of frame alignment

SIGFRZ Signaling Fr eeze—Real-time SIGFRZ status indicates w hen input ABCD signaling bi t updates

are no longer being written to the receive signaling buffer [RSIGn; addr IA0–IBF].

Consequentl y, ABCD signali ng on RPCMO (i f signalin g insertion enab led) and RSIGO output

pins are fixed to their existing buffered values. SIGFRZ remains active for 6 to 12 ms longer

after COFA or RLOF clears. SIGFRZ statu s is also af fected by manual SIGFRZ on/of f cont rols

[RSIG_CR; addr 0D7].

0 = no alar m (or FRZ_OFF)

1 = signaling freeze (or FRZ_ON)

048—Alarm 2 Status (ALM2)

Reports real-t i me st atu s of t ransmi t alarms and inband lo opback codeword detectors. Any change in the cu rrent

status activates the corresponding interrupt status bit [ISR6; addr 005].

Unused bits are reser ved and should be written to 0.

LOOPDN Inband Loopback Deactivate—Repor ts detection or loss of an inband loopback code which

matches the programmed LOOPDN code [LBD; addr 044].

0 = no inband code (or lost)

1 = LOOPDN code detected

LOOPUP Inband Loopback Activate—Reports detection or loss of an inband loopback code which

matches the programmed LOOPUP code [LBA; addr 043].

0 = no inband code (or lost)

1 = LOOPUP code detected

TLOC Transmit Loss of Clock— Clock mo nitor circu it reports TCKI lost if no signal transitions a r e

detected on TCKI pin for eight clock cycles of T1ACKI(T1) or EIACKI(E1). TCKI is

reported as present if four or more signal transitions are detected on TCKI pin during eight

clock c y cl es of T 1/E1 ACKI. When use d in co nj unct i on wi th AI SCLK [ ad dr 068], TLOC al so

identifies which transmit li ne rate clock (TCKI or T1/E1A CKI) is presentl y in use and w hether

AIS data transmission is enforced. Note that TLOC status is indeterminate if the T1/E1ACKI

input signal is not present.

0 = TCKI present

1 = TCKI lost

TLOF Transmit Loss of Frame Alignment—Report s transmit framer status per selected mode

[TFRAME; addr 070] and loss criteria [TLOFA–TLOFC; addr 071].

0 = recovered

1 = lost

7 6 5 4 3 2 1 0

LOOPDN LOOPUP — — TLOC — TLOF —

3.0 Registers CX28394/28395/28398

3.9 Receiver Registers Quad/x16/Octal—T1/E1/J1 Framers

3-48 Conexant 100054E

049—Alarm 3 Status (ALM3)

Reports real-time status of the re cei ve framer (not af fected b y ONESEC l atch mode), a nd miscell aneous lat ched

err or status (SEF and RMAIS). Any change of the logical OR of (FRED or MRED or SRED) status activates

RLOF interrupt [ISR7; a ddr 004]. Refer t o Table 2-2, Criteria for Loss/Recovery of Receive Fr a mer Ali gnment ,

[RFRAME; addr 001] to find the criteria for loss/recovery of frame alignment.

RMAIS Receive TS16 Alarm Indication Signal (CAS mode only)—RMAIS is latched active high and

cleared by a processor read. Criteria for detection and clearance of RMAIS is per ITU G.775.

SEF Severely E rrored Frame—SEF is latched active high and cleared by a processor read. Criteria

for detection and clearance of SEF is per ANSI T1.231.

SRED Loss of CAS Alignment—Real-time status of CAS alignment machine. SRED is applicable if

CAS is enabled, otherwise SRED is zero.

0 = recovery of CAS alignment

1 = loss of CAS alignment

MRED Loss of MFAS Alignment—Real-time status of MFAS alignment machine. MRED is

applicable if MFAS is enabled, otherwise MRED is zero.

0 = recovery of MFAS alignment

1 = loss of MFAS alignment

FRED Loss of T1/FAS Alignment —Real-time statu s of basi c frame alig nment machi ne. FRED ala rm

counter [AERR; addr 05A] increments for each low-to-high FRED transition.

0 = recovery of frame alignment

1 = loss of frame alignment

LOF[1:0] Reason for Loss of F rame Alignment—LOF sta tus is latched w hene ver FRED reports a loss of

frame alignment and remains he ld at the latc hed value until th e next loss of frame alignment.

7 6 5 4 3 2 1 0

— RMAIS SEF SRED MRED FRED LOF[1] LOF[0]

Mode RMAIS Criteria

CAS Set if TS16 contains three or fewer zeros out of 128 bits in

each mutiframe ov er two consecutive multiframes (4 ms).

Other Not applicable (read zero).

Mode SEF Criteria

E1 Set if two or more (FAS or NFAS) error s detected out of six frames.

(FAS + NFAS, or 2 FAS, or 2 NFAS erro rs, etc.).

FT/SF/SLC Set if two or more Ft errors are detected out of 3 Ft bits.

ESF Set if two or more FPS errors detected out of six FPS bits.

LOF[1:0] LOF Criteria

00 Three consecutive FAS pattern errors

01 Three consecuti ve NFAS pattern errors

10 915 or more CRC4 errors out of 1000 blocks checked

11 Eight ms timeout while searching for MFAS

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.10 Per f orm ance Mon itoring Register s

100054E Conexant 3-49

3.10 Performance Monitoring Registers

If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective Performance Monitoring

counter, the count er is allowed to roll over after reaching its maximum c ount value. If the overflow inter rupt is

disabled, the counter will hold its maximum value upon saturation. Refer also to LATCH [addr 046] for a

description of one-second latched counter operation. Processor must read LSB before reading MSB of each

multi -byte counter.

050—Framing Bit Error Counter LSB (FERR)

FERR[7:0] Ft/Fs/T1D M/F PS/FAS Error Count

051—Framing Bit Error Counter MSB (FERR)

If LATCH_CNT [addr 046] is inactive, reading FERR [addr 051] clears the entire FERR[11:0] count value.

FERR[11:8] Ft/Fs/T1DM/F PS/FAS Error Count

052—CRC Error Counter LSB (CERR)

CERR[7:0] CRC6/CRC4 Error Count

053—CRC Error Counter MSB (CERR)

If LATCH_CNT [addr 046] is inactive, reading CERR [addr 053] clears the entire CERR[9:0] count value.

CERR[9:8] CRC6/CRC4 Error Count

7 6 5 4 3 2 1 0

FERR[7] FERR[6] FERR[5] FERR[4] FERR[3] FERR[2] FERR[1] FERR[0]

15 14 13 12 11 10 9 8

0 0 0 0 FERR[11] FERR[10] FERR[9] FERR[8]

7 6 5 4 3 2 1 0

CERR[7] CERR[6] CERR[5] CERR[4] CERR[3] CERR[2] CERR[1] CERR[0]

15 14 13 12 11 10 9 8

000000CERR[9]CERR[8]

3.0 Registers CX28394/28395/28398

3.10 Performance Monitori ng Regist ers Quad/x16/Octal—T1/E1/J1 Framers

3-50 Conexant 100054E

054—Line Code Violation Counter LSB (LCV)

LCV[7:0] BPV and EXZ (if EXZ_LCV enabled) Error Count

055—Line Code Violation Counter MSB (LCV)

If LATCH_CNT [addr 046] is inactive, reading LCV [addr 055] clears the entire LCV[15:0] count value.

LCV[15:8] BPV and EXZ (if EXZ_LCV enabled) Er ror Count

056—Far End Block Error Counter LSB (FEBE)

FEBE[7:0] FEBE Count (applicable only in E1 mode)

057—Far End Block Error Counter MSB (FEBE)

If LATCH_CNT [addr 046] is inactive, reading FEBE [addr 056, 057] clears the entire FEBE[9:0] count value.

FEBE[9:8] FEBE Count (applicable only in E1 mode)

058—PRBS Bit Error Counter LSB (BERR)

Reading BERR transfers the most recent 12-bit count from the intern al PRBS error counter to BERR[11:0],

then clears the internal error counter without affecting the reported BERR[11:0] value. Subsequent reads of

BERR MSB [addr 059] repor t the BERR [11:8] count value latched when BERR LSB was last read.

BERR[7:0] BERR Count (applicable only for test pattern)

7 6 5 4 3 2 1 0

LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0]

15 14 13 12 11 10 9 8

LCV[15] LCV[14] LCV[13] LCV[12] LCV[11] LCV[10] LCV[9] LCV[8]

7 6 5 4 3 2 1 0

FEBE[7] FEBE[6] FEBE[5] FEBE[4] FEBE[3] FEBE[2] FEBE[1] FEBE[0]

15 14 13 12 11 10 9 8

000000FEBE[9]FEBE[8]

7 6 5 4 3 2 1 0

BERR[7] BERR[6] BERR[5] BERR[4] BERR[3] BERR[2] BERR[1] BERR[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.10 Per f orm ance Mon itoring Register s

100054E Conexant 3-51

059—PRBS Bit Error Counter MSB (BERR)

BERR[11:8] BERR Count (suspended if BSTART = 0)

05A—SEF/FRED/COFA Alarm Counter (AERR)

Reading AERR clears the SEF[1:0], COFA[1:0] and FRED[3:0] count values.

FRED[3:0] Receive loss of basic frame alignment count—Increments for each occurrence of FRED

[ALM3; addr 049]. The four bit count is large enough to count more than 100 ms worth of

MFAS timeout intervals (8 ms each) during E1 modes. Processor may therefore use FRED

counter overflow interrupt to indicate that a receive MFAS alignment search has timed out.

COFA[1 :0] Change of Frame Alignment Count—Increments each time the offline framer generates a

reframe pulse that aligns the receiver timebase to a new bit position.

SEF[1:0] Severely Errored Frame Count—Increments for each occurrence of SEF [ALM3; addr 049].

15 14 13 12 11 10 9 8

0 0 0 0 BERR[11] BERR[10] BERR[9] BERR[8]

7 6 5 4 3 2 1 0

FRED[3] FRED[2] FRED[1] FRED[0] COFA[1] COFA[0] SEF[1] SEF[0]

3.0 Registers CX28394/28395/28398

3.11 Receive Sa-Byte Buff er s Quad/x16/Octal—T1/E1/J1 Framers

3-52 Conexant 100054E

3.11 Receive Sa-Byte Buffers

Five receive S a- Byte buffers [RSA4 –RSA8] are double-buffered. All five re gi ste r s are upd ated wit h th e Sa- bits

received in TS0 of odd frames at each receive multiframe interrupt [RMF; addr 008]. Bit 0 of all RSA registers

contains data from frame 1, Bit 1 contains data from frame 3, Bit 2 contains data from frame 5, etc. This gives

the processor a full 2 ms after RMF interrupt to read any Sa-Byte buffer before the buffer content changes.

Processor shou ld ign ore RSA buf fer contents at all times dur ing T1 mode and a lso w hen rec ei v er repo rts loss of

FAS alignment [FRED=1; addr 049] in E1 mode.

05B—Receive Sa4 Byte Buffer (RSA4)

RSA4[7] Sa4 bit received in frame 15

RSA4[6] Sa4 bit received in frame 13

RSA4[5] Sa4 bit received in frame 11

RSA4[4] Sa4 bit received in frame 9

RSA4[3] Sa4 bit received in frame 7

RSA4[2] Sa4 bit received in frame 5

RSA4[1] Sa4 bit received in frame 3

RSA4[0] Sa4 bit received in frame 1

05C—Receive Sa5 Byte Buffer (RSA5)

RSA5[7] Sa5 bit received in frame 15

RSA5[6] Sa5 bit received in frame 13

RSA5[5] Sa5 bit received in frame 11

RSA5[4] Sa5 bit received in frame 9

RSA5[3] Sa5 bit received in frame 7

RSA5[2] Sa5 bit received in frame 5

RSA5[1] Sa5 bit received in frame 3

RSA5[0] Sa5 bit received in frame 1

7 6 5 4 3 2 1 0

RSA4[7] RSA4[6] RSA4[5] RSA4[4] RSA4[3] RSA4[2] RSA4[1] RSA4[0]

7 6 5 4 3 2 1 0

RSA5[7] RSA5[6] RSA5[5] RSA5[4] RSA5[3] RSA5[2] RSA5[1] RSA5[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.11 Receive Sa-B yte Buffers

100054E Conexant 3-53

05D—Receive Sa6 Byte Buffer (RSA6)

RSA6[7] Sa6 bit received in frame 15

RSA6[6] Sa6 bit received in frame 13

RSA6[5] Sa6 bit received in frame 11

RSA6[4] Sa6 bit received in frame 9

RSA6[3] Sa6 bit received in frame 7

RSA6[2] Sa6 bit received in frame 5

RSA6[1] Sa6 bit received in frame 3

RSA6[0] Sa6 bit received in frame 1

05E—Receive Sa7 Byte Buffer (RSA7)

RSA7[7] Sa7 bit received in frame 15

RSA7[6] Sa7 bit received in frame 13

RSA7[5] Sa7 bit received in frame 11

RSA7[4] Sa7 bit received in frame 9

RSA7[3] Sa7 bit received in frame 7

RSA7[2] Sa7 bit received in frame 5

RSA7[1] Sa7 bit received in frame 3

RSA7[0] Sa7 bit received in frame

7 6 5 4 3 2 1 0

RSA6[7] RSA6[6] RSA6[5] RSA6[4] RSA6[3] RSA6[2] RSA6[1] RSA6[0]

7 6 5 4 3 2 1 0

RSA7[7] RSA7[6] RSA7[5] RSA7[4] RSA7[3] RSA7[2] RSA7[1] RSA7[0]

3.0 Registers CX28394/28395/28398

3.11 Receive Sa-Byte Buff er s Quad/x16/Octal—T1/E1/J1 Framers

3-54 Conexant 100054E

05F—Receive Sa8 Byte Buffer (RSA8)

RSA8[7] Sa8 bit received in frame 15

RSA8[6] Sa8 bit received in frame 13

RSA8[5] Sa8 bit received in frame 11

RSA8[4] Sa8 bit received in frame 9

RSA8[3] Sa8 bit received in frame 7

RSA8[2] Sa8 bit received in frame 5

RSA8[1] Sa8 bit received in frame 3

RSA8[0] Sa8 bit received in frame 1

7 6 5 4 3 2 1 0

RSA8[7] RSA8[6] RSA8[5] RSA8[4] RSA8[3] RSA8[2] RSA8[1] RSA8[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-55

3.12 Transmitter Registers

070—Transmit Framer Configuration (TCR0)

TCR0 selects the of fline framer's criteria for recovery of transmit frame alignment and determines the output of

transmit frame and alarm for matters overhead bits. In addition, TCR0 works in conjunction with TCR1

[addr 071] and TFRM [addr 072] to select the transmit online frame monitor's criteria for loss of frame

alignment and to select which overhead bits are supplied by the transmit frame and alarm formatters.

Unused bits are reser ved and should be written to 0.

TINCF Transmit CRC6 includes F-bit—Determines if the F-b it is included in the CR6 remain der

calculation in T1 mode (T1/E1N = 1). This bit is ignored in E1 mode (T1/E1N = 0).

7 6 5 4 3 2 1 0

— — — TINCF TFRAME[3] TFRAME[2] TFRAME[1] TFRAME[0]

0 = T1 ESF CRC6 calculation is performed on the

transmit data including a 1 in place of the F-bit.

1 = T1 ESF CRC6 calculation i s p er fo rmed on transmit

data including the F-bit.

3.0 Registers CX28394/28395/28398

3.12 Transmitter Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-56 Conexant 100054E

TFRAME[3:0] Frame formatter gener at es Ft , Fs , FP S, FAS, MFAS, and CRC bits . Alarm formatter generates

YB2, YJ, Y0, and Y16 bits. Frame a nd alarm overhead formats are selected by TFRAME[3:0]

and T1/E1N settings as given in Tables 3-15 through 3-18. Each yellow alarm is capable of

being generated manually, automatically [TALM; addr 075], or bypassed [INS_MYEL; addr

072].

Frame formatter does not generate CAS or Sa-bit overhead. These bits are either supplied

by TPCMI in bypass mode [TFRM; addr 072] or by programming TSIGn [addr 120–13F] or

TSA4–TSA8 [addr 07B–07F] buffer contents. To insert CAS, the processor selects TLOCAL

output signaling for time slot 0 and time slot 16 by programming transmit per-channel control

registers TPC0 [addr 100] and TPC16 [addr 110]. The processor then fills ABCD local

signaling value for TPC0 with MAS pattern (ABCD = 0000) and TPC16 with XYXX pattern

(ABCD = 1011).

Frame formatter does not generate SLC, T1DM, or FDL overhead. These bits are either

supplied by TPCMI in bypass mode [TFRM; addr 072] or by programming TSLIP

[addr 140–17F], TDL1 [addr 0AD], or TDL2 [addr 0B8] buffer contents.

To insert SLC concentrator, maintenance, alarm, and switch field values, the processor

selects any SLC framer format and prog rams either TDL1 or TDL2. This is done in order to

operate in unformatted Pack6 mode over the F-bit channel during even frames, thus

overwriting all Fs bits inserted by frame formatter. The data pattern to be sent in 36 Fs bit

multiframe is then written as six 6-bit words to TDL1 or TDL2 circular buffer. For real-time

overhead manipulation, the processor can rewrite the circular buffer with a new 36-bit pattern

as desired.

To insert T1DM, the processor enables TIDLE insertion on time slot 24 by programming

the system bus per-channel control [SBC24; addr 0F8], then filling TSLIP buffer locations for

TS24 [addr 138, 158] with the T1DM framing pattern (TS24 = 10111YR0). If specific T1DM

elements need to be inserted and others bypassed, the processor conf igures TDL1 or TDL2 to

selectively insert only the desired bits. T1DM sync pattern, R-bits, and/or Y-bits. The

processor accomplishes this by programming data link bit enables [DL1_BIT; addr 0A5 or

DL2_BIT; addr 0B0].

To insert FDL, the processor configures TDL1 to operate over the F-bit channel during odd

frames [DL1_TS; addr 0A4] and Automatic Performance Report Messages [AUTO_PRM;

addr 0AA] or manually programs TDL1 to send each message.

Table 3-15. E1 Transmit Fr amer Mo des (T1/E1N = 0)

TFRAME Fram er Mode TS0 Overhead Insertion Yellow Alarms

MFAS FEBE CRC4 FAS YEL MYEL

00XX FAS Only One s Ones Ones Yes Y0 –

01XX FAS + CRC Yes Yes Yes Yes Y0 –

10XX FAS + CAS Ones Ones Ones Yes Y0 Y16

11XX FAS + CRC + CAS Y e s Yes Yes Yes Y0 Y16

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-57

Table 3-16. T1 Transmit Fr amer Mo des (T1/E1N = 1)

TFRAME Framer Mode F-bit Overhead Insertion Yellow Alarms

Fs FPS CRC6 Ft YEL MYEL

0000 FT Only Ones – – Y es Y B2 –

0100 SF Yes – – Yes YB2 –

0101 SF + JYEL Yes – – Yes YJ –

100X SLC Yes – – Yes YB2 –

0001 ESF + No CRC – Yes Ones – YB2 YF

1100 ESF + Mimic CRC – Yes Y es – YB2 YF

1101 ESF + Force CRC – Yes Yes – YB2 YF

Table 3-17. Criteri a for E1 Loss/Recovery of Transmit Frame A lignm ent

Mode Description

FAS Basic Frame Alignment (BFA) is recovered when the following search criteria are satisfied:

•FAS patte rn (0011011) is f o und in frame N.

•Frame N+1 contains bit 2 equal to 1.

•Frame N +2 also contains FAS pattern (0 011011).

During FAS only modes, BFA is recovered when the following search criteria are satisfied:

•FAS patte rn (0011011) is f o und in frame N.

•No mimics of the FAS pattern present in frame N+1 .

•FAS patte rn (0011011) is f o und in frame N+2.

NOTE(S): If FAS pattern is not found in frame N+2 or FAS mimic is found in frame N +1, then the search

restarts in frame N+2.

Transmit Loss of Frame (TLOF) al ignment i s declared when:

•Three consecutive FAS pattern errors are detected, where FAS pattern consists of a 7-bit (x0011011)

pattern in FAS frame s as well as bit 2 eq ualling one in NFAS frames.

MFAS MFAS—CRC Multiframe Alignment is recovered when the following search criteria are satisfied:

•BFA is recovered, identifying FAS and NFAS frames.

•Within 6 ms after BFA, bit 1 of NFAS frames contains the first MFAS pattern (001011xx).

•With in 8ms after BFA, bit 1 of NFAS frames contains the second MFAS pattern (001011x x), aligne d

to first MFAS.

MF AS errors do not cause Transmit Loss of Frame (TLOF) alignment.

CAS CAS Multiframe Alignment is recovered when the following search criteria are satisfied:

•BFA is recovered, iden tifying TS0 through TS31.

•MAS (0000xxxx) Multiframe Alignment Signal pattern is found in the first 4 bits of TS16, and 8 bits

of TS16 in preceding frame contains nonzero value.

CAS errors do not cause Transmit Loss of Frame (TLO F) alignment.

3.0 Registers CX28394/28395/28398

3.12 Transmitter Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-58 Conexant 100054E

Table 3-18. Criteri a for T1 Loss/Recovery of Transmit Frame A lignm ent

Mode Description

FT Only Terminal Frame Alignment is recovered when:

•One and only one valid Ft pattern (1010) is found in 12 alternate F-bit locations (3 ms), where F-bits

are sep arated by 193 bi ts.

Transmit Loss of Frame (TLOF) al ignment i s declared when:

•Number of Ft bit errors detected meets se lected loss of frame criteria [TLOFA–TLOFC ; addr 071].

SF S uperframe alig nment is recovered when:

•Te rminal frame alignment is recovered, identifying Ft bits.

•Depends on SF submode:

If JYEL:

If SF patte rn (00111x) found in F s bits

If no JYEL:

SF patt ern (0011 10) found in Fs bits. Fs errors do not c ause Transmit Loss of Frame (TLOF) a lign-

ment.

Transmit loss of frame ali gnment (TLOF) declared whe n:

•Number of Ft bit errors detected meets se lected reframe criteria [TLOFA–TLOFC ; addr 071]. Notice

that Fs bit multiframe errors are reported in TMER R [ISR0; addr 00B], but do not cause a loss of

transmit frame al ignment.

SLC Superfra me alignment is recovered when:

•Te rminal frame alignment is recovered, identifying Ft bits.

•SLC pattern (refer to Table A-3, SLC - 96 Fs Bit Cont ents) found in 16 of 32 Fs bits accordin g to

Bellcore TR-TSY-000008.

Fs errors do not cause Transmit Loss of Frame (TLOF) alignment .

Transmit loss of frame ali gnment (TLOF) declared whe n:

•Number of Ft bit errors detected meets se lected reframe criteria [TLOFA–TLOFC ; addr 071]. Notice

that Fs bit multiframe errors are reported in TMER R [ISR0; addr 00B], but do not cause a loss of

transmit frame al ignment.

ESF Extended superframe alignment is recovered when:

•Valid FPC candidate located (001011). Candidate bits are each separated by 772 digits and received

without pattern errors:

If on ly one vali d FPS candidate and:

No CRC mode: align to FPS regardless of CRC6 comparison.

Mimic CRC mode: align to FPS regardless of CRC6 comparison.

Force CRC mod e : align to FPS only if CRC6 is correct.

If two or more valid FPS candidates and:

No CRC mode: do not align (INVALID status)

Mimic CRC mo de: align to first FPS with correct CRC6.

Force CRC mode: ali gn to first FPS with corre ct CRC6 .

Transmit loss of frame ali gnment (TLOF) declared whe n:

•Number of FPS pattern e r ro rs detected me ets selected loss of frame crit eria [TLOFA–TLOFC;

addr 071].

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-59

071—Transmitter Configuration (TCR1)

TNRZ Transmit NRZ Data—Transmit dual-rail unipolar outputs TPOSO/TNEGO are replaced by

non-retur n to zero unipolar data (TNRZO) and transmit multiframe sync (MSYNCO). Both

outputs are clocked on the rising edge of transmitter clock (TCKI). TNRZ must be written to 1

on the CX28395 device.

0 = TPOSO/TNEGO encoded per TZCS[1:0]

1 = TPOSO/TNEGO replaced by TNRZO/MSYNCO

NOTE: MS YNCO activ e (high) al w a ys marks the first bit of transmit multiframe according to

the selected transmit framer mode.

TABORT Abort/Disable TX Offline Framer—Offline framer ignores reframe requests from the online

framer (TLOF) and aborts any in progress TLOF reframe requests. Loss of frame status

[TLOF; addr 048 ] is not af fe cted. While TABOR T r emains acti v e, of fli ne framer r esponds onl y

to the processor force reframe request (TFORCE), which allows the processor to manually

control reframe criteria or lock out changes in the current transmit frame alignment.

0 = normal framer operation

1 = framer disabled

TABORT also interacts with EMBED [addr 0D0] to select which data stream is examined

by online and offline transmit framer during embedded framing modes. If EMBED is active,

TXDATA output from TSLIP is examined and used to align the TX timebase. Otherwise,

TPCMI data stream is examined and used to align the TSB timebase as given in Table 3-19.

TFORCE Force TX Reframe (auto clear)—Forces the offline framer to perform a single reframe

according to the selected transmit framer mode. TFORCE is automatically cleared when the

framer ack nowledges a requ est [ ACTIVE; addr 017] . The pr ocessor does not typi cal ly need to

force reframe since online framer reframe request (TLOF) is active when reframe criteria

TLOFC–A is met. Ho w ev er , the processo r may wish to force reframe if frame or CRC bit error

ratio indicates the framer has aligned to a mimic pattern.

0 = no effect

1 = force TX reframe

7 6 5 4 3 2 1 0

TNRZ TABORT TFORCE TLOFC TLOFB TLOFA TZCS[1] TZCS[0]

Table 3-19. Transmit Framer Position

TABORT EMBED TSB Alignment Tx Alignment Tx Framing Mode Notes

0 0 TPCMI Flywheel Transmit Framing (1–5)

0 1 TFSYNC/TMSYNC TXDATA Embedded Framing (6–8)

1 X TFSYNC/TMSYN C Flywheel Normal (5, 6)

NOTE(S):

1. TFSYNC and TMSYNC must be programmed as outputs.

2. Offline framer examines TPCMI to supply TSB frame alignment.

3. Onli ne framer exam ines TPCMI to s upply TSB multiframe alignment.

4. SBI mode must mat ch 2048k or 1544k line rate.

5. TX timebase flywheels at ini tial alignment un til TSB_CTR or TX_ALIGN [addr 0D4 ].

6. TSB tim ebase flywheel s if TFSYNC/TMSYNC programmed as outputs.

7. Offline framer exa mines TXDATA to supply TX frame alig nment.

8. Onli ne framer examines TXDATA to supply TX multiframe alignment.

3.0 Registers CX28394/28395/28398

3.12 Transmitter Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-60 Conexant 100054E

TLOFC–TLOFA Transmit Loss Of Frame Criteria—Deter mines the number of frame errors that the online

framer must detect before declaring loss of frame alignment [TLOF; addr 048]. Refer to

TFRAME [addr 070] to find which frame bits are monitored during the selected framer mode.

TZCS[1: 0] Transmit Zero Code Suppression—Selects ZCS and Pulse Density Violation (PDV)

enforcement options for TPOSO/TNEGO outputs. B8ZS and HDB3 replace transmitted

sequences of 8 zeros or 4 zeros with a recoverable code and are standard T1 and E1 line code

options, respectively (see Table 3-20).

T1/E1N TLOFC–A Reframe Criteria

0 100 Three consecutive FAS errors

1 001 Two out of four frame bit errors

1 010 Two out of five frame bit errors

1 100 Two out of six frame bit errors

NOTE(S): All other TLOFC–A combina tions are invalid.

Tab le 3-20. Transmit Zero Code Su ppression

TZCS T1/E1N T1DM ZCS PDV Zero Code Substitution

(Sent left to right)

00 X X AMI None None

01 0 X HDB3 None 00 0V or B0 0V

01 1 X B8ZS None 000VB0VB

10 1 1 UMC None 10011000

11 1 X AMI Enforced on PDV errors

AMI Altern ate Mark Inversion. Bipolar li ne code forces suc cessive ones to alternate t heir output pu lse polarity. Analog and

digital dual-rail outputs are always AMI encod ed, although certain AMI codes are modified to include zero

suppression.

HDB3 Prior to tran smission, 4 consecutive zeros are subst it uted by 000 V or B 00V code, whe r e B is an AMI pulse an d V is a

bipolar violation. ZCS encoder selects the code which will force the BPV output polarity opposite that of the prior BPV.

B8ZS P rior to transmi ssion, 8 con secutive zeros a r e substitute d by 000VB0VB code, where B is an AMI encoded pulse and

V is a bipolar violation.

PDV Enforcer overwrites transmit zeros that would otherwise cause output data to fail to meet the minimum required pulse

density per ANSI T1.403 sliding window. Note that the enforcer will never overwrite a framing bit and is not applicable

during E1 mode. Note that each PDV enforced one causes a nonrecoverable transmitted bit error.

UMC Unassigned Mux Code. DS0 channels that contain 8 zer os are substituted w ith the 10011000 code, per Bel lcore

TA-TSY-000278. Note that the recei ver's ZCS decoder cannot recover original data content from UMC encoded sig nal .

NOTE(S): PRBS, inband loo pback, and YB2 a larm insertion occur after PDV enf orcement. Therefore, output data might violate

minimum pulse density requirements while these functions are active.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-61

072—Transmit Frame Format (TFRM)

TFRM controls the insertion of overhead bits generated by transmit frame and alarm formatters. Bypassed

overhead bits flow transparently from TPCMI system bus input through TSLIP buffer.

Unused bits are reser ved and should be written to 0.

INS_M YEL In sert Mu ltiframe Yellow Alar m —Applic able to E1 modes on ly. Enables the alarm formatter

to output Y16 Multiframe Yellow Alarm. Once enabled, TMYEL and AUTO_MYEL [addr

075] control the alarm output state. This bit must be set to 0 in T1 modes.

0 = bypass

1 = insert multiframe yellow ala rm

INS_YEL Insert Yellow Alarm—The alarm formatter outputs yellow alarms YB2 or YJ during T1

modes; or Y0 dur i ng E1 mod e s. In E SF f ra med T 1 mode, th e YF Yellow Alarm is tr ansmi t ted

by programming the DL1 data link controller and by transmitting the appropriate bit oriented

code message (BOP message). Once enabled, TYEL and AUTO_YEL [addr 075] control the

yel lo w alarm output state. If the sy stem wa nts to b ypass JYEL (Fs bit in frame 12), t hen it must

bypass all Fs bits with INS_MF [addr 072].

0 = bypass

1 = insert yellow alarm.

INS _MF In sert Multiframe Alignmen t—The frame for matter ou tputs 6-bit SF alignm ent pattern in T1

mode, o r 6-bit M FAS alignment pattern in E1 mode. INS _MF should be set while T FRAME

(addr 070) selects Fs (T1) or MFAS (E1) alignment.

0 = bypass

1 = insert multiframe alignment

INS_FE Insert FEBE— During E1 mode, the alarm formatter aut omatically outpu ts TS0 bit 1 o f fr ame

13 (FEBE13) and frame 15 (FEBE15) in response to received CRC4 err ors. FEBE13 is active

low for each received CRC4 err or detected in SMF I. FEBE15 is active low for each received

CRC4 error detected in SMF II. INS_FE should be set while TFRAME (addr 070) selects

FEBE (E1) alignment.

0 = bypass

1 = insert FEBE

INS_CRC Insert Cyclic Redundancy Check—The frame formatter outputs the calculated CRC6 bits in

T1 mode or CRC4 bits in E1 mode.

0 = bypass

1 = insert cyclic redundancy check

INS_FBI T Insert Terminal Frami ng—The frame formatter outputs a 2-bit Ft alignmen t pattern in F-bi ts of

odd frames (SF framing) or FPS framing pattern (ESF framing) during T1 modes—or 8-bit

FAS/NFAS alignment pattern during E1 modes. INS_FBIT should be set while TFRAME

(addr: 070) selects Ft (T1, SF), FPS (T1, ESF), or FAS (E1) alignment.

0 = bypass

1 = insert termina l fra ming

If F-bits are bypassed while TSLIP is enabled, the system must either use embedded T1

framing or apply at least a double frame (250 µs) multiframe sync pulse (TMSYNC) to

provide odd/even frame alignment.

7 6 5 4 3 2 1 0

— — INS_MYEL INS_YEL INS_MF INS_FE INS_CRC INS_FBIT

3.0 Registers CX28394/28395/28398

3.12 Transmitter Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-62 Conexant 100054E

073—Transmit Error Insert (TERROR)

Transmit error inser tion capabilities are provided for system diagnostic, production test, and test equipment

applications. Writing a one to any TERROR bit injects a single occurrence of the respective error on

TPOSO/TNEGO or TNRZO outputs. Writing a zero has no effect. Multiple transmit errors can be generated

simultaneously. Injected errors also affect data sent during a Framer Loopback [FLOOP; addr 014].

TSERR Inject CAS Multiframe (MAS) Error—Injects a single MAS pattern error. TSERR performs a

logical inversion of the first M AS bit transmitted.

0 = no effect

1 = inject MAS error

TMERR Inject Multiframe Error—Injects a single Fs bit (T1) or MFAS (E1) bit error. TMERR

performs a logical in version of the next multiframe bit transmitted. Processor can pace writing

to TMERR to control which MFA S bit is errored.

0 = no effect

1 = inject m ultiframe e rror

TBERR In je ct PRBS Test Pattern Error—Injects a si ngle PRBS error by logically inverting the next

PRBS generator output bit. Processor can pace writing to TBERR to create the desired bit

err or ratio (up to 5E-3 if TBERR asserted 1/192 bits at every frame interrupt).

0 = no effect

1 = inject PRBS error

BSLIP/TCOFA Inject Transmit COFA—Forces a 1-bit shif t in the locatio n of tra nsmit frame al ignment by

deleting (or inserting) one bit position from the transmit frame. During E1 modes, BSLIP

determines in which directi on the bit slip will occu r. In T1 modes, only one bit deletion is

provided. TCOFA alters the extraction rat e o f dat a from t he transmit sl ip buffer; t hus, repea ted

TCOFAs eventually cause a controlled frame slip where one frame of data is repeated

(T1/BSLIP = 0) or one frame of data is deleted (BSLIP = 1).

TCERR Inject CRC Error—Inje ct s a single CRC6 (T1) or CR C4 (E1) bit error. TCERR performs a

log ical inv ersion of the ne xt CRC bit transmitted. The processor can pace writing to TCERR to

control which CRC bit is errored.

0 = no effect

1 = inject CRC er ror

TFERR Inject Frame Bit Error—Injects a single Ft, FPS, or FAS bit error depending on the selected

transmit framer mode. TFERR performs a logical inversion of the next frame bit transmitted.

The processor can pace writing to TFERR, to control which frame bit is errored.

0 = no effect

1 = inject frame error

7 6 5 4 3 2 1 0

TSERR TMERR TBERR BSLIP TCOFA TCERR TFERR TVERR

TCOFA T1/E1N BSLIP Transmit COFA

0XXNo effect

100Inhibit output of TS0 bit 1 for one frame

101Insert 1 prior to FAS pattern for one frame

11XInhibit output of F-bit for one frame

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-63

TVERR Inject Line Code Violation—Injects a single LCV error, depending on line mode and ZCS

selected. In T1 mod e, the L CV injector w aits for transmission of two c onsecuti v e p ulses on t he

data output before performing BPV error insertion and clearing the TVERR bit. Therefore, a

BPV error cannot be injected i nto a transmit data stre am that does not contain t wo cons ecuti v e

ones. TVERR is latche d until an opportunity to in ject a BPV error is presen ted. This prevents

the receiving end from de tecting: frame or multiframe bit errors, CRC errors, multiple BPV

err ors (due to ZCS pattern corr uption), or PRBS test pattern bit errors as a consequence of

error insertion. In E1 mode with HDB3 selected, the LCV injector sends two consecutive

BPVs of the same polarity, which causes the receiving end to detect a single LCV error.

0 = no effect

1 = inject line code violation

074—Transmit Manual Sa-Byte/FEBE Configuration (TMAN)

INS_SA[ 8] Manual Sa8-Byte Transmit (0-bypass)

INS_SA[ 7] Manual Sa7-Byte Transmit (0-bypass)

INS_SA[ 6] Manual Sa6-Byte Transmit (0-bypass)

INS_SA[ 5] Manual Sa5-Byte Transmit (0-bypass)

INS_SA[ 4] Manual Sa4-Byte Transmit (0-bypass)

FEBE_II Transmit FEBE Frame 15.

FEBE_I Transmit FEBE Frame 13.

TFEBE Manual Transmit FEBE (Overrides INS_FE; addr 072)—Prov ides a manual override for

FEBE bits that are normally sent by the alarm formatter [INS_FE; addr 072]. When active,

FEBE_I control s the data o utput in TS0 bi t 1 of fr ame 13 ( FEB E13) an d, FEBE _II co ntro ls th e

data output in TS0 bit 1 of frame 15 (FEBE15).

7 6 5 4 3 2 1 0

INS_SA[8] INS_SA[7] INS_SA[6] INS_SA[5] INS_SA[4] FEBE_II FEBE_I TFEBE

INS_FE TFEBE FEBE[13] FEBE[15] Description

0 X TPCMI TPCMI Bypass FEBE

1 0 SMF I SMF II Automatic FEBE

1 1 FEBE_I FEBE_II Manual FEBE

NOTE(S): Automatic FEBE insertio n uses two separate CRC4 error signals from t he receiver to

indicate SMF I and SMF II errors. Each error signal is latched and held for one full multiframe to

compensate for phase differences b etween receive and transmit multiframe t iming.

3.0 Registers CX28394/28395/28398

3.12 Transmitter Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-64 Conexant 100054E

075—Transmit Alarm Signal Configuration (TALM)

Unused bits are reser ved and should be written to 0.

AISCLK Enab le Automatic ACKI Switching—When AISCLK is acti v e and the clock monit or reports a

loss of tran smit clock [TLOC; addr 04 8], the transmitter clock is automa tically switche d to

reference TIACKI or EIACKI instead of TCKI. The transmitte r is also forced to send AIS (all

ones) data. If both AISCLK and TAIS [addr 075] are active, AIS is transmitted using TIACKI

or EIACKI clock regardless of the clock monitor status. AISCLK should be set only if the

system supplies an alternate line rate clock on TIACKI for TI or EIACKI for EI applications.

AUTO_MYEL/TMYEL Manual/ A utomatic Transmit Multiframe Ye llow Alarm—Man ual mode se nds alarm for as

long as TMYEL is active. Automatic mode sends alarm for the duration of a receive loss of

multiframe alignment [SRED; addr 049].

AUTO _YEL /TY EL Manual/Automatic Transmit Yellow Alar m—Manual mode sends the alarm for as long as

TYEL is active and yellow alarm insertion [INS_YEL; addr 072] is enabled. Automatic mode

sends yellow alarm for the duration of a receive loss of frame alignment [FRED; addr 049].

7 6 5 4 3 2 1 0

— AISCLK AUTO_MYEL AUTO_YEL AUTO_AIS TMYEL TYEL TAIS

Inputs Status Transmit

TAIS AUTO_AIS AISCLK RLOS TLOC CLOCK DATA

00 X X 0TCKI Normal

00 1 X 0TCKI Normal

0X 1 X 1TI/EIACKIAIS

01 X 0 0TCKI Normal

01 0 0 1TCKI Normal

01 0 1 XTCKI AIS

1X 1 X XTI/EIACKIAIS

1X 0 X XTCKI AIS

00 0 X 1TCKI Normal

01 1 1 0TI/E1ACKIAIS

INS_MYEL TMYEL AUTO_MYEL Transmit Multiframe Yellow

0 X X Supp li e d by TPC MI

10 0Inactive

1 0 1 Follows SRED status

11 XActive

NOTE(S): To transmit T1DM yellow alarm (Y24), the processor must program TDL1,

TDL2, or TSL IP buffer to transmit Y-bit outp ut in time slot 24.

INS_YEL TYEL AUTO_YEL Transmit Yellow Alarm

0 X X Supplied by TPCMI

1 0 0 Inactive

1 0 1 Follows FRED status

11 XActive

NOTE(S): To transmi t T 1D M yellow alarm (Y24), proc essor must program TDL1,

TDL2 or TSLIP buffer to transmit Y-bit output in time slot 24.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-65

AUTO_AI S /TAIS Manual/Automatic Transmit Alarm Indication Signal—When activated manually (TAIS) or

automatically (AUTO_AIS), the alarm formatter replaces all data output on

TPOSO/TNEGO/T NRZO with an unframed al l ones signal (AIS). This includes rep lacing data

from the rec ei ver d uring line loopb ack [LLOOP; add r 014]. Auto matic mode send s AIS for the

duration of receive loss of signal [RLOS; addr 047]. If AISCLK [addr 075] is enabled, then

TAIS also pro vides manual s w itch control over A C KI clock input. AUTO_AIS does not af fect

ACKI switching.

AIS transmission [TAIS, AUTO_AIS; addr 075, or AISCLK; addr 075] does not affect

transmit data that is looped back to the receiver during framer loopback [FLOOP; addr 014].

This allows both FLOOP and LLOOP to be active simultaneously, during a loss of signal,

without disrupting data in the framer loopback path.

076—Transmit Test Pattern Configuration (TPATT)

Unused bits are reser ved and should be written to 0.

TPSTART Enable Test Pattern Transmission.

FRAMED PRBS Framed—When set, the PRBS pattern does not overwrite framing bit positions and is

stopped during these bit periods. In T1 mode, the frame bit (ev ery 193rd bit) is not o verwritten.

In E1 mode, the PRBS test pattern is not written to time slot 0 (FAS and NFAS words) and

time slot 16 (CAS sign a lling word) if CAS framing is also sele ct e d. CAS framing is selected

by setting TFRAME[3] to 1 in the Transmit Configuration register [TCR0; addr 070]. If

FRAMED is disabled, the test pattern is transmitted in all tim e slots.

ZLIMIT Enable Zero Limit; 7/14 depending on pattern.

TPATT[1:0] PRBS test patterns used by RPATT [addr 041] and TPATT [addr 076] are defined in the ITU

standards O.151 and O .152 to use ei ther inverted or non-in verted data. Standard dat a inversion

is used for the selected PRBS test pattern unless ZLIMIT is enabled, in which case the test

pattern uses non-inverted data (see Table 3-12).

TAIS AUTO_AIS AISCLK Transmit Data Transmit Clock (TCKO)

00 0

Normal, No AIS TCKI

00 1

AIS during TLOC TI/EIACKI w hile TLOC

01 0

AIS During RLOS TCKI

01 1

AIS During TLOC or RLOS TI/EIA CKI while TLOC

1X 0

Manua l AIS TCKI

1X 1

Manual AIS and ACKI ACKI

NOTE(S): Systems that transm it framed all ones can utilize inband loopback code generator

[TLB ; addr 0 77] to send all ones in payloa d only.

7 6 5 4 3 2 1 0

— — — TPSTART FRAMED ZLIMIT TPATT[1] TPATT[0]

3.0 Registers CX28394/28395/28398

3.12 Transmitter Registers Quad/x16/Octal—T1/E1/J1 F ramers

3-66 Conexant 100054E

077—Transmit Inband Loopback Code Configuration (TLB)

Unused bits are reser ved and should be written to 0.

LB_LEN[1:0] Inband Loopback Code Len gth (from LBP):

00 = 4 bits

01 = 5 bits

10 = 6 bits

11 = 7 bits

UNFRAM ED Loopback Code Overwrites Framing.

LBSTART Start Inband Loopback Code Transmission.

Tab le 3-21. Transmit PRBS Test Pattern Meas urements

FRAMED ZLIMIT TPATT Tes t Pattern Measurements Inversion

0 0 00 Unframed 2^11 No

0 0 01 Unframed 2^15 Yes

0010

Unframed 2^20 No

0011

Unframed 2^23 Yes

0 1 00 Unframed 2^11 wi th 7 zero limit No

0 1 01 Unframed 2^15 wi th 7 zero limit No

0 1 10 Unframed 2^20 with 14 zero limit (QRSS/QRS/QRTS) No

0 1 11 Unfr amed 2^23 with 14 z e ro limit (non-st d) No

1 0 00 Framed 2^11 No

1 0 01 Framed 2^15 Yes

1 0 10 Framed 2^20 No

1 0 11 Framed 2^23 Yes

1 1 00 Framed 2^11 with 7 zero limit No

1 1 01 Framed 2^15 with 7 zero limit (non std) No

1 1 10 Framed 2^20 with 14 zero limit (QRS S/QRS/QRTS)) No

1 1 11 Framed 2^23 with 14 zero limit (non-std) No

7 6 5 4 3 2 1 0

— — — — LB_LEN[1] LB_LEN[0] UNFRAMED LBSTART

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.12 Transmitter Registers

100054E Conexant 3-67

078—Transmit Inband Loopback Code Pattern (LBP)

Unused bits are reser ved and should be written to 0.

LBP[1] First bit transmitted

LBP[2] Second bit transmitted

LBP[3] Th ird bit transmitted

LBP[4] Fourth bit transmit ted

LBP[5] Fifth bit transmitted

LBP[6] Sixth bit transmitted

LBP[7] Seventh bit transmitted

7 6 5 4 3 2 1 0

LBP[1] LBP[2] LBP[3] LBP[4] LBP[5] LBP[6] LBP[7] —

3.0 Registers CX28394/28395/28398

3.13 Trans m it Sa- By te Buffers Quad/x16/Octal—T1/E1/J1 Framers

3-68 Conexant 100054E

3.13 Transmit Sa-Byte Buffers

Five transm it Sa-Byte buffers (TSA4–TSA8) are used to inser t Sa-bits in TS0. The entire group of 40 bits is

sampled e very 16 frames, coincide nt with the TMF interrupt bound ary [addr 008]. Bit 0 from each TSA regi ster

is then i nserted during frame 1, Bit 1 during frame 3, Bi t 2 during fr ame 5 and so on. This gi v es the processor up

to 2 ms after TMF i nter rupt to write new Sa-Byt e buffer values. Transmit Sa-bits maintai n a fixed relatio nsh ip

to the transmit CRC mu ltiframe.

07B—Transmit Sa4 Byte Buffer (TSA4)

TSA4[7] Sa4 bit transmitted in frame 15

TSA4[6] Sa4 bit transmitted in frame 13

TSA4[5] Sa4 bit transmitted in frame 11

TSA4[4] Sa4 bit tr ansmitted in frame 9

TSA4[3] Sa4 bit tr ansmitted in frame 7

TSA4[2] Sa4 bit tr ansmitted in frame 5

TSA4[1] Sa4 bit tr ansmitted in frame 3

TSA4[0] Sa4 bit tr ansmitted in frame 1

07C—Transmit Sa5 Byte Buffer (TSA5)

TSA5[7] Sa5 bit transmitted in frame 15

TSA5[6] Sa5 bit transmitted in frame 13

TSA5[5] Sa5 bit transmitted in frame 11

TSA5[4] Sa5 bit tr ansmitted in frame 9

TSA5[3] Sa5 bit tr ansmitted in frame 7

TSA5[2] Sa5 bit tr ansmitted in frame 5

TSA5[1] Sa5 bit tr ansmitted in frame 3

TSA5[0] Sa5 bit tr ansmitted in frame 1

7 6 5 4 3 2 1 0

TSA4[7] TSA4[6] TSA4[5] TSA4[4] TSA4[3] TSA4[2] TSA4[1] TSA4[0]

7 6 5 4 3 2 1 0

TSA5[7] TSA5[6] TSA5[5] TSA5[4] TSA5[3] TSA5[2] TSA5[1] TSA5[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.13 Transmit Sa-Byte Buffers

100054E Conexant 3-69

07D—Transmit Sa6 Byte Buffer (TSA6)

TSA6[7] Sa6 bit transmitted in frame 15

TSA6[6] Sa6 bit transmitted in frame 13

TSA6[5] Sa6 bit transmitted in frame 11

TSA6[4] Sa6 bit tr ansmitted in frame 9

TSA6[3] Sa6 bit tr ansmitted in frame 7

TSA6[2] Sa6 bit tr ansmitted in frame 5

TSA6[1] Sa6 bit tr ansmitted in frame 3

TSA6[0] Sa6 bit tr ansmitted in frame 1

07E—Transmit Sa7 Byte Buffer (TSA7)

TSA7[7] Sa7 bit transmitted in frame 15

TSA7[6] Sa7 bit transmitted in frame 13

TSA7[5] Sa7 bit transmitted in frame 11

TSA7[4] Sa7 bit tr ansmitted in frame 9

TSA7[3] Sa7 bit tr ansmitted in frame 7

TSA7[2] Sa7 bit tr ansmitted in frame 5

TSA7[1] Sa7 bit tr ansmitted in frame 3

TSA7[0] Sa7 bit tr ansmitted in frame 1

7 6 5 4 3 2 1 0

TSA6[7] TSA6[6] TSA6[5] TSA6[4] TSA6[3] TSA6[2] TSA6[1] TSA6[0]

7 6 5 4 3 2 1 0

TSA7[7] TSA7[6] TSA7[5] TSA7[4] TSA7[3] TSA7[2] TSA7[1] TSA7[0]

3.0 Registers CX28394/28395/28398

3.13 Trans m it Sa- By te Buffers Quad/x16/Octal—T1/E1/J1 Framers

3-70 Conexant 100054E

07F—Transmit Sa8 Byte Buffer (TSA8)

TSA8[7] Sa8 bit transmitted in frame 15

TSA8[6] Sa8 bit transmitted in frame 13

TSA8[5] Sa8 bit transmitted in frame 11

TSA8[4] Sa8 bit tr ansmitted in frame 9

TSA8[3] Sa8 bit tr ansmitted in frame 7

TSA8[2] Sa8 bit tr ansmitted in frame 5

TSA8[1] Sa8 bit tr ansmitted in frame 3

TSA8[0] Sa8 bit tr ansmitted in frame 1

7 6 5 4 3 2 1 0

TSA8[7] TSA8[6] TSA8[5] TSA8[4] TSA8[3] TSA8[2] TSA8[1] TSA8[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.14 Bit-O r ie nte d Pro t ocol Regist er s

100054E Conexant 3-71

3.14 Bit-Oriented Protocol Registers

The Bit Oriented Protocol (BOP) transceiver sends and receives BOP messages, including ESF Yellow Alarm.

These messages consist of repeated 16-bit patterns with an embedded 6-bit codeword. The BOP message

channel is configured to operate over the same channel selected by the DL1 Time Slot Enable Register

[DL1_TS; addr 0A4]. The channel must be configured to operate over the FDL channel in order for BOP

messages to convey Priority, Command, and Response codeword messages according to ANSI T1.403,

Section 9.4.1. Therefore, DL1 must be configured and enabled to allow BOP operation, as described in

Table 3-22.

The pr ece dence of tran smitted BO P messages with respect to curr e nt DL1 transm it activity is configurable

[TBOP_MODE; addr 0A0]. BOP messages can also be transmitted during E1 mode, although the 16-bit

codeword patter n has not currently been adopted as an E1 standard. BOP message format:

0xxxxxx0 11111111 (transmitted right to left)

[543210] 6-bit codeword

0A0—Bit Oriented Protocol Transceiver (BOP)

RBOP_START BOP Receiver Enable—When active, BOP receiver searches FDL channel for data that

matches a 16-bit pattern in the form of 0xxxxxx011111111, where xxxxxx equals a 6-bit

codeword. Otherwise, BOP receiver is disabled.

0 = disabled

1 = BOP receiver enable

RBOP_INTEG RBOP Integration—Requires receipt of two identical consecutive 16-bit patterns (without

errors or gaps between patterns) to validate a single codeword. In this case, an er rored

codewo rd does not increment the pattern count. RBOP integration must be enabled to meet

codeword detection criteria while receiving 1E-3 bit error ratio. RBOP_INTEG adds at least

one to the numb er of successi ve 16-b it patterns needed to qualify receipt of BOP messa ge (2 in

a row counts as 1 pattern, 11 in a row counts as 10, and 26 in a row counts as 25).

0 = no integration

1 = RBOP integration

Table 3-22. DLI Configuration for T1 -ESF, FDL

Datalink Configuration Registers Value Description

DL1_TS [addr 0A4] 0 × 40 Enabling odd frames, Fbit (T1)

DL1_BIT [addr 0A5] 0 × 00 Select bits to use in time slot.

DL1-CT L [ad d r 0A6] 0 × 03 Select normal FI FO mode, FCS, Tx enabled, Rx enabled.

RDL1 _FFC [addr 0A7] 0 0###### ##### # is the threshold for rec eiver FIFO near full.

TDL1_FEC [ad dr 0AB] 00###### ###### is the thre shold FIFO near empty.

7 6 5 4 3 2 1 0

RBOP_START RBOP_INTEG RBOP_LEN[1] RBOP_LEN[0] TBOP_LEN[1] TBOP_LEN[0] TBOP_MODE[1] TBOP_MODE[0]

3.0 Registers CX28394/28395/28398

3.14 Bi t-Ori ented Pro tocol Re gisters Quad/x16/Octal—T1/E1/J1 Framers

3-72 Conexant 100054E

RBO P_LEN[1:0] RBOP Message Length—Selects the number of successive identical 16-bit patterns that are

needed to qualify receipt of a single BOP message and to update RBOP [addr 0A2] with the

recei ved code w ord. At t his time RBOP interrupt [ISR1; addr 00A] is also acti v ated. Successi v e

patterns can be se par at ed by any number of bits as l on g as th ey do n ot contain a d ifferent valid

codeword.

TBOP_LEN[1:0] TBOP Message Length—Selects the number of repeated 16-bit patterns sent as a single

message when a TBOP [addr 0A1] codeword is written. Another message, with the same or

different codeword value, can be written to TBOP as soon as prior message start is

acknowledged via activation of TBOP inter rupt [ISR2; addr 009]. If no new message is

written, the FDL channel returns to TDL1 output control upon completion of message

transmission. Processor changes TBOP_LEN to end transmission of a continuously repeating

message.

TBO P_M ODE[1:0] Transmit BOP Mode—Enables BOP transmitter and establishes priority of TBOP [addr 0A1]

output in relation to TDL1 [addr 0AD] output. When TBOP messages are given output

priority, any write to TBOP aborts T D L1 output with in the next eight FDL bit times and then

suspends TDL1 data output unt il TB OP ha s compl eted transmissi on. The processor can check

TMSG1 status [addr 0AE] before writing TBOP to determine if TDL1 output is idle. TDL1

buffer can be written while TBOP is granted priority.

When TDL1 messages are given output pr i ority, TBOP output is su spended w hen the TDL1

buffer becomes non-empty. Furthermore, TBOP is forced to wait until the TDL1 buffer is

empty and the TDL1 output is in the idle state. If TBOP_LEN is continuous and TDL1/PRM

message output is pending, then TBOP will be suspended at the next 16-bit pattern boundary.

TDL1 priority is used to transmit PRM, DS1 Idle (ISID), or optional path maintenance (PID,

TSID) messages separated by ESF Yellow Alarm codewords as def ined in Annex D of ANSI

T1.403.

RBOP_LEN Succe ssive Patterns N otes

00 1 Single 16-bit pattern updates RBOP

01 10 Minimum command, response length

10 25 Preferred command, response length

11 Change RBOP updates on receipt of each new pattern

TBOP_LEN Repeated

Patterns Message

Length (ms) Notes

00 1 4 Single message sends 16 FDL bits

01 10 40 Minimum command, response length

10 25 100 Preferred command

11 Continuous Continuous Required for ESF yellow alarm

TBOP_MODE Mode Description

0X Disabled: TBOP writes are ignored

10 TBOP output priority

11 TDL1 output priority

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.14 Bit-O r ie nte d Pro t ocol Regist er s

100054E Conexant 3-73

0A1—Transmit BOP Codeword (TBOP)

TBOP[5] 6th bit transmitted

TBOP[4] 5th bit transmitted

TBOP[3] 4th bit transmitted

TBOP[2] 3r d bit transmitted

TBOP[1] 2nd bit transmitted

TBOP[0] Transmit BOP codeword, 1st bit tra nsmitted

0A2—Receive BOP Codeword (RBOP)

RBOP_LOST Previous Message Overwritten—Activated when RBOP is updated and RBOP_VALID is

already set, indicating that the previous codeword was never read by the processor.

0 = no error

1 = prior codeword lost

RBOP_VALID RBOP Message Valid—Set each time RBOP[5:0] is updated with a codeword value. Reading

from RBOP clears RBOP_VALID.

0 = no message or message read

1 = new RBOP message received

RBOP[5] 6th bit rece iv ed

RBOP[4] 5th bit rece iv ed

RBOP[3] 4th bit rece iv ed

RBOP[2] 3rd bit received

RBOP[1] 2nd bit received

RBOP[0] Receive BOP codeword, 1st bit received

7 6 5 4 3 2 1 0

— — TBOP[5] TBOP[4] TBOP[3] TBOP[2] TBOP[1] TBOP[0]

7 6 5 4 3 2 1 0

RBOP_LOST RBOP_VALID RBOP[5] RBOP[4] RBOP[3] RBOP[2] RBOP[1] RBOP[0]

3.0 Registers CX28394/28395/28398

3.14 Bi t-Ori ented Pro tocol Re gisters Quad/x16/Octal—T1/E1/J1 Framers

3-74 Conexant 100054E

0A3—BOP Status (BOP_STAT)

Real-time status of the BOP transmitter and receiver is reported primarily for diagnostic purposes.

TBOP_ACTIVE TBOP Active—Remains set for th e en tire lengt h of a message as de fined by T BOP_LEN[1:0]

[addr 0A0].

RBOP_ACTIVE RBOP Active—Is set as soon as eight ones are detected and remains set if subsequent 1st and

8th bits are zero. For pattern length 1, RBOP_ACTIVE is a short pulse reported at the end of a

received 16-bit pattern. For longer lengths, the signal goes high at the end of the first pattern

and is held a ct ive until the desired number (or change) of patterns is d etected. At this p oint

RBOP interrupt is generated. Consequently, this signal is usually high.

7 6 5 4 3 2 1 0

TBOP_ACTIVE RBOP_ACTIVE — — — — — —

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-75

3.15 Data Link Registers

Each framer contains two independent Data Link Controllers (DL1, DL2), which are programmed to send and

recei ve HDLC fo rmatted or unfo rmatted serial data o v er an y combination of bi ts within a select ed time slot. The

serial data channels operate at a multiple of 4 kbps up to the full 64 kbps time slot rate by selecting a

combination of time slot bits from odd, even, or all frames. DL1 and DL2 each contain a 64-byte receive and

64-byte transmit buffer which, function either as programmable length circular buffers or full-length data

FIFOs.

0A4—DL1 Time Slot Enable (DL1_TS)

DL1_ TS[7] Unchannelized—Test mode only; all time slots selected. Zero for normal operation.

DL1_ TS[6, 5] Frame Select—Transmit and receive data link 1 operates on data only during the specified

T1/E1 frames. Frame select options give the processor access to different types of data link

channels as well as overhead channels. Note that overhead bit insertion is performed after

TDL1, so internal transmitter overhead insertion must be bypassed [TFRM; addr 072] before

processor supplied overhead can be output from TDL1.

00 = all frames

01 = even frames only

10 = odd frames only

11 = no t valid

DL1_TS[4:0] Time Slot Word Enable—Transmit and receive data link 1 operates on data only during the

specified time slo t. During T1 mode, selecting ti me slot zero ena b les data link operation o n the

F-bit positions.

7 6 5 4 3 2 1 0

DL1_TS[7] DL1_TS[6] DL1_TS[5] DL1_TS[4] DL1_TS[3] DL1_TS[2] DL1_TS[1] DL1_TS[0]

DL1_TS[4:0] T im e Slot Enable

00000 F-bit (T1) or TS0 (E1)

00001 TS1

11110 TS30

11111 TS31

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-76 Conexant 100054E

0A5—DL1 Bit Enable (DL1_BIT)

DL1_BIT[7:0] DL1 Bit Select—Works in conjunction with DL1_TS [addr 0A4] to select one or more time

slot bits f or data l ink input and output. Any combinati on of bi ts may be enabled by writ i ng t he

corresponding DL1_BIT active (high). The LSB enables first bit transmitted or received, and

MSB enables eig hth bi t t ransmi tted or recei ved. DL1 _BIT ha s no ef fect when DL1_ TS sel ects

T1 F-bits.

0 = disable data link bit

1 = enable data link bit

0A6—DL1 Control (DL1_CTL)

Unused bits are reser ved and should be written to 0.

TDL1_RPT Circular Transmit Buffer Enable—Processor can fill the transmit FIFO [T DL1; addr 0AD]

with up to 64 b yte s (P ack6 or P ack8 bits /b yt e) of unformatted data to be sent repeatedly. Whil e

TDL1_RPT is active high, data written to TDL1 is held until the processor writes an end of

message [TDL1_EOM; addr 0AC]. Af te r TDL1_EOM is written, th e t r a nsmitter waits for the

be ginni ng of the ne x t ou tput multif r ame (based on the select ed t ransmi t fr ami ng mod e) befor e

sending the first byte of the circular buffer. Subsequent bytes are output in the selected time

slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the

processor writes new buffer data and another TDL1_EOM. This allows the processor to send

multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS or CAS overhead bits.

0 = normal transmit FIFO

1 = enable circular transmit buffer

DL1[1: 0] Data Link 1 Mode—Selects either HDLC-formatted (FCS or Non-FCS) transmit and receive

data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC

modes, the transmit/rec eive circuits perform zero insertion/removal afte r each occurrence of 5

consecutive ones contained in the message bits, FLAG (0x7E) charac ter insertion/r emov al

during idle channel conditions, and ABORT (0xFF) code inser tion/detection upon errored

channel cond itions. Refe r to ITU-T Recommendatio n Q .921 for comp lete detail s of the HDLC

link-layer protocol. FCS mode automatically generates, inserts, and checks the 16-bit Frame

Check Sequence (FCS) without passing FCS bits through transmit and receive FIFOs.

7 6 5 4 3 2 1 0

DL1_BIT[7] DL1_BIT[6] DL1_BIT[5] DL1_BIT[4] DL1_BIT[3] DL1_BIT[2] DL1_BIT[1] DL1_BIT[0]

7 6 5 4 3 2 1 0

— — — TDL1_RPT DL1[1] DL1[0] TDL1_EN RDL1_EN

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-77

Non-FCS mode passes all message bits that exist between the opening and closing FLAG

character s through the F IFOs, with out gen erating or ch ecking FCS bits . Non-FC S mode al lows

the processor to generate and check the entire contents of each HDLC frame. Unformatted

data link modes provide transparent channel access in which every data link bit transmitted is

supplied by the processor through TDL1 and each bit received is passed to the processor

through RDL1 [addr 0A8]. Pack8 and Pack6 unformatted mode options select the number of

bits per byte that are stored in transmit/receive FIFOs, eight or six bits, respectively. The only

data processing performed during unformatted mode is the alignment of transmitted and

recei ved data bits with respect to the transmit/recei v e multiframe.

00 = FCS

01 = No FCS

10 = Pack8

11 = Pack6

TDL1_EN Transmit Data Link 1 Enable—When enabled, transmitter begins to empty and to format the

contents of the transmit data link FIFO for output during the selected time slot bits according

to the sele cted DL1[1:0] mode. Also enables generation of transmitter d ata link inte rrupt

events.

0 = disabled

1 = enable transmit data link

RDL1_EN Receive Data Link 1 Enable—When enabled, receiver begins to format data from the selected

time slot bits and to fill the receive data link FIFO according to the selected DL1[1:0] mode.

Also enables generation of receiver data link interrupt events.

0 = disabled

1 = enable receive data link

0A7—RDL #1 FIFO Fill Control (RDL1_FFC)

MSG_FILL[1:0] Unformatted Message Fill Limit—Applicable only for Pack8 and Pack6 modes, the message

fill limit selects how many receive FIFO loc ations [RDL1; addr 0A8] are filled before the

receive data link generates an RFULL interr upt [ISR2; addr 009] and generates a

corresponding RDL1 Partial message status word entry. Fill limit thus determines how many

bytes co nstitute an un form atted message. Fill limits give the processor an alternative to using

RNEAR inter rupts to signal the end of a received unformatted message. Note the number of

bits per unformatted message must divide evenly by the number of bits monitored per

multiframe.

7 6 5 4 3 2 1 0

MSG_FILL[1] MSG_FILL[0] FFC[5] FFC[4] FFC[3] FFC[2] FFC[1] FFC[0]

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-78 Conexant 100054E

For example, SLC applications monitor Fs bits during even frames for a total of 36 bits

monitored out of 72 frames. Using Pack6 mode, that group of 36 Fs bits from each SLC

multiframe can be chosen to constitute one unformatted message by selecting a message f ill

limit which equals 6 bytes (of 6 bits/byte). In the SLC example, an RFULL interrupt would

then be generated every 9 ms on each SLC multiframe boundary. Fill limits provided for T1

cases are multiples of 6 bytes (i.e. 6, 12 or 18 FIFO locations) to hold 1 or more multiframes

worth of monitored data. In E1 mode, fill limits are multiples of 8 bytes to correspond with the

16 frame multiframe lengths (i.e. monitoring CRC4 in MFAS framing mode or TS16 in CAS

framing mode).

FFC[5:0] Near Full FIFO Thre shold—Sel ects FIFO dep th of near full i nterrupt [RNEAR; addr 00 9] and

near full l eve l status [RNEAR1; addr 0A9]. The RNEAR interrupt and RNEAR1 indi cat or are

both activated when the number of empty FIFO locations equals the selected threshold. The

threshold controls how many data and/or status bytes (64 minus threshold value) that the

processor must read from RDL1 after RNEAR interr upt. This is done to clear the RNEAR1

indicator as well as to determine how much time remains (in bytes) for the processor to read

RDL1 before the receive FIFO is full. If a receive message is in progress when the near full

threshold is reached, the receiver issues a message interr upt [RMSG; addr 009] and places a

Partial message in th e receive FIFO.

T1/E1N MSG_FILL[1:0] Message Fill Limit

X 00 Disabled

001 8 bytes

010 16 bytes

011 24 bytes

101 6 bytes

110 12 bytes

111 18 bytes

FFC[5:0] Empty @ RNEAR Filled @ RNEAR

00 0000 none 64 = RFULL

00 0001 1 empty FIFO location 63 filled

00 0010 2 empty FIFO locations 62 filled

|||

11 1110 62 empty FIFO locations 1 filled

11 1111 63 empty FIFO locations 0 filled = empty

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-79

0A8—Receive Data Link FIFO #1 (RDL1)

Two different re ad byte values are supplied: WORD0 equals message stat us, and WORD1 equals message dat a.

The processor determines which byte value is located in the FIFO by fi rst reading the receiver data link status

[RDL1_STAT; addr 0A9]. In some cases, multiple consecutive status bytes may be placed in the FIFO, so the

processor must always read RDL1_STAT before reading RDL1 to distinguish between WORD0 and WORD1

byte values. However, each time a non-zero byte count [RDL1_CNT] status is read, the processor is guaranteed

the next RDL1_CNT reads from RDL1 will equal message data [WORD1] and not message status. Note that a

status byte occupies 1 byte of FIFO space, just the same as a message data byte occupies 1 byte of FIFO space.

WORD0: Message Status

EOM[1, 0] End of Message—Recei v e data link reports an End of Message statu s for each occurrence of a

complete (Good), a continued (Partial), an errored (FCS/Non-integer), or an aborted (Abort)

message. Note that properly received unformatted messages are reported with a Partial end of

message status. The processor responds to Good or Partial status by reading the indicated

number of data bytes [RDL1_CNT] from RDL1. For abort or error cases, RDL1_CNT equals

zero to indica te that all recei ved data from that message w as discarded. Note that a Good status

with RDL1_CNT=0 is reported if the processor reads RDL1 while the receiver is in progress

of filling the FIFO (in which case RDL1_STAT contains RSTAT1=1 and RMSG1=1). If an

abort or error status with zero byte coun t is reported after the processor has already buf fered a

prior HDLC Partial message, that partial buffered processor data should be discarded. Abort

status is reported if the recei v er detects a string of 7 o r more consecuti v e ones during an HDLC

message. FCS error status is reported if FCS mode is enabled, and the checksum calculated

over the received HDLC message does not match the received 16-bit FCS. Non-integer error

status is reported if the receiver detects a closing FLAG character that yields an HDLC

message length which is not an integer number of 8-bit octets.

00 = Good

01 = FCS/Non-integer

10 = Abort

11 = Partial

RDL1_CNT[5:0] Byte Count [5:0]—Indicates the number of Message Data [WORD1] bytes that are stored in

subsequent consecutive FIFO locations, constituting one received message. The reported byte

count is the actual number of by tes, in the range of 0 to 63 bytes, where 0 indicates zero bytes

for the processor to read. The processor can either read the specified number of message data

bytes consecutively from RDL1 or can poll RDL1_STAT after reading each data byte until

RDL1_STAT reports an end of message (i.e. RMPTY1=1 or RSTAT1=1).

7 6 5 4 3 2 1 0

EOM[1] EOM[0] RDL1_CNT[5] RDL1_CNT[4] RDL1_CNT[3] RDL1_CNT[2] RDL1_CNT[1] RDL1_CNT[0]

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-80 Conexant 100054E

WORD1: Message Data

RDL1[7:0] Receiv e Message Data—F ill ed b y the recei v er data link, from LSB to MSB , with bits from the

selected channel. Processor reads 8-bit FIFO data during HDLC and Pack8 modes. During

Pack6 mode, only the six least significant bits RDL1[5:0] are filled.

0A9—RDL #1 Status (RDL1_STAT)

RMSG1 In Progress Receive Message—Real time status of receive message sequencer is prov ided

mostly for processor polled applications. During HDLC modes, RMSG1 is high for the

interval between opening and closing FLAG characters to indicate the receiver is actively

fi lling FIFO locations (in which case RSTAT1 is also held high). RMSG1 is low while the

channel receives FLAG or Abort characters. During unformatted modes, RMSG1 is high

continuously.

0 = channel idle

1 = channel actively filling FIFO

RSTAT1 Next FIFO Read Equals Message Status—For non-empty FIFO conditions (RMPTY1=0),

RSTAT1 indicates th e next byte rea d f rom RDL1 returns WORD0 mes sage status or WORD1

message data. Note that RSTAT1 equals zero i f the FIFO is empty a nd there is no messag e in

progress. The pro c essor polls RSTAT1 before reading RDL1 to determine how to interpre t

RDL1 read byte value or t he p rocessor check s RSTAT1 in resp onse to RMSG int errupt [ISR2;

addr 009].

0 = RDL1 byte equals Message Data (or empty FIFO, if RMTPY1=1)

1 = RDL1 byte equals Message Status (if RMPTY1=0)

RMPTY1 Receive FIFO Empty—Indicates no data or status bytes are present in the receive data link

FIFO.

0 = FIFO contains data or status as indicated by RSTAT1

1 = FIFO empty

RNEAR1 Recei ve FIFO Near Full—Ind icates da ta li nk has filled recei ve FIFO to the near full threshol d

le vel specified in FFC[5:0]. Upon reaching the near full le vel , the recei v er updates t he message

status byte [WORD0] placed on top of the FIFO and repor ts the current in progress message

with a Par tial end of message status. The processor must read those filled FIFO locations to

clear RNEAR1 status indicator and to enable the next RNEAR interrupt.

0 = FIFO depth is below the near full level

1 = FIFO h as been filled to the near fu ll level

7 6 5 4 3 2 1 0

RDL1[7] RDL1[6] RDL1[5] RDL1[4] RDL1[3] RDL1[2] RDL1[1] RDL1[0]

7 6 5 4 3 2 1 0

— — — RMSG1 RSTAT1 RMPTY1 RNEAR1 RFULL1

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-81

RFULL1 Receive FIFO Full—Indicates data link has completely filled 64 byte locations in the receive

FIFO. In all cases, RFULL1 is an error, indicating the processor didn’t keep pace with the

receiver and indicates one or more received messages were discarded after the FIFO became

full. The FIFO may still contain one or more Good received messages, and the processor may

still process all receive FIFO contents as usual. However, any message that was in progress

when FIFO reached full is discarded and is also reported with Partial end of message status

and a zer o byte coun t ( which d isti ngui shes a f ul l end of message status f rom a normal abort or

error message status).

0 = FIFO is less than full

1 = FIFO has been completely filled

0AA—Performance Report Message (PRM)

AUTO_PRM Automatic PRM Insertion—A UT O_PRM instructs the data link transmitter to format and send

a Performance Report Message on the selected transmit channel after each occurrence of the

ONESEC interr upt. To meet PRM requirements specified in ANSI T1.403-1995, FCS mode

[DL1_CTL; addr 0A6] and one second error count latching [LATCH_CNT; addr 046] must

both be enabled. In addition, the data link channel must be selected to output on Facility Data

Link (FDL) framing bits [DL1_TS=0x40; addr 0A4]. Octets 1-14 of the transmit PRM

message contents are automatically encoded as shown in Table A-5, Performance Report

Message Structure. The encodings are based on the number of received CRC, FPS, LCV, SEF

and FRED errors [addr 050-05A]. RFSLIP errors [SSTAT; addr 0D9] are also automatically

encoded if AUTO_SL (described below) is enabled. The remaining PRM message contents

typicall y remain fix ed and are suppl ied by the processor from oth er bits that follow in the PRM

TDL1 is granted output priority [TBOP_MODE=11; addr 0A0]. Note also that AUTO_PRM

messages take up no space in the transmit data link FIFO, but are inserted on the transmit

channel onl y after the FIFO i s empty. Therefo re, if the processor nee ds to tran smit anot her type

of FDL message between PRM messages, the processor must write that message after

AUTO_PRM has begun sending (i.e. after ONESEC interrupt).

0 = no auto matic PRM

1 = send PRM automatically every ONESEC

PRM_CR Transmit CR Message Bit—The processor writes the selected C/R bit val ue to send in each

PRM.

PRM_R Transmit R Message Bit—The processor writes the selected R bit val ue to send in each PRM.

PRM_U1 Transmit U1 Message Bit—The processor writes the selected U1 bit value to send in each

PRM.

PRM_U2 Transmit U2 Message Bit—The processor writes the selected U2 bit value to send in each

PRM.

PRM_SL Transmit SL Message Bit—The processor writes the selected SL bit value to send in each

PRM.

7 6 5 4 3 2 1 0

AUTO_PRM PRM_CR PRM_R PRM_U1 PRM_U2 PRM_SL AUTO_SL SEND_PRM

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-82 Conexant 100054E

AUTO_SL Auto m atic SL Bit Insertio n—RFSLIP e rr or status is encod e d into the tran sm it PRM co ntents.

Or, the PRM_SL bit value supplied by the processor is sent.

0 = send PRM_SL value in SL bit

1 = send RFSLIP err or status in SL bit

SEND_PRM Immediately Generate an d Sen d PR M— Simil ar t o AUTO_PRM mode, S END_P RM instructs

the data l ink tr ansmitter to format and send a P e rformance Report Message according to ANSI

T1.403-1995. But SEND_PRM executes immediately rather than waiting for ONESEC

interrupt. Thus SEND_PRM g ives processor control over PRM tra nsmit timing . Th is is easier

for the processor to manage if other FDL message types must also be transmitted.

0AB—TDL #1 FIFO Empty Control (TDL1_FEC)

Unused bits are reser ved and should be written to 0.

FEC[5:0] Near Empty T ransmit FIFO Thresh old—Selects FIFO dep th of near e mpty interrupt [TNEAR;

addr 009] and near empty level status [TNEAR1; addr 0AE]. The TNEAR interrupt is

activ ated when the number of data bytes remaining to be transmitted from the FIFO falls below

the selected threshold. The TNEAR1 indicator is active as long as the number of processor

filled FIFO locations is below the selected threshold. Thus TN EAR1 is active high when the

transmit FIFO is completely empty and remains active until the processor writes the selected

threshold number of bytes to TDL1 [addr 0AD]. Assuming the processor writes 64 bytes to

completely fill an empty FIFO, then a TNEAR inter rupt occurs after the transmitter has sent

the number of bytes required to bring the FIFO level back down below the selected threshold.

Hence, the processor can consecutively write 64 - FEC[5:0] number of bytes to the transmit

FIFO in response to a TNEAR interrupt. The interrupt also signifies how much time remains

(in bytes) for the processor to wri te TDL1 before transm it FIFO is emptied . Typically,

FEC[5:0] is set to a small value (bel ow 10 byte thresh ol d) to mini mize the numb er of TNEAR

interrupts and maximize the time between TN EAR interrupts.

7 6 5 4 3 2 1 0

— — FEC[5] FEC[4] FEC[3] FEC[2] FEC[1] FEC[0]

FEC[5:0] Byte threshold @ TNEAR Empty @ TNEAR

00 0000 Disa bled Disable d

00 0001 1 byte threshold 63 empty

00 0010 2 byte threshold 62 empty

|| |

11 1110 62 by t e thr eshold 2 empty

11 1111 63 by t e thr eshold 1 empty

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-83

0AC—TDL #1 End Of Message Control (TDL1_EOM)

Unused bits are reser ved and should be written to 0.

TDL1_EOM End of Transmit Message. Writing any data value to TDL1_EOM marks the last byte of data

written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or

marks the end of a transmit circular buffer. Processor must write TDL1_EOM after writing a

complete message or the last byte of a circular buffer into TDL1 [addr 0AD]. The written data

value is ignored and cannot be read back. Multiple HDLC messages are allowed to be queued

in the transmit FIFO sim ultaneously. In addition, the transition from one c ircular buffer to

another occurs only after the end of message byte of the current circular buffer has been sent.

0AD—Transmit Data Link FIFO #1 (TDL1)

TDL1[7:0] Transmit Message Data—Output by the transmitter data link, from LSB to MSB, and sent on

the selected time slot bits. Processor writes 8-bit FIFO data during HDLC and Pack8 modes.

During Pack6 mode, only the six least significant bits TDL1[5:0] are used.

0AE—TDL #1 Status (TDL1_STAT)

TMSG1 In Progress Transmit Message—The real time status of the transmit message sequencer is

provided mostly for diagnostic purposes. During HDLC modes, TMSG1 is high for the

interval between opening and closing FLAG characters. This indicates that transmitter is

actively pulling dat a bytes from transmit FIF O locations. TMSG1 is low while the channel

transmits FLAG or Abor t characters. During unformatted and circular buffer modes, TMSG1

is high continuously.

0 = channel idle

1 = channel actively emptying FIFO

7 6 5 4 3 2 1 0

EOM[7] EOM[6] EOM[5] EOM[4] EOM[3] EOM[2] EOM[1] EOM[0]

7 6 5 4 3 2 1 0

TDL1[7] TDL1[6] TDL1[5] TDL1[4] TDL1[3] TDL1[2] TDL1[1] TDL1[0]

7 6 5 4 3 2 1 0

— — — — TMSG1 TMPTY1 TNEAR1 TFULL1

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-84 Conexant 100054E

TMPTY1 Transmit FIFO Empty—Indicates no message data is pres ent in transm it data link FIFO. This

is typically checked by the processor in response to a TMSG or TNEAR interrupt. If this is a

TMSG interrupt, the processo r c hecks TMPTY1 to determine that al l queued message s were

sent (TMPTY1=1) or more queued messages remain to be sent (TMPTY1=0). If this is a

TNEAR int errup t, th e processor confirms TMPTY1=0 to verify the part ia l transmit me ssa ge

was not aborted by a FIFO underrun.

0 = FIFO contains data to be transmitted

1 = FIFO empty

TNEAR1 Transmit FIFO Near Empty—Indicates data link has emptied transmit FIFO to below the near

empty threshold specified in FEC[5:0]. After sending the byte that occupied the near empty

FIFO threshold level, TNEAR1 goes active high, which generates a TNEAR interrupt. The

processor must write data to TDL1 to fill the transmit FIFO beyond the near empty threshold

in order to clear TNEAR1 status and enable the next TNEAR inter rupt event.

0 = FIFO depth is below the near empty level

1 = FIFO has been emptied pa st the near empt y level

TFULL1 Transmit FIFO Full—Indic ates proce ssor has complet ely filled 64 byte locatio ns in transmit

FIFO . While TFULL1 remains ac tiv e, a ny subsequent pro cessor writes t o TDL1 are ignored. I f

the proc essor shoul d i nad v ertently write to TDL1 wh il e T FULL1 i s a ctive, the proces sor must

allow FIFO to become completely empty witho ut writing to TDL1_EOM in order to force the

transmit ter to send an Abor t c haracter.

0 = FIFO is less than full

1 = FIFO has been completely filled

0AF—DL2 Time Slot Enable (DL2_TS)

DL2_ TS[7] Unchannelized—Test mode only; all time slots selected. Zero for normal operation.

DL2_ TS[6, 5] Frame Select—Transmit and receive data link 2 operates on data only during the specified

T1/E1 frames. Frame select options give the processor access to different types of data link

channels, as well as overhead channels. Overhead bit insertion is performed after TDL2, so

internal transmitter overhead insertion must be bypassed [TFRM; addr 072] before the

processor supplied overhead can be output from TDL2.

00 = all frames

01 = even frames only

10 = odd frames only

11 = Not valid

7 6 5 4 3 2 1 0

DL2_TS[7] DL2_TS[6] DL2_TS[5] DL2_TS[4] DL2_TS[3] DL2_TS[2] DL2_TS[1] DL2_TS[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-85

DL2_TS[4:0] Time Slot Word Enable—Transmit and receive data link 2 operates on data only during the

specified time slo t. During T1 mode, selecting ti me slot zero ena b les data link operation o n the

F-bit positions.

0B0—DL2 Bit Enable (DL2_BIT)

DL2_BIT[7:0] DL2 Bit Select—Works in conjunction with DL2_TS [addr 0AF] to select one or more time

slot bits f or data l ink input and output. Any combinati on of bi ts may be enabled by writ i ng t he

corresponding DL2_BIT active (high). The LSB enables the first bit transmitted or received,

and MSB enables eighth bit transmitted or received. DL2_BIT has no effect when DL2_TS

selects T1 F-bits.

0 = disable data link bit

1 = enable data link bit

0B1—DL2 Control (DL2_CTL)

Unused bits are reser ved and should be written to 0.

TDL2_RPT Circula r Transmi t Buffer Enable— Proce ssor can fill transmi t FIFO [TDL2 ; addr 0B 8] with up

to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be sent repeatedly. While

TDL2_RPT is active high, data written to TDL2 is held until the processor writes an end of

message [TDL2_EOM; addr 0B7]. A fter TDL2_EOM is written , the transmitter waits for th e

be ginni ng of the ne x t ou tput multif r ame (based on the select ed t ransmi t fr ami ng mod e) befor e

sending the first byte of the circular buffer. Subsequent bytes are output in the selected time

slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the

processor writes new buffer data and another TDL2_EOM. This allows the processor to send

multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS, or CAS overhead bits.

0 = normal transmit FIFO

1 = enable circular transmit buffer

DL2_TS[4:0] T im e Slot Enable

00000 F-bit (T1) or TS0 (E1)

00001 TS1

11110 TS30

11111 TS31

7 6 5 4 3 2 1 0

DL2_BIT[7] DL2_BIT[6] DL2_BIT[5] DL2_BIT[4] DL2_BIT[3] DL2_BIT[2] DL2_BIT[1] DL2_BIT[0]

7 6 5 4 3 2 1 0

— — — TDL2_RPT DL2[1] DL2[0] TDL2_EN RDL2_EN

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-86 Conexant 100054E

DL2[1: 0] Data Link 2 Mode—Selects either HDLC formatted (FCS or Non-FCS) transmit and receive

data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC

modes, the transmit/rec eive circuits perform zero insertion/removal afte r each occurrence of 5

consecutive ones contained in the message bits. These include FLAG (0x7E ) character

insertion/remov al du r ing idl e cha nnel cond it i ons and ABORT (0xF F) code insertion/detection

upon errored channel con diti ons. Refer to IT U-T Recommen dation Q.921 for comple te d etail s

of the HDLC link-layer protocol. FCS mode automatically generates, inserts, and checks the

16-bit Frame Check Sequence (FCS) without passing FCS bits through transmit and receive

FIFOs. While Non-FCS mode passes all message bits that exist between the opening and

closing FLAG characters through the FIFOs, without generating or checking FCS bits.

Non-FCS mode allows the processor to generate and check the entire contents of each HDLC

frame. Unformatted data link modes provide transparent channel access in which every data

link bit t ransmitted i s supplied by the proc essor through T DL1, and each bit received is passed

to the processor thr ough RDL2 [add r 0B3]. P ack8 and Pack6 unformatted mode opt ions sele ct

the number of bits per byte that are stored in transmit/receive FIFOs, eight or six bits,

respecti v el y. The only data pr ocessing perfo rmed during unformatted mode i s the alignment of

transmitted and received data bits with respect to the transmit/receive multiframe.

00 = FCS

01 = No FCS

10 = Pack8

11 = Pack6

TDL2_EN Transmit Data Link 2 Enable—When enabled, the transmitter begins to empty and to format

the contents of the transmit data link FIFO for o utput duri ng the selec te d time slot bit s

according to the select ed DL2[1:0] mode. Also ena bles gene ration of tran sm itter data link

interrupt events.

0 = disabled

1 = enable transmit data link

RDL2_EN Receive Data Link 2 Enable—When enabled, the receiver begins to format data from the

selected time slot bit s and to fill the recei v e data link FIFO accord ing to the selected DL2[1:0]

mode. Also ena bles gener ation of rece iver da ta lin k interrupt events.

0 = disabled

1 = enable receive data link

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-87

0B2—RDL #2 FIFO Fill Control (RDL2_FFC)

MSG_FILL[1:0] Unformatted Message Fill Limit—This is applicable only for Pack8 and Pack6 modes. The

message fill limit selects how many recei v e FIFO locations [RDL2; a ddr 0B3] are filled before

the receive data link generates an RFULL interrupt [ISR1; addr 00A] and a corresponding

RDL2 Partial message status word entry. Fill limit thus determines how m any bytes constitute

an unformatted message. The fill limits give the processor an alternative to using RNEAR

interrupts to signal the end of a received unformatted message. The number of bits per

unformatted message must divide evenly by the number of bits monitored per multiframe. For

example, SLC ap plications monitor Fs bits during even frames for a total of 36 bits mo nitored

out of 72 frames. Using P ack6 mode, the group of 36 Fs bits from each SLC multi frame can be

chosen to constitute one unformatted message. This is accomplished by selecting a message

fill limit which equals 6 bytes (of 6 bits/byte). In the SLC example, an RFULL interrupt would

then be generated every 9 ms on each SLC multiframe boundary. Fill limits provided for T1

cases are mu lti ples of 6 b ytes (i.e . 6, 12 or 18 FI FO loc ation s) to hol d one or more multi frames

w orth of monitored data. In E1 mode, fill limits are multiples of 8 bytes to correspond with the

16-frame multiframe lengths (i.e. monitoring CRC4 in MFAS framing mode or TS16 in CAS

framing mode).

FFC[5:0] Near Full FIFO Threshol d—Selects F IFO depth of nea r full int errupt [RNEAR; addr 00A] an d

near full l evel status [R NEAR 2; addr 0 B4]. T he R NEAR i nte rrupt and R NEAR 2 i ndi cat or ar e

both activated when the number of empty FIFO locations equals the selected threshold. The

threshold con trols how many data and /or st atu s bytes (64 min us t hre sh ol d value) the proce ssor

must read from RDL2 after RNEAR interrupt to clear the RNEAR2 indicator as well as how

much time remains (in bytes) for the processor to read RDL2 before receive FIFO is full. If a

receive message is in progress when the near full threshold is reached, the receiver issues a

message interrupt [RMSG; addr 00A] and places a Partial message in the receive FIFO.

7 6 5 4 3 2 1 0

MSG_FILL[1] MSG_FILL[0] FFC[5] FFC[4] FFC[3] FFC[2] FFC[1] FFC[0]

T1/E1N MSG_FILL[1:0] Message Fill Limit

X 00 Disabled

001 8 bytes

010 16 bytes

011 24 bytes

101 6 bytes

110 12 bytes

111 18 bytes

FFC[5:0] Empty @ RNEAR Filled @ RNEAR

00 0000 None 64 = RFULL

00 0001 1 empty FIFO location 63 filled

00 0010 2 empt y FIFO locatio ns 62 filled

|| |

11 1110 62 empty FIFO locations 1 filled

11 1111 63 empty FIFO locations 0 filled = empty

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-88 Conexant 100054E

0B3—Receive Data Link FIFO #2 (RDL2)

Two different re ad byte values are supplied: WORD0 equals message stat us, and WORD1 equals message dat a.

The processor determines which byte value is located in the FIFO by fi rst reading the receiver data link status

[RDL2_STAT; addr 0B4]. In so me cases, multiple conse cutiv e status b yte s ma y be placed in the FIFO . Thus, t he

processor must always read RDL2_STAT before reading RDL2 to distinguish between WORD0 and WORD1

byte values. However, each time a non-zero byte count [RDL2_CNT] status is read, the processor is guaranteed

the next RDL2_CNT reads from RDL2 will equal message data [WORD1] and not message status. A status

byte occupies 1 byte of FIFO space, just the same as a message data byte occupies 1 byte of FIFO space.

WORD0: Message Status

EOM[1, 0] End of Message—The receive data link reports an End of Message status for each occurrence

of a complete (Good), a continued (Partial), an errored (FCS/Non-integer), or an aborted

(Abort) message. Note t hat properl y re cei ved unformatted me ssages are reported with a Partial

end of message status. The processor responds to Good or Partial status by reading the

indicated number of data bytes [RDL2_CNT] from RDL2. For abort or error cases,

RDL2_CNT equals zero to indicate all received data from that message was discarded. Note

that a Good sta tus with RDL2_CNT=0 is reporte d if the processor reads RDL2 while the

receiver is in progress of filling the FIFO (in which case RDL2_STAT contains RSTAT2=1

and RMSG2=1). If an abort or error status with zero byte count is reported after the processor

has already buf fered a prior HDLC Partial message, that partial buf fered processo r data should

be discarded. Abort status is reported if the receiver detects a string of 7 or more consecutive

ones during an HDLC message. FCS error status is reported if FCS mode is enabled, and the

checksum calculated over the received HDLC message does not match the received 16-bit

FCS. Non-integer error status is reported if the receiver detects a closing FLAG character

yielding an HDLC message length which is not an integer number of 8-bit octets.

00 = Good

01 = FCS/Non-integer

10 = Abort

11 = Partial

RDL2_CNT[5:0] Byte Count [5:0]—Indicates the number of Message Data [WORD1] bytes that are stored in

subsequent consecutive FIFO locations, constituting one received message. The reported byte

count is the actual number of bytes in the range of 0 to 63 bytes, where 0 indicates for the

processor to read. The processor can either read the specified number of message data bytes

consecutively from RDL2 or can poll RDL2_STAT after reading each data byte until

RDL2_STAT reports an end of message (i.e. RMPTY2=1 or RSTAT2=1).

WORD1: Message Data

RDL2[7:0] Receiv e Message Data—F ill ed b y the recei v er data link, from LSB to MSB , with bits from the

selected channel. The processor re ads 8-bit FIF O data during HDLC and Pack 8 modes. Durin g

Pack6 mode, only the six least significant bits RDL2[5:0] are filled.

7 6 5 4 3 2 1 0

EOM[1] EOM[0] RDL2_CNT[5] RDL2_CNT[4] RDL2_CNT[3] RDL2_CNT[2] RDL2_CNT[1] RDL2_CNT[0]

7 6 5 4 3 2 1 0

RDL2[7] RDL2[6] RDL2[5] RDL2[4] RDL2[3] RDL2[2] RDL2[1] RDL2[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-89

0B4—RDL #2 Status (RDL2_STAT)

RMSG2 In Progress Receive Message—The real-time status of the receive message sequencer is

provided mostly for processor polled applications. During HDLC modes, RMSG2 is high for

the interval between opening and closing FLAG characters to indicate the receiver is actively

fi lling FIFO locations (in which case RSTAT2 is also held high). RMSG2 is low while the

channel receives FLAG or Abort characters. During unformatted modes, RMSG2 is high

continuously.

0 = channel idle

1 = channel actively filling FIFO

RSTAT2 Next FIFO Read Equals Message Status—For non-empty FIFO conditions (RMPTY2=0),

RSTAT2 indicates that the next byte rea d from RDL2 will b e WORD0 m essage status or

WOR D1 message data. Notice that RSTAT 2 equals zero if the FIFO is empty, and there is no

message in progress. Processor polls RSTAT2 before reading RDL2 to deter mine how t o

interpret RDL2 read byte value, or checks RSTAT2 in response to RMSG interrupt [ISR1; addr

00A].

0 = RDL2 byte equals Message Data (or empty FIFO, if RMTPY2=1)

1 = RDL2 byte equals Message Status (if RMPTY2=0)

RMPTY2 Receive FIFO Empty—Indicates no data or status bytes are present in receive data link FIFO.

0 = FIFO contains data or status as indicated by RSTAT2

1 = FIFO empty

RNEAR2 Receive FIFO Near Full—Indicates the data link has filled receive FIFO to the near full

threshold level specified in FFC[5:0]. Upon reaching the near full level, the receiver updates

the message status byte [WORD0] placed on top of the FIFO and reports the current in

progress message with a Partial end of message stat us. The processor must re a d those filled

FIFO locations to clear RNEAR2 status indicator, and to enable the next RNEAR interrupt.

0 = FIFO depth is below the near full level

1 = FIFO h as been filled to the near fu ll level

RFULL2 Receive FIFO Full—Indicates data link has completely filled 64 byte locations in the receive

FIFO. In all cases, RFULL2 is an error, indicating the processor didn’t keep pace with the

receiver and indicates one or more received messages were discarded after the FIFO became

full. The FIFO may still contain one or more Good received messages, and the processor may

still process all receive FIFO contents as usual. However, any message that was in progress

when FIFO reached full is discarded and is also reported with Partial end of message status

and a zer o byte coun t ( which d isti ngui shes a f ul l end of message status f rom a normal abort or

error message status).

0 = FIFO is less than full

1 = FIFO has been completely filled

7 6 5 4 3 2 1 0

— — — RMSG2 RSTAT2 RMPTY2 RNEAR2 RFULL2

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-90 Conexant 100054E

0B6—TDL #2 FIFO Empty Control (TDL2_FEC)

FEC[5:0] Near Empty Transmit FIFO Threshold—Selects a FIFO depth of near empty interr upt

[TNEAR; addr 00A] and near empty level status [TNEAR2; addr 0B9]. The TNEAR interrupt

is activated when the number of data bytes remaining to be transmitted from the FIFO falls

below the selected threshold. The TNEAR2 indicator is active as long as the number of

processor filled FIFO locations is below the selected threshold. Thus, TNEAR2 is active high

when the transmit FIFO is completely empty and remains active until the processor writes the

selected threshold number of bytes to TDL2 [addr 0B8]. Assuming the processor writes 64

b ytes to completel y fill an empty FIFO, TNEAR interrupt occurs after the transmitter has sent

the number of bytes required to bring the FIFO level back down below the selected threshold.

Hence, the processor is guaranteed to be able to consecutively write 64 – FEC[5:0] number of

b ytes to the transmit FIFO in response to a TNEAR interrupt. The interrupt also signifies how

much time remains (in bytes) for the processor to write TDL2 before transmit FIFO is emptied.

Typically, FEC[5:0] is set to a small value (approximately 5–10 b yte thresho ld) to minimize th e

number of TNEAR interrupts and maximize the time between TNEAR interrupts.

0B7—TDL #2 End Of Message Control (TDL2_EOM)

TDL2_EOM End of Transmit Message. Writing any data value to TDL2_EOM marks the last byte of data

written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or the

end of a transmit circular buffer. The processor must write TDL2_EOM after writing a

complete message or the last byte of a circular buffer into TDL2 [addr 0B8]. The written data

value is ignored and cannot be read back. Multiple HDLC messages are allowed to be queued

in the transmit FIFO sim ultaneously. In addition, the transition from one c ircular buffer to

another occurs only after the end of message byte of the current circular buffer has been sent.

7 6 5 4 3 2 1 0

— — FEC[5] FEC[4] FEC[3] FEC[2] FEC[1] FEC[0]

FEC[5:0] Byte Threshold @ TNEAR Empty @ TNEAR

00 0000 Disa bled Disable d

00 0001 1 byte threshold 63 empty

00 0010 2 byte threshold 62 empty

|| |

11 1110 62 by t e thr eshold 2 empty

11 1111 63 by t e thr eshold 1 empty

7 6 5 4 3 2 1 0

EOM[7] EOM[6] EOM[5] EOM[4] EOM[3] EOM[2] EOM[1] EOM[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-91

0B8—Transmit Data Link FIFO #2 (TDL2)

TDL2[7:0] Transmit Message Data—Output by the transmitter data link from LSB to MSB and sent on

the selected time slot bits. Processor writes 8-bit FIFO data during HDLC and Pack8 modes.

During Pack6 mode, only the six leas t significan t bits, TDL2[5:0], are used .

0B9—TDL #2 Status (TDL2_STAT)

TMSG2 In Progress Transmit Message—The real time status of the transmit message sequencer is

provided mostly for diagnostic purposes. During HDLC modes, TMSG2 is high for the

interval between the ope ning and closing FLAG characters to indi cate the transmitter is

actively pulling dat a bytes from transmit FIF O locations. TMSG2 is low while the channel

transmits FLAG or Abor t characters. During unformatted and circular buffer modes, TMSG2

is co ntinuously high.

0 = channel idle

1 = channel actively emptying FIFO

TMPTY2 Transmit FIFO Empty—Indicate s that no message data is prese nt in the transmit data link

FIFO. This is typically checked by processor in respo nse to a TMSG or TNEAR interr upt. If

this is a TMSG interrupt, the processor ch ecks TMPTY2 to determine th at all queue d

messages were sent (TMPTY2=1) or more queued messages remain to be sent (TMPTY2=0).

If this is a TNEAR interrupt, the processor confirms TMPTY2=0 to verify the partial transmit

message was not aborted by a FIFO underrun.

0 = FIFO contains data to be transmitted

1 = FIFO empty

TNEAR2 Transmit FIFO Near Empty—Indicates data link has emptied transmit FIFO to below the near

empty threshold specified in FEC[5:0]. After sending the byte that occupied the near empty

FIFO threshold level, TNEAR2 goes active high, which generates a TNEAR interrupt. The

processor must write data to TDL2 to fill the transmit FIFO beyond the near empty threshold.

This is done in order to clear TNEAR2 status and enable the next TNEAR interr upt event.

0 = FIFO depth is below the near empty level

1 = FIFO has been emptied pa st the near empt y level

TFULL2 Transmit FIFO Full—Indic ates proce ssor has complet ely filled 64 byte locatio ns in transmit

FIFO . While TFULL2 remains ac tiv e, a ny subsequent pro cessor writes t o TDL2 are ignored. I f

the proc essor shoul d i nad v ertantly write to TDL2 wh il e T FULL2 i s a ctive, the proces sor must

allow FIFO to become complete l y empty without writ ing to T DL2_EOM, in or der to force the

transmit ter to send an Abor t c haracter.

0 = FIFO is less than full

1 = FIFO has been completely filled

7 6 5 4 3 2 1 0

TDL2[7] TDL2[6] TDL2[5] TDL2[4] TDL2[3] TDL2[2] TDL2[1] TDL2[0]

7 6 5 4 3 2 1 0

— — — — TMSG2 TMPTY2 TNEAR2 TFULL2

3.0 Registers CX28394/28395/28398

3.15 D ata Link Registers Quad/x16/Octal—T1/E1/J1 Framers

3-92 Conexant 100054E

0BA—DLINK Test Configuration (DL_TEST1)

Data link test registers [addr 0BA-0BE] are for Conexant production test. Set to zero for normal operation.

Unused bits are reser ved and should be written to 0.

DL_TEST1[3] Clock Test—Zero for normal operati on , w here clocks cont ro ll ed by DL1_CTL and DL2_CTL

[addr 0A6, 0B1]. When active high, clocks are always enabled.

DL_TEST1[2] Shadow Select—Report shadow pointers instead of normal read/write pointers.

DL_T EST1[1, 0] FIFO S elect: 00 = RDL1; 01 = RDL2; 10 = TDL1; 11 = TD L2

0BB—DLINK Test Status (DL_TEST2)

Unused bits are reser ved and should be written to 0.

DL_TEST2[5:0] Read or Shadow Read Pointer—Reports selected FIFO read pointer current address.

0BC—DLINK Test Status (DL_TEST3)

Unused bits are reser ved and should be written to 0.

DL_TEST3[5:0] Write or Shadow Wr ite Pointer—Specifies selected FIFO write pointer address.

0BD—DLINK Test Control #1 or Configuration #2 (DL_TEST4)

DL_TEST4[6] TFIFO1 Read Clear—Force transmit FIFO read pointer to empty.

DL_TEST4[5] TFIFO1 Write Clear—Force transmit FIFO write pointer to empty.

DL_TEST4[4] TFIFO1 Write—MPU data goes to specified write pointer address.

DL_TEST4[3] RFIFO1 Read Clear—Force receive FIFO read pointer to empty state (flush).

DL_TEST4[2] RFIFO1 Write Clear—Force receive FIFO write pointer to empty state (flush).

DL_TEST4[1] RFIFO1 Write—MPU data goes to specified write pointer address.

DL_TEST4[0] RFIFO1 Bypass—Pipe receive data.

7 6 5 4 3 2 1 0

— — — — DL_TEST1[3] DL_TEST1[2] DL_TEST1[1] DL_TEST1[0]

7 6 5 4 3 2 1 0

— — DL_TEST2[5] DL_TEST2[4] DL_TEST2[3] DL_TEST2[2] DL_TEST2[1] DL_TEST2[0]

7 6 5 4 3 2 1 0

— — DL_TEST3[5] DL_TEST3[4] DL_TEST3[3] DL_TEST3[2] DL_TEST3[1] DL_TEST3[0]

7 6 5 4 3 2 1 0

— DL_TEST4[6] DL_TEST4[5] DL_TEST4[4] DL_TEST4[3] DL_TEST4[2] DL_TEST4[1] DL_TEST4[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.15 Data Link Registers

100054E Conexant 3-93

0BE—DLINK Test Control #2 or Configuration #2 (DL_TEST5)

Unused bits are reser ved and should be written to 0.

DL_TEST5[6] TFIFO2 Read Clear—Force transmit FIFO read pointer to empty.

DL_TEST5[5] TFIFO2 Write Clear—Force transmit FIFO write pointer to empty.

DL_TEST5[4] TFIFO2 Write—MPU data goes to specified write pointer address.

DL_TEST5[3] RFIFO2 Read Clear—Force receive FIFO read pointer to empty state (flush).

DL_TEST5[2] RFIFO2 Write Clear—Force receive FIFO write pointer to empty state (flush).

DL_TEST5[1] RFIFO2 Write—MPU data goes to specified write pointer address.

DL_TEST5[0] RFIFO2 Bypass—Pipe receive data.

7 6 5 4 3 2 1 0

— DL_TEST5[6] DL_TEST5[5] DL_TEST5[4] DL_TEST5[3] DL_TEST5[2] DL_TEST5[1] DL_TEST5[0]

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-94 Conexant 100054E

3.16 System Bus Registers

0D0—System Bus Interface Configuration (SBI_CR)

X2CLK Enable Times 2 Clocks—X2CLK modifies the number of RSB/TSB clock cycles used to

clock a single data bit onto RSB and TSB. When X2CLK is active, two RSBCKI/TSBCKI

clock cycles occur for each RPCMO, RSIGO, SIGFRZ, TPCMI, and TSIGI bit. But the

FSYNC and MSYNC signals remain at the full 1x RSBCKI/TSBCKI clock rate.

0 = RSB/TSB signals at RSBCKI/TSBCKI

1 = Two SBCKI clock cycles per SBI bit (except FSYNC and MSYNC).

SBI_OE Enable System Bus Outputs—Places RPCMO, RSIGO, RINDO, and SIGFRZ output buffers

under the control of the RSB timebase. SBI_OE also places the TINDO output buffer under

the control of TSB timebase. Inactive (low) forces SBI output buffers to a high-impedance

state. Power on and RESET [addr 001] force SBI_OE to an inactive state to avoid bus

contention on devices sharing system bus connections.

0 = SBI outputs forced to high-impedance state

1 = SBI outputs controlled by respective RSB or TSB timebase

EMF Embedded Framing—During T1 mode, EMF controls placement of T1 framing bits on

RPCMO and sampling of T1 framing bits from TPCMI according to the selected embedded

framing format. EMF supports system buses that carry T1 frames but operate above T1 line

rate. EMF allo ws the system bus to transport and maintain 193-bit frame integrity as T1 data is

passed through RSLIP and/or TSLIP buffers.

0 = G.802 embedded format

1 = Reserved embedded for mat

EMBED EMBED instructs the transmit framer (refer to [TABOR T; addr 071]) t o align the TX timebase

with respect to the frame and multif rame alignme nt embedd ed in the tra nsmit line rate data

output from TSLIP (TXDATA). EMBED is required during applications that bypass frame

formatter [TFRM; addr 072] or Sa-bits [TMAN; addr 074]. If TSLIP is enabled, EMBED is

inactive, and overhead is bypassed, TX timebase is not guaranteed to align to TXDATA, and

b ypassed o v erhead cann ot reliabl y pass through TSLIP. EMBED is applicab le to all system bus

modes.

7 6 5 4 3 2 1 0

X2CLK SBI_OE EMF EMBED SBI[3] SBI[2] SBI[1] SBI[0]

EMBED T1/E1N Embedded Framing Mode

0 X Transmit framer searches TPCMI

1 0 TS0 embedded; search TXDATA

1 1 G.802 embedded; search TXDATA

NOTE(S): Embedded F-bits reach TX output only if frame formatter [TFRM; addr 072]

is in bypass or transparent mode.

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-95

SBI[3:0] System Bus Interface Mode—Defines transmit and receive system bus data format. System

buses operate in one of nine basic formats which differ in the number of total available data

time slots and the associat ed system bus clo ck ra te. If the total time slots are a mul tiple of 32,

SBI also defines which bus group of 32 byte-interleaved time slots are assigned to the

respective device.

TS0 Embedd ed Th e offline fr amer examines TXDATA to align TX timebase to the

embedded FAS pattern. If MFAS is also enabled [TFRAME; addr

070], transmit onlin e framer ex amin es TXD ATA to align TX timebase

to the embedded MFAS pattern. While EMBED is active, TXDATA

output is monitored, and transmit frame errors are reported in ISR0

[addr 00B]. Embedded TS0 supports E1 overhead bypass options for

applications where TSLIP buffer is enabled.

G.802 Embedded Automatically supports ITU–T Recommendation G.802, which

defines frame format conversion betw een T1 and E1 line rates. This is

accomplished by locating T1 F-bits in Bit 1 of Time Slot 26 of each

system bus frame. G.802 embedded mode is applicable for system

buses that are 1x, 2x, or 4x multiples of E1 line rate. Full

implementation of G.802 also requires the processor to program TS0,

TS16, and TS26–TS31 as unassigned system bus time slots [SBCn;

addr 0E0–0FF].

SBI[3:0] Mode Clock ( K bps) Total Time Slots Bus Group

0000 128A 8192 128 Group 0

0001 128B 8192 128 Group 1

0010 128C 8192 128 Group 2

0011 128D 8192 128 Group 3

0100 64A 4096 64 Group 0

0101 64B 4096 64 Group 1

0110 32 2048 32 —

0111 24+F 1544 24 + F- bit —

1000 24 1536 24 —

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-96 Conexant 100054E

0D1—Receive System Bus Configuration (RSB_CR)

BUS_RSB Enab le Bussed RSB Outputs—Appli cable onl y if the system bus outputs are contro lled b y SBI

timebases [SBI_OE = 1; addr 0D0]. When BUS_RSB is active, RPCMO , RSIGO , and RINDO

outputs from multiple devices are allowed to share common receive system bus connections.

Unused time slots are three-stated during those bus groups that are not selected by SBI mode

[addr 0D0]. Otherwise, unused time slots repeat their output data value for all bus groups.

0 = RSB time slot value repeated for all bus groups

1 = three-state RSB outputs during unused bus groups

SIG_OFF Inhibit RPCMO Signaling Reinsertion—Disables insertion of ABCD signaling for all time

slots on the receive system bus PCM output (RPCMO). Otherwise, ABCD signaling is

reinserted on RPCMO as controlled by System Bus Per-Channel [SBCn; addr 0E0–0FF] and

RX Per-Channel [RPCn; addr 180–19F] controls.

0 = enable insertion of signaling onto RPCMO

1 = inhibit RPCMO signaling

RPCM_NEG Output Data on Falling Edge Clock—Selects RSBCKI rising or falling edge clock signal to

output RPCMO, RSIGO, RINDO, and SIGFRZ.

0 = RSB rising edge outputs

1 = RS B falling edge outputs

RSYN_NEG Output Sync on Falling Edge Clock—Selects RSBCKI rising or falling edge clock signal for

RFSYNC or RMSYNC outputs. Opposite RSBCKI edge is used if RFSYNC or RMSYNC is

prog rammed as an input.

0 = RFSYNC or RMSYNC rising edge output (falling edge input)

1 = RFSYNC or RMSYNC falling edge output (rising edge input)

BUS_FRZ Enable Bused SIGFRZ Output—Enables SIGFRZ fro m multiple devices to share a common

receive syst em bus connection. When act ive, SIGFRZ three-stat es dur ing bus group time slots

that are unused by the selected SBI mode [addr 0D0].

0 = SIGFRZ repeats for all bus groups

1 = three-state SIGFRZ during unused bus groups

RSB_CTR Force RSLIP to Center—Writing a one to RSB_CTR forces RSLIP read buffer pointer to its

initial delay condition. If RFSYNC or RMSYNC is programmed as an output, RSB_CTR

consequently forces a change of system bus sync alignment. The processor must assert

RSB_CTR after configuration of the receive slip buffer. Centering RSLIP does not effect

RSLIP status reported in ISR.5 [addr 006].

0 = no effect

1 = force RSLIP to center

7 6 5 4 3 2 1 0

BUS_RSB SIG_OFF RPCM_NEG RSYN_NEG BUS_FRZ RSB_CTR RSBI[1] RSBI[0]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-97

RSBI[1:0] Recei v e Slip Buf fer Interface Mod e—Selects configuration of RSLIP buf fer . RSBI determines

the total buffer depth and initial delay conditions. While RSLIP is bypassed, RSB outputs and

RSBCKI is ignored. RFSYNC and RMSYNC are also ignored in bypass mode if they are

programmed as inputs.

0D2—RSB Sync Bit Offset (RSYNC_BIT)

Unused bits are reser ved and should be written to 0.

OFFSET[2:0] RSB Sync Bit Of fset—Selec ts which RSB bi t number coincid es with RFSYNC and RMSYNC

sync pulses. Sync pulses are prog rammed to align to one bit in relation to RPCMO, RSIGO,

RINDO, and SIGFRZ time sl ots. If th e sync pul ses are desir ed to coinci de wi th locati on of T1

F-bit or time slot z ero Bit 1, then OFF SET is programmed to equal zer o. Sync bit offset is

added to time slot offset [RSYNC_TS; addr 0D3] to form a 10-bit OFFSET value. This value

applies to RFSYNC location, which is then added to frame offset [RSYNC_FRM; addr 0D8]

to for m a 15-bit OFFSET value that app lies to RMSYNC location. Both RFSYNC an d

RMSYNC offsets are expressed as RSB.OFFSET, allowing the system to generate or accept

sync pu lse s at any bit location wit hin the RSB multiframe.

RSBI Mode Total

Depth Initial Delay Conditions

00 Normal 2 Frame 1 Frame When RFSYNC is output

0.5 to 1.5 Frames When RFSYNC is input

01 Short 2 Frame 32 bits Reverts to normal upon slip

10 Elastic 674 bits 32 bits Recenters automatically upon slip

11 Bypass 0 bits 0 bits R SBCKI ignored

7 6 5 4 3 2 1 0

— — — — — OFFSET[2] OFFSET[1] OFFSET[0]

OFFSET[2:0] RSYNC Location

000 Bit 1 or F-bit

001 B it 2

110 B it 7

111 B it 8

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-98 Conexant 100054E

0D3—RSB Sync Time Slot Offset (RSYNC_TS)

Unused bits are reser ved and should be written to 0.

OFFS ET[9:3] RSB Sync Time Slot Offset—Selects which RSB time slot number coincides with RFSYNC

and RMSYNC sync pulses, in the range of Time Slots 0–127. If the sync pulses coincide with

location of T1 F-bit or TS0, then OFFSET is programmed to equal zero. Refer also to

RSYNC_BIT and RSYNC_FRM [addr 0D2, 0D8].

7 6 5 4 3 2 1 0

— OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3]

2048, 1544, and 1536 Kbps/sec SBI Mo de

OFFSET[9:3] RSYNC Time Slot

0000000 0 or F-bit

0000001 1

0011110 30

0011111 31

4096 Kbps/sec SBI Mode

OFFSET[9:4] OFFSET[3] RSYNC Time Slot Group

000000 0 0 A

000000 1 0 B

000001 0 1 A

000001 1 1 B

|| | |

011110 0 30 A

011110 1 30 B

011111 0 31 A

011111 1 31 B

8192 Kbps/sec SBI Mode

OFFSET[9:5] OFFSET[4:3] RSYNC Time Slot Grou p

00000 00 0 A

00000 01 0 B

00000 10 0 C

00000 11 0 D

00001 00 1 A

00001 01 1 B

00001 10 1 C

00001 11 1 D

|| | |

11110 00 30 A

11110 01 30 B

11110 10 30 C

11110 11 30 D

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-99

0D4—Transmit System Bus Configuration (TSB_CR)

BUS_TSB Enable Bused TSB Output—Applicable only if system bus outputs are controlled by SBI

timebases [SBI_OE = 1; addr 0D0]. When BUS_TSB is active, TINDO outputs from multiple

devices are allowed t o share a common t r ansmit system bus connection. Unused time slo ts are

three-stated during those bus groups that are not selected b y SBI mode [add r 0D0]. Otherwise,

unused time slots repeat their TINDO value for all bus groups.

0 = TINDO repeated for all bus groups

1 = three-state TINDO during unused time slots

TX_ALIGN Transmitter Output Multiframe Alig ns to TSB Timeba se —Allows multiframe alignment

located at TSB (from TMSYNC or TFRAMER to pass across TSLIP b uffer and force the

corresponding multiframe alignment onto the transmitter timebase. Used primarily to pass

TMSYNC from system bus.

0 = Transmitter multi fra me does not follow TSB

1 = Transmitter multiframe follows TSB multiframe

TPCM_NEG Output Data on Falling Edge Clock—Selects TSBCKI rising or falling edge clock signal to

output TINDO and the opposite TSBCKI edge to sample TPCMI and TSIGI inputs.

0 = TINDO rising edge output (TPCMI and TSIGI falling edge inputs)

1 = TINDO falling edge outputs (TPCMI and TSIGI rising edge inputs)

TSYN_NEG Output Sync on Falling Edge Clock—Selects TSBCKI rising or falling edge clock signal for

TFSYNC or TMS YNC outputs. The opposi t e TS BCKI ed g e is used if TFSYNC or TMSYNC

is programmed as input.

0 = TFSYNC or TMSYNC rising edge output (falling edge input)

1 = TFSYNC or TMSYNC falling edge output (rising edge input)

TSB_ALIGN Transmit Syste m Bus Multifra me Aligns to Transmit Timebase—Allows multiframe

alignment located at TX timebase to pass across TSLIP and force the corresponding

multiframe al ignment onto the T SB timebase. Used primaril y to pass CAS or MFAS alignment

located by the transmit online framer onto the TMSYNC output.

0 = TSB multiframe does not follow XMTR

1 = TSB multiframe aligned by XMTR

11111 00 31 A

11111 01 31 B

11111 10 31 C

11111 11 31 D

NOTE(S): Offsets which are outside the RSB timebase range result in no pulses on

RFSYNC and RMSYNC outputs.

7 6 5 4 3 2 1 0

BUS_TSB TX_ALIGN TPCM_NEG TSYN_NEG TSB_ALIGN TSB_CTR TSBI[1] TSBI[0]

8192 Kbps/sec SBI Mode

OFFSET[9:5] OFFSET[4:3] RSYNC Time Slot Grou p

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-100 Conexant 100054E

TSB_CTR Force TSLIP to Center—Writing a one to TSB_CTR forces TSLIP read buffer pointer to its

initial delay condition. This can possibly force a change of transmit frame alignment if TSLIP

is configured in Elastic or Bypass modes. Writing a zero has no eff ect. The processor must

assert TSB_CTR after configuration of the transmit slip buffer. Afterwards, CX28398

automatically recenters TSLIP buffer according to the configured mode. Centering TSLIP

does not effect TSLIP status reported in ISR5[addr 006].

0 = no effect

1 = force TSLIP to center

TSBI [1:0] Transmit Slip Buffer Interface Mode—Selects the configuration of the TSLIP buffer. The

TSBI dete rmines the total buffer depth and initial de lay conditi ons. While TS LIP is bypassed,

TCKI cloc ks TSB input/out put, and TSBCKI is igno red.

0D5—TSB Sync Bit Offset (TSYNC_BIT)

Unused bits are reser ved and should be written to 0.

OFFS ET[2:0] TSB Sync Bit Of fset—Select s which T SB bit number coincide s with TFSYNC and TMSYNC

sync pulses. Sync pulses are programmed to align to one bit in relation to TPCMI, TSIGI and

TINDO time slots. If the syn c pulses are desired to coincide with location of T1 F-bit or time

slot zero Bit 1, then OFFSET is pro grammed to equal zer o. Sync bit of fs et is added to time slot

offset [TSYNC_TS; addr 0D6] to form a 10-bit OFFSET value. This value applies to

TFSYNC and TMSYNC location. Both TFSYNC and TMSYNC offsets are expressed as

TSB.OFFSET, allowing the system to generate or accept sync pulses at any bit location within

the TSB frame.

TSBI Mode Total

Depth Initial Delay Conditions

00 Normal 2 Frame 0.5 to 1.5 Frames Dependent on present depth, no

change of output frame.

01 Short 2 Frame 3 2 Bits Reverts to normal upon slip

10 Elastic 64 Bits 32 Bits Recenters automatically upon slip

11 Bypass 0 Bits 0 Bits TSBCKI ignored

NOTE(S):

1. Bypass req uires system bus equal to line rate.

2. Idle code and local signal ing inserti on apply to all modes.

7 6 5 4 3 2 1 0

— — — — — OFFSET[2] OFFSET[1] OFFSET[0]

OFFSET[2:0] TSYNC Location

000 Bit 1 or F-bit

001 Bit 2

110 Bit 7

111 Bit 8

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-101

0D6—TSB Sync Time Slot Offset (TSYNC_TS)

Unused bits are reser ved and should be written to 0.

OFFSET[9:3] TSB Sync Ti me Slot Offset—Selects which TSB time slot number coincides with TFSYNC

and TMSYNC sync pulses, in the range of Time Slots 0 through 127. If the sync pulses

coincide with location of T1 F-bit or TS0, then OFFSET is programmed to equal zero. Refer

also to TSYNC_TS [addr 0D6].

7 6 5 4 3 2 1 0

— OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3]

2048, 154 4, an d 15 36 K bps / se c SBI Mod e

OFFSET[9:3] TSYNC Time Slot

0000000 0 or F-bit

0000001 1

0011110 30

0011111 31

4096 K bps/sec S BI Mode

OFFSET[9:4] OFFSET [3 ] TSYNC Time

Slot Group

000000 0 0 A

000000 1 0 B

000001 0 1 A

000001 1 1 B

||||

011110 0 30 A

011110 1 30 B

011111 0 31 A

011111 1 31 B

8192 K bps/sec S BI Mode

OFFSET[9:5] OFFSET[4: 3] TSYNC Time

Slot Group

00000 00 0 A

00000 01 0 B

00000 10 0 C

00000 11 0 D

00001 00 1 A

00001 01 1 B

00001 10 1 C

00001 11 1 D

||||

11110 00 30 A

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-102 Conexant 100054E

0D7—Receive Signaling Configuration (RSIG_CR)

SET_RSIG Force 2 ms RSIG Interrupt—Allows t he processor to receive an interrupt on RSIG [addr 008]

at e v ery CAS multi frame boun dary. Appli cab le only to E1 mode with CAS enab l ed. Ov errides

STACK interrupt.

0 = RSIG interrupt on signaling STACK change

1 = RSIG interrupts every 2 ms at CAS multiframe

SET_SIG Overwrite Robbed-Bit Signaling—Applicable only during T1 mode and function dependent

on RIDLE. When RIDLE is inactive, SET_SIG forces received robbed-bit signaling to one

before updating RSLIP time slot value. Therefore, bit 8 of each time slot received during

signaling frames 6, 1 2, 18, an d 24 i s replaced with a one. This function i s particularl y u seful in

cross-connect and exchange systems that strip robbed-bit signaling or use different signaling

frame alignment on inbound and outbound ports.

0 = no change to receive signaling

1 = replace robbed-bit signaling

UNICODE Inband Signaling Freeze (applicable to T1 modes only)—If UNICODE is enabled, received

ABCD signaling on all channels is searched on a per-channel basis for the 4-bit UNICODE

pattern. UNICODE p attern detect ion i nhibit s STACK. R SIG buf f er update s f or that chan nel as

long as UNICODE is present, but does not affect SIGFRZ output and is not reported to the

processor. This function is described in Bellcore TR-TSY-000303, Section 4.4.9, Revision 2,

July 1989.

0 = no effect

1 = enable UNICODE detection and per-channel signaling freeze

11110 01 30 B

11110 10 30 C

11110 11 30 D

11111 00 31 A

11111 01 31 B

11111 10 31 C

11111 11 31 D

NOTE(S): Offsets whi ch are outside the TSB timebase range result in no pulses on

TFSYNC an d TM SYNC outpu ts .

7 6 5 4 3 2 1 0

— SET_RSIG SET_SIG UNICODE DEBOUNCE FRZ_OFF FRZ_ON THRU

8192 K bps/sec S BI Mode

OFFSET[9:5] OFFSET[4: 3] TSYNC Time

Slot Group

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-103

DEBOUNCE Debounce Receive ABCD Signaling—Applicable only to those channels where signaling

stack is enabled (SIG_STK; addr 180–19F). Output signaling buffer (RSIG) updates for these

channels are e v aluated aft er D-bit signaling is recei v ed. Ne w signaling is place d into RSIG and

STA CK buffers onl y if the RSIG input and output values dif fer. DEBOUNCE filters single bit

errors on ABCD signaling. This is accomplished by comparing incoming ABCD bits on a

bit-by-bit basis with current buffered input and output ABCD bits and inverting the update

signaling bit value when incoming and output bits are equal. However, these differ from the

buffered input value below. At the end of each multiframe, the entire input ABCD value is

copied to the output ABCD value.

0 = no effect

1 = debounce receive ABCD signaling

FRZ_OFF/FRZ_ON Manual Sig na ling Update and SIGFRZ Output—Allows the processor to manually control

updates of the receive signaling buffer [RSIGn; addr 1A0–1BF], the signaling stack [addr

0DA], and the SIGFRZ output pin. FRZ_ON and FRZ_OFF control the SIGFRZ pin’s output

state, but do not affect normal operations of the SIGFRZ interrupt [ISR7; addr 004]. Receive

ABCD input signaling is pla ced int o S TACK and RSIG buffers according t o t he modes shown

below. Stack updates are individually enabled on a per-channel basis according to SIG_STK

[addr 180–19F].

Sig Input Current Bit I/O Update Bit I/O Notes

000 00 —

0 01 00 Change output

0 10 00 Debounce

011 01 —

100 10 —

1 01 11 Debounce

1 10 11 Change output

111 11 —

NOTE(S): Normal (non -debounced) signaling always transfers ABCD input to ABC D output

buffer space coincident with the D-bit update.

SIGFRZ

FRZ_ON FRZ_OFF SIG_STK Interrupt Pin STACK RSIGn

0 0 0 0 0 No update All ABCD

0 0 X 1 1 No update No update

0 0 1 0 0 ABCD Changes All ABCD

X 0 X 0 No Update All ABCD

X 1 1 X 0 ABCD Changes All ABCD

1 0 X X 1 No update No Update

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-104 Conexant 100054E

THRU Enable Transparent Robbed-Bit Signaling—RMSYNC is forced to align with respect to RX

timebase and to follow each change of receiver’s multiframe alignment, plus any frame offset

caused by RSLIP buffer delay. In this m a nner, RMSYNC is able to reta in its signaling

multifra m e alignment with respect t o RPCMO outpu t data frames. THRU mode is require d

when RSLIP is configured in bypass mode. It is also useful for ADPCM transcoder systems

that utilize robbed-bit signaling during frames other than the normal (modulo 6) signaling

frames and therefo re cann ot utili ze RPCMO si gn aling reinsertion in ADPCM c oded chan nel s.

During THRU mode, RMSYNC must be programmed as an output [PIO; addr 018].

RMSYNC can follow a change of RX multiframe alignment without generating an alarm

indication (e.g., receiver change of SF alignment without accompanying loss of basic frame

alignment).

0 = no effect

1 = transparent robbed-bit signaling

0D8—Signaling Reinsertion Frame Offset (RSYNC_FRM)

Unused bits are reser ved and should be written to 0.

OFFSET[14:10] RSB Sync Frame Offset—Selects which RSB frame number coincides with RMSYNC pulse

in the range of frame 0–23. OFFSET specifies the frame in which RMSYNC is applied as an

input or in which RMSYNC appears as an output, consequently locating RPCMO signaling

frames used for T1 robbed-bit (frames 6,12,18, and 24) or E1 CAS signaling reinsertion. The

only RPCMO channels affected are those with signaling insertion enabled [INSERT; addr

0E0–0FF].

7 6 5 4 3 2 1 0

— — — OFFSET[14] OFFSET[13] OFFSET[12] OFFSET[11] OFFSET[10]

T1/E1N OFFSET[14:10] RMSYNC Pulse

0 X0000 RS B frame 0

0 X0001 RS B frame 1

|| |

0 X1110 RSB frame 14

0 X1111 RSB frame 15

1 00000 RSB frame 1

1 00001 RSB frame 2

|| |

1 10110 RSB fr ame 23

1 10111 RSB fr ame 24

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-105

0D9—Slip Buffer Status (SSTAT)

SSTAT[7:0] are updated at the start of each respective receive/transmit internal frame boundary (i.e. 125 µs

interval). Each bit in SSTAT is latched upon event detection and held until read cleared by the processor.

TSDIR Transmi t Sli p Direction—TSDIR is updated each t ime a TSLIP error is latched in TFSLIP and

TSDIR indicates which direction the slip occurred.

0 = TSLIP error deleted 1 frame on TX data output

1 = TSLIP error repeated 1 frame on TX data output

TFSLIP Controlled TSLIP Event—TUSLIP and TFSLIP event status are latched active high when

transmit slip error is detected. Either event reports a TSLIP error in ISR5 [addr 006]. Active

high hold interval is defined by LATCH_ERR [addr 046].

Two types of errors are detected:

1. FSLIP = Controlled ± frame slip on T X data o utput . FSLIP af f ects tra nsmit

time slot data, but does not change transmit timebase or frame alignment.

2. USLIP = Uncontrolled ± 1 t o ± 256 bi t sli p on TX data. USLI P affects both

time slot data and frame alignment. TUSLIP and TFSLIP status depends

on transmit system bus configuration [TSB_CR; addr 0D4].

TUSLIP Uncontrolled TSLIP Event—See TFSLIP description.

TDLY Transmit Slip Buffer Delay > One Frame—Indicates that real-time phase difference between

TSLIP read and write pointers is more than 192 bits (T1) or 256 bits (E1). TDLY provides a

coarse phase indicator and toggles (low) if transmit system bus clock phase advances with

respect to the transmit line rate clock. A finer granularity of TSLIP phase is reported in

TPHASE [ad dr 0DC].

0 = TSLIP delay less than or equal to 1 frame

1 = TSLIP delay greater than 1 frame

7 6 5 4 3 2 1 0

TSDIR TFSLIP TUSLIP TDLY RSDIR RFSLIP RUSLIP RDLY

TSBI Mode TUSLIP TFSLIP TSLIP Event

Normal 0 0 None

0 1 FSLIP

10 USLIP

11(1) Both FSLIP and USLIP

Short 0 0 None

0 1 FSLIP

10 USLIP

Elastic 0 n/a None

1n/a USLIP

Bypass n/a n/a —

NOTE(S):

(1) Most rece nt slip error direct ion is reported in TSDIR.

2. TFSLIP not applicable (read zero value) if TSLIP is bypassed or configured as elastic store.

TUSLIP not applicable if TSLIP bypassed. In short delay mode, if the bus clock is faster than the

receive cl ock, the system bus will resynchronize and USLIP i s reported. If the receive clock is

faster, RSLIP reverts to normal mode and subsequently reports FSLIP errors.

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-106 Conexant 100054E

RSDIR Receiv e Slip Direction —RSDIR is updated each time an RSLIP error is latched in RFSLIP or

RUSLIP and indicates which direction the slip occurred.

0 = RSLIP error deleted one frame on RPCMO or SBI resync detected

1 = RSLIP error repeated one frame on RPCMO or SBI time slot reassigned

RFSLIP Controlled RSLIP Event—RUSLIP and RFSLIP event status are latched active high when

recei v e slip error is detect ed. Either ev ent rep orts RSLIP error in ISR5 [addr 006]. Active high

hold interval is defined by LATCH_ERR [addr 046]. Two types of errors are detected:

1. FSLI P = Control led ± 1 frame slip on RPCMO data output. FSLIP affects

RPCMO, but does not change alignment of system bus RFSYNC or

RMSYNC signals.

2. USLIP = Uncontrolled ± 1 to ± 256 bit slip on RPCMO. USLIP affects

both system bus data and sync outputs. RUSLIP and RFSLIP status

depends on receive system bus configuration [RSB_CR; addr 0D1].

RUSLIP Uncontrolled RSLIP Event—See RFSLIP description.

RDLY Receive Slip Buffer Delay > 1 Frame—Indicates that real-time phase difference between

RSLIP read and write pointers is more than 192 bits (T1) or 256 bits (E1). RDLY provides a

coarse phase indicator and toggles (low) if receive clock phase advances with respect to

receive system bus clock. A finer granularity of RSLIP phase is reported in RPHASE [addr

0DB].

0 = RSLIP delay less than or equal to 1 frame

1 = RSLIP delay greater than 1 frame

RSBI Mode RUSLIP RFSLIP RSLIP

Event Notes

Normal 0 0 None

0 1 FSLIP Most recent slip error direction is reported

in RSDIR.

10USLIPAn uncontrolled slip can occur in Normal

mode due to a resync of the SBI, or in T1

rate converted applications, the active

time slots are reassigned. The former sets

RSDIR = 0, the latter RSDIR = 1.

Short 0 0 None

0 1 FSLIP

10USLIPIn short delay mode, if bus clock is faster

than receive clock, system bus will

resynchronize and USLIP is reported. If

receive clock is faster, RSLIP reverts to

Normal mode and subsequently reports

FSLIP errors.

Elastic 0 0 None

10USLIPRFSLIP is not applicable (read zero

value) while RSLIP buffer is bypassed or

configured as elastic store. FSLIP or

USLIP errors reported upon bypass mode

initialization should be ignored.

Bypass – – –

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-107

0DA—Receive Signaling Stack (STACK)

STACK contains new signaling information from those channels with SIG_STK [addr 180–19F] enabled.

STACK allows the processor to conveniently monitor only changed ABCD signaling values from the selected

channels. RSIG interrupt [addr 008] is triggered at the end of any multiframe where one or more ABCD

signaling values have changed. The processor reads the STACK address twice to retrieve the channel number

(WORD = 0) and to retrieve the new ABCD value (WORD = 1). The processor continues to read from STACK

until the la st new value is retrieved (MORE = 0).

Internal STACK read/write pointers are initialized by RESET [addr 001]. STACK contents are updated for

each channel in which the stack is enabled [SIG_STK; addr 180–19F]. STACK contents are updated with new

output signaling if the buf fered RSIGn input and output ABCD signaling va lues dif fer. STA CK is e v aluated on a

channel-by-channel basis after the D-bit is updated. The processor must poll the RSIG interrupt to determine

w hen STAC K has ne w info rmation.

Word 0: Channel Number (first read)

WORD Stack Word ID (always 0 in Word 0)

MORE More Stack Content s (alway s 1 in Word 0)

CH[4:0] Channel Number (E1 range 0–31; T1 range 1–24)

Word 1: New Signaling Value (second read)

WORD Stack Word ID (always 1 in Word 1)

MORE More Stack Contents equal 1 if more available.

SIG_BITA–D Signaling Bit A–D–Processor reads the new ABCD signaling value from this location. The

ABCD v alue i s also p reset in RSI Gn (addr 1A0–1BF) output signali ng buf f er, so the proc essor

does not need to store a local copy of each channel’s signaling status.

7 6 5 4 3 2 1 0

WORD MORE — CH[4] CH[3] CH[2] CH[1] CH[0]

7 6 5 4 3 2 1 0

WORD MORE — — SIG_BITA SIG_BITB SIG_BITC SIG_BITD

WORD MORE MPU Resp onse

0 0 First word, get channel

01Never used

1 0 No change or last change, stop

1 1 New signaling, keep reading

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-108 Conexant 100054E

0DB—RSLIP Phase Status (RPHASE)

RDELAY[5:0] RSLIP Buffer Delay—Difference between RX and RSB timebase in time slot intervals.

Reported once per frame coincident with RFRAME interrupt [ISR3; addr 008]. Actual delay

may vary significantly, depending on which time slots are assigned.

000000 = RX to RSB delay in the range of 0–7 bits

111111 = RX to RSB delay in the range of 504–511 bits

RSLIP_WR Active RSB Slip Buffer Half—Th is bit indicates which half of the receive slip buffer is

currently supplying data to the Receive System Bus (0 = RLIP_LO, 1 = RSLIP_HI). The

processor can write data to the opposite buffer half.

RSLIP_R D Active Receiver Slip Buffer Half—This bit indica te s which h a lf of the receive slip buffer is

currently rece iving data from the receiver (0 = RSLIP_LO, 1 = RSLIP_HI). The proc essor can

read data from the opposite buffer half.

0DC—TSLIP Phase Status (TPHASE)

TDELAY[5:0] TSLIP Buffer Delay—Difference between TSB and TX timebase in time slot intervals.

Reported once per frame coincident with TFRAME interrupt [ISR3; addr 008]. The actual

delay may vary significantly, depending on which time slots are assigned.

000000 = TSB to TX delay in the range of 0–7 bits

111111 = TSB to TX delay in the range of 496–503 bits

TSLIP_WR Active T ransmitter Slip Buffer Half—This bit indicates which half of the transmit slip buffer is

currentl y suppl y ing dat a to t he transmi tter ( 0 = TS LIP_LO, 1 = TSLI P_HI). Th e proce ssor can

write data to the opposite buffer half.

TSLIP_RD Active TSB Slip Buffer Half—This bit indic ates which half of the transmit slip buffer is

currently receiving data from the Transmit System Bus (0 = TSLIP_LO, 1 = TSLIP_HI). The

processor can read data from the opposite buffer half.

7 6 5 4 3 2 1 0

RDELAY[5] RDELAY[4] RDELAY[3] RDELAY[2] RDELAY[1] RDELAY[0] RSLIP_WR RSLIP_RD

7 6 5 4 3 2 1 0

TDELAY[5] TDELAY[4] TDELAY[3] TDELAY[2] TDELAY[1] TDELAY[0] TSLIP_WR TSLIP_RD

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-109

0DD—RAM Parity Status (PERR)

All system bus data, si gnaling, and cont rols are tran sferred through a set of internal RAMs tha t ha ve pa rity error

detection capabilities. Any parity error that is detected during a RAM access is reported in PERR. Each error

e ven t is latched active high and held until the processor read clears PERR. Parity errors are indicative of system

clock glitches (REFCKI, TSBCKI, or RSBCKI), a failing or excessively noisy power supply, or general circuit

failure.

PERR_TPC TPC (Transmit) RAM Parity Error

PERR_RPC RPC (Receive) RAM Parity Err or

PERR_SBC SBC (Control) RAM Parity Error

0E0–0FF—System Bus Per-Channel Control (SBCn; n = 0 to 31)

INS ERT Insert RX Signal ing on RPCMO—En abl es per- channel signal ing insertion on RPCMO o utput,

where ABCD signaling is supplied by RLOCAL signaling (RPCn; addr 180–19F) or buffered

signaling [RSIGn; addr 1A0–IBF]. INSERT is a lower priority than no signaling (SIG_OFF;

addr 0D1). RSB signaling frame locations are specified by RMSYNC signal in conjunction

with programmed frame offset [OFFSET; addr 0D8].

SIG_LP Local Signaling Loopback—RSIGO output signaling supplied from TSIGn buffer contents.

0 = normal

1 = local signaling loopback

RLOOP Local Loopback—RPCMO output data supplied from TSLIP buffer contents.

0 = normal

1 = local loopback

RINDO Activate RINDO Time Slot Indicator—Receive system bus time slots are individually marked

(active high for 8 bits) by RINDO. Note that SBI_OE (addr 0D0) over rides RINDO.

0 = RINDO signal inactive (low)

1 = RINDO signal active (high)

TINDO Activ ate TINDO Time Slot Indicator—T ransmit system bus time slots are indi viduall y marked

(active high for 8 bits) by TINDO.

0 = TINDO inactive

1 = TINDO active

7 6 5 4 3 2 1 0

— — — — — PERR_TPC PERR_RPC PERR_SBC

7 6 5 4 3 2 1 0

— INSERT SIG_LP RLOOP RINDO TINDO TSIG_AB ASSIGN

SIG_OFF INSERT RLOCAL RPCMO Inserte d Signal

1XXNone

0 1 0 A BCD from RSIG n output buffer

0 1 1 ABCD from RPCn local buffer

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-110 Conexant 100054E

TSIG_AB TSIG_AB—AB Signaling. In T1 mode, only AB signaling bit s are up dat ed f r om TSI GI to t he

TSIGn buffer. If SIGFRZ active, outpu t CD sign ali ng bits are copi ed f rom t he buffered output

AB bits r espect ivel y. In E1 mode, setting TSI G_AB for ces C = 0 an d D = 1 when updati ng the

TSIGn buffer.

0 = ABCD signaling

1= AB signaling

ASSIGN Assign System Bus Time Slot—During T1 line applications where the system bus g roup

consis ts of 32 tim e slots, ASSIGN selects which 24 of 32 time slots are use d to transport li ne

time slot s. The numb er of assigned system bu s time sl ots must a l ways equal the numb er of line

time slots, therefore ASSIGN must be active in all 32 SBCn locations during E1 modes.

Unassigned time slots are not updated by the receiver as it fills the RSLIP buffer. T1 time slots

are filled sequentially from RSLIP 1 to 24. Time slots 0 and 25 to 31 are reserved for

unassigned values. Values are read from either the assigned or unassigned locations in a

sequential fashion based upon the ASSIGN bit. System bus output data for unassigned time

slots is taken from RSLIP buffer, which the processor can fill with any desired 16-bit fixed

value (8 bits in RSLIP_LO, plus 8 bits in RSLIP_HI).

0 = unassigned system bus time slot

1 = assigned system bus time slot

100–11F—Transmit Per-Channel Control (TPCn; n = 0 to 31)

TB7ZS /E M F- BI T Bit7 Zero Code Substitution/Embedded F-bit Value (Applicable in T1 mode only)—For

assigned system bus time slots [ASSIGN; addr 0E0-0FF], TB7ZS replaces Bit 7 of the time

slot with a 1, if examination of 8-bit output detects all zeros. F or an unassigned time slot w here

TIDLE is active, EMF-BIT replaces all embedded F-bit outputs with the programmed

EMF-BIT value.

0 = no effect or force embedded F-bit (low)

1 = enable B7ZS or force embedded F-bit (high)

7 6 5 4 3 2 1 0

TB7ZS/EMF-BIT TLOOP TIDLE TLOCAL TSIGA/TSIGO TSIGB/RSIGO TSIGC TSIGD

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-111

TLOOP Remote DS0 Channel Loopback—Transmit data supplied from RSLIP buffer contents.

TLOOP works in conjunction with other TPCn control bits to select the sour c e of transmitt ed

data and signaling (see Table 3-23).

TIDLE Transmit Idl e—Transmit data supplie d from TSL IP_L O buffer conten ts. T he processo r wri tes

an 8-bit idle pattern to TSLIP_LO for output on the selected time slot or optionally writes

real-time data output to TSLIP_LO after each TFRAME interrupt [ISR3; addr 008]. Only the

TSLIP_HI buffer is updated from TPCMI to allow continued local DS0 channel loopback.

0 = normal data output

1 = transmit idle data output

TLOCAL T ransmi t Local Signaling—When act iv e, TLOCAL transmit s TSIGA–TSIGD values in out put

ABCD signaling bits.

0 = TSIGO or RSIGO control output signaling

1 = transmit signaling from TSIGA–TSIGD

TSIGA–T SIGD Transmit Local Signaling—Holds the 4-bit ABCD signaling value, which is output when

TLOCAL is active. In AB onl y app licat ions, such as T1/SF frami ng, TSIGC and TSIGD must

also be written with the same data as TSIGA and TSIGB. In E1 modes, TS0 and TS16 local

signaling value determines CAS multiframe alignment signal (MAS) and XYXX output.

TSIGO Transmit Signaling Output—Applicable only if TLOCAL is inactive. ABCD signaling from

TSIGn bu ffer is transmitted.

0 = no effect

1 = transmit signaling from TSIGn buffer

RSIGO Receive Signaling Output—Applicable only if TLOCAL is inactive. Forces transmit ABCD

signaling to be supplied from RSIGn buffer, affecting a remote signaling loopback.

0 = no effect

1 = transmit signaling from RSIGn buffer

Table 3-23. Remote DS0 Channel Loopback

TLOOP TIDLE Data Source Channel Mode

00TPCMINormal

0 1 TSLIP_LO Transmit Idle

1 0 RXDATA Remote Loop

1 1 TSLIP_LO Transmit Idle

NOTE(S): If RX Signaling, then RSIGn output buffer supplies transmit signaling.

Tab le 3-24. S ignaling Loopback

TLOCAL TSIGO RSIGO Sig So urce Signaling Mode

0 0 0 None No Transmit Signaling

0 0 1 RSIGn Remote Signaling Lo opback

0 1 0 TSIGn TX Signaling Loopback

1 X X TSIGA–D Local Signaling

NOTE(S): If RX Signaling, then RSIGn output buffer supplies transmit signaling.

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-112 Conexant 100054E

120–13F—Transmit Signaling Buffer (TSIGn; n = 0 to 31)

T r ansmit signal ing fr om the TSI GI pin is aut omatic all y p laced in to the TSIGn buf f er. Processor control s TSIGn

insertion into the transmitter output b y selecting TSIGO[inTPCn]. The processor can read monitor TSIGn from

system supplied signaling or can use TSIGn for inter-processor communication. During E1 modes, TSIG0 and

TSIG16 buffer locations hold the CAS multiframe alignment signal (MAS.1 through MAS.4), Extra bits (X.1

through X.4), and multiframe yellow alarm (MYEL) bits supplied from TSIGI.

Unused bits are reser ved and should be written to 0.

140–15F—Transmit PCM Slip Buffer (TSLIP_LOn; n = 0 to 31)

TPCM[1] First bit

TPCM[2] Second bit

TPCM[3] Third bit

TPCM[4] Fourth bit

TPCM[5] Fifth bit

TPCM[6] Sixth bit

TPCM[7] Seventh bit

TPCM[8] Eighth bit received on TPCMI

7 6 5 4 3 2 1 0

— — — — TSIGn[3] TSIGn[2] TSIGn[1] TSIGn[0]

TSIG0 (E1) TSIG16 (E1)

TSIGn.3. Input Signaling A Bit MAS.1 X.1

TSIGn.2. Input Signaling B Bit MAS.2 MYEL

TSIGn.1. Input Signaling C Bit MAS.3 X.3

TSIGn.0. Input Signaling D Bit MAS.4 X.4

7 6 5 4 3 2 1 0

TPCM[1] TPCM[2] TPCM[3] TPCM[4] TPCM[5] TPCM[6] TPCM[7] TPCM[8]

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-113

160–17F—Transmit PCM Slip Buffer (TSLIP_HIn; n = 0 to 31)

TPCM[1] First bit

TPCM[2] Second bit

TPCM[3] Third bit

TPCM[4] Fourth bit

TPCM[5] Fifth bit

TPCM[6] Sixth bit

TPCM[7] Seventh bit

TPCM[8] Eighth bit received on TPCMI

180–19F—Receive Per-Channel Control (RPCn; n = 0 to 31)

RSIG_AB/EMF-BIT AB Signaling (Per-Channel RSIG_AB [without DEBOUNCE])—In E1 mode, received

signaling is placed into RSIGn as usual. However, RSIGO output duplicates the buffered AB

bit value in the CD output bits, thu s sendi ng ABAB on RSIGO instead of ABCD. In T1 mod e,

RSIG_AB instructs the receiver to use available RSIGn buffer space to meet PUB43801 and

TR-170. PUB43801 and TR-170 require three SF multiframes of receive signaling buffer

storage before outpu t. Ev ery 24 frames, t he recei ved ABCD signali ng v alue i s transferred from

the RSIGn i nput buffer space to RSIGn ou tp ut buffer space, regard le ss of whether the receiver

operates in SF, SLC, or ESF mode. Therefore, in SF mode, the ABCD value contains AB =

AB(N-1) and CD = AB(N) fro m two multiframes. Since multiframe N-1 is the older sample,

AB(N-1) replaces AB(N) in the event of signaling freeze. RSIGO and RPCMO signaling bit

output values are always taken from the RSIGn output buffer, according to the RSB frame

number.

7 6 5 4 3 2 1 0

TPCM[1] TPCM[2] TPCM[3] TPCM[4] TPCM[5] TPCM[6] TPCM[7] TPCM[8]

7 6 5 4 3 2 1 0

RSIG_AB/

EMF-BIT RIDLE SIG_STK RLOCAL RSIGA RSIGB RSIGC RSIGD

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-114 Conexant 100054E

AB Signaling (Per-Channel RSIG_AB [with DEB OUNCE])— Debounce is applicable only

for T1 modes and affects the RSIGn input buffer update mechanism. This is accomplished by

comparing, on a bit-by-bit basis, the present received input signaling bit value with the current

buffered signaling bit values from two prior multiframes. If signaling from prior multiframe

(N) differs from input, and input equals buffered value from 2 multiframes prior (N-1),

signaling bit value from multiframe N is inverted when the input buffer is updated.

When RIDLE is active in an unassigned time slot defined to carry embedded F-bits,

EMFBIT replaces all embedded F-bit outputs on RPCMO with the programmed value.

0 = normal ABCD and embedded F-bit throughput

1 = AB signaling and embedded F-bit replacement

RIDLE Time Slot Idle—When RIDLE is active, the incoming RX time slot data is only updated in the

RSLIP_HIn buffer, and the RSB time slot data output is only extracted from RSLIP_LOn

buffer. Thus, the processor can write an 8-bit idle code pattern in RSLIP_LOn buffer for

output during the RSB time slot.

0 = no effect

1 = RSB time slot replaced by contents of RSLIP_LOn

SIG_STK Receive Signaling Stack—Selects whether changes detected in the ABCD signaling value are

reported in signaling stack [addr 0DA]. Note that signaling for all time slots is continuously

updated in RSIGn buffer, regardless of the SIG_STK setting.

0 = no effect

1 = signaling stack

RLOCAL Enable Local Signaling Output—Determines whether the RSIGO output signaling and

RPCMO inserted signaling [INSERT; addr 0E0-0FF] are supplied from RSIGn output buffer

or processor supplied local signaling from RSIGA–RSIGD.

0 = RSIGn buffer signaling

1 = RSIGA-RSIGD local signaling

RSIGA–RSIGD Local Receive Signaling—When RLOCAL is active, these 4 bits are inserted into RSIGO

instead of the buffered signaling from RSIG n. If bot h RLOCAL and INS ERT are active, these

4 bits are also inserted into RPCMO during system bus signaling frames.

0 = output signaling bit equals zero

1 = output signaling bit equals one

Sig Input Buffer N, N-1 Update N, N-1 Notes

00000—

0 01 00 Change update

0 10 00 Debounce

01101—

10010—

1 01 11 Debounce

1 10 11 Change update

11111—

CX28394/28395/28398 3.0 Registers

Quad/x16/Octal—T1/E1/J1 Framers 3.16 System Bus Registers

100054E Conexant 3-115

1A0–1BF—Receive Signaling Buffer (RSIGn; n = 0 to 31)

The Receive Signaling Buffer (RSIGn) contains all ABCD signaling inputs from all channels, regardless of

whether signaling is active [SIG_STK; addr 180–19F]. RSIGn is not updated during signaling freeze

conditions, or when the receive framer is configured in a non-signaling mode. Normal signaling buffer

operation transfers ABCD input to ABCD output coincident with the D-bit update (in T1 mode) or coincident

with receipt of respective channel's ABCD signaling during TS16 (in E1 mode). When DEBOUNCE is active,

output sig naling for act i v e chann els is updat ed coin cident with t he sampling of each input signali ng bit and may

cause the buffered output value to transition in the middle of the received multiframe.

RSIGn[7] Output Signaling A Bit

RSIGn[6] Output Signaling B Bit

RSIGn[5] Output Signaling C Bit

RSIGn[4] Output Signaling D Bit

1C0–1DF—Receive PCM Slip Buffer (RSLIP_LOn; n = 0 to 31)

RPCM[1] First bit

RPCM[2] Second bit

RPCM[3] Third bit

RPCM[4] Fourth bit

RPCM[5] Fifth bit

RPCM[6] Sixth bit

RPCM[7] Seventh bit

RPCM[8] Eighth bit received from receiver

7 6 5 4 3 2 1 0

RSIGn[7] RSIGn[6] RSIGn[5] RSIGn[4] RSIGn[3] RSIGn[2] RSIGn[1] RSIGn[0]

RSIG0 (E1) RSIG16 (E1)

RSIGn[3]. Input Signaling A Bit MAS.1 X.1

RSIGn[2]. Input Signaling B Bit MAS.2 MYEL

RSIGn[1]. Input Signaling C Bit M AS.3 X.3

RSIGn[0]. Input Signaling D Bit MAS.4 X.4

7 6 5 4 3 2 1 0

RPCM[1] RPCM[2] RPCM[3] RPCM[4] RPCM[5] RPCM[6] RPCM[7] RPCM[8]

3.0 Registers CX28394/28395/28398

3.16 System Bus Registers Quad/x16/Octal—T1/E1/J1 Framers

3-116 Conexant 100054E

1E0–1FF—Receive PCM Slip Buffer (RSLIP_HIn; n = 0 to 31)

RPCM[1] First bit

RPCM[2] Second bit

RPCM[3] Third bit

RPCM[4] Fourth bit

RPCM[5] Fifth bit

RPCM[6] Sixth bit

RPCM[7] Seventh bit

RPCM[8] Eighth bit received from receiver

7 6 5 4 3 2 1 0

RPCM[1] RPCM[2] RPCM[3] RPCM[4] RPCM[5] RPCM[6] RPCM[7] RPCM[8]

CX28394/28395/28398

3.0 Register

Quad/x16/Octal—T1/E1/J1 Framers

3.17 Register Summary

100054E

Conexant

3-117

3.17 Register Summar y

Table 3-25. Global Control and Status Registers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

000 DID R DID[7] DID[6] DID[5] DID[4] DID[3] DID[2] DID[1] DID[0]

080FCRR/WGRESET————ONESEC_IOSBIMODE[1]SBIMODE[0]

081 MIR R MIR[7] MIR[6] MIR[5] MIR[4] MIR[3] MIR[2] MIR[1] MIR[0]

082 MIE R/W MIE[7] MIE[6] MIE[5] MIE[4] MIE[3] MIE[2] MIE[1] MIE[0]

083TESTR/W——————TEST—

Table 3-26. Primary Control Register

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

001 CR0 R/W RESET — — RFRAME[3] RFRAME[2] RFRAME[1] RFRAME[0] TI/EIN

Table 3-27. Interrupt Control Register

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

003 IRR R ALARM1 ALARM2 ERROR COUNT TIMER DL1 DL2 PATT

2.0 Register

CX28394/28395/28398

3.17 Register Summary

Quad/x16/Octal—T1/E1/J1 Framers

3-118

Conexant

100054E

Table 3-28. Interrupt Status Registers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

004 ISR7 R RMYEL RYEL RPDV RAIS RALOS RLOS RLOF SIGFRZ

005 ISR6 R LOOPDN LOOPUP TPDV — TLOC — TLOF ONESEC

006 ISR5 R TSLIP RSLIP — — CERR SERR MERR FERR

007 ISR4 R RLOF[4] COFA[2] SEF[2] BERR[12] FEBE[10] LCV[16] CRC[10] FERR[12]

008 ISR3 R TSIG TMSYNC TMF TFRAME RSIG RMSYNC RMF RFRAME

009 ISR2 R TBOP RFULL1 RNEAR1 RMSG1 TDLERR1 TEMPTY1 TNEAR1 TMSG1

00A ISR1 R RBOP RFULL2 RNEAR2 RMSG2 TDLERR2 TEMPTY2 TNEAR2 TMSG2

00B ISR0 R — — BSLIP PSYNC TCERR TSERR TMERR TFERR

Table 3-29. Interrupt Enable Registers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

00C IER7 R/W RMYEL RYEL RPDV RAIS RALOS RLOS RLOF SIGFRZ

00D IER6 R/W LOOPDN LOOPUP TPDV — TLOC — TLOF ONESEC

00E IER5 R/W TSLIP RSLIP — — CERR SERR MERR FERR

00F IER4 R/W LOF COFA SEF BERR FEBE LCV CRC FERR

010 IER3 R/W TSIG TMSYNC TMF TFRAME RSIG RMSYNC RMF RFRAME

011 IER2 R/W TBOP RFULL1 RNEAR1 RMSG1 TDLERR1 TEMPTY1 TNEAR1 TMSG1

012 IER1 R/W RBOP RFULL2 RNEAR2 RMSG2 RDLERR2 TEMPTY2 TNEAR2 TMSG2

013 IER0 R/W — — BSLIP PSYNC TCERR TSERR TMERR TFERR

CX28394/28395/28398

3.0 Register

Quad/x16/Octal—T1/E1/J1 Framers

3.17 Register Summary

100054E

Conexant

3-119

Table 3-30. P r i mary Control and St atus Registers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

014 LOOP R/W — — — — PLOOP LLOOP FLOOP —

015 DL3_TS R/W DL3EN ODD EVEN TS[4] TS[3] TS[2] TS[1] TS[0]

016 DL3_BIT R/W DL3_BIT[7] DL3_BIT[6] DL3_BIT[5] DL3_BIT[4] DL3_BIT[3] DL3_BIT[2] DL3_BIT[1] DL3_BIT[0]

017 FSTAT R — — — INVALID FOUND TIMEOUT ACTIVE RX/TXN

018 PIO R/W RMSYNC_EN RDL_IO TMSYNC_EN TDL_IO RFSYNC_IO RMSYNC_IO TFSYNC_IO TMSYNC_IO

019 POE R/W — — TDL_OE RDL_OE INDY_OE TCKO_OE — —

01A CMUX R/W — RSBCK — TSBCK — — TXCLKI[1] TXCLKI[0]

020 RAC R/W — — — RAL_CON — — — —

021 RSTAT R — — ZCSUB EXZ BPV — — —

Table 3-31. Serial I nterfac e Regis ters

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

022 SER_CTL R/W SER_A[6] SER_A[5] SER_A[4] SER_A[3] SER_A[2] SER_A[1] SER_A[0] SER_RW

023 SER_DAT R/W SER_DAT[7] SER_DAT[6] SER_DAT[5] SER_DAT[4] SER_DAT[3] SER_DAT[2] SER_DAT[1] SER_DAT[0]

024SER_STATR/W———————SER_DONE

025 SER_CONFIG R/W SER_CS SER_CLK — — — — — SER_IER

026 RAM Test R/W RT[7] RT[6] RT[5] RT[4] R T[3] RT[2] R T[1] RT[0]

2.0 Register

CX28394/28395/28398

3.17 Register Summary

Quad/x16/Octal—T1/E1/J1 Framers

3-120

Conexant

100054E

Table 3-32. Receiver Regist ers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

040 RCR0 R/W RAMI RABORT RFORCE RLOFD RLOFC RLOFB RLOFA RZCS

041 RPATT R/W — — RESEED BSTART FRAMED ZLIMIT RPATT[1] RPATT[0]

042 RLB R/W — — — — DN_LEN[1] DN_LEN[0] UP_LEN[1] UP_LEN[0]

043 LBA R/W LBA[1] LBA[2] LBA[3] LBA[4] LBA[5] LBA[6] LBA[7] —

044 LBD R/W LBD[1] LBD[2] LBD[3] LBD[4] LBD[5] LBD[6] LBD[7] —

045 RALM R/W — — FS_NFAS EXZ_LCV YEL_INTEG RLOF_INTEG RPCM_YEL RPCM_AIS

046 LATCH R/W — — — — STOP_CNT LATCH_CNT LATCH_ERR LATCH_ALM

047 ALM1 R RMYEL RYEL — RAIS RALOS RLOS RLOF SIGFRZ

048 ALM2 R LOOPDN LOOPUP — — TLOC — TLOF —

049 ALM3 R — RMAIS SEF SRED MRED FRED LOF[1] LOF[0]

CX28394/28395/28398

3.0 Register

Quad/x16/Octal—T1/E1/J1 Framers

3.17 Register Summary

100054E

Conexant

3-121

Table 3-33. P erformance Mo nitoring Registers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

050 FERR R FERR[7] FERR[6] FERR[5] FERR[4] FERR[3] FERR[2] FERR[1] FERR[0]

051FERRR0000FERR[11]FERR[10]FERR[9]FERR[8]

052 CERR R CERR[7] CERR[6] CERR[5] CERR[4] CERR[3] CERR[2] CERR[1] CERR[0]

053CERRR000000CERR[9]CERR[8]

054 LCV R LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0]

055 LCV R LCV[15] LCV[14] LCV[13] LCV[12] LCV[11] LCV[10] LCV[9] LCV[8]

056 FEBE R FEBE[7] FEBE[6] FEBE[5] FEBE[4] FEBE[3] FEBE[2] FEBE[1] FEBE[0]

057FEBER000000FEBE[9]FEBE[8]

058 BERR R BERR[7] BERR[6] BERR[5] BERR[4] BERR[3] BERR[2] BERR[1] BERR[0]

059BERRR0000BERR[11]BERR[10]BERR[9]BERR[8]

05A AERR R FRED[3] FRED[2] FRED[1] FRED[0] COFA[1] COFA[0] SEF[1] SEF[0]

Table 3-34. Receive S a-Byte Buffers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

05B RSA4 R RSA4[7] RSA4[6] RSA4[5] RSA4[4] RSA4[3] RSA4[2] RSA4[1] RSA4[0]

05C RSA5 R RSA5[7] RSA5[6] RSA5[5] RSA5[4] RSA5[3] RSA5[2] RSA5[1] RSA5[0]

05D RSA6 R RSA6[7] RSA6[6] RSA6[5] RSA6[4] RSA6[3] RSA6[2] RSA6[1] RSA6[0]

05E RSA7 R RSA7[7] RSA7[6] RSA7[5] RSA7[4] RSA7[3] RSA7[2] RSA7[1] RSA7[0]

05F RSA8 R RSA8[7] RSA8[6] RSA8[5] RSA8[4] RSA8[3] RSA8[2] RSA8[1] RSA8[0]

2.0 Register

CX28394/28395/28398

3.17 Register Summary

Quad/x16/Octal—T1/E1/J1 Framers

3-122

Conexant

100054E

Table 3-35. Transmitter Re gisters

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

070 TCR0 R/W — — — — TFRAME[3] TFRAME[2] TFRAME[1] TFRAME[0]

071 TCR1 R/W TNRZ TABORT TFORCE TLOFC TLOFB TLOFA TZCS[1] TZCS[0]

072 TFRM R/W — — INS_MYEL INS_YEL INS_MF INS_FE INS_CRC INS_FBIT

073 TERROR R/W TSERR TMERR TBERR BSLIP TCOFA TCERR TFERR TVERR

074 TMAN R/W INS_SA[8] INS_SA[7] INS_SA[6] INS_SA[5] INS_SA[4] FEBE_II FEBE_I TFEBE

075 TALM R/W — AISCLK AUTO_MYEL AUTO_YEL AUTO_AIS TMYEL TYEL TAIS

076 TPATT R/W — — — TPSTART FRAMED ZLIMIT TPATT[1] TPATT[0]

077 TLB R/W — — — — LB_LEN[1] LB_LEN[0] UNFRAMED LBSTART

078 LBP R/W LBP[1] LBP[2] LBP[3] LBP[4] LBP[5] LBP[6] LBP[7] —

Table 3-36. Transmit Sa-Byt e Buffers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

07B TSA4 R/W TSA4[7] TSA4[6] TSA4[5] TSA4[4] TSA4[3] TSA4[2] TSA4[1] TSA4[0]

07C TSA5 R/W TSA5[7] TSA5[6] TSA5[5] TSA5[4] TSA5[3] TSA5[2] TSA5[1] TSA5[0]

07D TSA6 R/W TSA6[7] TSA6[6] TSA6[5] TSA6[4] TSA6[3] TSA6[2] TSA6[1] TSA6[0]

07E TSA7 R/W TSA7[7] TSA7[6] TSA7[5] TSA7[4] TSA7[3] TSA7[2] TSA7[1] TSA7[0]

07F TSA8 R/W TSA8[7] TSA8[6] TSA8[5] TSA8[4] TSA8[3] TSA8[2] TSA8[1] TSA8[0]

CX28394/28395/28398

3.0 Register

Quad/x16/Octal—T1/E1/J1 Framers

3.17 Register Summary

100054E

Conexant

3-123

Table 3-37. Bit-Oriented Protocol Registers

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

0A0 BOP R/W RBOP_START RBOP_INTEG RBOP_LEN[1] RBOP_LEN[0] TBOP_LEN[1] TBOP_LEN[0] TBOP_MODE[1] TBOP_MODE[0]

0A1 TBOP R/W — — TBOP[5] TBOP[4] TBOP[3] TBOP[2] TBOP[1] TBOP[0]

0A2 RBOP R RBOP_LOST RBOP_VALID RBOP[5] RBOP[4] RBOP[3] RBOP[2] RBOP[1] RBOP[0]

0A3 BOP_STAT R TBOP_ACTIVE RBOP_ACTIVE — — — — — —

Table 3-38. Data Link Registers (1 of 2)

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

0A4 DL1_TS R/W DL1_TS[7] DL1_TS[6] DL1_TS[5] DL1_TS[4] DL1_TS[3] DL1_TS[2] DL1_TS[1] DL1_TS[0]

0A5 DL1_BIT R/W DL1_BIT[7] DL1_BIT[6] DL1_BIT[5] DL1_BIT[4] DL1_BIT[3] DL1_BIT[2] DL1_BIT[1] DL1_BIT[0]

0A6 DL1_CTL R/W — — — TDL1_RPT DL1[1] DL1[0] TDL1_EN RDL1_EN

0A7 RDL1_FFC R/W MSG_FILL[1] MSG_FILL[0] FFC[5] FFC[4] FFC[3] FFC[2] FFC[1] FFC[0]

0A8 RDL1 R EOM[1] EOM[0] RDL1_CNT[5] RDL1_CNT[4] RDL1_CNT[3] RDL1_CNT[2] RDL1_CNT[1] RDL1_CNT[0]

RDL1[7] RDL1[6] RDL1[5] RDL1[4] RDL1[3] RDL1[2] RDL1[1] RDL1[0]

0A9 RDL1_STAT R — — — RMSG1 RSTAT1 RMPTY1 RNEAR1 RFULL1

0AA PRM R/W AUTO_PRM PRM_CR PRM_R PRM_U1 PRM_U2 PRM_SL AUTO_SL SEND_PRM

0AB TDL1_FEC R/W — — FEC[5] FEC[4] FEC[3] FEC[2] FEC[1] FEC[0]

0ACTDL1_EOMW————————

0AD TDL1 W TDL1[7] TDL1[6] TDL1[5] TDL1[4] TDL1[3] TDL1[2] TDL1[1] TDL1[0]

0AE TDL1_STAT R — — — — TMSG1 TMPTY1 TNEAR1 TFULL1

0AF DL2_TS R/W DL2_TS[7] DL2_TS[6] DL2_TS[5] DL2_TS[4] DL2_TS[3] DL2_TS[2] DL2_TS[1] DL2_TS[0]

0B0 DL2_BIT R/W DL2_BIT[7] DL2_BIT[6] DL2_BIT[5] DL2_BIT[4] DL2_BIT[3] DL2_BIT[2] DL2_BIT[1] DL2_BIT[0]

0B1 DL2_CTL R/W — — — TDL2_RPT DL2[1] DL2[0] TDL2_EN RDL2_EN

0B2 RDL2_FFC R/W MSG_FILL[1] MSG_FILL[0] FFC[5] FFC[4] FFC[3] FFC[2] FFC[1] FFC[0]

2.0 Register

CX28394/28395/28398

3.17 Register Summary

Quad/x16/Octal—T1/E1/J1 Framers

3-124

Conexant

100054E

0B3 RDL2 R EOM[1] EOM[0] RDL2_CNT[5] RDL2_CNT[4] RDL2_CNT[3] RDL2_CNT[2] RDL2_CNT[1] RDL2_CNT[0]

RDL2[7] RDL2[6] RDL2[5] RDL2[4] RDL2[3] RDL2[2] RDL2[1] RDL2[0]

0B4 RDL2_STAT R — — — RMSG2 RSTAT2 RMPTY2 RNEAR2 RFULL2

0B6 TDL2_FEC R/W — — FEC[5] FEC[4] FEC[3] FEC[2] FEC[1] FEC[0]

0B7TDL2_EOMW————————

0B8 TDL2 R/W TDL2[7] TDL2[6] TDL2[5] TDL2[4] TDL2[3] TDL2[2] TDL2[1] TDL2[0]

0B9 TDL2_STAT R — — — — TMSG2 TMPTY2 TNEAR2 TFULL2

0BA DL_TEST1 R/W — — — — DL_TEST1[3] DL_TEST1[2] DL_TEST1[1] DL_TEST1[0]

0BB DL_TEST2 R/W — — DL_TEST2[5] DL_TEST2[4] DL_TEST2[3] DL_TEST2[2] DL_TEST2[1] DL_TEST2[0]

0BC DL_TEST3 R/W — — DL_TEST3[5] DL_TEST3[4] DL_TEST3[3] DL_TEST3[2] DL_TEST3[1] DL_TEST3[0]

0BD DL_TEST4 R/W — DL_TEST4[6] DL_TEST4[5] DL_TEST4[4] DL_TEST4[3] DL_TEST4[2] DL_TEST4[1] DL_TEST4[0]

0BE DL_TEST5 R/W — DL_TEST5[6] DL_TEST5[5] DL_TEST5[4] DL_TEST5[3] DL_TEST5[2] DL_TEST5[1] DL_TEST5[0]

Tab le 3-39. S ystem B us Regis ters (1 of 2)

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

0D0 SBI_CR R/W X2CLK SBI_OE EMF EMBED SBI[3] SBI[2] SBI[1] SBI[0]

0D1 RSB_CR R/W BUS_RSB SIG_OFF RPCM_NEG RSYN_NEG BUS_FRZ RSB_CTR RSBI[1] RSBI[0]

0D2 RSYNC_BIT R/W — — — — — OFFSET[2] OFFSET[1] OFFSET[0]

0D3 RSYNC_TS R/W — OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3]

0D4 TSB_CR R/W BUS_TSB TX_ALIGN TPCM_NEG TSYN_NEG TSB_ALIGN TSB_CTR TSBI[1] TSBI[0]

0D5 TSYNC_BIT R/W — — — — — OFFSET[2] OFFSET[1] OFFSET[0]

0D6 TSYNC_TS R/W — OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3]

0D7 RSIG_CR R/W — SET_RSIG SET_SIG UNICODE DEBOUNCE FRZ_OFF FRZ_ON THRU

Table 3-38. Data Link Registers (2 of 2)

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

CX28394/28395/28398

3.0 Register

Quad/x16/Octal—T1/E1/J1 Framers

3.17 Register Summary

100054E

Conexant

3-125

0D8 RSYNC_FRM R/W — — — OFFSET[14] OFFSET[13] OFFSET[12] OFFSET[11] OFFSET[10]

0D9 SSTAT R TSDIR TFSLIP TUSLIP TDLY RSDIR RFSLIP RUSLIP RDLY

0DA STACK R WORD MORE — CH[4] CH[3] CH[2] CH[1] CH[0]

WORD MORE — — SIG_BITA SIG_BITB SIG_BITC SIG_BITD

0DB RPHASE R RDELAY[5] RDELAY[4] RDELAY[3] RDELAY[2] RDELAY[1] RDELAY[0] RSLIP_WR RSLIP_RD

0DC TPHASE R TDELAY[5] TDELAY[4] TDELAY[3] TDELAY[2] TDELAY[1] TDELAY[0] TSLIP_WR TSLIP_RD

0DD PERR R — — — — — PERR_TPC PERR_RPC PERR_SBC

0E0–0FF SBCn; n = 0 to 31 R /W — IN SERT SIG_LP RLOOP R I ND O TIND O TSIG_AB ASSIGN

100–11F TPCn; n = 0 to 31 R/W TB7ZS/EM FBI T TLOOP TID LE TLOCAL T S IGA/ TSIGO TSIG B/RSIGO TSIGC TSIGD

120–13F TSIGn; n = 00 to 31 R/W — — — — TSIGn[3] TSIGn[2] TSIGn[1] TSIGn[0]

140–15F TSLIP_LOn; n = 0 to 31 R/W TPCM[1] TPCM[2] TPCM[3] TPCM[4] TPCM[5] TPCM[6] TPCM[7] TPCM[8]

160–17F TSLIP–HIn; n = 0 to 31 R/W TPCM[1] TPCM[2] TPCM[3] TPCM [4] TPCM[5] TPCM[6] TPCM[7] TPCM[8]

180–19F RPCn; n = 0 to 31 R/W RSIG_AB/ EMFBIT RIDLE SIG_STK RLOCAL RSIGA RSIGB RSIGC RSIGD

1A0–1BF RSIG n; n = 0 to 31 R/W RSIGn[7] RSIGn[6] RSIGn[5] RSIG n[4 ] RSIGn[3] RSIGn[2] RSIGn[1] RSIGn[0]

1C0–1DF RSLIP_LOn; n = 0 to 31 R/W RPCM[1] RPCM[2] RPCM[3] RPCM[4] RPCM[5] RPCM[6] RPCM[7] RPCM[8]

1E0–1FF RSLIP_HIn; n = 0 to 31 R/W RPCM[1] RPCM[2 ] RPCM[3] RPCM[4] RPCM[5] RPCM[6] R PCM [7] RPCM[8]

Tab le 3-39. S ystem B us Regis ters (2 of 2)

ADDR

(hex) Register

Label Read

Write

Bit Number

7 6 5 4 3 2 1 0

2.0 Register

CX28394/28395/28398

3.17 Register Summary

Quad/x16/Octal—T1/E1/J1 Framers

3-126

Conexant

100054E

100054E Conexant 4-1

4.0 Electrical/Mechanical Specifications

4.1 Absolute Maximum Ratings

Table 4-1. Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Units

VDD Power Supply (measured to GND) –0.5 5.75 V

VGG High Voltage Reference –0.5 5.75 V

∆VDD Voltage Differential (between any 2 VDD pins) — 0.5 V

ViConstant Voltage on any Sign al Pin –1.0 VGG + 0.5 V

ESD Transient Voltage on any Signal Pin

HBM rating

CDM rat ing

MMM rating

—

1.5

200

100

IiConstant Current on a ny Signa l Pin –10 +10 mA

LATCHUP Transient Current on any Signal Pin –200 +200 mA

TsStorag e Temperature –65 150 °C

TjJunction Temperature: (θjA x VDD x IDD) + Tamb –40 125 °C

Tvsol Vapor Phase Soldering Temperature (1 minute) — 220 °C

θjA Thermal Resistance (208 PQ FP), Still Ai r — 20 °C/W

θjA Thermal Re sistance (128 TQFP), Still Air — 36 °C/W

θjA Thermal Re sistance (272 BG A), Still Air — 29 °C/W

θjA Thermal Re sistance (318 BG A), Still Air — 29 °C/W

θjA Thermal Resistance (208 CABGA), Still Air — 44.6 °C/W

NOTE(S): Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at these or any other conditions beyond those indicated in the other sections of

this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.2 Re commended Opera ting Conditi ons Quad/x16/Octal—T1/E1/J1 Framers

4-2 Conexant 100054E

4.2 Recommended Operating Conditions

Table 4-2. Recommended Operating Conditions

Symbol Parameter Minimum Typical Maximum Units

VDD Supply Voltage 3.135 3.3 3.465 V

VGG High Voltage Refere nce (5 V Tolerant Inputs) 4.7 5 5.0 5.25 V

VGG High Voltage Ref e rence (Non-5 V Tolera nt Inputs) 3 .135 3.3 3.465 V

Tamb Ambient Operating Temperature

KPF Suff ix

EPF Suffix 0

–40 25

25 70

85 °C

°C

Vih Input High Voltage 2.0 — VGG + 0.5 V

Vil Input Low Voltage –0.5 — 0.8 V

SYSCL K SYS CLK Frequ e ncy 32.765 32.768 32.771 MH z

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.3 Electri cal Ch aracteristics

100054E Conexant 4-3

4.3 Electrical Characteristics

Tab le 4-3. D C C haract eristi cs

Symbol Parameter Minimum Typical Maximum Units

IDD Supply Current

(All signals and clo cks operating at maximu m

frequency. All outputs load ed: 85 pF + 1 mA)

CX28394

CX28398

CX28395

—

140

280

155

310

IGG High Voltage Reference Current — — 1 mA

Vih Input Hi gh Voltage 2.0 — V GG + 0.5 V

Vil Input Low Voltage — — 0.8 V

Voh Output High Voltage (Ioh = –2 mA) 2.4 — — V

Vol Outp ut Low Voltage (Iol = 2 mA) — — 0.4 V

Iod Open Drain Output Current Sink — — 4 mA

Ipr Resistiv e P u llu p C u r ren t 40 100 500 µA

IlInpu t L eakage Current –10 1 10 µA

Ioz Three-state Leakage Current –10 1 10 µA

Cin Input Cap acitance (f = 1MH z , Vin = 2.4V) — 2 5 pF

Cio I/O Capacitance (PIO, AD[7:0] pins) — 5 10 pF

Cout Outp ut Capa citance — 2 5 pF

Cld Capacitive Loading (Test Condition) — 70 85 pF

Iosc Short Circuit Output Current 37 50 160 mA

NOTE(S):

1. All ty pical values are at VDD = 3.3 V and Tamb = 25 °C.

2. Maximum and minimum values are over VDD = 3. 3 V + 5% and T amb = appropriate temperature range: KPF suffix (0 to 70 °C)

or EP F suffix (–40 to 85 °C).

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.4 AC Chara ct eris ti cs Quad/x16/Octal—T1/E1/J1 Framers

4-4 Conexant 100054E

4.4 AC Characteristics

Tab le 4-4. Input Clock Timing

Symbol Parameter Minimum Maximum Units

1 MCLK Freque n cy 8.0 35.7 MHz

SYSCL K Fr equency 32.765 32.771 MHz

RCKI, TCKI, ACKI Frequency 1.5 2.1 MHz

RSBC KI, TS BCK I Fre qu enc y 1.5 8.2 MHz

TCK Frequency 0 5.0 MHz

2 Clock Width High 0.4 x t(1) 0.6 x t(1) ns

3 Clock Width Low 0.4 x t(1) 0.6 x t(1) ns

4Clock Rise Time — 20 ns

5 Clock Fall Time — 20 ns

Figure 4-1. Minimum Clock Puls e Widths

90%

50%

10%

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.4 AC Characteristics

100054E Conexant 4-5

Tab le 4-5. Input Data Setu p and Hold Timing

Symbol Clock Edge Input Data Minimum Maximum Units

(tsetup)MCLK Rising ONESEC 5 — ns

RST* 5 — ns

RCKI Rising RPOSI 2 — ns

RNEGI 2 — ns

TDLCKO Falling TDLI 6 — ns

RSBCKI RSYN_NEG

(addr 0D1) RMSYNC 5 — ns

RFSYNC 5—ns

TSBCKI

TCKI(1) TPCM_NEG

(addr 0D4) TPCMI 5 — ns

TSIGI 5 — ns

TSYN_NEG

(addr 0D4) TFSYNC 5—ns

TMSYNC 5 — ns

(thold)MCLK Rising ONESEC 5 — ns

RST* 5 — ns

RCKI Rising RPOSI 3 — ns

RNEGI 3 — ns

TDLCKO Falling TDLI 2 — ns

RSBCKI RSYN_NEG

(addr 0D1) RMSYNC 5 — ns

RFSYNC 5—ns

TSBCKI

TCKI(1) TPCM_NEG

(addr 0D4) TPCMI 2 — ns

TSIGI 5 — ns

TSYN_NEG

(addr 0D4) TFSYNC(2) 2—ns

TMSYNC 2 — ns

NOTE(S):

(1) If the TSLIP bu ffer is bypassed (TSB_CR; addr OD4) , TCKI is used; otherwise, TSBCKI is used.

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.4 AC Chara ct eris ti cs Quad/x16/Octal—T1/E1/J1 Framers

4-6 Conexant 100054E

Table 4-6. Output Da ta Delay Timing

Symbol Clock Edge Output Data Minimum Maximum Units

(tdelay)MCLK Rising ONESEC 0 10 ns

INTR 0 10 ns

TCKI or ACKI — TCKO 0 15 ns

—TDLCKO020ns

Rising TNRZO 0 28 ns

MSYNCO 0 28 ns

TCKO Rising TPOSO 0 10 ns

TNEGO 0 10 ns

RDLCKO Rising RDLO 0 20 ns

RSBCKI RPCM_NEG

(addr 0D1) RPCMO 0 20 ns

RSIGO 0 10 ns

RINDO 0 20 ns

SIGFRZ 0 20 ns

RSYN_NEG

(addr 0D1) RFSYNC 0 10 ns

RMSYNC 0 10 ns

TSBCKI

TCKI(1) TPCM_NEG

(addr 0D4) TINDO 0 10 ns

TSYN_NEG

(addr 0D4) TFSYNC 0 10 ns

TMSYNC 0 10 ns

NOTE(S):

(1) If the TSLIP bu ffer is bypassed (TSB_CR; addr OD4) , TCKI is used; otherwise, TSBCKI is used.

Table 4-7. One-Second Input/Output Timing

Symbol Parameter Minimum Maximum Units

1 Input Pulse Width 1/MCLK 1 second

–125 µsAs shown

2 Output Pulse Width 125 250 µs

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.4 AC Characteristics

100054E Conexant 4-7

Figure 4-2. Input Data Setup/Hold Timing

Input Data

Rising Edge

Clock

Input Data

Falling Edge

Figure 4-3. Output Data Delay Timin g

Output Data

Rising Edge

Clock

Output Data

Falling Edge

Figure 4-4. One-Second Input/Output Timing

NOTE(S): ONESEC pin can be either an input (ONESECI) or an output (ONESECO).

ONESECI

ONESECO

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.5 MPU Interface Timing Quad/x16/Octal—T1/E1/J1 Framers

4-8 Conexant 100054E

4.5 MPU Interface Timing

Figure 4-5. Mot orola A s ynchronous Read Cycl e

AS*

Address

Read Data

A[8:0]

AD[7:0]

R/W*

DS*

CS*

MOTO* = 0, SYNCMD = 0

Table 4-8. Mot orola A s ynchronous Read Cycle

Symbol Parameter Minimum Maximum Units

1 AS* high pulse width 15 — ns

2 A[8:0] Address setup to AS* low 5 — ns

3 A[8:0] Address hold after AS* low 10 — ns

4 CS* low and R/W* high, and DS* low to AD [7:0]

valid —80ns

5 CS* high and DS* high, and R/W* low to AD[7:0]

invalid/three-state 520ns

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.5 MPU Interface Timing

100054E Conexant 4-9

Figure 4-6. Motorol a Asynchronous Write Cycle

AS*

Address

Write Data

A[8:0]

AD[7:0]

R/W*

DS*

CS*

MOTO* = 0, SYNCMD = 0

Table 4-9. Motorola Asynchronous Write Cycle

Symbol Parameter Minimum Maximum Units

1 AS* high pulse width 15 — ns

2 A[8:0] Address setup to AS* low 5 — ns

3 A[8:0] Address hold after AS* low 2 — ns

4 CS* low and R/W* low to DS* low 5 — ns

5 AD[7: 0] setu p to DS* low 0 — ns

6 AD[7: 0] hold after DS* low 1 5 — ns

7 DS* low pulse width 38 — ns

8 CS*, R/W* hold af ter DS* low 38 — ns

9 DS* low to AS* high 70 — ns

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.5 MPU Interface Timing Quad/x16/Octal—T1/E1/J1 Framers

4-10 Conexant 100054E

Figure 4-7. Intel Asynchronous Re ad Cycle

ALE

Address

Address Read Data

A[8]

AD[7:0]

RD*

WR*

CS*

5 8

MOTO* = 1, SYNCMD = 0

Table 4-10. Intel Asynchronous Read Cycle

Symbol Parameter Minimum Maximum Units

1 ALE high pulse width 15 — ns

2 A[8], AD[7:0] Address setup to ALE low 2 — ns

3 A[8], AD[7:0] Address hold after ALE low 5 — ns

4 ALE low to RD* and CS* both low 0 — ns

5 WR* high setup to RD* and CS* both low 0 — ns

6 RD* and CS* both low to AD[7:0] valid — 80 ns

7 RD* or CS* high to AD[7:0] invalid/three-state 0 25 ns

8 WR* high hold after RD* or CS* high 0 — ns

9 RD* or CS* high to next ALE 0 — ns

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.5 MPU Interface Timing

100054E Conexant 4-11

Figure 4-8. Intel Asynchronous Write Cycle

ALE

Address

Address Write Data

A[8]

AD[7:0]

WR*

RD*

CS*

MOTO* = 1, SYNCMD = 0

Table 4-11. Intel Asynchronous Write Cycle

Symbol Parameter Minimum Maximum Units

1 ALE high pulse width 15 — ns

2 A[8], AD[7:0] Address setup to ALE low 2 — ns

3 A[8], AD[7:0] Address hold after ALE low 5 — ns

4 CS*, RD* setup to WR* low 0 — ns

5 WR* pulse width low 20 — ns

6 AD[7:0] input data setup to WR* or CS* hi gh 2 — ns

7 AD[7:0] input dat a hold aft e r WR* or CS* high 10 — ns

8 RD* hol d after WR* or CS* high 0 — ns

9 End writ e cycle to next ALE high 55 — ns

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.5 MPU Interface Timing Quad/x16/Octal—T1/E1/J1 Framers

4-12 Conexant 100054E

Figure 4-9. Motorol a Synchronous Read Cyc le

MCLK

AS*

Address

Read Data

A[8:0]

AD[7:0]

R/W*

DS*

DTACK*

CS*

MOTO* = 0, SYNCMD = 1

Table 4-12. Motorola Synchronous Read Cycle

Symbol Parameter Minimum Maximum Units

1 AS* high pulse width 15 — ns

2 A[8:0] Address setup to AS* low 2 — ns

3 A[8:0] Address hold after AS* low 2 — ns

4 AS* and CS* low to DTACK* low 0 10 ns

5 AS* or CS* high to DTACK* high 0 10 ns

6 AS*, DS*, CS*, R/W* setup to MCLK high 15 — ns

7 DS* sampled low to AD[7:0] valid — 0.5/MCLK +20 ns

8 CS* or DS* high to AD [7:0] invalid/t hree-state 0 30 ns

9 MCLK high to AS* high 1/MCLK + 12 — ns

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.5 MPU Interface Timing

100054E Conexant 4-13

Figure 4-10. Motorola Synchronous Write Cycle

MCLK

AS*

Address

Write Data

A[8:0]

AD[7:0]

R/W*

DS*

DTACK*

CS*

MOTO* = 0, SYNCMD = 1

Table 4-13. Motorola Synchronous Write Cycle

Symbol Parameter Minimum Maximum Units

1 AS* high pulse width 15 — ns

2 A[8:0] Address setup to AS* low 5 — ns

3 A[8:0] Address hold after AS* low 2 — ns

4 AS* and CS* low to DTACK* low 0 10 ns

5 AS* or CS* high to DTACK* high 0 10 ns

6 CS* and R/W* low to DS* low 2 — ns

7 AD[7: 0] setu p to DS* low 2 — ns

8 AD[7: 0] hold after DS * low 5 — ns

9 DS* setup to MCLK high 2 — ns

10 DS* hold after MCLK high 5 — ns

11 D S* sampl e d low to d a ta latch (internal) — 1/MCLK+15 ns

12 D S* sample d low to AS* high 1/2 MCLK + 15 — ns

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.5 MPU Interface Timing Quad/x16/Octal—T1/E1/J1 Framers

4-14 Conexant 100054E

Figure 4-11. Intel Synchronous Read Cycle

MCLK

ALE

Address

Address Read Data

A[8]

AD[7:0]

RD*

WR*

CS*

45 6

MOTO* = 1, SYNCMD = 1

Table 4-14. Intel Synchronous Read Cycle

Symbol Parameter Minimum Maximum Units

1 ALE high pulse width 15 — ns

2 A[8], AD[7:0] Address setup to ALE low 2 — ns

3 A[8], AD[7:0] Address hold after ALE low 5 — ns

4 ALE low to RD* and CS* both low 5 — ns

5 RD*, CS*, WR* setup to MCLK high (Start RD cycle) 3 — ns

6 RD*, CS*, WR* hold after MCLK high 5 — ns

7 Start RD* cycle to AD[7:0] valid — (1) ns

8 RD* or CS* high to AD[7:0] invalid/three-state 0 25 ns

9 End RD cycle to next ALE high 0 — ns

NOTE(S):

(1) Parameter 7 equals 40 ns or 1/2* MCLK + 17 ns, whiche ver is greater.

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.5 MPU Interface Timing

100054E Conexant 4-15

Figure 4-12. Intel Synchronous Write Cycle

MCLK

ALE

Address

Address Write Data

A[8]

AD[7:0]

WR*

RD*

CS*

4 5

MOTO* = 1, SYNCMD = 1

Table 4-15. Intel Synchronous Write Cycle

Symbol Parameter Minimum Maximum Units

1 ALE high pulse width 15 — ns

2 A[8], AD[7:0] Address setup to ALE low 2 — ns

3 A[8], AD[7:0] Address hold after ALE low 5 — ns

4 WR*,RD*,CS* setup to MCLK high (start WR cycle) 2 — ns

5 WR*,RD*,CS* hold after MCLK high 5 — ns

6 Start WR* cycle to AD[7:0] input data valid — 1/MCLK–10 ns

7 AD[7:0] inp ut data hold aft er Start WR cycle 1/ MCLK+9 — ns

8 Start WR cycl e to next ALE high 1/MCLK+10 — ns

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.5 MPU Interface Timing Quad/x16/Octal—T1/E1/J1 Framers

4-16 Conexant 100054E

Figure 4-13. Serial Contro l Port Timing

Read Timing

CS\

SCLK

SDI

SDO

R/W A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

Write Timing

CS\

SCLK

SDI

SDO

R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7

Address/Control Byte

8394-8-5_071

Figure 4-14. Serial Contro l Port Write Timing

SERCKO

SERCS*

SERDO A0

123

Address/Command

Byte Write Data Byte

D7D6D5

8394-8-5_072

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.5 MPU Interface Timing

100054E Conexant 4-17

Figure 4-15. Serial Contro l Port Read Timing

SERCKO

SERCS*

SERDO

SERDI

A01

123

Address/Command

Byte

Read Data Byte

D7D6D5

8394-8-5_073

Table 4-16. Host Serial Por t Timing

Symbol Parameter Minimum Maximum Units

1 SERCKO Falling Edge to SERCS* and SERDO 10 — ns

2, 3 SERCKO Duty Cycle 40 60 %

2, 3 SERCKO Freque ncy (Programmable) 1.024 8.19 2 MHz

4 SERDI to SERCKO Ri sing Edge Setup Time 10 — ns

5 SERCKO Rising Edge to SERDI Hold Time 5 — ns

— Ri se/Fall Time (10% to 90%)

SERCKO, SERDI, SERDO — 20 ns

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.6 System Bus Interface (SBI) Timing Quad/x16/Octal—T1/E1/J1 Framers

4-18 Conexant 100054E

4.6 System Bus Interface (SBI) Timing

Figure 4-16. SBI Timing—1536K Mode(1)

NOTE(S):

(1) Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for othe r edge combinations.

(2) RINDO/TINDO pr ogrammed high or low on a per-ti me slot basis (SBCn; a ddr 0E0-0FF).

(3) TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offse t.

(4) Multiple offset values shown for illustration, refer to OFFSE T control s (addr 0D 2-0D3, 0D5-0D6 ).

(5) X2CLK control bit located in SBI_CR (addr 0D0).

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 45 6 7 8

RSBCKI

RPCMO

RSIGO

TS1 TS2 TS3TS24

RSYNCO

RSYNCI

RSYNCO

RSYNCI

RSYNCO

RSYNCI

Offset = 008 (TS1, Bit1)

Offset = 018

Offset = 0C7

RSYNCO

RSYNCI

RSYNCO

RSYNCI

Offset = 008

Offset = 018

RSBCKI

X2CLK = 0X2CLK = 1

ReceiveTransmit

RINDO

SIGFRZ

TSBCKI

TPCMI

TSIGI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSBCKI

TINDO

A B C D A B C D A B C D

SIG24 SIG1 SIG2

SBI Signal Group

(4)

(5)

(3) (3)

(2) (2)

(5)

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.6 Syst em Bus In terface (SBI) Timing

100054E Conexant 4-19

Figure 4-17. SBI Timing—1544K Mode(1)

NOTE(S):

(1) Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for othe r edge combinations.

(2) RINDO/TINDO programmed high or low during F-bit (SBC0; addr 0E0).

(3) TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offse t.

(4) Multiple offset values shown for illustration, refer to OFFSE T control s (addr 0D 2-0D3, 0D5-0D6 ).

(5) X2CLK control bit located in SBI_CR (addr 0D0).

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 45 6 7 8

RSBCKI

RPCMO

RSIGO

TS1 TS2 TS3TS24

RSYNCO

RSYNCI

RSYNCO

RSYNCI

RSYNCO

RSYNCI

Offset = 000 (F-bit)

Offset = 00F

Offset = 0C7

RSYNCO

RSYNCI

RSYNCO

RSYNCI

Offset = 000

Offset = 00F

RSBCKI

X2CLK = 0X2CLK = 1

ReceiveTransmit

RINDO

SIGFRZ

TSBCKI

TPCMI

TSIGI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSBCKI

TINDO

A B C D A B C D A B C D

SIG24 SIG1 SIG2

SBI Signal Group

(4)

(5)

(3) (3)

(2) (2)

(5)

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.6 System Bus Interface (SBI) Timing Quad/x16/Octal—T1/E1/J1 Framers

4-20 Conexant 100054E

Figure 4-18. SBI Timing—2048K Mode(1)

NOTE(S):

(1) Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for othe r edge combinations.

(2) RINDO/TINDO pr ogrammed high or low on a per-ti me slot basis (SBCn; a ddr 0E0-0FF).

(3) TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offse t.

(4) Multiple offset values shown for illustration, refer to OFFSE T control s (addr 0D 2-0D3, 0D5-0D6 ).

(5) X2CLK control bit located in SBI_CR (addr 0D0).

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 45 6 7 8

RSBCKI

RPCMO

RSIGO

TS0 TS1 TS2TS31

RSYNCO

RSYNCI

RSYNCO

RSYNCI

RSYNCO

RSYNCI

Offset = 000 (TS0, Bit1)

Offset = 00B

Offset = 0FF

RSYNCO

RSYNCI

RSYNCO

RSYNCI

Offset = 000

Offset = 00B

RSBCKI

X2CLK = 0X2CLK = 1

ReceiveTransmit

RINDO

SIGFRZ

TSBCKI

TPCMI

TSIGI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSYNCO

TSYNCI

TSBCKI

TINDO

A B C D A B C D A B C D

SIG31 SIG0 SIG1

SBI Signal Group

(4)

(5)

(3) (3)

(2) (2)

(5)

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.6 Syst em Bus In terface (SBI) Timing

100054E Conexant 4-21

Figure 4-19. SBI Timing—4096K Mode(1),(5)

NOTE(S):

1. Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for other edge c ombinations.

5. BUSSED or NON- BUSSED signal group controls located in BUS_RSB , BUS_FR Z (addr 0D 1) and BUS_TSB (addr 0D4).

GroupA

GroupB

1 2 3 4 5 6 7 8

1 2 3 45 6 7 8

SBCKI

GroupA

GroupB

TS0A

TS0B

TS1A

TS1BTS31B

SYNCO

SYNCI

SYNCO

SYNCI

SYNCO

SYNCI

Offset = 000

Offset = 008

Offset = 1FF

TS0A

1234567812345678 123456781234

TS0A TS1A TS1A

45678

TS31A

TS0B

1234567812345678 123456781234

TS0B TS1B TS1B

45678

TS31B

BUSSED

SYNCO

SYNCI

SYNCO

SYNCI

Offset = 000

Offset = 008

SBCKI

X2CLK = 0NON-BUSSEDX2CLK = 1

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.6 System Bus Interface (SBI) Timing Quad/x16/Octal—T1/E1/J1 Framers

4-22 Conexant 100054E

Figure 4-20. SBI Timing—8192K Mode

GroupA

GroupB

GroupC

GroupD

1 2 3 4 5 6 7 8

1 2 3 45 6 7 8

SBCKI

GroupA

GroupB

GroupC

GroupD

TS0A

TS0B

TS0C

TS0DTS31D

SYNCO

SYNCI

SYNCO

SYNCI

SYNCO

SYNCI

Offset = 000

Offset = 010

Offset = 3FF

TS0A

1234567812345678 123456781234

TS0A TS0A TS0A

4 5 6 7 8

TS31A

TS0B

1234567812345678 123456781234

TS0B TS0B TS0B

4 5 6 7 8

TS31B

TS0C

1234567812345678 123456781234

TS0C TS0C TS0C

4 5 6 7 8

TS31C

TS0D

1234567812345678 123456781234

TS0D TS0D TS0D

4 5 6 7 8

TS31D

BUSSED

SYNCO

SYNCI

SYNCO

SYNCI

Offset = 000

Offset = 010

SBCKI

X2CLK = 0NON-BUSSEDX2CLK = 1

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.6 Syst em Bus In terface (SBI) Timing

100054E Conexant 4-23

Figure 4-21. SBI Timing—Eight Clock Edge Combinations (Applicable to Any SBI Mode)

NOTE(S):

PCM out put/sample points are show n only for the corr espondi ng SYNC ou tput/sample point.

PCM

SYNC

PCM_NEG SYN_NEGX2CLK 001

PCM

SYNC

PCM

SYNC

PCM

SYNC

PCM_NEG SYN_NEGX2CLK 011

PCM_NEG SYN_NEGX2CLK 101

PCM_NEG SYN_NEGX2CLK 111

SBCKI

PCM

SBCKI

SYNC

PCM_NEG SYN_NEGX2CLK 000

PCM

SYNC

PCM

SYNC

PCM

SYNC

PCM_NEG SYN_NEGX2CLK 010

PCM_NEG SYN_NEGX2CLK 100

PCM_NEG SYN_NEGX2CLK 110

LEGEND: Rising Edge Sample Rising Edge Output

Falling Edge Sample Falling Edge Output

100054_004

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.7 JTAG Interface T i m ing Quad/x16/Octal—T1/E1/J1 Framers

4-24 Conexant 100054E

4.7 JTAG Interface T iming

Table 4-17. Test and Diagnostic I nterfa c e Timing Re quirements

Symbol Parameter Minimum Maximum Units

1 TCK pulse width hi gh 80 —ns

2 TCK pul se width low 80 —ns

3 TMS, TDI setup to TCK rising edg e 5 —ns

4 TMS, TDI hold after TCK high 20 —ns

Tab le 4-18. Test and Diagnostic Interface Switching Characterist ics

Symbol Parameter Minimum Maximum Units

5 TDO hold after TCK falling edge 0 —ns

6 TDO delay after TC K low —20 ns

7 TDO enable (Low Z) after TCK fall ing edge 10 —ns

8 TDO di sable (Hig h Z) after TCK low —10 ns

Figure 4-22. JTAG Interface Timing

7 8

TDO

TCK

TDI

TMS

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.8 Mech an ic al Sp ec ific a tio ns

100054E Conexant 4-25

4.8 Mechanical Specifications

Figure 4-23. 318-Pin Ball Grid Array (BGA)

8394-8-5_010

27.000

24.000

18.000

27.000

24.000

18.000

Triangle

Pin #1

Indicator

2.000 Dia.

TYP 4 PL

(Ejector Pin)

R 1.7 MM

TYP 4 PL

1.414 Chamfer

Optional

R .500

TYP 3 PL

Engraving

Cavity ID

TOP VIEW

BOTTOM VIEW

.520

.070

.600

.100

2.220

.220

1.100

.050

SIDE VIEW

SEATING

PLANE

24.130

12.065 1.270

24.130

12.065 1.270

Pin #1

Triangle

5 Perimeter Rows

+ 18 Balls (1.27 MM Pitch)

NOTES:

- ALL DIMENSIONS ARE IN MILLIMETERS (MM).

- REFLOW APPLIES TO SOLDERING TO HOST

PC BOARD.

- THERMAL BALLS IN CENTER CONNECTED

TO GROUND.

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.8 Mechanical Specifications Quad/x16/Octal—T1/E1/J1 Framers

4-26 Conexant 100054E

Figure 4-24. 272-Pin Ball Grid Array (BGA)

8394-8-5_009

27.000

24.000

18.000

27.000

24.000

18.000

Triangle

Pin #1

Indicator

2.000 Dia.

TYP 4 PL

(Ejector Pin)

R 1.7 MM

TYP 4 PL

1.414 Chamfer

Optional

R .500

TYP 3 PL

Engraving

Cavity ID

TOP VIEW

BOTTOM VIEW

.520

.070

.600

.100

2.220

.220

1.100

.050

SIDE VIEW

SEATING

PLANE

24.130

12.065 1.270

24.130

12.065 1.270

Pin #1

Triangle

4 Perimeter Rows

+ 16 Balls (1.27 MM Pitch)

NOTES:

- ALL DIMENSIONS ARE IN MILLIMETERS (MM).

- REFLOW APPLIES TO SOLDERING TO HOST

PC BOARD.

- THERMAL BALLS IN CENTER CONNECTED

TO GROUND.

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.8 Mech an ic al Sp ec ific a tio ns

100054E Conexant 4-27

Figure 4-25. 208-Pin Ball Grid Array (CABGA)

DD1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(208 Solder Balls)

1234567891011121314151617

Coplanarity

Warpage

Ref: 208-Pin CABGA (GP00-D576-001)

0.31

0.65

0.29

0.12

0.026

0.011

0.016

0.030

0.015

0.41

0.76

0.39

1.50

15.00 REF.

12.80 REF.

15.00 REF.

12.80 REF.

0.80 REF.

0.48 REF.

0.12 MAX.

0.10 MAX.

1.059

0.591 REF.

0.504 REF.

0.591 REF.

0.504 REF.

0.031 REF.

0.018 REF.

0.005 MAX.

0.004 MAX.

208

Dim. Min. Max. Min.

Millimeters InchesMax.

100054_002

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.8 Mechanical Specifications Quad/x16/Octal—T1/E1/J1 Framers

4-28 Conexant 100054E

Figure 4-26. 208-Pin Plastic Quad Flat Pack (PQFP)

DD1D1

8394-8-5_008

DETAIL A

AA2

NOM.

1.00 REF.

0.500

MIN.

3.64

0.25

3.39

30.40

27.90

30.40

27.29

0.50

0.215

MAX

4.09

0.50

3.50

30.80

28.10

30.80

27.99

0.75

0.225

ALL DIMENSIONS

IN MILLIMETERS

PIN 1

REF

CX28394/28395/28398 4.0 Electrical/Mechanical Specifications

Quad/x16/Octal—T1/E1/J1 Framers 4.8 Mech an ic al Sp ec ific a tio ns

100054E Conexant 4-29

Figure 4-27. 128-Pin (TQFP) Mechanical Drawing

DD1D1

2.00

DETAIL A

PIN 1

REF

PIN 1 REF MARK

1.6 MAX.

1.4 REF

20.0 REF

18.5 REF

14.0 REF

12.5 REF

1.0 REF

0.50 BSC

MIN.

0.10

21.85

15.8

0.4

0.17

0.11

MAX

0.15

22.15

16.15

0.65

0.27

0.17

ALL DIMENSIONS

IN MILLIMETERS

Ref. 128-PIN TQFP (GP00-D268)

8394-8-5_002

4.0 Electrical/M ech anical Specificatio ns CX28394/28395/28398

4.8 Mechanical Specifications Quad/x16/Octal—T1/E1/J1 Framers

4-30 Conexant 100054E

100054E Conexant A-1

Appendix A

A.1 Superframe Format (SF)

The Superframe Format (SF), is also referred to as the D4 format. The

requirement for associated signaling in frames 6 and 12 dictates that the frames

be distinguishable. This leads to a multiframe structure consisting of 12 frames

per superframe (SF). See Figure A-1 and Tables A-1 and A-2.

The SF structure consists of a multiframe of 12 frames. Each frame has 24

channels, plus an F-bit, and 8 bits per channel. A channel is equivalent to one

voice circuit or one 64 kbps data circuit.

This structure of frames and multiframes is defined by the F-bit pattern. The

F-bi t is designat ed alternately as an F t bit (terminal framing b it) or Fs b it

(signalling framing bit). The Ft bit carries a pattern of alternating zeros and ones

(101010) in odd frames that defines the frame boundaries so that one channel

may be distinguished from another. The Fs bit carries a pattern of (001110) in

even frames and defines the multiframe boundaries so that one frame may be

distinguished from another.

Figure A-1. T1 Superframe PC M Form at

12345678

1CH

2CH

13 CH

1FR

2FR

7FR

Frame 12

Frame 6

Bit 8

During:

24 Channels per Frame

Frame = 193 Bits

Multiframe

SF = 12 Frames

8 Bits per Channel

Signaling Information

Appendix A CX28394/28395/28398

A.1 Superframe Format (SF) Quad/x16/Octal—T1/E1/J1 Framers

A-2 Conexant 100054E

Table A-1. Superframe Format

Frame # Bit #

F-Bits Bit Use in Each Time Slot Signaling

Channel

Terminal

Framing Ft Signaling

Frami n g Fs Traffic Sig

10 1 —1–8——

2193 —01–8——

3386 0 —1–8——

4579 —01–8——

5772 1 —1–8——

6965 —11–78 A

71158 0 —1–8——

81351 —11–8——

91544 1 —1–8——

10 1737 —11–8——

11 1930 0 —1–8——

12 2123 —01–78 B

CX28394/28395/28398 Appendix A

Quad/x16/Octal—T1/E1/J1 Framers A.2 T1DM Form at

100054E Conexant A-3

A.2 T1DM Format

Table A-2. T1DM Frame Format

Frame # Bit #

F-Bits Bit Use in Each Time

Slot

Terminal

Fram ing Ft Signaling

Framing Fs Sync Byte Info Ctrl

10 1——1–78

1185–192 ——10111YR0 ——

2193 —0—1–78

2378–385 ——10111YR0 ——

3386 0 ——1–78

3571–578 ——10111YR0 ——

4579 —0—1–78

4764–771 ——10111YR0 ——

5772 1 ——1–78

5957–964 ——10111YR0 ——

6965 —1—1–78

61150–1157 ——10111YR0 ——

71158 0 ——1–78

71343–1350 ——10111YR0 ——

81351 —1—1–78

81536–1543 ——10111YR0 ——

91544 1 ——1–78

91729–1736 ——10111YR0 ——

10 1737 —1—1–78

10 1922–1929 ——10111YR0 ——

11 1930 0 ——1–78

11 2115–2122 ——10111YR0 ——

12 2123 —0—1–78

Note(s):

1. Y bit is used to indic ate a Yellow Alarm (active low).

2. R bit is used solely by AT&T as an 8Kpbs communications channel to collect pe rformance data on long haul DDS

facilities.

Appendix A CX28394/28395/28398

A.3 SLC 96 Format (SLC) Quad/x16/Octal—T1/E1/J1 Framers

A-4 Conexant 100054E

A.3 SLC 96 Format (SLC)

SLC framing mode allows synchronization to the SLC 96 data link pattern. This

pattern, described in the Bellcore TR-TSY-000008, contains both signaling

information and a framin g pattern that overwrites the Fs bit of the SF framer

pattern. (See Table A-3).

Table A-3. SLC-96 Fs Bit Contents

Frame # Fs Bit Frame # Fs Bit Frame # Fs Bit

2 0 26 C2 50 0

4 0 28 C3 52 M1

6 1 30 C4 54 M2

8 1 32 C5 56 M3

10 1 34C658A1

12 0 36C760A2

14 0 38C862S1

16 0 40C964S2

18142C1066S3

20144C1168S4

221460701

24C1481720

Note(s):

1. The SLC-96 frame format is similar to that of SF as shown in Table A-1 with the

exceptions shown in this table.

2. C1 to C11 are concentrator field bits.

3. M1 to M3 ar e maintenance field bits.

4. A1 and A 2 are alarm field bi ts.

5. S1 to S4 are li ne switch field bits.

6. The Fs bits in frames 46, 48, and 70 are spoiler bits which are used to p rotect against

false multiframing.

CX28394/28395/28398 Appendix A

Quad/x16/Octal—T1/E1/J1 Framers A.4 Extended Superframe Format (ESF)

100054E Conexant A-5

A.4 Extended Superframe Format (ESF)

In Extended Superframe For m at (ESF), as illustrated i n Figure A-2 and

Table A-4, the multiframe structure is extended to 24 frames. The channel

structure is identica l to D4 (SF) format. Robbed-bit signaling is ac commodated in

frame 6 (A-bit), frame 12 (B-bit), frame 1 8 (C-bit), and frame 24 (D-bit).

The F-bit pattern of ESF contains three functions:

1. Fr aming Patt ern Sequence ( FPS) , which defines the fr ame an d mul tifr ame

boundaries.

2. Facility Data Link (FDL), which allows data such as error performance to

be passed w ithin the T1 lin k.

3. Cyclic Redundancy Check (CRC), which allows error performance to be

moni tored and en hances the reliab ility of the receiver's framin g algorit hm.

Figure A-2. T1 Extended Sup erframe Format

12345678

1CH

2CH

13 CH

1FR

2FR

13 FR

Frame 12

Frame 6

Bit 8

During:

24 Channels per Frame

Frame = 193 Bits

Multiframe

ESF = 24 Frames

8 Bits per Channel

Signaling Information

FDL

CRC

FPS

Frame 18

Frame 24

Appendix A CX28394/28395/28398

A.4 Ext ended Superframe Format (ESF) Quad/x16/Octal—T1/E1/J1 Framers

A-6 Conexant 100054E

Table A-4. Extended Superframe Format

Fram e # Bit # F-Bits Bit Use in Each

Time Slot Signalin g Channel

FPS DL CRC Traffic Sig 16 4 2

10—m—1–8————

2193——C1 1–8————

3386—m—1–8————

45790——1–8————

5772—m—1–8————

6965——C2 1–78AAA

71158—m—1–8————

813510 ——1–8————

91544—m—1–8————

10 1737 ——C3 1–8————

11 1930 —m—1–8————

12 2123 1 ——1–78BBA

13 2316 —m—1–8————

14 2509 ——C4 1–8————

15 2702 —m—1–8————

16 2895 0 ——1–8————

17 3088 —m—1–8————

18 3281 ——C5 1–78CAA

19 3474 —m—1–8————

20 3667 1 ——1–8————

21 3860 —m—1–8————

22 4053 ——C6 1–8————

23 4246 —m—1–8————

24 4439 1 ——1–78DBA

Note(s):

1. FPS indi cates the Framing Pattern Sequence (...0 01011...).

2. DL indicates the 4Kbps Data Link with message bits m.

3. CRC indic ates the cyclic redundancy check with bits C1 to C6.

4. Signaling options include 16 state, 4 state, and 2 state.

CX28394/28395/28398 Appendix A

Quad/x16/Octal—T1/E1/J1 Framers A.4 Extended Superframe Format (ESF)

100054E Conexant A-7

Table A-5. Performance Report Message Structure

Octet No. LSB MSB

1FLAG

2SAPIC/REA

3TEIEA

4 CONTROL

5 G3LVG4U1U2G5SLG6

6 FE SE LB G1 R G2 Nm NI

7 G3LVG4U1U2G5SLG6

8 FE SE LB G1 R G2 Nm NI

9 G3LVG4U1U2G5SLG6

10 FE SE LB G1 R G2 Nm NI

11 G3 LV G4 U1 U2 G5 SL G6

12 FE SE LB G1 R G2 Nm NI

13 FCS (Most Significant Byte)

14 FCS (Lea st Signifi cant Byte)

Note(s):

1. The 1-second repo rt consists of o c tets 5–12.

2. R, U1, and U2 are reserved for future standard ization an d should be set to 0.

Appendix A CX28394/28395/28398

A.5 E1 Frame Format Quad/x16/Octal—T1/E1/J1 Framers

A-8 Conexant 100054E

A.5 E1 Frame Format

Figure A-3. E1 Format

0FR

1FR

2FR

3FR

4FR

5FR

6FR

7FR

8FR

9FR

10 FR

11 FR

12 FR

13 FR

14 FR

I 1ANNNNN ABCDABCD 12345678

0TS

1TS

2TS

3TS

4TS

5TS

6TS

7TS

8TS

9TS

10 TS

11 TS

12 TS

13 TS

14 TS

15 TS

16 TS

17 TS

18 TS

19 TS

20 TS

21 TS

22 TS

23 TS

24 TS

25 TS

26 TS

27 TS

28 TS

29 TS

30 TS

I0011011 0000XYXX

a. Even Frames (0, 2, 4–14)

b. Odd Frames (1, 3, 5–15)

FAS

Time Slot 0

a. Frame 0

b. Frames 1–15

MAS

Time Slot 16 Time Slots 1–15, 17–31

Channel Data

32 Time Slots/Frame

16 Frames/Multiframe

8Bits/

Time Slot

CX28394/28395/28398 Appendix A

Quad/x16/Octal—T1/E1/J1 Framers A.5 E1 Frame Format

100054E Conexant A-9

Table A-6. ITU–T CEPT Frame Format Time Slot 0 Bit Allocations

SMF Frame # Time Slot 0 Bits 1 to 8 of each frame

1 2 3 4 5 6 7 8

0C1/Si0011011

1 0/Si 1 A SA4 SA5 SA6 SA7 SA8

2C2/Si0011011

3 0/Si 1 A SA4 SA5 SA6 SA7 SA8

4C3/Si0011011

5 1/Si 1 A SA4 SA5 SA6 SA7 SA8

6C4/Si0011011

7 0/Si 1 A SA4 SA5 SA6 SA7 SA8

8C1/Si0011011

9 1/Si 1 A SA4 SA5 SA6 SA7 SA8

10C2/Si0011011

11 1/Si 1 A SA4 SA5 SA6 SA7 SA8

12C3/Si0011011

13 E/Si 1 A SA4 SA5 SA6 SA7 SA8

14C4/Si0011011

15 E/Si 1 A SA4 SA5 SA6 SA7 SA8

Note(s):

1. SMF indicates the sub- multiframe. This part itioning is us ed in the CR C-4 calculation.

2. Si bits are International Spare Bits.

3. A bit is used to indicate a remote alarm condition (acti ve high).

4. SA4 to SA8 are spare bits that may be recommended by ITU–T for use in specific point-to-point applications (e.g., transcoder

equipment conforming to Recommendation G.761).

5. SA4 to SA8 where these are not used should be set to 1 on links crossing an internat ional border.

6. E bit is used to indicate a CRC-4 error. The normal state is both bits set to 1; when a CRC-4 error is detected, one of the E bits

is set to 0.

7. C1 to C4 bits are u sed to carry the CRC-4 co de.

8. Time slot 0 that contains the 0011011 sequence is defined as the FAS word. Time slot 0 that do es not contain the FAS is th e

Not-Word.

Appendix A CX28394/28395/28398

A.6 IRSM CE PT Fra m e Format Quad/x16/Octal—T1/E1/J1 Framers

A-10 Conexant 100054E

A.6 IRSM CEPT Frame Format

Table A-7. IRSM CEPT Frame Format Time Slot 0 Bit Allocations

SMF Frame # Time Slot 0 Bits 1 to 8 of each frame

1 2 3 4 5 6 7 8

0C1/Si0011011

1 0/Si 1 A D E0 E1 E16 E17

2C2/Si0011011

3 0/Si 1 A D E2 E3 E18 E19

4C3/Si0011011

5 1/Si 1 A D E4 E5 E20 E21

6C4/Si0011011

7 0/Si 1 A D E6 E7 E22 E23

8C1/Si0011011

9 1/Si 1 A D E8 E9 E24 E25

10C2/Si0011011

11 1/Si 1 A D E10 E11 E26 E27

12C3/Si0011011

13 E/Si 1 A D E12 E13 E28 E29

14C4/Si0011011

15 E/Si 1 A D E14 E15 E30 E31

Note(s):

1. SMF indicates the sub- multiframe. This part itioning is us ed in the CR C-4 calculation.

2. Si bits are International Spare Bits.

3. NA bit is used to indicate a remote al arm conditi on (active high).

4. Ei are per ch an ne l control bits.

5. E bit is used to indicate a CRC-4 error. The normal state is both bits set to 1; when a CRC-4 error is detected, one of the E bits

is set to 0.

6. C1 to C4 bits are u sed to carry the CRC-4 co de.

7. Time sl ot 0 that contains the 0011011 sequence is defined as the FAS word. Time slot 0 that does not contain the FAS is the

Not-Word.

8. D bits are a 4 kbps data link.

9. Bit 2 of the Not-Word is defined as the alternate framing bit.

CX28394/28395/28398 Appendix A

Quad/x16/Octal—T1/E1/J1 Framers A.6 IRSM CEPT Frame Format

100054E Conexant A-11

Table A-8. CEPT (ITU–T and IRSM) Frame Format Time Slot 16 Bi t A llocat ions

SMF Frame # Time S lot 16 Bits 1 to 8 of each fram e

1 2 3 4 5 6 7 8

00000X0YX1X2

1 A1B1C1D1A17B17C17D17

2 A2B2C2D2A18B18C18D18

3 A3B3C3D3A19B19C19D19

4 A4B4C4D4A20B20C20D20

5 A5B5C5D5A21B21C21D21

6 A6B6C6D6A22B22C22D22

7 A7B7C7D7A23B23C23D23

8 A8B8C8D8A24B24C24D24

9 A9B9C9D9A25B25C25D25

10 A10 B10 C10 D10 A26 B26 C26 D26

11 A11 B11 C11 D11 A27 B27 C27 D27

12 A12 B12 C12 D12 A28 B28 C28 D28

13 A13 B13 C13 D13 A29 B29 C29 D29

14 A14 B14 C14 D14 A30 B30 C30 D30

15 A15 B15 C15 D15 A31 B31 C31 D31

Note(s):

1. SMF indicate s th e su b - multif ra me.

2. Ai–Di are the per channel signaling bits.

3. X0–X2 are the X spar e bits normally set to 1.

4. Y is the Remote Multi frame Yellow Alarm Indicat ion bit. When Y is set to a 1, this indicates that the alarm is active.

5. The Mul tiframe Alignment Sequ ence (MAS) is defined as the Time S lot 16 word that contains the 0 000XYXX sequence.

Appendix A CX28394/28395/28398

A.6 IRSM CE PT Fra m e Format Quad/x16/Octal—T1/E1/J1 Framers

A-12 Conexant 100054E

100054E Conexant B-1

Appendix B

B.1 Applicable Standards

Table B-1. Applicable Standards (1 of 3)

Standard Title

ANSI

T1.101 - 19 87 Digital Hiera rchy—Timing Synchronization

T1.102 - 19 93 Digital Hiera rchy—Electrical Interfaces

T1.107-1991

(Newer Draft Standard

T1X1.4/93-002R3)

Digital Hierarchy—Formats Specification

T1.4 03-1995 Network to Customer Installation —DS1 Metallic Interface

T1.408-1990 ISDN Primary Rate—Customer Installation Metallic Interfaces

T1.231-1993 Layer 1 In-Service Digital Transmission Per f ormance Monitoring

AT&T

TR 414 49-1986 ISDN Primary Rate I nter face Specification

TR 43801( A ) -19 8 5 Digital Channe l Ba nk —Requirements and Objectives

TR 54016-1989 Rqts. for Interfacing DTE to Services Employing Extended Superframe Format

TR 624 11-1990 Accunet T1.5 Serv ice Description and I nter face Specification

Bellcore

TR-TSY-000008 Issue 2, 1987 Digital Interf ace Between the SLC 96 Di gital Loop Carrier System and a Local

Digital Swit ch

TR-TS Y-000009 Issue 1, 1986 A synchronous Digital Multiplexer Requirements and Objectives

TR-NPL-000054 Issu e 1, 1989 High-Capacity Digital Service (HCDS) Interfac e Generic Requi rements

TR-NWT-000057 Issue 2, 1993 Functional Criteria for Digital Loop Carrier Systems

TA-TSY-00014 7 Issue 1, 1987 DS1 Rate Digital Service Monitori ng Unit

TR-TSY-00 0170 Issue 2, 1993 Digital Cross-Connect System (DCS) R equirements and Objectives

TR-TSY-000191 Issue 1, 1986 Al arm Indication Signal (AIS) Requirements and O bjectives

Appendix B CX28394/28395/28398

B.1 Applicable Standards Quad/x16/Octal—T1/E1/J1 Framers

B-2 Conexant 100054E

TR-TSY-000194 Issue 1, 1987 The Extended Superframe Format Interface

TA-TSY-000278 Issu e 1, 1985 Digital Data System (DDS)—T1 Digit al Multiplexer (T1D M) Requirement s

TR-TSY-000303 Issu e 2, 1992 Integrated Digital Loop Carrier (I DLC) Sy stem Gener ic Requir ements

TR-TSY-000312 Issu e 1, 1988 Functional Cri teria for the DS1 Interface Connect or

TR-NPL-000320 Issue 1, 1988 Fundamental Generic Requirements fo r Met allic Digital Si gnal Cross-connect Systems

TA-TSY-000435 Issue 1, 1987 DS1 Automatic Facility Protection Switching (AFPS) Rqts. an d Objectives

TR-NWT-000499 Issue 5, 1993 Transport Systems Generic Requirements

TR-TS Y-000510 Issue 2, 1987 L SSGR: System Inter faces, Sec ti on 10

TR-NWT-000773 Issue 1, 1991 Local Acce ss System Requirements, Objectives and In terfaces for SMDS

TR-TSY-000776 Issue 2, 1993 Network Interface Description for ISDN Customer Access

GR-820-CORE Issue 1, 1994

(replaced TR-NWT-000820) Generic Digital Tr ansmissio n Sur veillance

TA-NWT-000821 Issue 1, 1991

(replaced TR-TSY-00 0821) Additional Transport and Transport-Based Surveillance Gen eric Rqts.

SR-TSY-000977 Iss ue 1, 1988 ISDN Primary Rate Access Maintenance

TR-NWT-001219 Issue 1, 1992

(Rev 1, 19 93 ) ISDN Primar y Rate Access Testing Req uirements

SR-NWT-002343 Issue 1, 1993 ISDN Primary Rate I nt e rface Guidelines for Custome r Premises Equipment

ETSI

ETS 30 0 011 (4/92) ISDN Primary Rate User-Network Interfac e Specification and Test Principle s

ETS 300 233 Access Digital Section for ISDN Prima ry Rate

ITU-T

Recommendation G .703 (1991) Physical/Electrical Characteristics of Hierarchical Di gital Interfaces

Recommendation G .704 (1991) Synchronous Frame Stru ctures used at Primary Hi erarchic al Levels

Recommendation G.706 (1991) Frame Alignment and CRC Procedures Re latin g to G.704 Frame Structures

Recommendation G.732 Characteristics of Primary PCM Multiplex Equipment at 2048 kbps

Recommendation G.733 Characteristics of Primary PCM Multiplex Equipment at 1544 kbps

Recommendation G.73 4 Characteri s tics of Synchronous Digit al Multiplex Equipment at 1544 kbps

Recommendation G.735 Characteristics of Primar y PCM Multiplex Equipmen t at 2048 kbps; offering

Synchronous Di gital Access at 384 kbp s and/or 64 kbps

Recommendation G.73 6 Characteri s tics of Synchronous Digit al Multiplex Equipment at 2048 kbps

Recommendation G.737 Characteristics of External Ac cess Equipment at 2048 kbp s ; offering S ynchronous

Digital Access at 384 kbps and/or 64 kbps

Recommendation G.738 Characteristics of Primar y PCM Multiplex Equipmen t at 2048 kbps; offering

Synchronous Di gital Access at 320 kbp s and/or 64 kbps

Recommendation G.739

Recommendation G.76 1 Characteristics of External Access Equipment at 2048 kbp s; Offering Sync hronous

Digital Access at 320 kbps and/or 64 kbps

Table B-1. Applicable Standards (2 of 3)

Standard Title

CX28394/28395/28398 Appendix B

Quad/x16/Octal—T1/E1/J1 Framers B.1 Applicable St andards

100054E Conexant B-3

Draft R ecommendati on G.775 Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection

Recommendation G .796 C haracteristics of 64 kbps Cross-Connect E quipment with 2048 kbps Access Ports

Recommendation G.802 (1988) Interwo rking be tween Net works based on Di fferent Digital Hierarchies

Recommendat ion G.821 Error Perfo rmance Mon itorin g on International Connections

Recommendation G.823 (3/93) Cont rol of Jitter and Wander in Digital Networks based on 2048 kbp s

Recommendation G.824 (3/93) Cont rol of Jitter and Wander in Digital Networks based on 1544 kbp s

Recommendati on G.921 Digit al Sections based on 2048 kbps Hierarchy

Recommendation G.962 (3/93) Access Digi tal Section for ISDN Pri mary Rate at 2048 kbps

Recommendation G.963 (3/93) Access Digi tal Section for ISDN Pri mary Rate at 1544 kbps

Recommendation I.411 ISDN User-Network Interfaces—Reference s Config urations

Recommendation I.412 ISDN User-Network Interfaces—Structures and Access Capabilities

Recommenda tio n I.421 Prima ry Rate User-Netw ork Interface

Recommenda tio n I.431 Prima ry Rate User-Netw ork Interface—Layer 1 Specification

Recommendation K.10 Unbalance ab out Eart h of Telecommunication Installati ons

Recommendati on K.20 Resistibilit y of Switching Equipment to Overvoltages and Ov ercurren ts

Recommendation M.3604 Applicat ion of Maintenance Pr inciples to ISDN Prim ary Ra te Access

Recommendation O.150 Digital Test Patterns for Performance Measurements

Recommendation O .151 Error Performance Measuring Equ ipment Operating at Primary Rate and Above

Recommendation O.152 Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and NX 64 kbit/s

Recommendation O.162 (10/92) Equipment to Perform In-Service Monitoring on 2048 kbps Signals

Recomm endation Q.921 ISD N User-Network Interface - Data Lin k Layer Specific ation

IEEE Std 1149.1a-1993 IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG)

Natural Microsystems Corporation,

Release 1.0, March 1993 Multi-Vendor Integration Pro tocol (MV IP) Refere nce Manual

FCC Pa rt 6 8.302 (d) Environment Simulati on metallic voltage su rge

FCC Part 68.308 Signal Power Limitations

Table B-1. Applicable Standards (3 of 3)

Standard Title

Appendix B CX28394/28395/28398

B.1 Applicable Standards Quad/x16/Octal—T1/E1/J1 Framers

B-4 Conexant 100054E

100054E Conexant C-1

Appendix C

C.1 System Bus Compatibility

C.1.1 AT&T Concentration Highway Interface (CHI):

DX = RPCMO

+ output on rising or falling edge of clock

+ out put on every CLKXR or CLKXR/2

+ Tri-stated during inactive time slots

DR = TPCMI

+ sampled on risi ng or falling edge of clock

+ sampled on every CLKXR or CLKXR/2 (see X2CLK mode)

FS = TFSYNC

+ sampled on rising or falling edge of clock ( FE sele ct)

+ rising edge determines frame start

+ 8 kHz ra te

TSC* = RINDO

+ Optional C HI pin is driven low during active DX time sl ots

CLKXR = TSB CLKI = RSBCLKI

+ N x 64 kHz rates, where N = 4, 8, 16, 32, 48 or 64

Appendix C CX28394/28395/28398

C.1 System Bus Compatibility Quad/x16/Octal—T1/E1/J1 Framers

C-2 Conexant 100054E

C.1.2 CHI Programming Options:

CMS = clock mode select

0 = line ra te

1 = 2X line rate

XEN = tran sm itter enable

0 = disable (DX tri-stated)

1 = enable (DX driven during active time slots)

FE = frame edge select

0 = falling edge

1 = rising edge

XCE = CLKXR output edge select for DX

0 = falling edge

1 = rising edge

RCE = CLKXR input edge select for DR

0 = falling edge

1 = rising edge

XBOFF = 3-bit transmit output bit offset

000-1111 = CLKXR (or 2xCLKXR) delay from FS to DX bit0

RBOFF = 3-bit receive input bit offset

000-111 = CLKXR (or 2xCLKXR) delay from FS to DR bit0

XTS = 6-bit transmit output TS offset

00-3F = CLKXR (or 2xCLKXR) TS delay from FS to DX bit0

RTS = 6-bit receive input TS offset

00-3F = CLKXR (or 2xCLKXR) TS delay from FS to DR bit0

The device only supports CHI and GCI buses if N = 24, 32, or 48, although

either bus is defined to operate at N x 64 from N = 4 to N = 48. The device does

not support AT&T's Dual CHI (separate A/B buses) or K2 buses, nor does it

support INTEL's SLD (ping/pong) 3-pin bus.

100054E Conexant D-1

Appendix D

D.1 Notation and Acronyms

D.1.1 Arithmetic Notation

Time Slot Bit Numbering associated with time slots in the primary rate channel,

are numbere d 1 to 8, where b it number 1 is t ransmitted first and is speci fied as the

MSB.

Configuration and Status Word Bit Numberi ng , asso ciated with co nfiguration

or status words, 7 to 0, where bit number 7 is specified as the MSB, and bit

number 0 is specified as the LSB.

Appendix D CX28394/28395/28398

D.2 Acronyms and Abbrev iatio ns Quad/x16/Octal—T1/E1/J1 Framers

D-2 Conexant 100054E

D.2 Acronyms and Abbreviations

ADC Analog to Digital Converter

AFPS Auto m atic Facility Pro te ction Switc hing

AGC Automatic Gain Control

AIS Alarm Indication Signal

ALBO Automatic Line Build Out

ALOS Analog Loss of Signal

AMI Alternate Mark Inversion

ANSI America n National Standards Institute

B8ZS Bina ry with 8 Zero Su bstitutio n

BER Bit Error Rate

BERR Bit Error Co unter

BFA Basic Frame Alignment

BOP Bit-Oriented Protocol

BPV Bipolar Violation

BSDL Boundary Scan Description Language

CAS Channel Associated Signaling

ITU–T Inter national Telegraph and Telephone Consultative

Committee

CCS Common Channel Signali ng

CERR CRC Errors

CGA Carrier Group Alarm

CI Customer Installation

CLAD Clock Rate Adapter

CMOS Complementary Metal Oxide Semiconductor

COFA Change of Frame Alignment

CRC Cyclic Redundancy Check

CSU Channel Service Unit

DAC Digital to An al og Converter

DCS Digit al Cross-Connect System

DDS Digital Data System

DMI D igital Mul tiplexed Interface

DPLL Digital Phase Locked Loop

DPM Driver Performance Monitor

DS1 D igital Signal Level 1

DSU Data Service Unit

ESF Extended Superframe

EXZ Excessive Zeros

CX28394/28395/28398 Appendix D

Quad/x16/Octal—T1/E1/J1 Framers D.2 Acr onyms and Abbre viations

100054E Conexant D-3

FAS Frame Alignment Sequence (E1 Format)

FCC Federal Communications Committee

FCS Fr ame Che ck Sequen ce

FDL Facility Data Link

FEBE Far End Block Error

FERR Framing Bit Error

FPS Frame Pattern Sequence (EFS Format)

HCDS High -Capacity Digital Service

HDB3 High-Density Bipolar of Order 3

ICOT Intercit y and Outs tate Tr unk

IDLC Integrated Digital Loop Car rier

ISDN Integrated Service Digital Network

JAT Jitter Attenuator

JCLK Jitter Attenuated Clock

JTAG Joint Test Action Group

LBO Line Build Out

LCV Line Code Violation

LEC Local Exchange Carrier

LIU Line Interface Unit

LOAS Loss of Analog Signal

LOF Loss of Frame

LOS Loss of Signal –DS1

LSB Least Significant Bit

MAIS Multiframe AIS

MART Maximum Average Reframe Time

MAS M ultiframe Al ignment Seq uence (CAS Format)

MAT Metropolitan Area Trunk

MERR MFAS Error

MFAS Multiframe Alignment Sequence (CRC4 format)

MOP Message Oriented Protocol

MOS Message Oriented Signaling

MPU Microprocessor Interface

MQFP Metric Quad Flat Pack

MSB M ost Significant Bit

MUX Multiplexer

MVIP Multi-Vendor Integration Protocol

MYEL Multiframe Yellow Alarm

NCO Numerical Controlled Oscillator

NI Network Interface

NRZ Non-Ret urn to Zero

OOF Out of Frame

Appendix D CX28394/28395/28398

D.2 Acronyms and Abbrev iatio ns Quad/x16/Octal—T1/E1/J1 Framers

D-4 Conexant 100054E

PCM Pulse Code Modulation

PDV Pulse Density Violation

PIC Poly e thylene-Insulated Cable

PLCC Plastic Leaded Chip Carrier

PLL Phase Locked Loop

PM Performance Monitoring

PQFP Plastic Quad Flat Pack

PRBS Pseudo-Random Bit Sequence

PRI Primary Rate Interface

PRM Performance Report Message

RAI Remote Alarm Indication

RBOP Bit-Oriented Protocol Detector

RBS Rob bed Bit Signaling

RCVR Receiver

RDL1 Receive Data Link 1

RDL2 Receive Data Link 2

RDL3 External Receive Data Link

RFRAME Receive Framer

RJAT Receive Jitter Attenuator

RLIU Receive Line Interface Unit

RMAIS Receive Multiframe AIS

RPDV Receive Pulse Density Violation

RPLL Receive Phase Locked Loop

RSB Receive System Bus

RSBI Receive System Bus Interface

RSIG Receive Signaling Buffer

RSLIP Receive Slip Buffer

RXCLK Receive Clock

RZCS AMI/HDB3/B8ZS Line Decoder

QRSS Quasi-Random Signal Source

SEF Severely Errored Framing Event

SERR CAS Erro r

SF Super Frame

SLC Subscriber Loop Carrier

TAP Test Access Port

TBOP Bit Oriented Protocol Formatter

TDL1 Transmit Data Link 1

TDL2 Transmit Data Link 2

TDL3 Exte rna l Transmit Data Lin k

TDM Time D ivision Multiplexed

TSB Transmit System Bus

TSBI Transmit System Bus Interface

TJAT Transmit Jitt er Attenuator

TLIU Transmit Line Interface Unit

CX28394/28395/28398 Appendix D

Quad/x16/Octal—T1/E1/J1 Framers D.2 Acr onyms and Abbre viations

100054E Conexant D-5

TLOS Transmit Loss of Signal

TSB Transmit System Bus

TSIC Time Slot Intercha n ge

TSIG Transmit Signaling Buffer

TSLIP Transmit Slip Buffer

TZCS AMI/HDB3/B8ZS Line Encoder

UI Unit Inter val

UMC Unassigned Mux Code

UNICODE Universal Trunk Out of Service Code

UTP Unshielded Twisted Pair

VCO Voltage Controlled Oscillator

VCXO Voltage Controlled Crystal Oscillator

VGA Variable Gain Amp li fier

XMTR Digital Transmitter

YEL Yellow Alarm

ZCS Zero Code Suppression

Appendix D CX28394/28395/28398

D.2 Acronyms and Abbrev iatio ns Quad/x16/Octal—T1/E1/J1 Framers

D-6 Conexant 100054E

100054E Conexant E-1

Appendix E

E.1 Revision History

Table E-1. Document Revision History

Revision Level Date Description

A Advanced July 1998 Cre a ted

B Preliminary April 1999 1. Added two new products to the data sheet: CX28394

(quad framer) and CX28395 (x16 framer).

2. Re-named data sheet .

3. Changed the device part number from RS8398 to

CX28398.

4. Transmitt er, Ove r head Pattern Generator, Alarm

Generator section rewritten for clarity. Removed RLOC

from automatic AIS generati on descrip ti on. Removed

refere nce to RDIGI bit. Added de scription of RLOF

integration to automatic Yellow Alarm/RAI generation

description.

5. Removed 2Kbps datalink mode and ZBTSI support.

6. Added chapter: System Bu s, to describe multiplexed

and non-multiplexed modes.

7. Changed RL OS clearing criteria for T1 to “at least

12.5% density over a period of 114 bits.”

8. Change d defa ult regi ster setting s for regist ers 0 40, 04 1,

042, and 043. These registers are not reset.

9. Removed 8398 Embedded mode from the System Bus

description and SBI_CR register descript ion.

C Prelim inary May 1999 1. Incorporated edits f rom Errata #N8398ER1A dated

May 13, 1999.

D Final November 199 9 1. Incorporat ed edits from Errata #100354C, formerly

N8398ER1C.

2. Updated timing paramet ers.

E Prelimin ary Ma y 2000 1. Updated marking numbers.

Appendix E CX28394/28395/28398

E.1 Revision History Quad/x16/Octal—T1/E1/J1 Framers

E-2 Conexant 100054E

Further Information

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Offi

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