MB90F423GCPMC - Fujitsu Limited

FUJITSU MICROELECTRONICS

DATA SHEET

2008.8

The information for microcontroller supports is shown in the following homepage.

Be sure to refer to the "Check Sheet" for the latest cautions on development.

"Check Sheet" is seen at the following support page

"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in

system development. http://edevice.fujitsu.com/micom/en-support/

16-Bit Original Microcontroller

CMOS

F2MC-16LX MB90420G/425G Series

MB90423GA/423GC/F423GA/F423GC/427GA/427GC/428GA/428GC/

MB90F428GA/F428GC/V420G

■DESCRIPTIONS

The FUJITSU MICROELECTR ONICS MB90420G/425G Series is a 16-bit general purpose high-capacity micro-

controller designed for vehicle meter control applications etc.

The instruction set retains the same AT architecture as the FUJITSU MICROELECTRONICS original F 2MC-8L

and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing

mode, enhanced (signed) multipler-divider computation and bit processing.

In addition, a 32-bit accumulator is built in to enable long word processing.

■FEATURES

• 16-bit input capture (4 channels)

Detects rising, falling, or both edges.

16-bit capture register × 4

Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.

• 16-bit reload timer (2 channels)

16-bit reload timer operation (select toggle output or one-shot output)

Event count function selection provided

• Watch timer (main clock)

Operates directly from oscillator clock.

Compensates for oscillator deviation

Read/write enabled second/minute/hour register

Signal interrupt (Continued)

DS07-13711-5E

MB90420G/425G Series

2DS07-13711-5E

• 16-bit PPG (3 channels)

Output pins (3) , external trigger input pin (1)

Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26

• Delay interr upt

Generates interrupt for task switching.

Interruptions to CPU can be generated/deleted by software setting.

• External interrupts (8 channels)

8-channel independent operation

Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.

• A/D converter

10-bit or 8-bit resolution × 8 channels (input multiplexed)

Conversion time : 6.13 µs or less (at fCP = 16 MHz)

External trigger startup available (P50/INT0/ADTG)

Internal timer startup available (16-bit reload timer 1)

• UART (2 channels)

Full duplex double buffer type

Supports asynchronous/synchronous transfer (with start/stop bits)

Internal timer can be selected as clock (16-bit reload timer 0)

Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps

Synchronous : 500 Kbps, 1Mbps, 2Mbps (at fCP = 16 MHz)

• CAN interface *1

Conforms to CAN specifications version 2.0 Part A and B.

Automatic resend in case of error.

Automatic transfer in response to remote frame.

16 prioritized message buffers for data and messages for data and ID

Multiple message support

Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks

Supports up to 1 Mbps

CAN WAKEUP function (connects RX internally to INT0)

• LCD controller/driver (1 channel)

Segment driver and command driver with direct LCD panel (display) drive capability

• Low voltage/Program Looping detect reset *2

Automatic reset when low voltage is detected

Program Looping detection function

• Stepping motor controller (4 channels)

High current output for all channels × 4

Synchronized 8/10-bit PWM for all channels × 2

• Sound generator

8-bit PWM signal mixed with tone frequency from 8-bit reload counter.

PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16MHz)

Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)

• Input/output ports

Push-pull output and Schmitt trigger input

Programmable in bit units for input/output or peripheral signals. (Continued)

MB90420G/425G Series

DS07-13711-5E 3

(Continued)

•Flash memory

Supports automatic programming, Embeded AlgorithmTM, write/erase/erase pause/erase resume instructions

Flag indicates algorithm completion

Minato Electronics flash writer

Boot block configuration

Erasa ble by blocks

Block protection by external programming voltage

*1 : MB90420G series has 2 channels built-in, MB90425G series has 1 channel built-in

*2 : Built-in to MB90420GA/425GA series only. Not built-in to MB90420GC/425GC series.

Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc.

MB90420G/425G Series

4DS07-13711-5E

■PRODUCT LINEUP

• MB90420G Series

* : When used with emulation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-50

Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) .

• MB90425G Series

Note : MB90V420G can be used as evaluation model for MB90420G/425G series.

Part

number

Parameter

MB90F423GA MB90F423GC MB90423GA MB90423GC MB90V420G

Configuration Flash ROM model Mask ROM model Evaluation model

CPU F2MC-16LX CPU

Clock 1 system 2 systems 1 system 2 systems 2 systems

System clock On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)

ROM Flash ROM 128 KB Mask ROM 128 KB External

RAM 6 KB 6 KB 6 KB

CAN interface 2 channels

Low voltage/

CPU operation

detection reset Yes No Yes No No

Packages QFP100, LQFP100 PGA-256

Emulator

dedicated

power supply* ⎯No

Part number

Parameter MB90F428GA MB90F428GC MB90427GA MB90427GC MB90428GA MB90428GC

Configuration Flash ROM model Mask ROM model

CPU F2MC-16LX CPU

Clock 1 system 2 systems 1 system 2 systems 1 system 2 systems

System clock On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)

ROM Flash ROM 128 KB Mask ROM 64 KB Mask ROM 128 KB

RAM 6 KB 4 KB 6 KB

CAN interface 1 channel

Low voltage/CPU

operation

detection reset Yes No Yes No Yes No

Packages QFP100, LQFP100

Emulator

dedicated

power supply ⎯

MB90420G/425G Series

DS07-13711-5E 5

■PIN ASSIGNMENTS

• QFP 100

(TOP VIEW)

(FPT-100P-M06)

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

VSS

SEG8

SEG9

SEG10

SEG11

P36/SEG12

P37/SEG13

P40/SEG14

P41/SEG15

P42/SEG16

P43/SEG17

P44/SEG18

VCC

P45/SEG19

P46/SEG20

P47/SEG21

P90/SEG22

P91/SEG23

X0A

X1A

P57/SGA

RST

P56/SGO/FRCK

P55/RX0

P54/TX0

DVSS

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

DVCC

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DVSS

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

DVCC

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

DVSS

P53/INT3

MD2

100

VSS

VCC

P00/SIN0/INT4

P01/SOT0/INT5

P02/SCK0/INT6

P03/SIN1/INT7

P04/SOT1

P05/SCK1/TRG

P06/PPG0/TOT1

P07/PPG1/TIN1

P10/PPG2

P11/TOT0/WOT

P12/TIN0/IN3

P13/IN2

P14/IN1

P15/IN0

COM0

COM1

MD1

MD0

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P67/AN7

P66/AN6

P65/AN5

P64/AN4

VSS

P63/AN3

P62/AN2

P61/AN1

P60/AN0

AVSS

P50/INT0/ADTG

AVRH

AVCC

MB90420G/425G Series

6DS07-13711-5E

• LQFP 100

(TOP VIEW)

(FPT-100P-M20)

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

P36/SEG12

P37/SEG13

P40/SEG14

P41/SEG15

P42/SEG16

P43/SEG17

P44/SEG18

P45/SEG19

P46/SEG20

P47/SEG21

RST

P56/SGO/FRCK

P55/RX0

P54/TX0

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

100

P57/SGA

X1A

X0A

P00/SIN0/INT4

P01/SOT0/INT5

P02/SCK0/INT6

P03/SIN1/INT7

P04/SOT1

P05/SCK1/TRG

P06/PPG0/TOT1

P07/PPG1/TIN1

P10/PPG2

P11/TOT0/WOT

P12/TIN0/IN3

P13/IN2

P14/IN1

P15/IN0

COM0

COM1

COM2

COM3

P53/INT3

MD2

MD1

MD0

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P67/AN7

P66/AN6

P65/AN5

P64/AN4

P63/AN3

P62/AN2

P61/AN1

P60/AN0

P50/INT0/ADTG

AVRH

P91/SEG23

P90/SEG22

MB90420G/425G Series

DS07-13711-5E 7

■PIN DESCRIPTIONS

(Continued)

Pin no. Symbol Circuit

type Description

LQFP QFP

80 82 X0 AHigh speed oscillator input pin.

81 83 X1 High speed oscillator output pin.

78 80 X0A A

Low speed oscillator input pin. If no oscillator is connected, apply

pull-down processing.

77 79 X1A Low speed oscillator output pin. If no oscillator is connected, leave

open.

75 77 RST B Reset input pin.

83 85

P00

General purpose input/output port.

SIN0 UART ch.0 serial data input pin.

INT4 INT4 external interrupt input pin.

84 86

P01

General purpose input/output port.

SOT0 UART ch.0 serial data output pin.

INT5 INT5 external interrupt input pin.

85 87

P02

General purpose input/output port.

SCK0 UART ch.0 serial clock input/output pin.

INT6 INT6 external interrupt input pin.

86 88

P03

General purpose input/output port.

SIN1 UART ch.1 serial data input pin.

INT7 INT7 external interrupt input pin.

87 89 P04 GGeneral purpose input/output port.

SOT1 UART ch.1 serial data output pin.

88 90

P05

General purpose input/output port.

SCK1 UART ch.1 serial clock input/output pin.

TRG 16-bit PPG ch.0-2 external trigger input pin.

89 91

P06

General purpose input/output port.

PPG0 16-bit PPG ch.0 output pin.

TOT1 16-bit reload timer ch.1 TOT output pin.

90 92

P07

General purpose input/output port.

PPG1 16-bit PPG ch.1 output pin.

TIN1 16-bit reload timer ch.1 TIN output pin.

91 93 P10 GGeneral purpose input/output port.

PPG2 16-bit PPG ch.2 output pin.

MB90420G/425G Series

8DS07-13711-5E

(Continued)

Pin no. Symbol Circuit

type Description

LQFP QFP

92 94

P11

General purpose input/output port.

TOT0 16-bit reload timer ch.0 TOT output pin.

WOT Real-time watch timer WOT output pin.

93 95

P12

General purpose input/output port.

TIN0 16-bit reload timer ch.0 TIN output pin.

IN3 Input capture ch.3 trigger input pin.

94 to 96 96 to 98 P13 to P15 GGeneral purpose input/output ports.

IN2 to IN0 Input capture ch.0-2 trigger input pins.

97 to 100 99 to 100,

1 to 2 COM0 to

COM3 I LCD controller/driver common output pins.

1 to 8,

10 to 13 3 to 10,

12 to 15 SEG0 to

SEG11 I LCD controller/driver segment output pins.

14 to 15 16 to 17 P36 to P37 EGeneral purpose output ports.

SEG12 to

SEG13 LCD controller/driver segment output pins.

16 to 20,

22 to 24 18 to 22,

24 to 26

P40 to P47 EGeneral purpose input output ports.

SEG14 to

SEG21 LCD controller/driver segment output pins.

26, 27 28, 29 P90, P91 EGeneral purpose input output ports.

SEG22,

SEG23 LCD controller/driver segment output pins.

34 36

P50

General purpose input output ports.

INT0 INT0 external interrupt input pin.

ADTG A/D converter external trigger input pin.

36 to 39,

41 to 44 38 to 41,

43 to 46

P60 to P67 FGeneral purpose input output ports.

AN0 to

AN7 A/D converter input pins.

45 47

P51

General purpose input output port.

INT1 INT1 external interrupt input pin.

(RX1 *1) CAN interface 1 RX intput pin.

46 48

P52

General purpose input output port.

INT2 INT2 external interrupt input pin.

(TX1 *1) CAN interface 1 TX output pin.

50 52 P53 GGeneral purpose input output port.

INT3 INT3 external interrupt input pin.

MB90420G/425G Series

DS07-13711-5E 9

(Continued)

Pin no. Symbol Circuit

type Description

LQFP QFP

52 to 55 54 to 57

P70 to P73

General purpose input output ports.

PWM1P0

PWM1M0

PWM2P0

PWM2M0

Stepping motor controller ch.0 output pins.

57 to 60 59 to 62

P74 to P77

General purpose input output ports.

PWM1P1

PWM1M1

PWM2P1

PWM2M1

Stepping motor controller ch.1 output pins.

62 to 65 64 to 67

P80 to P83

General purpose input output ports.

PWM1P2

PWM1M2

PWM2P2

PWM2M2

Stepping motor controller ch.2 output pins.

67 to 70 69 to 72

P84 to P87

General purpose input output ports.

PWM1P3

PWM1M3

PWM2P3

PWM2M3

Stepping motor controller ch.3 output pins.

72 74 P54 GGeneral purpose input output port.

TX0 CAN interface 0 TX output pin.

73 75 P55 GGeneral purpose output port.

RX0 CAN interface 0 RX input pin.

74 76

P56

General purpose input output port.

SGO Sound generator SGO output pin.

FRCK Free-run timer clock input pin.

76 78 P57 GGeneral purpose input output port.

SGA Sound generator SGA output pin.

28 to 31 30 to 33 V0 to V3 ⎯LCD controller /driver reference power supply pins.

56, 66 58, 68 DVCC ⎯High current output buffer with dedicated power supply input pins

(pin numbers 54-57, 59-62, 64-67, 69-72) .

51, 61, 71 53, 63, 73 DVSS ⎯High current output buffer with dedicated power supply GND pins

(pin numbers 54-57, 59-62, 64-67, 69-72) .

32 34 AVCC ⎯A/D converter dedicated power supply input pin.

35 37 AVSS ⎯A/D converter dedicated GND supply pin.

33 35 AVRH ⎯A/D converter Vref + input pin. Vref − AVss.

MB90420G/425G Series

10 DS07-13711-5E

(Continued)

*1 : MB90420G series only.

*2 : Type C in the flash ROM models, type D in the mask ROM models.

Pin no. Symbol Circuit

type Description

LQFP QFP

47, 48 49, 50 MD0, MD1 C Test mode input pins. Connect to VCC.

49 51 MD2 C/D *2Text mode input pin. Connect to VSS.

25 27 C ⎯External capacitor pin. Connect an 0.1 µF capacitor between this

pin and VSS.

21, 82 23, 84 VCC ⎯Power supply input pins.

9, 40, 79 11, 42, 81 VSS ⎯GND power supply pins.

MB90420G/425G Series

DS07-13711-5E 11

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

• Oscillation f eedback resistance :

approx. 1 MΩ (X0, X1 : MAIN)

• Oscillation f eedback resistance :

approx. 10 MΩ (X0A, X1A : SUB)

• Pull-up resistance attached :

approx. 50 kΩ, hysteresis input

• Hysteresis input

• Pull-down resistance attached :

approx. 50 kΩ, hysteresis input

• CMOS output

• LCDC output

• Hysteresis input

X1/X1A

X0/X0A

Standby control signal

Hysteresis input

Hyteresis input

LCDC output

Hysteresis input

MB90420G/425G Series

12 DS07-13711-5E

(Continued)

Type Circuit Remarks

• CMOS output

• Hysteresis input

• Analog input

• CMOS output

• Hysteresis input

• CMOS high current output

• Hysteresis input

• LCDC output

Analog input

Hysteresis input

High current

Hysteresis input

LCDC output

MB90420G/425G Series

DS07-13711-5E 13

■HANDLING DEVICES

Precautions for Handling Semiconductor Devices

• Strictly observe maximum rated voltages (prevent latchup)

When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output

pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in

excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup

condition, supply current can increase dramatically and may destroy semiconductor elements. In using semi-

conductor devices, always take sufficient care to avoid exceeding maximum ratings.

Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power

supply (AVCC, AVRH) , analog input and dedicated power supply for the high current output buffer pins (DVCC)

do not exceed the digital power supply (VCC) .

Once the digital pow er supply (VCC) is switched on, the analog po wer (AVCC,AVRH) and dedicated power supply

for the high current output buffer pins (DVCC) may be turned on in any sequence.

• Stable supply voltage

Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage can

cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre-

quencies (50 Hz to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur

during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.

• Power-on procedures

In order to pre vent abnormal operation of the internal b uilt-in step-down circuits, v oltage rise time during power-

on should be attained within 50 µs (0.2 V to 2.7 V) .

• Treatment of unused pins

If unused input pins are left open, the y ma y cause abnormal operation or latchup which ma y lead to permanent

damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least

2 kΩ.

Any unused input/output pins should be left open in output status, or if found set to input status, they should be

treated in the same way as input pins.

Any unused output pins should be left open.

• Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS.

• Use of external clock signals

Even when an exter nal clock is used, a stabilization period is required following a power-on reset or release

from sub clock mode or stop mode . Also, when an external clock is used it should drive only the X0 pin and the

X1 pin should be left open, as shown in the following figure.

OPEN

MB90420G/425G Series

Sample external clock connection

MB90420G/425G Series

14 DS07-13711-5E

• Power supply pins

De vices are designed to prevent prob lems such as latchup when m ultiple VCC and VSS supply pi ns are used, b y

providing internal connections between pins having the same potential. However, in order to reduce unwanted

radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total

output current ratings, all such pins should always be connected externally to power supplies and ground.

As shown in figure below, all VCC power supply pins must have the same potential. All VSS power supply pins

should be handled in the same wa y. If there are multiple VCC or VSS systems, the de vice will not operate properly

even within the warranted operating range.

In addition, care must be giv en to connecting the VCC and VSS pins of this device to a current source with as little

impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and

VSS as close to the pins as possible.

• Proper sequence of A/D converter power supply analog input

A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply

(VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off

before the digital power supply is sw itched on (VCC) . In both power-on and shut-off, care should be taken that

AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input por ts, be

sure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digital

power supplies are turned off and on at the same time.)

• Handling the power supply for high-current output buffer pins (DVCC, DVSS)

Alwa ys apply po wer to high-current output b uffer pins (DVCC, DVSS) after the digital power supply (VCC) is turned

on. Also when s witching power off, alwa ys shut off the pow er supply to the high-current output buff er pins (D VCC,

DVSS) bef ore s witching off the digital po w er supply (VCC) . (There will be no prob lem if high-current output b uffer

pins and digital power supplies are turned off and on at the same time.)

Even when high-current output b uff er pins are used as general purpose ports, the power f or high current output

buffer pins (DVCC, DVSS) should be applied to these pins.

• Pull-up/pull-down resistance

The MB90420G/425G series does not support internal pull-up/pull-down resistance. If necessary, use external

components.

VCC

VSS

Power supply input pins (VCC/VSS)

MB90420G/425G Series

DS07-13711-5E 15

• Precautions f or when not using a sub clock signal.

If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and lea ve

the X1A pin open.

• Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e v en

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

MB90420G/425G Series

16 DS07-13711-5E

■BLOCK DIAGRAM

Note: MB90420G series is equipped with 2-channel CAN interface and MB90425G series is equipped with 1-channel

CAN interface. MB90F423GA, MB90423GA, MB90F428GA, MB90427GA and MB90428GA have low volt-

age/CPU operation detection reset. MB90F423GC, MB90423GC, MB90F428GC, MB90427GC, MB90428GC

and MB90V420G do not have low voltage/CPU operation detection reset.

See “■ Product Lineup” for detail.

X0, X1

X0A, X1A

RST

P57/SGA

P56/SGO/FRCK

P55/RX0

P54/TX0

P53/INT3

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P50/INT0/ADTG

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

P67 to P60/

AN7 to AN0

AVCC/AVSS

AVRH

P91, P90/

SEG23, SEG22

P47 to P40/

SEG21 to SEG14

P37, P36/

SEG13 to SEG12

SEG11 to SEG0

COM3 to COM0

V3 to V0

P00/SIN0/INT4

P01/SOT0/INT5

P02/SCK0/INT6

P03/SIN1/INT7

P04/SOT1

P05/SCK1/TRG

P06/PPG0/TOT1

P07/PPG1/TIN1

P10/PPG2

P11/TOT0/WOT

P12/TIN0/IN3

P13/IN2

P14/IN1

P15/IN0

RAM

ROM

UART0/1

ICU0/1/2/3

PPG0/1/2

F2MC-16LX BUS

Clock control

circuit CPU

F2MC-16LX core

Interrupt

controller

Low voltage/

CPU operation

detection reset

Sound generator

CAN controller

Prescaler

0/1

Reload timer

0/1

Real-time

Watch timer

Free-run timer

External interrupt

(8 ch)

Port 8

Port 7

Port 6

Port 9

Port 4

Port 3

Port 5

Port 0

Port 1

Stepping

motor

Controller

0/1/2/3

A/D converter

(8 ch)

LCD controller/

driver

Evaluation device (MB90V420G)

No built-in ROM

Built-in RAM is 6 KB.

MB90420G/425G Series

DS07-13711-5E 17

■MEMORY MAP

Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The

image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enab le efficient use of

small C compiler models. The lower 16-bit address for the FF bank will be assign ed to the same address,

so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example

when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank

ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore

because the ROM data from FF4000H to FFFFFF H will appear in the image from 004000H to 00FFFFH, it is

recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH.

000000

0000C0

000100

Address #2

Address #1

003900

004000

010000

FFFFFF

Single chip mode

(with ROM mirror function)

Peripheral area

ROM area

(FF bank image)

ROM area

RAM area

Peripheral area

: Internal access memory

: Access prohibited

Parts No. Address #1 Address #2

MB90423GA/GC FE0000H001900H

MB90427GA/GC FF0000H001100H

MB90428GA/GC FE0000H001900H

MB90F423GA/GC FE0000H001900H

MB90F428GA/GC FE0000H001900H

MB90V420G FE0000H001900H

MB90420G/425G Series

18 DS07-13711-5E

■I/O MAP

• Other than CAN Interface

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

00HPort 0 data register PDR0 R/W Port 0 XXXXXXXX

01HPort 1 data register PDR1 R/W Port 1 - - XXXXXX

02H(Disabled)

03HPort 3 data register PDR3 R/W Port 3 X X - - - - - -

04HPort 4 data register PDR4 R/W Port 4 XXXXXXXX

05HPort 5 data register PDR5 R/W Port 5 XXXXXXXX

06HPort 6 data register PDR6 R/W Port 6 XXXXXXXX

07HPort 7 data register PDR7 R/W Port 7 XXXXXXXX

08HPort 8 data register PDR8 R/W Port 8 XXXXXXXX

09HPort 9 data register PDR9 R/W Port 9 - - - - - -XX

0AH to

0FH (Disabled)

10HPort 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0

11HPort 1 direction register DDR1 R/W Port 1 - - 0 0 0 0 0 0

12H (Disabled)

13HPort 3 direction register DDR3 R/W Port 3 0 0 - - - - - -

14HPort 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0

15HPort 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0

16HPort 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0

17HPort 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0

18HPort 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0

19HPort 9 direction register DDR9 R/W Port 9 - - - - - - 0 0

1AHAnalog input enable ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1

1BH to

1FH (Disabled)

20HA/D control status register lower ADCSL R/W

A/D converter

0 0 0 0 0 0 0 0

21HA/D control status register higher ADCSH R/W 0 0 0 0 0 0 0 0

22HA/D data register lower ADCRL R XXXXXXXX

23HA/D data register higher ADCRH R/W 0 0 1 0 1 XXX

24HCompare clear register CPCLR R/W

16-bit free-run timer

XXXXXXXX

25HR/W XXXXXXXX

26HTimer data register TCDT R/W 0 0 0 0 0 0 0 0

27HR/W 0 0 0 0 0 0 0 0

28HTimer control status register lower TCCSL R/W 0 0 0 0 0 0 0 0

29HTimer control status register higher TCCSH R/W 0 - - 0 0 0 0 0

MB90420G/425G Series

DS07-13711-5E 19

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

2AHPPG0 control status register lower PCNTL0 R/W 16-bit PPG0 0 0 0 0 0 0 0 0

2BHPPG0 control status register higher PCNTH0 R/W 0 0 0 0 0 0 0 -

2CHPPG1 control status register lower PCNTL1 R/W 16-bit PPG1 0 0 0 0 0 0 0 0

2DHPPG1 control status register higher PCNTH1 R/W 0 0 0 0 0 0 0 -

2EHPPG2 control status register lower PCNTL2 R/W 16-bit PPG2 0 0 0 0 0 0 0 0

2FHPPG2 control status register higher PCNTH2 R/W 0 0 0 0 0 0 0 -

30HExternal interrupt enable ENIR R/W

External interrupt

0 0 0 0 0 0 0 0

31HExternal interrupt request EIRR R/W 0 0 0 0 0 0 0 0

32HExternal interrupt level lower ELVRL R/W 0 0 0 0 0 0 0 0

33HExternal interrupt level higher ELVRH R/W 0 0 0 0 0 0 0 0

34HSerial mode register 0 SMR0 R/W

UART 0

0 0 0 0 0 - 0 0

35HSerial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0

36HInput data register 0/

Output data register 0 SIDR0/

SODR0 R/W XXXXXXXX

37HSerial status register 0 SSR0 R/W 0 0 0 0 1 0 0 0

38HSerial mode register 1 SMR1 R/W

UART1

0 0 0 0 0 − 0 0

39HSerial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0

3AHInput data register 1/

Output data register 1 SIDR1/

SODR1 R/W XXXXXXXX

3BHSerial status register 1 SSR1 R/W 0 0 0 0 1 0 0 0

3CH (Disabled)

3DHClock division control register 0 CDCR0 R/W Prescaler 0 - - - 0 0 0 0

3EHCAN wake-up control register CWUCR R/W CAN - - - - - - - 0

3FHClock division control register 1 CDCR1 R/W Prescaler 0 - - - 0 0 0 0

40H to 4FH Area reserved for CAN interface 0

50HTimer control status register 0 lower TMCSR0L R/W

16-bit reload timer 0

0 0 0 0 0 0 0 0

51HTimer control status register 0 high-

er TMCSR0H R/W - - - 0 0 0 0 0

52HTimer register 0/

Reload register 0 TMR0/

TMRLR0 R/W XXXXXXXX

53HXXXXXXXX

54HTimer control status register 1 lower TMCSR1L R/W

16-bit reload timer 1

0 0 0 0 0 0 0 0

55HTimer control status register 1 high-

er TMCSR1H R/W - - - 0 0 0 0 0

56HTimer register 1/

Reload register 1 TMR1/

TMRLR1 R/W XXXXXXXX

57HXXXXXXXX

58HWatch timer control register lower WTCRL R/W Real-time

watch timer 0 0 0 - - 0 0 0

59HWatch timer control register higher WTCRH R/W 0 0 0 0 0 0 0 0

MB90420G/425G Series

20 DS07-13711-5E

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

5AHSound control register lower SGCRL R/W

Sound generator

0 0 0 0 0 0 0 0

5BHSound control register higher SGCRH R/W 0 - - - - - 0 0

5CHFrequency data register SGFR R/W XXXXXXXX

5DHAmplitude data register SGAR R/W 0 0 0 0 0 0 0 0

5EHDecrement grade register SGDR R/W XXXXXXXX

5FHTone count register SGTR R/W XXXXXXXX

60HInput capture register 0 IPCP0 R

Input capture 0/1

XXXXXXXX

61HXXXXXXXX

62HInput capture register 1 IPCP1 R XXXXXXXX

63HXXXXXXXX

64HInput capture register 2 IPCP2 R

Input capture 2/3

XXXXXXXX

65HXXXXXXXX

66HInput capture register 3 IPCP3 R XXXXXXXX

67HXXXXXXXX

68HInput capture control status 0/1 ICS01 R/W Input capture 0/1 0 0 0 0 0 0 0 0

69H (Disabled)

6AHInput capture control status 2/3 ICS23 R/W Input capture 2/3 0 0 0 0 0 0 0 0

6BH (Disabled)

6CHLCD control register lower LCRL R/W LCD controller/

driver 0 0 0 1 0 0 0 0

6DHLCD control register higher LCRH R/W 0 0 0 0 0 0 0 0

6EHLow voltage/CPU operation

detection reset control register LVRC R/W Low voltage/CPU opera-

tion detection reset 1 0 1 1 1 0 0 0

6FHROM mirror ROMM W ROM mirror XXXXXXX1

70H to 7FHArea reserved for CAN interface 1

80HPWM control register 0 PWC0 R/W Stepping motor

controller0 0 0 0 0 0 - - 0

81H (Disabled)

82HPWM control register 1 PWC1 R/W Stepping motor

controller1 0 0 0 0 0 - - 0

83H (Disabled)

84HPWM control register 2 PWC2 R/W Stepping motor controller2 0 0 0 0 0 - - 0

85H (Disabled)

86HPWM control register 3 PWC3 R/W Stepping motor controller3 0 0 0 0 0 - - 0

87H to

9DH (Disabled)

MB90420G/425G Series

DS07-13711-5E 21

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

9EHROM correction control register PACSR R/W Address match

detection function - - - - - 0 - 0

9FHDelay interrupt/release DIRR R/W Delayed interrupt - - - - - - - 0

A0HPower saving mode LPMCR R/W Power saving

control circuit 0 0 0 1 1 0 0 0

A1HClock select CKSCR R/W 1 1 1 1 1 1 0 0

A2H to

A7H (Disabled)

A8HWatchdog control WDTC R/W Watchdog timer XXXXX 1 1 1

A9HTime base timer control register TBTC R/W Time base timer 1 - - 0 0 1 0 0

AAHWatch timer control register WTC R/W Watch timer

(sub-clock) 1 X 0 0 0 0 0 0

ABH to

ADH (Disabled)

AEHFlash control register FMCS R/W Flash interface 0 0 0 X 0 XX 0

AFH (Disabled)

B0HInterrupt control register 00 ICR00 R/W

Interrupt controller

0 0 0 0 0 1 1 1

B1HInterrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1

B2HInterrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1

B3HInterrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1

B4HInterrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1

B5HInterrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1

B6HInterrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1

B7HInterrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1

B8HInterrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1

B9HInterrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1

BAHInterrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1

BBHInterrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1

BCHInterrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1

BDHInterrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1

BEHInterrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1

BFHInterrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1

C0H to

FFH (Disabled)

MB90420G/425G Series

22 DS07-13711-5E

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

1FF0HROM correction address 0 PADR0 R/W

Address match

detection function

XXXXXXXX

1FF1HROM correction address 1 PADR0 R/W XXXXXXXX

1FF2HROM correction address 2 PADR0 R/W XXXXXXXX

1FF3HROM correction address 3 PADR1 R/W XXXXXXXX

1FF4HROM correction address 4 PADR1 R/W XXXXXXXX

1FF5HROM correction address 5 PADR1 R/W XXXXXXXX

3900H to

391FH (Disabled)

3920HPPG0 down counter register PDCR0 R

16-bit PPG 0

1 1 1 1 1 1 1 1

3921H1 1 1 1 1 1 1 1

3922HPPG0 cycle setting register PCSR0 W XXXXXXXX

3923HXXXXXXXX

3924HPPG0 duty setting register PDUT0 W XXXXXXXX

3925HXXXXXXXX

3926H to

3927H (Disabled)

3928HPPG1 down counter register PDCR1 R

16-bit PPG 1

1 1 1 1 1 1 1 1

3929H1 1 1 1 1 1 1 1

392AHPPG1 cycle setting register PCSR1 W XXXXXXXX

392BHXXXXXXXX

392CHPPG1 duty setting register PDUT1 W XXXXXXXX

392DHXXXXXXXX

392EH to

392FH (Disabled)

3930HPPG2 down counter register PDCR2 R

16 bit PPG 2

1 1 1 1 1 1 1 1

3931H1 1 1 1 1 1 1 1

3932HPPG2 cycle setting register PCSR2 W XXXXXXXX

3933HXXXXXXXX

3934HPPG2 duty setting register PDUT2 W XXXXXXXX

3935HXXXXXXXX

3936H to

3959H (Disabled)

MB90420G/425G Series

DS07-13711-5E 23

(Continued)

Address Register name Symbol Read/write Peripheral function Initial value

395AH

Sub second data register WTBR R/W

Real time

watch timer

XXXXXXXX

395BHXXXXXXXX

395CH- - - XXXXX

395DHSecond data register WTSR R/W - - XXXXXX

395EHMinute data register WTMR R/W - - XXXXXX

395FHHour data register WTHR R/W - - - XXXXX

3960H to

396BHLCD display RAM VRAM R/W LCD controller/

driver XXXXXXXX

396CH to

397FH (Disabled)

3980HPWM1 compare register 0 PWC10 R/W

Stepping motor

controller 0

XXXXXXXX

3981H- - - - - - XX

3982HPWM2 compare register 0 PWC20 R/W XXXXXXXX

3983H- - - - - - XX

3984HPWM1 select register 0 PWS10 R/W - - 0 0 0 0 0 0

3985HPWM2 select register 0 PWS20 R/W - 0 0 0 0 0 0 0

3986H to

3987H (Disabled)

3988HPWM1 compare register 1 PWC11 R/W

Stepping motor

controller 1

XXXXXXXX

3989H- - - - - - XX

398AHPWM2 compare register 1 PWC21 R/W XXXXXXXX

398BH- - - - - - XX

398CHPWM1 select register 1 PWS11 R/W - - 0 0 0 0 0 0

398DHPWM2 select register 1 PWS21 R/W - 0 0 0 0 0 0 0

398EH to

398FH (Disabled)

3990HPWM1 compare register 2 PWC12 R/W

Stepping motor

controller 2

XXXXXXXX

3991H- - - - - - XX

3992HPWM2 compare register 2 PWC22 R/W XXXXXXXX

3993H- - - - - - XX

3994HPWM1 select register 2 PWS12 R/W - - 0 0 0 0 0 0

3995HPWM2 select register 2 PWS22 R/W - 0 0 0 0 0 0 0

3996H to

3997H (Disabled)

MB90420G/425G Series

24 DS07-13711-5E

(Continued)

• Initial value symbols :

“0” initial value 0.

“1” initial value 1.

“X” initial v a lue undetermined

“-” initial value undetermined (none)

• Write/read symbols :

“R/W” read/write enabled

“R” read only

“W” write only

• Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access

attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.

Address Register name Symbol Read/write Peripheral function Initial value

3998HPWM1 compare register 3 PWC13 R/W

Stepping motor

controller 3

XXXXXXXX

3999H- - - - - - XX

399AHPWM2 compare register 3 PWC23 R/W XXXXXXXX

399BH- - - - - - XX

399CHPWM1 select register 3 PWS13 R/W - - 0 0 0 0 0 0

399DHPWM2 select register 3 PWS23 R/W - 0 0 0 0 0 0 0

399EH to

39FFH (Disabled)

3A00H to

3AFFHArea reserved for CAN interface 0

3B00H to

3BFFHArea reserved for CAN interface 1

3C00H to

3CFFHArea reserved for CAN interface 0

3D00H to

3DFFHArea reserved for CAN interface 1

3E00H to

3EFFH (Disabled)

MB90420G/425G Series

DS07-13711-5E 25

• I/O Map for CAN Interface

(Continued)

Address Register name Symbol Read/

write Initial value

CAN0 CAN1

000040H000070HMessage buffer valid area BVALR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000041H000071H

000042H000072HTransmission request register TREQR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000043H000073H

000044H000074HTransmission cancel register TCANR (W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000045H000075H

000046H000076HTransmission completed register TCR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000047H000077H

000048H000078HReceiving completed register RCR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

000049H000079H

00004AH00007AHRemote request receiving register RRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00004BH00007BH

00004CH00007CHReceiving overrun register ROVRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00004DH00007DH

00004EH00007EHReceiving interrupt enable register RIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00004FH00007FH

003C00H003D00HControl status register CSR (R/W, R) 0 0 - - - 0 0 0 0 - - - - 0 - 1

003C01H003D01H

003C02H003D02HLast event indicator register LEIR (R/W) - - - - - - - - 0 0 0 - 0 0 0 0

003C03H003D03H

003C04H003D04HRX/TX error counter RTEC (R) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C05H003D05H

003C06H003D06HBit timing register BTR (R/W) - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

003C07H003D07H

003C08H003D08HIDE register IDER (R/W) XXXXXXXX XXXXXXXX

003C09H003D09H

003C0AH003D0AHTransmission RTR register TRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C0BH003D0BH

003C0CH003D0CHRemote frame receiving wait register RFWTR (R/W) XXXXXXXX XXXXXXXX

003C0DH003D0DH

003C0EH003D0EHTransmission interrupt enable register TIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C0FH003D0FH

MB90420G/425G Series

26 DS07-13711-5E

(Continued)

Address Register name Symbol Read/

write Initial value

CAN0 CAN1

003C10H003D10H

Acceptance mask select register AMSR (R/W)

XXXXXXXX XXXXXXXX

003C11H003D11H

003C12H003D12HXXXXXXXX XXXXXXXX

003C13H003D13H

003C14H003D14H

Acceptance mask register 0 AMR0 (R/W)

XXXXXXXX XXXXXXXX

003C15H003D15H

003C16H003D16HXXXXX- - - XXXXXXXX

003C17H003D17H

003C18H003D18H

Acceptance mask register 1 AMR1 (R/W)

XXXXXXXX XXXXXXXX

003C19H003D19H

003C1AH003D1AHXXXXX- - - XXXXXXXX

003C1BH003D1BH

003A00H

003A1FH

003B00H

003B1FHGeneral purpose RAM ⎯ (R/W) XXXXXXXX to XXXXXXXX

003A20H003B20H

ID register 0 IDR0 (R/W)

XXXXXXXX XXXXXXXX

003A21H003B21H

003A22H003B22HXXXXX- - - XXXXXXXX

003A23H003B23H

003A24H003B24H

ID register 1 IDR1 (R/W)

XXXXXXXX XXXXXXXX

003A25H003B25H

003A26H003B26HXXXXX- - - XXXXXXXX

003A27H003B27H

003A28H003B28H

ID register 2 IDR2 (R/W)

XXXXXXXX XXXXXXXX

003A29H003B29H

003A2AH003B2AHXXXXX- - - XXXXXXXX

003A2BH003B2BH

003A2CH003B2CH

ID register 3 IDR3 (R/W)

XXXXXXXX XXXXXXXX

003A2DH003B2DH

003A2EH003B2EHXXXXX- - - XXXXXXXX

003A2FH003B2FH

003A30H003B30H

ID register 4 IDR4 (R/W)

XXXXXXXX XXXXXXXX

003A31H003B31H

003A32H003B32HXXXXX- - - XXXXXXXX

003A33H003B33H

MB90420G/425G Series

DS07-13711-5E 27

(Continued)

Address Register name Symbol Read/

write Initial value

CAN0 CAN1

003A34H003B34H

ID register 5 IDR5 (R/W)

XXXXXXXX XXXXXXXX

003A35H003B35H

003A36H003B36HXXXXX- - - XXXXXXXX

003A37H003B37H

003A38H003B38H

ID register 6 IDR6 (R/W)

XXXXXXXX XXXXXXXX

003A39H003B39H

003A3AH003B3AHXXXXX- - - XXXXXXXX

003A3BH003B3BH

003A3CH003B3CH

ID register 7 IDR7 (R/W)

XXXXXXXX XXXXXXXX

003A3DH003B3DH

003A3EH003B3EHXXXXX- - - XXXXXXXX

003A3FH003B3FH

003A40H003B40H

ID register 8 IDR8 (R/W)

XXXXXXXX XXXXXXXX

003A41H003B41H

003A42H003B42HXXXXX- - - XXXXXXXX

003A43H003B43H

003A44H003B44H

ID register 9 IDR9 (R/W)

XXXXXXXX XXXXXXXX

003A45H003B45H

003A46H003B46HXXXXX- - - XXXXXXXX

003A47H003B47H

003A48H003B48H

ID register 10 IDR10 (R/W)

XXXXXXXX XXXXXXXX

003A49H003B49H

003A4AH003B4AHXXXXX- - - XXXXXXXX

003A4BH003B4BH

003A4CH003B4CH

ID register 11 IDR11 (R/W)

XXXXXXXX XXXXXXXX

003A4DH003B4DH

003A4EH003B4EHXXXXX- - - XXXXXXXX

003A4FH003B4FH

003A50H003B50H

ID register 12 IDR12 (R/W)

XXXXXXXX XXXXXXXX

003A51H003B51H

003A52H003B52HXXXXX- - - XXXXXXXX

003A53H003B53H

MB90420G/425G Series

28 DS07-13711-5E

(Continued)

Address Register name Symbol Read/

write Initial value

CAN0 CAN1

003A54H003B54H

ID register 13 IDR13 (R/W)

XXXXXXXX XXXXXXXX

003A55H003B55H

003A56H003B56HXXXXX- - - XXXXXXXX

003A57H003B57H

003A58H003B58H

ID register 14 IDR14 (R/W)

XXXXXXXX XXXXXXXX

003A59H003B59H

003A5AH003B5AHXXXXX- - - XXXXXXXX

003A5BH003B5BH

003A5CH003B5CH

ID register 15 IDR15 (R/W)

XXXXXXXX XXXXXXXX

003A5DH003B5DH

003A5EH003B5EHXXXXX- - - XXXXXXXX

003A5FH003B5FH

003A60H003B60HDLC register 0 DLCR0 (R/W) - - - -XXXX - - - -XXXX

003A61H003B61H

003A62H003B62HDLC register 1 DLCR1 (R/W) - - - -XXXX - - - -XXXX

003A63H003B63H

003A64H003B64HDLC register 2 DLCR2 (R/W) - - - -XXXX - - - -XXXX

003A65H003B65H

003A66H003B66HDLC register 3 DLCR3 (R/W) - - - -XXXX - - - -XXXX

003A67H003B67H

003A68H003B68HDLC register 4 DLCR4 (R/W) - - - -XXXX - - - -XXXX

003A69H003B69H

003A6AH003B6AHDLC register 5 DLCR5 (R/W) - - - -XXXX - - - -XXXX

003A6BH003B6BH

003A6CH003B6CHDLC register 6 DLCR6 (R/W) - - - -XXXX - - - -XXXX

003A6DH003B6DH

003A6EH003B6EHDLC register 7 DLCR7 (R/W) - - - -XXXX - - - -XXXX

003A6FH003B6FH

003A70H003B70HDLC register 8 DLCR8 (R/W) - - - -XXXX - - - -XXXX

003A71H003B71H

003A72H003B72HDLC register 9 DLCR9 (R/W) - - - -XXXX - - - -XXXX

003A73H003B73H

003A74H003B74HDLC register 10 DLCR10 (R/W) - - - -XXXX - - - -XXXX

003A75H003B75H

MB90420G/425G Series

DS07-13711-5E 29

(Continued)

Address Register name Symbol Read/

write Initial value

CAN0 CAN1

003A76H003B76HDLC register 11 DLCR11 (R/W) - - - -XXXX - - - -XXXX

003A77H003B77H

003A78H003B78HDLC register 12 DLCR12 (R/W) - - - -XXXX - - - -XXXX

003A79H003B79H

003A7AH003B7AHDLC register 13 DLCR13 (R/W) - - - -XXXX - - - -XXXX

003A7BH003B7BH

003A7CH003B7CHDLC register 14 DLCR14 (R/W) - - - -XXXX - - - -XXXX

003A7DH003B7DH

003A7EH003B7EHDLC register 15 DLCR15 (R/W) - - - -XXXX - - - -XXXX

003A7FH003B7FH

003A80H

003A87H

003B80H

003B87HData register 0 (8 bytes) DTR0 (R/W) XXXXXXXX to XXXXXXXX

003A88H

003A8FH

003B88H

003B8FHData register 1 (8 bytes) DTR1 (R/W) XXXXXXXX to XXXXXXXX

003A90H

003A87H

003B90H

003B97HData register 2 (8 bytes) DTR2 (R/W) XXXXXXXX to XXXXXXXX

003A98H

003A9FH

003B98H

003B9FHData register 3 (8 bytes) DTR3 (R/W) XXXXXXXX to XXXXXXXX

003AA0H

003AA7H

003BA0H

003BA7HData register 4 (8 bytes) DTR4 (R/W) XXXXXXXX to XXXXXXXX

003AA8H

003AAFH

003BA8H

003BAFHData register 5 (8 bytes) DTR5 (R/W) XXXXXXXX to XXXXXXXX

003AB0H

003AB7H

003BB0H

003BB7HData register 6 (8 bytes) DTR6 (R/W) XXXXXXXX to XXXXXXXX

003AB8H

003ABFH

003BB8H

003BBFHData register 7 (8 bytes) DTR7 (R/W) XXXXXXXX to XXXXXXXX

003AC0H

003AC7H

003BC0H

003BC7HData register 8 (8 bytes) DTR8 (R/W) XXXXXXXX to XXXXXXXX

003AC8H

003ACFH

003BC8H

003BCFHData register 9 (8 bytes) DTR9 (R/W) XXXXXXXX to XXXXXXXX

MB90420G/425G Series

30 DS07-13711-5E

(Continued)

Address Register name Symbol Read/

write Initial value

CAN0 CAN1

003AD0H

003AD7H

003BD0H

003BD7HData register 10 (8 bytes) DTR10 (R/W) XXXXXXXX to XXXXXXXX

003AD8H

003ADFH

003BD8H

003BDFHData register 11 (8 bytes) DTR11 (R/W) XXXXXXXX to XXXXXXXX

003AE0H

003AE7H

003BE0H

003BE7HData register 12 (8 bytes) DTR12 (R/W) XXXXXXXX to XXXXXXXX

003AE8H

003AEFH

003BE8H

003BEFHData register 13 (8 bytes) DTR13 (R/W) XXXXXXXX to XXXXXXXX

003AF0H

003AF7H

003BF0H

003BF7HData register 14 (8 bytes) DTR14 (R/W) XXXXXXXX to XXXXXXXX

003AF8H

003AFFH

003BF8H

003BFFHData register 15 (8 bytes) DTR15 (R/W) XXXXXXXX to XXXXXXXX

MB90420G/425G Series

DS07-13711-5E 31

■INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt source EI2OS

compatible Interrupt vector Interrupt control register Priority

Number Address ICR Address

Reset × #08 08HFFFFDCH⎯⎯High

INT9 instruction × #09 09HFFFFD8H⎯⎯

Exception processing × #10 0AHFFFFD4H⎯⎯

CAN0 RX × #11 0BHFFFFD0HICR00 0000B0H *1

CAN0 TX/NS × #12 0CHFFFFCCH

CAN1 RX × #13 0DHFFFFC8HICR01 0000B1H *1

CAN1 TX/NS × #14 0EHFFFFC4H

Input capture 0 #15 0FHFFFFC0HICR02 0000B2H *1

DTP/external interrupt - ch 0 detected #16 10HFFFFBCH

Reload timer 0 #17 11HFFFFB8HICR03 0000B3H *1

DTP/external interrupt - ch 1 detected #18 12HFFFFB4H

Input capture 1 #19 13HFFFFB0HICR04 0000B4H *1

DTP/external interrupt - ch 2 detected #20 14HFFFFACH

Input capture 2 #21 15HFFFFA8HICR05 0000B5H *1

DTP/external interrupt - ch 3 detected #22 16HFFFFA4H

Input capture 3 #23 17HFFFFA0HICR06 0000B6H *1

DTP/external interrupt - ch 4/5 detected #24 18HFFFF9CH

PPG timer 0 #25 19HFFFF98HICR07 0000B7H *1

DTP/external interrupt - ch 6/7 detected #26 1AHFFFF94H

PPG timer 1 #27 1BHFFFF90HICR08 0000B8H *1

Reload timer 1 #28 1CHFFFF8CH

PPG timer 2 #29 1DHFFFF88HICR09 0000B9H *1

Real time watch timer × #30 1EHFFFF84H

Free-run timer over flow × #31 1FHFFFF80HICR10 0000BAH *1

A/D converter conversion end #32 20HFFFF7CH

Free-run timer clear × #33 21HFFFF78HICR11 0000BBH *1

Sound generator × #34 22HFFFF74H

Time base timer × #35 23HFFFF70HICR12 0000BCH *1

Watch timer (sub-clock) × #36 24HFFFF6CH

UART 1 RX #37 25HFFFF68HICR13 0000BDH *1

UART 1 TX #38 26HFFFF64H

UART 0 RX #39 27HFFFF60HICR14 0000BEH *1

UART 0 TX #40 28HFFFF5CH

Flash memory status × #41 29HFFFF58HICR15 0000BFH *1

Delayed interrupt generator module × #42 2AHFFFF54HLow

MB90420G/425G Series

32 DS07-13711-5E

: Compatible, with EI2OS stop function

: Compatible

: Compatible when interrupt sources sharing ICR are not in use

× : Not compatible

*1 : • Peripheral functions sharing the ICR register have the same interrupt level.

• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other

cannot be used.

• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,

the interrupt from the other function cannot be used.

*2 : Priority applies when interrupts of the same level are generated.

MB90420G/425G Series

DS07-13711-5E 33

■PERIPHERAL FUNCTIONS

1. I/O Ports

The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O

pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in

bit units by the port direction register (DDR) as required. The following list shows each of the functions as well

as the shared peripheral function for each port.

• Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG)

• Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/watch timer/ICU)

• Port 3 : General purpose I/O port, shared with peripheral functions (LCD)

• Port 4 : General purpose I/O port, shared with peripheral functions (LCD)

• Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG)

• Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter)

• Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)

• Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)

• Port 9 : General purpose I/O port, shared with peripheral functions (LCD)

(1) List of Functions

(Continued)

Port Pin name Input

format Output for-

mat Function

Port 0 P00/SIN0/INT4 to

P07/PPG1

CMOS

(hysteresis)

(Automotive level*)

CMOS

General purpose I/O port

Peripheral function

Port 1 P10/PPG2 to

P15/IN0 General purpose I/O port

Peripheral function

Port 3 P36/SEG12,

P37/SEG13 General purpose I/O port

Peripheral function

Port 4 P40/SEG14 to

P47/SEG21 General purpose I/O port

Peripheral function

Port 5 P50/INT0 to

P57/SGA General purpose I/O port

Peripheral function

Port 6 P60/AN0 to

P67/AN7

Analog

CMOS

(hysteresis)

(Automotive level*)

General purpose I/O port

Peripheral function

Port 7 P70/PWM1P0 to

P77/PWM2M1 CMOS

(hysteresis)

(Automotive level*)

General purpose I/O port

Peripheral function

Port 8 P80/PWM1P2 to

P87/PWM2M3 General purpose I/O port

Peripheral function

Port 9 P90/SEG22,

P91/SEG23 General purpose I/O port

Peripheral function

MB90420G/425G Series

34 DS07-13711-5E

(Continued)

*: Range of input voltage.

For ratings see “3. DC Characteristics” in “■ ELECTRICAL CHARACTERISTICS”.

Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write

“0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset.

Port bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Port 0

P07 P06 P05 P04 P03 P02 P01 P00

PPG1 PPG0 SCK1 SOT1 SIN1 SCK0 SOT0 SIN0

TIN1 TOT1 ⎯⎯INT7 INT6 INT5 INT4

Port 1

⎯⎯P15 P14 P13 P12 P11 P10

⎯⎯IN0 IN1 IN2 IN3 WOT PPG2

⎯⎯⎯⎯⎯TIN0 TOT0 ⎯

Port 3 P37 P36 ⎯⎯⎯⎯⎯⎯

SEG13 SEG12 ⎯⎯⎯⎯⎯⎯

Port 4 P47 P46 P45 P44 P43 P42 P41 P40

SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14

Port 5

P57 P56 P55 P54 P53 P52 P51 P50

SGA SGO RX0 TX0 INT3 INT2 INT1 INT0

⎯FRCK ⎯⎯⎯TX1 RX1 ⎯

Port 6 P67 P66 P65 P64 P63 P62 P61 P60

AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

Port 7 P77 P76 P75 P74 P73 P72 P71 P70

PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0

Port 8 P87 P86 P85 P84 P83 P82 P81 P80

PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2

Port 9 ⎯⎯⎯⎯⎯⎯P91 P90

⎯⎯⎯⎯⎯⎯SEG23 SEG22

MB90420G/425G Series

DS07-13711-5E 35

(2) Block Diagrams

Ports 0, 1, 3, 4, 5, 7, 8, 9

Peripheral function input

Peripheral function output

Peripheral function output enabled

PDR (Port data register)

DDR (Port direction register)

Internal data bus

PDR read

DDR read

Output latch

Direction

latch

PDR write

DDR write

Standby control (SPL = 1)

or LCD output enabled

ADER

Port 6

PDR (Port data register)

DDR (Port direction register)

Analog input

RDR read

PDR write

Internal data bus

Output latch

Direction

latch

DDR write

DDR read Standby control (SPL = 1)

MB90420G/425G Series

36 DS07-13711-5E

2. Watchdog Timer/Time Base Timer/Watch Timer

The watchdog timer, timer base timer, and watch timer have the following circuit configuration.

• Watchdog timer : Watchdog counter, control register, watchdog reset circuit

• Time base timer : 18-bit timer, interval interrupt control circuit

• Watch timer : 15-bit timer, interval interrupt control circuit

(1) Watchdog timer function

The watchdog timer is composed of a 2-bit watchdog counter that uses the carr y signal from the 18-bit time

base timer or 15-bit watch timer as a clock source, plus a control register and watchdog reset control circuit.

After startup, this function will reset the CPU if not cleared within a given time.

(2) Time base timer function

The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count cloc k

(base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other

functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or

other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS

bit or SCS bit in the CKSCR register.

(3) Watch timer function

The watch timer pro v ides functions including a clock source for the watchdog timer, a sub clock base oscillator

stabilization wait timer, and an interval timer to generate an interrupt at fix ed interv als. Note that the watch timer

uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.

MB90420G/425G Series

DS07-13711-5E 37

•Block Diagram

TBTC

PONR

WRST

ERST

SRST

TBC0

TBR

TBIE

TBOF

TBC1

WT1

WT0

WTE

WTC

WDCS

SCE

WTC2

WTC0

WTR

WTIE

WTOF

WDTC

AND

CLR OF CLR

211

213

216

218

TBTRES

210

211

212

213

214

216

WTRES

211 213 216 218

210 213 214 216

AND QR

AND

Main base oscillator

divided by 2

Selector Clock input

Time base timer

Time base

interrupt

Selector

2-bit

counter Watchdog reset

generator circuit To WDGRST

internal reset

generator circuit

MC-16LX bus

Power-on reset,

sub-clock stop

SCM

Watch timer

Clock input

Watch interrupt Sub base oscillator divided by 4

From power-on generator

RST pin

From RST bit in LPMCR

MB90420G/425G Series

38 DS07-13711-5E

3. Input Capture

This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.

(1) Input capture ( × 4)

The input capture circuits consist of four independent external input pins and corresponding capture registers

and control registers. When the specified edge of the e xternal signal input (at the input pin) is detected, the value

of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be

generated.

• The valid edge (rising edge, falling edge, both edges) of the external signal can be selected.

• The four input capture circuits can operate independently.

• The interrupt can be generated from the valid edge of the external input signal.

(2) 16-bit free-run timer ( × 1)

The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and

prescaler. The output values from this counter are used as the base time for the input capture circuits.

• The counter clock operation can be selected from 8 options. The eight inter nal clock settings are φ, φ/2, φ/4,

φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle.

• Interrupts can be generated from overflow events, or from compare match events with the compare register.

(Compare match operation requires a mode setting.)

• The counter value can be initialized to “0000H” by a reset, soft clear, or a compare match with the compare

(3) Block diagram

IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0

MSI2

MSI0 ICLR

EG11 EG10 EG01 EG00

ICRE

IN0/2

IN1/3

ICP0 ICP1 ICE0 ICE1

interrupt

#31 (1F

)

Divider

Clock

16-bit free-run timer

MC-16LX bus

16-bit compare clear register Compare circuit Interrupt

#33 (21

)

A/D startup

Capture data register 0/2

Capture data register 1/3

Edge detection

Interrupt

#19, #23

Interrupt

#15, #21

MB90420G/425G Series

DS07-13711-5E 39

4. 16-bit Reload Timer

The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in

internal cloc k mode, or count down at the detection of the designated edge of an external signal. The user may

select either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus an

underflow occurs when counting from the value [Reload register setting + 1].

A selection of two counter operating modes are a vailab le. In reload mode, the counter is reset to the count value

and continues counting after an underflow, and in one-shot mode the count stops after an underflow. The counter

can generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services

(EI2OS) .

(1) 16-bit Reload timer operating modes

(2) Internal clock mode

One of three input clocks is selected as the count clock, and can be used in one of the following operations.

• Soft trigger operation

When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation

starts.Tr igger input at the TRG bit is normally valid with an ex ternal trigger input, as well as an external gate

input.

• External trigger operation

Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin.

• External gate input operation

Counting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin.

(3) Event count mode (External clock mode)

In this mode a down count event occurs when a selected valid edge (r ising, falling, both edges) is input at the

TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used.

(4) Counter operation

• Reload mode

In down count operation, when an underflow event (transition from “0000H” to “FFFFH”) occurs, the set count

value is reloaded and count operation continues. The function can be used as an interval timer by generating

an interrupt request at each underflow event. Also, a toggle waveform that inver ts at each underflow can be

output from the TOT0/1 pin.

φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz.

Clock mode Counter mode 16-bit reload timer operation

Internal clock mode Reload mode Soft trigger operation

External trigger operation

External gate input operation

One-shot mode

Event count mode

(external clock mode) Reload mode Soft trigger operation

One-shot mode

Counter clock Counter clock period Interval time

Internal clock

21/φ (0.125 µs) 0.125 µs to 8.192 ms

23/φ (0.5 µs) 0.5 µs to 32.768 ms

25/φ (2.0 µs) 2.0 µs to 131.1 ms

External clock 23/φ or greater (0.5 µs) 0.5 µs or greater

MB90420G/425G Series

40 DS07-13711-5E

(5) One-shot mode

In down count oper ation, the count stops when an underflow event (transition from “0000H” to “FFFFH”) occurs.

This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave

form indicating that the count is in progress can be output form the TOT0 and TOT1 pins.

(6) Block diagram

CLK

3 2

⎯⎯⎯⎯CSL1 CSL0 OUTEOUTL RELD INTE UF CNTE TRG

WOD2WOD1WOD0

P12/TIN0 *1

TMRLR0 *1

TMR0 *1

<TMR1>

P11/TOT0 *1

Internal data bus

16-bit reload register

Reload

control circuit

Reload signal

16-bit timer register (down counter)

Wait signal

Valid clock

decision circuit

Gate input

Prescaler

Machine

clock

To UART 0,1*1

Pins

Output signal

generator

circuit

Inverted

Clock

selector

External clock

Input

control

circuit

Pins

Function selection

Select

signal

Operation

control

circuit

Interrupt

request signal

#17 (11h)*2

<#28 (1CH)>

Timer control status register (TNGSR0)*1

*1: Channel 0 and channel 1. Figures in < > are for channel 1.

*2: Interrupt number

MB90420G/425G Series

DS07-13711-5E 41

5. Real Time Watch Timer

The real time watch timer is composed of a real time watch timer control register, sub second data register,

second/minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Because

the MCU oscillation frequency operates on a given real time watch timer operation, a 4 MHz frequency is

assumed. The real time watch timer operates as a real world timer and provides real world time information.

•Block diagram

INTE0 INT0

LOAD CO CO

OE WOT

IRQ#30

INTE1

STUPDT

INT1 INTE2 INT2 INTE3 INT3

Main oscillator clock 1/2 clock

divider 21-bit

prescaler

Sub second

Second

counter Minute

counter Hour

counter

6-bit 6-bit 5-bit

Second/minute/hour register

MB90420G/425G Series

42 DS07-13711-5E

6. PPG Timer

The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting,

and 16-bit compare register with buffer for duty setting, plus pin control circuits.

The timer can output pulses synchronized with an e xternally input soft trigger . The period and duty of the output

pulse can be adjusted by rewriting the values in the two 16-bit registers.

(1) PWM function

Programmable to output a pulse, synchronized with a trigger.

Can also be used as a D/A converter with an external circuit.

(2) One-shot function

Detects the edge of a trigger input, and outputs a single pulse.

(3) Pin control

• Set to “1” at a duty match (priority) .

• Reset to “0” at a counter borrow event

• Has a fixed output mode to output a simple all “L” ( or “H”) signal.

• Polarity can be specified

(4) 16-bit down counter

• Select from f our types of counter operation clocks . F our internal clocks (φ, φ/4, φ/16, φ/64) φ : Machine clock

cycles.

• The counter value can be initialized to “FFFFH” at a reset or counter borrow event.

(5) Interrupt requests

• Timer startup

• Counter borrow event (period match)

• Duty match event

• Counter borrow event (period match) or duty match event

(6) Multiple channels can be set to start up at an external trigger, or to restart during operation.

MB90420G/425G Series

DS07-13711-5E 43

(7) Block diagram

1/1

1/4

1/16

1/64

P05/SCK1/TRG

CMP

PCSR PDUT

Prescaler

Load

PCNT

16-bit down counter

Start Borrow

PPG mask

Machine clock PPG

output

Inversion bit

Enable

Trigger inputInterrupt IRQ#25, 27, 29

Edge detection

Soft trigger

Interrupt

selection

MB90420G/425G Series

44 DS07-13711-5E

7. Delayed Interrupt Generator Module

The delayed interrupt generator module is a module that generates interrupts for task switching. This module

makes it possible to use software to generate/cancel interrupt requests to the F2MC-16LX CPU.

•Block diagram

F2MC-16LX bus

Delayed interrupt source generate/delete decoder

Source latch

MB90420G/425G Series

DS07-13711-5E 45

8. DTP/External Interrupt Circuit

The DTP (Data transf er peripheral) /e xternal interrupt circuit is located between an e xternally connected periph-

eral de vice and the F2MC-16LX CPU and sends interrupt requests or data transf er requests generated from the

peripheral de vice to the CPU, thereby generating e xternal interrupt requests or starting the expanded intelligent

I/O services (EI2OS) .

(1) DTP/external interrupt function

The DTP/e xternal interrupt function uses a signal input from the DTP/e xternal interrupt pin as a startup source.

And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an

external interrupt or start the expanded intelligent I/O service (EI2OS) .

When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI2OS) is

prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the

EI2OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, then

branching to an interrupt routine after the completion of the specified number of data transfers.

ICR : Interrupt control register

External interrupt DTP function

Input pins 8 pins (P50/INT0/ADTG to P53/INT3, P00/SIN0/INT4 to P03/INT7)

Interrupt sources

Request level setting register (ELVR) sets the detection level, or selected edge for

each pin

“H” level/ “L” level/ rising edge/falling

edge input “H” level/ “L” level input

Interrupt numbers #16 (10H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH)

Interrupt control DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output

Interrupt flags DTP/interrupt enable register (EIRR) stores interrupt sources

Process selection When EI2OS prohibited (ICR : ISE = 0) When EI2OS is enabled (ICR : ISE = 1)

Processing Branch to external interrupt processing

routine

EI2OS performs automatic data transfer,

then after a specified number of cycles,

branches to an interrupt routine

MB90420G/425G Series

46 DS07-13711-5E

(2) Block diagram

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

P03/INT7

P02/INT6

P01/INT5

P00/INT4

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

P50/INT0

P51/INT1

P52/INT2

P53/INT3

#16 (10

)

#18 (12

)

#20 (14

)

#22 (16

)

#26 (1A

)

#24 (18

)

Request level setting register (ELVR)

Selector Selector

Selector

Selector Selector

Selector

Interrupt request number

Internal data bus

MB90420G/425G Series

DS07-13711-5E 47

9. 8/10-bit A/D Converter

The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analog

input v oltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, and

the conversion start can be selected from three types : by softw are, 16-bit reload timer 1 or a trigger input from

an external signal pin.

(1) 8/10-bit A/D converter functions

The A/D conv erter tak es analog voltage signals (input v oltage) input at analog input pins, and con v erts these to

digital values, providing the following features.

• Minimum conversion time is 6.13 µs (at machine clock frequency of 16 MHz, including sampling time) .

• Minimum sampling time is 3.75 µs (at machine clock 16 MHz)

• The conversion method is an RC sequential conversion in comparison with a sample hold circuit.

• Either 10-bit or 8-bit resolution can be selected.

• The analog input pin can select from 8 channels by a program setting.

• At completion of A/D conversion, an interrupt request can be generated, or EI2OS can be started.

• Because the conversion data protection function operates in an interrupt enabled state, no data is lost even

in continuous conversion.

• The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external

trigger input (falling edge) .

Three conversion modes are available

Conversion mode Single conversion operation Scan conversion operation

Single conversion mode Converts the specified channel (1 channel

only) one time, then stops.

Converts multiple consecutive channels (up

to 8 channels may be specified) one time,

then stops.

Continuous conversion

mode Converts the specified channel (1 channel

only) repeatedly. Converts multiple consecutive channels (up

to 8 channels may be specified) repeatedly.

Stop conversion mode Converts the specified channel (1 channel

only) one time, then pauses, waits until

the next start is applied.

Converts multiple consecutive channels (up

to 8 channels may be specified) , however

pauses after conversion of each channel,

waits until the next start is applied.

MB90420G/425G Series

48 DS07-13711-5E

(2) Block diagram

AVRH

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

MPX

ADCRH, L

ADCSH, L

P50/ADTG

D/A converter

Input circuit

Sequential comparator

Comparator

Sample & hold circuit

MC-16LX bus

A/D data register

Decoder

A/D control status register, high

A/D control status register, low

Timer start

16-bit reload timer 1 Trigger start Operating clock

Prescaler

MB90420G/425G Series

DS07-13711-5E 49

10. UART

The UART is a general purpose serial data communication interface for synchronous communication, or asyn-

chronous (start-stop synchronized) communication with external devices. Functions include normal bi-directional

functions, as well as master/slave type communication functions (multi-processor mode : master side only

supported) .

(1) UART Functions

The U ART is a general purpose serial data communication interface f or sending and receiving of serial data with

other CPU’s or peripheral devices, and provides the following functions.

Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only.

⎯ : Setting not available

*1 : “+ ” indicates an address/data selection bit (A/D) for communication control.

*2 : In receiving only one stop bit is detected.

Functions

Data buffer Full duplex double buffer

Transfer modes • Clock synchronous (no start/stop bits)

• Clock asynchronous (start-stop synchronized)

Baud rate • Exclusive baud rate generator provides a selection of 8 rates

• External clock input enabled

• Internal clock (can use internal clock feed from 16-bit reload timer)

Data length • 7-bit (asynchronous normal mode only)

•8-bit

Signal type NRZ (Non return to zero)

Receiving error detection • Framing errors

• Overrun errors

• Parity errors (not enabled in multiprocessor mode)

Interrupt request

• Receiving interrupt (receiving completed, receiving error detection)

• Sending interrupt (sending completed)

• Sending/receiving both compatible with expanded intelligent I/O services

(EI2OS)

Master/slave type

communication function

(multi-processor mode) 1 (master) -to-n (slave) communication enabled (only master side supported) .

Operating mode Data length Synchronization Stop bit length

No parity Parity

0 Normal mode 7-bit or 8-bit Asynchronous 1-bit or 2-bit *2

1 Multi-processor mode 8 + 1 *1⎯Asynchronous

2Normal mode 8 ⎯Synchronous None

MB90420G/425G Series

50 DS07-13711-5E

(2) Block diagram

Control bus

Machine clock

16-bit

reload timer

P02/SCK0

Pins

MD1

MD0

CS2

CS1

CS0

SCKE

SOE

PEN

SBL

A/D

REC

RXE

TXE

ORE

FRE

RDRF

TDRE

BOS

RIE

TIE

SIDR0/1

P01/SOT0

#39 (27H) *

<#37 (25H) *>

#40 (28H) *

<#38 (26H) *>

P00/SIN0

SODR0/1

Clock

selector

Sending clock

Receiving

interrupt signals

Sending

interrupt signals

Receiving

clock Receiving

control

circuit

Sending

control

circuit

Start bit

detection circuit Sending start

circuit

Receiving bit

counter Sending bit

counter

Receiving parity

counter Sending parity

counter Pin

Pins Receiving

shift register Sending

shift register

Rece-

iving

end Sending start

Receiving status

judging circuit EI2OS receiving error

generator circuit (to CPU)

Internal data bus

SMR0/1

*: Interrupt number

Exclusive baud

rate generator

Communication

prescaler

Control register

(CDCR)

MB90420G/425G Series

DS07-13711-5E 51

11. CAN Controller

The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controller

area network) controller is the standard protocol for serial transmissions among automotive controllers and is

widely used in the industry.

(1) CAN controller features

The CAN controller has the following features.

• Conforms to CAN specifications version 2.0 A and B.

Supports sending and receiving in standard frame and expanded frame format.

• Supports data frame sending by means of remote frame receiving.

• 16 sending/receiving message buffers

29-bit ID and 8-byte data

Multi-level message buffer configuration

• Supports full bit compare, full bit mask as well as partial bet mask filtering.

Provides tw o receiving mask registers for either standard frame or expanded frame format.

• Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz)

• CAN WAKE UP function

• The MB90420G series has a two-channel built-in CAN controller . The MB90425G series has a 1-channel built-

in CAN controller.

MB90420G/425G Series

52 DS07-13711-5E

(2) Block diagram

BTR

PSC

RSJ

TOE

NS1,0

NIE

HALT

CSR

RTEC

BVALR

TREQR

TCANR

TRTRR

RFWTR

TCR

TIER

RCR

RIER

RRTRR

ROVRR

AMSR

AMR0

AMR1

LEIR

IDR0 ~ 15,

DLCR0 ~ 15,

DTR0 ~ 15,

RAM

RBF

, TBF

, RDLC, TDLC, IDSEL

RBF

IDSEL

TBF

PH1

FRMER

ACKER

BITER

ARBLOST

STFERRDLC

CRCER

TDLC

TDLC RDLC IDSEL

ARBLOST TX

BITER, STFER,

CRCER, FRMER,

ACKER

SYNC, TSEG1, TSEG2

MC-16LX bus TQ (operating clock)

Machine

clock Prescaler 1-to-64

frequency divider Bit timing generator

Node status change

interrupt generator Node status

change interrupt

Bus

state

machine

IDLE, SUSPND,

TX, RX, ERR,

OVRLD

Error

control Send/receive

sequencer

TBFx

clear Send buffer

decision Data

counter Receiving

filter

control

Error

frame

generator

Overload

frame

generator

Output

driver

Send shift

TBFx, set, clear CRC

generator ACK

generator

Sending completed

interrupt generator

Sending

completed

interrupt

RBFx, set CRC generator

error check

Receiving completed

interrupt generator Receiving

completed

interrupt

RBFx, TBFx, set clear Receiving

shift register Destuffing/

stuffing

error check

RBFx

set Arbitration

check

Bit error

check

Receiving

filter Receiving bufferx

decision Acknowledge error

check

Form error

check Input

latch

RAM address

generator

MB90420G/425G Series

DS07-13711-5E 53

12. LCD Controller/Driver

The LCD controller/driver has a b uilt-in 16 × 8-bit displa y data memory, and controls the LCD display b y means

of f our common outputs and 24 segment outputs. A selection of three duty outputs are av ailab le. This b lock can

drive an LCD (liquid crystal display) panel directly.

(1) LCD controller/driver functions

The LCD controller/driver pro vides functions for directly displa ying the contents of displa y data memory (display

RAM) on the LCD panel by means of segment output and common output.

• LCD drive voltage divider resistance is built-in. External divider resistance can also be connected.

• Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used.

• 16-byte display data memory (display RAM) is built-in.

• The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) .

• Drives the LCD directly.

: Recommended mode

× : Use prohibited

Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they

cannot be used for segment output.

Bias 1/2 duty 1/3 duty 1/4 duty

1/2 bias × ×

1/3 bias ×

MB90420G/425G Series

54 DS07-13711-5E

(2) Block diagram

V0 V1 V2 V3

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

∼

LCDC control register Low

(LCRL) Divider resistance

Time base

timer output Prescaler Timing

controller Common

driver

Internal data bus

AC circuit

Display RAM,

16 × 8 bits

Segment

driver

LCDC control register High

(LCRH)

Controller Driver

MB90420G/425G Series

DS07-13711-5E 55

13. Low voltage/Program Looping Detection Reset Circuit

The Low v oltage detection reset circuit is a function that monitors po wer supply voltage in order to detect when

a voltage drops below a given voltage level. When a low voltage condition is detected, an inter nal reset signal

is generated.

The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal

reset signal if not cleared within a given time after startup.

(1) Low voltage detection reset circuit

When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an

internal reset signal is output.

Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage

condition generates an internal reset and releases stop mode.

During an inter nal RAM write cycle, an internal reset is generated after the completion of writing. During the

output of this internal reset, the reset output from the low voltage detection circuit is suppressed.

(2) Program Looping detection reset circuit

The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts

automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval

elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an

internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has

a width of 5 machine cycles.

* : This value assumes an oscillation clock waveform of 4 MHz.

During recovery from standby mode the detection period is the maximum interval plus 20 µs.

This circuit does not operate in modes where CPU operation is stopped.

The Program Looping detection reset circuit counter is cleared under any of the following conditions.

1. Writing “0” to the LVRC register CL bit

2. Internal reset

3. Main oscillation clock stop

4. Transition to sleep mode

5. Transition to time base timer mode or watch mode

Detection voltage

4.0 V ± 0.3 V

Interval duration

220/FC (Approx. 262 ms *)

MB90420G/425G Series

56 DS07-13711-5E

(3) Block diagram

−

Over flow

Reserved

CL LVRF CPUF

Voltage comparator

circuit

Constant

voltage

source

Program Looping detection circuit

Main oscillation clock

Counter

Internal reset

Clear Noise canceller

Low voltage/CPU operation detection reset control register (LVRC)

Internal data bus

ReservedReservedReserved

Reserved

MB90420G/425G Series

DS07-13711-5E 57

14. Stepping Motor Controller

The stepping motor controller is composed of two PWM pulse generators, four motor driv ers and selector logic

circuits.

The four motor dr ivers have a high output drive capacity and can be directly connected to the four ends of two

motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits

to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse gener-

ators.

•Block diagram

P1 P0

OE1

OE2

PWM1Pn

PWM2Pn

PWM1Mn

PWM2Mn

EN PWM

PWM

BS n : 0 ~ 3

Machine clock

Prescaler

Output enable

PWM1 pulse generator Selector

PWM1 compare register PWM1 selector register

PWM2 pulse generator

Output enable

Selector

Load

PWM2 compare register PWM2 select register

MB90420G/425G Series

58 DS07-13711-5E

15. Sound Generator

The sound generator is composed of a sound control register, frequency data register, amplitude data register,

decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter,

and tone pulse counter.

•Block diagram

S1 S0

TONE OE2

INTE INT ST

1/d

DEC

OE1

PWM

DEC

EN D

EN Q

SGA

SGO

IRQ#34

OE1

OE2

Clock input

Prescaler 8-bit PWM

pulse generator Frequency

counter Toggle

flip-flop

ReloadReload

Amplitude data

Frequency data

Decrement

counter

Decrement grade

Tone pulse

counter

Tone count

MB90420G/425G Series

DS07-13711-5E 59

16. Address Match Detect Function

If the address setting is the same as the address detection register, an INT9 instruction is executed. The

integrated address match detection function can be implemented by processing the INT9 interrupt service

routine.

Two address registers are used, each with its own compare enable bit. When there is a match between the

address register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is forcibly

executed by the CPU.

•Block diagram

Address latch

Compare

Address detection

Enable bit F2MC-16LX

CPU core

F2MC-16LX bus

MB90420G/425G Series

60 DS07-13711-5E

17. ROM Mirror Function Select Module

The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated

to the FF bank to be viewed in the 00 bank.

•Block diagram

ROM

F2MC-16LX bus

ROM mirror function select register

Address area

FF bank 00 bank

MB90420G/425G Series

DS07-13711-5E 61

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.

*2 : AVCC, AVRH and DVCC shall never exceed VCC.

Also, AVRH shall never exceed AVCC.

*3 : The maximum current to/from and input is limited by some means with extenal components, the ICLAMP rating

supersedes the VI rating.

*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.

*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times

“operating factor”. (Continued)

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage*1

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2

AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*2

DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2

Input voltage*1VIVSS − 0.3 VCC + 0.3 V *3

Output voltage*1VOVSS − 0.3 VCC + 0.3 V

Maximum clamp current ICLAMP − 400 + 400 µA*7

Total maximum clamp current Σ | ICLAMP |⎯4mA*7

“L”level maximum

output current*4IOL1 ⎯15 mA Other than P70 to P77, and P80 to P87

IOL2 ⎯40 mA P70 to P77, P80 to P87

“L”level average output

current*5IOLAV1 ⎯4 mA Other than P70 to P77, and P80 to P87

IOLAV2 ⎯30 mA P70 to P77, P80 to P87

“L”level maximum

total output current Σ IOL1 ⎯100 mA Other than P70 to P77, and P80 to P87

Σ IOL2 ⎯330 mA P70 to P77, P80 to P87

“L”level average total

output current Σ IOLAV1 ⎯50 mA Other than P70 to P77, and P80 to P87

Σ IOLAV2 ⎯250 mA P70 to P77, P80 to P87

“H”level maximum

output current IOH1*4⎯− 15 mA Other than P70 to P77, and P80 to P87

IOH2*4⎯− 40 mA P70 to P77, P80 to P87

“H”level average

output current IOHAV1*5⎯− 4 mA Other than P70 to P77, and P80 to P87

IOHAV2*5⎯− 30 mA P70 to P77, P80 to P87

“H”level maximum

total output current Σ IOH1 ⎯− 100 mA Other than P70 to P77, and P80 to P87

Σ IOH2 ⎯− 330 mA P70 to P77, and P80 to P87

“H”level average total

output current Σ IOHAV1*6⎯− 50 mA Other than P70 to P77, and P80 to P87

Σ IOHAV2*6⎯− 250 mA P70 to P77, P80 to P87

Power consumption PD⎯500 mW

Operating temperature TA− 40 + 105 °C

Storage temperature TSTG − 55 + 150 °C

MB90420G/425G Series

62 DS07-13711-5E

(Continued)

*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times

“ operating factor”.

*7 : • Applicable to pins : P00 to P07, P10 to P15, P50 to P57, P70 to P77, P80 to P87

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The + B signal should always be applied with a limiting resistance placed between the + B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the + B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect

other devices.

• Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplete operation may result.

• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the + B input pin open.

• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B

signal input.

• Sample recommended circuits :

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

+ B input (0 V to 16 V)

Limiting

resistance

Protective diode

• Input/Output equivalent circuits

MB90420G/425G Series

DS07-13711-5E 63

2. Recommended Operating Conditions (VSS = DVSS = AVSS = 0.0 V)

* : For smoothing capacitor Cs connections, see the illustration below.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are w arranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Max

Power supply

voltage

VCC

AVCC

DVCC

3.7 5.5 V

(MB90F428GA, MB90F423GA, MB90428GA,

MB90427GA, MB90423GA)

Low voltage detection reset starts to work when power

supply voltage is 4.0 V ± 0.3 V.

3.0 5.5 V (MB90F428GC, MB90F423GC, MB90428GC,

MB90427GC, MB90423GC)

4.3 5.5 V Holding stop operation status

(MB90F428GA, MB90F423GA, MB90428GA,

MB90427GA, MB90423GA)

3.0 5.5 V Holding stop operation status

(MB90F428GC, MB90F423GC, MB90428GC,

MB90427GC, MB90423GC)

Smoothing

capacitor* CS0.1 1.0 µFUse a ceramic capacitor or other capacitor of equivalent

frequency characteristics. A bypass capacitor on the VCC pin

should have a capacitance greater than Cs.

Operating

temperature TA− 40 + 105 °C

CSVSS DVSS AVSS

• C pin connection

MB90420G/425G Series

64 DS07-13711-5E

3. DC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

(Continued)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Typ Max

“H”level

input voltage VIHS ⎯⎯0.8 VCC ⎯VCC + 0.3 VCMOS hysteresis

Automotive level

input pin*1

VIHM ⎯⎯VCC − 0.3 ⎯VCC + 0.3 V MD pin*2

“L”level

input voltage VILS ⎯⎯VSS − 0.3 ⎯0.5 VCC VCMOS hysteresis

Automotive level

input pin*1

VILM ⎯⎯VSS − 0.3 ⎯VSS + 0.3 V MD pin*2

Power supply

current*3

ICC

VCC

Operating frequency

FCP = 16 MHz,

normal operation

⎯45 72 mA MB90F428GA/GC

MB90F423GA/GC

⎯38 61 mA MB90428GA/GC

MB90427GA/GC

MB90423GA/GC

ICCS Operating frequency

FCP = 16 MHz,

sleep mode

⎯15 24 mA MB90F428GA/GC

MB90F423GA/GC

⎯13 21 mA MB90428GA/GC

MB90427GA/GC

MB90423GA/GC

ICTS Operating frequency

FCP = 2 MHz,

time base timer mode ⎯0.75 1.0 mA

ICCL Operating frequency

FCP = 8 kHz, TA = + 25 °C,

subclock operation ⎯0.35 0.7 mA

MB90F428GC

MB90F423GC

MB90428GC

MB90427GC

MB90423GC

ICCLS

Operating frequency

FCP = 8 kHz, TA = + 25 °C,

sub sleep operation ⎯10 30 µA

MB90F428GC

MB90F423GC

MB90428GC

MB90427GC

MB90423GC

ICCT Operating frequency

FCP = 8 kHz, TA = + 25 °C,

watch mode ⎯40 100 µA

MB90F428GC

MB90F423GC

MB90428GC

MB90427GC

MB90423GC

ICCH TA = + 25 °C,

stop mode

⎯520µA

MB90F428GC

MB90F423GC

MB90428GC

MB90427GC

MB90423GC

⎯40 100 µA

MB90F428GA

MB90F423GA

MB90428GA

MB90427GA

MB90423GA

MB90420G/425G Series

DS07-13711-5E 65

(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

(Continued)

Parameter Sym

bol Pin name Conditions Value Unit Remarks

Min Typ Max

Input leakage

current IIL All input pins VCC = DVCC = AVCC = 5.5 V

VSS < VI < VCC − 5 ⎯5µA

Input

capacitance 1 CIN1

Other than

Vcc, Vss,

DVcc, DVss,

Avcc, Avss, C,

P70 to P77,

P80 to P87

⎯⎯515pF

Input

capacitance 2 CIN2 P70 to P77,

P80 to P87 ⎯⎯15 45 pF

Pull-up

resistance RUP RST, MD0,

MD1 ⎯25 50 100 kΩ

Pull-down

resistance RDOWN MD2 ⎯25 50 100 kΩ

Output H

voltage 1 VOH1 Other than

P70 to P77,

P80 to P87

VCC = 4.5 V

IOH = −4.0 mA VCC −

0.5 ⎯⎯V

Output H

voltage 2 VOH2 P70 to P77,

P80 to P87 VCC = 4.5 V

IOH = −30.0 mA VCC −

0.5 ⎯⎯V

Output L

voltage 1 VOL1 Other than

P70 to P77,

P80 to P87

VCC = 4.5 V

IOL = 4.0 mA ⎯⎯0.4 V

Output L

voltage 2 VOL2 P70 to P77,

P80 to P87 VCC = 4.5 V

IOL = 30.0 mA ⎯⎯0.55 V

Large current

output drive

capacity

variation 1

∆VOH2

PWM1Pn,

PWM1Mn,

PWM2Pn,

PWM2Mn,

n = 0 to 3

VCC = 4.5 V

IOH = 30.0 mA

VOH2 maximum variation 0⎯90 mV *4

Large current

output drive

capacity

variation 2

∆VOL2

PWM1Pn,

PWM1Mn,

PWM2Pn,

PWM2Mn,

n = 0 to 3

VCC = 4.5 V

IOH = 30.0 mA

VOL2 maximum variation 0⎯90 mV *4

LCD internal

divider

resistance RLCD V0 to V1,

V1 to V2,

V2 to V3 ⎯50 100 200 kΩ

MB90420G/425G Series

66 DS07-13711-5E

(Continued) (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

*1 : All input pins except X0, X0A, MD0, MD1, MD2 pins.

*2 : MD0, MD1, MD2 pins.

*3 : Supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware

that supply current levels differ depending on whether an external clock or oscillator is used.

*4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simul-

taneously ON. Similarly for other channels.

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Typ Max

COM0 to

COM3

output imped-

ance

RVCOM COMn

(n = 0 to 3) ⎯⎯⎯2.5 kΩ

SEG0 to

SEG3

output imped-

ance

RVSEG SEGn

(n = 00 to 23) ⎯⎯⎯15 kΩ

LCD leakage

current ILCDC

V0 to V3

COMm

(m = 0 to 3)

SEGn

(n = 00 to 23)

⎯− 5.0 ⎯+ 5.0 µA

MB90420G/425G Series

DS07-13711-5E 67

4. AC Characteristics

(1) Clock timing (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

Parameter Symbol Pin name Condi-

tions Value Unit Remarks

Min Typ Max

Base oscillation

clock frequency FCX0, X1

⎯

⎯4⎯MHz

FLC X0A, X1A ⎯32.768 ⎯kHz

Base oscillation

clock cycle time tCYL X0, X1 ⎯250 ⎯ns

tLCYL X0A, X1A ⎯30.5 ⎯µs

Input clock pulse

width PWH, PWL X0 10 ⎯⎯ns Use duty ratio of

40 to 60% as a guideline

PWLH, PWLL X0A ⎯15.2 ⎯µs

Input clock

rise, fall time tcr, tcf X0, X0A ⎯⎯ 5ns

With external

clock signal

Input operating

clock frequency FCP ⎯2⎯16 MHz Using main clock,

PLL clock

FLCP ⎯⎯8.192 ⎯kHz Using sub clock

Input operating

clock cycle time tCP ⎯62.5 — 500 ns Using main clock,

PLL clock

tLCP ⎯⎯122.1 ⎯µs Using sub clock

tcf tcr

0.8 VCC

0.2 VCC

PWL

tCYL

PWH

X0A

tLCYL

tcf tcr

0.8 VCC

0.2 VCC

PWLH PWLL

• X0 clock timing

• X0A clock timing

MB90420G/425G Series

68 DS07-13711-5E

• Range of warranted operation

The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA

enter reset mode at supply voltage below 4 V ± 0.3 V.

• Sample oscillator circuit

Oscillator element

manufacturer Oscillator Frequency C1 C2

Murata Manufacturing Co., Ltd. CSTCR4M00G15 ( ) A-R0 4 MHz 39 [pF] (Typ) 39 [pF] (Typ)

161282

5.5

3.7

3.3

3.0

Relation between internal operating clock frequency and supply voltage

MB90F428GA, MB90F423GA, MB90428GA,

MB90427GA, MB90423GA

range of warranted operation

Supply voltage V

(V)

PLL range of

warranted operation

MB90F428GC, MB90F423GC, MB90428GC,

MB90427GC, MB90423GC

range of warranted operation

Internal clock frequency f

(MHz)

4.5

MB90V420G

range of warranted

operation

Relation between oscillator clock frequency and internal operating clock frequency

Internal operating clock frequency

Main clock PLL clock

Multiplier

× 1 Multiplier

× 2 Multiplier

× 3 Multiplier

× 4

Oscillation clock

frequency 4 MHz 2 MHz ⎯8 MHz 12 MHz 16 MHz

X0 X1

CERALOCK

MB90F428A

MB90420G/425G Series

DS07-13711-5E 69

AC ratings are defined for the following measurement reference voltage values:

0.8 VCC

0.5 VCC

2.4 V

0.8 V

• Input signal waveform

Hysteresis input pin

• Output signal waveform

Output pin

MB90420G/425G Series

70 DS07-13711-5E

(2) Reset input (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several

hundred ms; f or a FAR/ceramic oscillator , this is several hundred ms to a f e w ms , and for an external clock this

is 100 µs.

Note : tCP : See “ (1) Clock input timing”.

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Reset input time tRSTL RST ⎯

16 tCP ⎯ns In normal operation

Oscillator oscillation

time* + 16 tCP ⎯ms

In stop mode,

sub clock mode,

sub sleep mode,

watch mode

RST

0.5 VCC

tRSTL

0.5 VCC

• Under normal operation

RST

16 tcp

RSTL

0.5 Vcc 0.5 Vcc

Internal

operation

clock

Internal

reset

90 % of

amplitude

Oscillator

oscillation time

Oscillator stabilization wait time

Execution of the instruction

• In stop mode, sub clock mode , sub sleep mode, watch mode

MB90420G/425G Series

DS07-13711-5E 71

(3) Power-on reset, power on conditions (VSS = 0.0 V, TA = 40 °C to + 105 °C)

Parameter Symbol Pin

name Conditions Value Unit Remarks

Min Max

Power supply rise time tR

VCC ⎯

0.05 30 ms

Power supply start voltage VOFF ⎯0.2 V

Power supply attained voltage VON 2.7 ⎯V

Power supply cutoff time tOFF 50 ⎯ms For repeat operation

0 V

5.0 V

tOFF

2.7 V

0.2 V 0.2 V0.2 V

Extreme variations in voltage supply may activate a power-on reset.

As the illustration below shows, when varying supply voltage during operation the use of a smooth

voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the

device should not be used, however it is permissible to use the PLL clock during a voltage drop of

1V/s or less.

3.0 V

RAM data hold

A rise slope of 50 mV or

less is recommended

MB90420G/425G Series

72 DS07-13711-5E

(4) UART0, UART1 timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

Notes : • AC ratings are for CLK synchronous mode.

• CL is load capacitance connected to pin during testing.

• tCP : See “ (1) Clock timing”.

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0, SCK1

⎯

8 tCP ⎯ns Internal shift

clock mode

output pin CL =

80 pF + 1•TTL

SCK fall to SOT delay time tSLOV SCK0, SCK1

SOT0, SOT1 − 80 80 ns

Valid SIN to SCK rise tIVSH SCK0, SCK1

SIN0, SIN1 100 ⎯ns

SCK rise to valid SIN hold time tSHIX 60 ⎯ns

Serial clock “H” pulse width tSHSL SCK0, SCK1

⎯

4 tCP ⎯ns

External shift

clock mode

output pin CL =

80 pF + 1•TTL

Serial clock “L” pulse width tSLSH 4 tCP ⎯ns

SCK fall to SOT delay time tSLOV SCK0, SCK1

SOT0, SOT1 ⎯150 ns

Valid SIN to SCK rise tIVSH SCK0, SCK1

SIN0, SIN1 60 ⎯ns

SCK rise to valid SIN hold time tSHIX 60 ⎯ns

• Internal shift clock mode

• External shift clock mode

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH tSHIX

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.5 VCC

0.8 VCC

0.5 VCC

SCK

SOT

SIN

tSLSH tSHSL

tSLOV

tIVSH tSHIX

0.5 VCC 0.5 VCC

0.8 VCC 0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.5 VCC

0.8 VCC

0.5 VCC

MB90420G/425G Series

DS07-13711-5E 73

(5) Timer input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

Note : tCP : See “ (1) Clock timing”.

(6) Trigger input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

Note : tCP : See “ (1) Clock timing”.

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse width tTIWH

tTIWL

TIN0, TIN1,

IN0, IN1,

IN2, IN3, ⎯4 tCP ⎯ns

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Input pulse width tTRGH,

tTRGL INT0 to INT7 ⎯5 tCP ⎯ns Under normal operation

1⎯µs In stop mode

TIN0 ∼ TIN1

IN0 ∼ IN3

0.8 V

0.5 V

TIWH

TIWL

• Timer input timing

INT0 ∼ INT7

0.8 V

0.5 V

TRGH

TRGL

• Trigger input timing

MB90420G/425G Series

74 DS07-13711-5E

(7) Low voltage detection (VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Typ Max

Detection voltage VDL VCC ⎯3.7 4.0 4.3 V During voltage

drop

Hysteresis width VHYS VCC ⎯0.1 ⎯⎯VDuring voltage

rise

Power supply voltage

fluctuation ratio dV/dt VCC ⎯− 0.1 ⎯0.02 V/µs

Detection delay time td⎯⎯⎯⎯35 µs

VHYS

VDL

VCC

Inter nal reset

MB90420G/425G Series

DS07-13711-5E 75

5. A/D Conversion Block

(1) Electrical Characteristics (VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)

*1 : At FCP = 16 MHz, tSMP = 32 × tCP = 2.000 (µs) .

*2 : At FCP = 16 MHz, tCMP = 66 × tCP = 4.125 (µs) .

*3 : Equiv alent to con v ersion time per channel at FCP = 16 MHz, and selection of tSMP = 32 × tCP and tCMP = 66 × tCP.

*4 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in

stop mode.

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Resolution ⎯⎯ ⎯ ⎯10 bit

Total error ⎯⎯ ⎯ ⎯±5.0 LSB

Non-linear error ⎯⎯ ⎯ ⎯±2.5 LSB

Differential linear error ⎯⎯ ⎯ ⎯±1.9 LSB

Zero transition voltage VOT AN0 to AN7 AVSS

− 3.5 LSB AVSS

+ 0.5 LSB AVSS

+ 4.5 LSB V1 LSB =

(AVRH − AVSS)

/ 1024

Full scale transition

voltage VFST AN0 to AN7 AVRH

− 6.5 LSB AVRH

− 1.5 LSB AVRH

+ 1.5 LSB V

Sampling time tSMP ⎯2.000 ⎯⎯µs*1

Compare time tCMP ⎯4.125 ⎯⎯µs*2

A/D conversion time tCNV ⎯6.125 ⎯⎯µs*3

Analog port

input current IAIN AN0 to AN7 ⎯⎯10 µAVAVSS = VAIN = VAVCC

Analog input current VAIN AN0 to AN7 0 ⎯AVRH V

Reference voltage AVR+AVRH 3.0 ⎯AVCC V

Power supply current IAAVCC ⎯2.3 6.0 mA

IAH ⎯⎯ 5µA*4

Reference voltage feed

current IRAVRH 50 180 260 µAVAVRH = 5.0 V

IRH AVRH ⎯⎯ 5µA*4

Inter-channel variation — AN0 to AN7 ⎯⎯ 4LSB

MB90420G/425G Series

76 DS07-13711-5E

• Notes of the external impedance of the analog input and its sampling time

•A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion presicion.

•To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

•If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

•About errors

As |AVRH| becomes smaller, values of relative errors grow larger.

Analog input Comparator

• Analog input circuit model

During sampling : ON

Note : The values are reference values.

MB90420GA/420GC

MB90F420GA/F420GC

MB90V420G

2.4 kΩ (Max)

2.6 kΩ (Max)

3.2 kΩ (Max)

36.4 pF (Max)

28.0 pF (Max)

30.0 pF (Max)

100

00 5 10 15 20 25 30 35

MB90420GA/

420GC

MB90F420GA/

F420GC

MB90V420G 20

00123456 87

MB90V420G

MB90420GA/

420GC

MB90F420GA/

F420GC

(External impedance = 0 kΩ to 100 kΩ)

External impedance [kΩ]

Minimum sampling time [µs]

(External impedance = 0 kΩ to 20 kΩ)

External impedance [kΩ]

Minimum sampling time [µs]

• The relationship between the external impedance and minimum sampling time

MB90420G/425G Series

DS07-13711-5E 77

(2) Definition of terms

• Resolution

Indicates the ability of the A/D converter to discriminate in analog conversion.

10-bit resolution indicates that analog voltage can be resolved into 210 = 1024 levels.

• Total error

Expresses the difference between actual and logical values. It is the total value of errors that can come from

offset error, gain error, non-linearity error and noise.

• Linearity error

Expresses the de viation between actual con version char acteristics and a straight line connecting the device’s

zero tr ansition point (00 0000 0000 ←→ 00 0000 0001) and full scale transition point (11 1111 1110 ←→ 11

1111 1111) .

• Differential linearity error

Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code.

11 1111 1111

11 1111 1110

11 1111 1101

11 1111 1100

00 0000 0011

00 0000 0010

00 0000 0001

00 0000 0000

1 LSB × N + VOT

VOT VNT VFSTV(N + 1)T

Digital output

Linearity error

Analog input

1 LSB =

Linearity error =

Differential linearity error =

VFST − VOT

1022

[LSB]

VNT − (1 LSB × N + VOT)

1 LSB

V (N + 1) T − VNT − 1

• 10-bit A/D converter conversion characteristics

MB90420G/425G Series

78 DS07-13711-5E

6. Flash Memory Program and Erase Performances

* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C)

Parameter Conditions Value Unit Remarks

Min Typ Max

Sector erase time

TA = + 25 °C

VCC = 5.0 V

⎯1 15 s Excludes 00H programming prior erasure

Chip erase time ⎯5⎯s Excludes 00H programming prior erasure

Word (16 bit width)

programming time ⎯16 3,600 µs Excludes system-level overhead

Erase/Program cycle ⎯10,000 ⎯⎯cycle

Flash data

retention time Average

TA = + 85 °C10 ⎯⎯year *

MB90420G/425G Series

DS07-13711-5E 79

■EXAMPLE CHARACTERISTICS

03.5 4.5 5.5

VCC (V)

ICC (mA)

6.5

FC = 16 MHz

FC = 11 MHz

FC = 8 MHz

FC = 5 MHz

FC = 4 MHz

FC = 2 MHz

900

800

700

600

500

400

300

200

100

03.5 4.5 5.5 6.5

VCC (V)

ICTS (µA)

FC = 16 MHz

FC = 11 MHz

FC = 8 MHz

FC = 5 MHz

FC = 4 MHz

FC = 2 MHz

ICC − VCC (TA = + 25 °C)

ICTS − VCC (TA = + 25 °C)

500

400

300

200

100

03.5 4.5 5.5 6.5

VCC (V)

ICCL (µA)

TA = +125 °C

TA = −40 °C

TA = +25 °C

ICCL − VCC (FC = 8 kHz)

MB90420G/425G Series

80 DS07-13711-5E

(Continued)

03.5 4.5 5.5 6.5

VCC (V)

ICCLS (µA)

TA = +25 °C

TA = −40 °C

TA = +125 °C

03.5 4.5 5.5 6.5

VCC (V)

ICCT (µA)

TA = +25 °C

TA = −40 °C

TA = +125 °C

ICCLS − VCC (FC = 8 kHz)

ICCT − VCC (FC = 8 kHz)

MB90420G/425G Series

DS07-13711-5E 81

■ORDERING INFORMATION

Part number Package Remarks

MB90F423GAPF

MB90F423GCPF

MB90F428GAPF

MB90F428GCPF

MB90423GAPF

MB90423GCPF

MB90427GAPF

MB90427GCPF

MB90428GAPF

MB90428GCPF

Plastic QFP, 100-pin

(FPT-100P-M06)

MB90F423GAPMC

MB90F423GCPMC

MB90F428GAPMC

MB90F428GCPMC

MB90423GAPMC

MB90423GCPMC

MB90427GAPMC

MB90427GCPMC

MB90428GAPMC

MB90428GCPMC

Plastic LQFP, 100-pin

(FPT-100P-M20)

MB90420G/425G Series

82 DS07-13711-5E

■PACKAGE DIMENSIONS

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

100-pin plastic QFP Lead pitch 0.65 mm

Package width ×

package length 14.00 × 20.00 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

3.35 mm MAX

Code

(Reference) P-QFP100-14×20-0.65

100-pin plastic QFP

(FPT-100P-M06)

(

FPT-100P-M06

)

2002 FUJITSU LIMITED F100008S-c-5-5

130

5180

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20

(.551±.008)

17.90±0.40

(.705±.016)

INDEX

0.65(.026) 0.32±0.05

(.013±.002) M

0.13(.005)

"A"

0.17±0.06

(.007±.002)

0.10(.004)

Details of "A" part

(.035±.006)

0.88±0.15

(.031±.008)

0.80±0.20

0.25(.010)

3.00 +0.35

–0.20

+.014

–.008

.118

(Mounting height)

0.25±0.20

(.010±.008)

(Stand off)

0~8˚

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB90420G/425G Series

DS07-13711-5E 83

(Continued)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

100-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 14.0 mm × 14.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm Max

Weight 0.65 g

Code

(Reference) P-LFQFP100-14×14-0.50

100-pin plastic LQFP

(FPT-100P-M20)

2005 FUJITSU LIMITED F100031S-c-2-1

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

125

76 50

100

0.50(.020) 0.20±0.05

(.008±.002) M

0.08(.003)0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX .059 –.004

+.008

–0.10

+0.20

1.50

(Mounting height)

0˚~8˚

(0.50(.020))

(.024±.006)

0.60±0.15 0.25(.010)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB90420G/425G Series

84 DS07-13711-5E

■MAIN CHANGES IN THIS EDITION

The vertical lines marked in the left side of the page show the changes.

Page Section Change Results

The package code is changed.

(FPT-100P-M05 → FPT-100P-M20)

5■ PIN ASSIGNMENTS Figure of QFP package pin assignment is changed.

81 ■ ORDERING INFORMATION

Order informations are changed.

(MB90423GAPFV → MB90423GAPMC,

MB90423GCPFV → MB90423GCPMC,

MB90427GAPFV → MB90427GAPMC,

MB90427GCPFV → MB90427GCPMC,

MB90428GAPFV → MB90428GAPMC,

MB90428GCPFV → MB90428GCPMC,

MB90F423GAPFV→ MB90F423GAPMC,

MB90F423GCPFV→ MB90F423GCPMC,

MB90F428GAPFV→ MB90F428GAPMC,

MB90F428GCPFV→ MB90F428GCPMC)

83 ■ PACKAGE DIMENSIONS The package figure is changed.

(FPT-100P-M05 → FPT-100P-M20)

MB90420G/425G Series

DS07-13711-5E 85

MEMO

MB90420G/425G Series

86 DS07-13711-5E

MEMO

MB90420G/425G Series

DS07-13711-5E 87

MEMO

MB90420G/425G Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

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FUJITSU MICROELECTRONICS AMERICA, INC.

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Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

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Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

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Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

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Singapore 556741

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

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Rm.3102, Bund Center, No.222 Yan An Road(E),

Shanghai 200002, China

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

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10/F., World Commerce Centre, 11 Canton Road

Tsimshatsui, Kowloon

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

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of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use b ased on su ch information. When you develop equipment incorporat-

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