ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 1/46
Revision History
Revision 1.0 (Feb. 13, 2008)
-Original
Revision 1.1 (Mar. 11, 2008)
-Modify ICC spec
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 2/46
SDRAM 512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
y 3.3V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
y EMRS cycle with address
y All inputs are sampled at the positive going edge of the
system clock
y Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
ORDERING INFORMATION
PRODUCT NO. MAX
FREQ. PACKAGE Comments
M52L64322A-6BG 166MHz 90 Ball FBGA Pb-free
M52L64322A-7BG 143MHz 90 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M52L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32
bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
90 Ball FBGA
1 2 3 4 5 6 7 8 9
A DQ26 DQ24 VSS VDD DQ23 DQ21
B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E VDDQ DQ31 NC NC DQ16 VSSQ
F VSS DQM3 A3 A2 DQM2 VDD
G A4 A5 A6 A10 A0 A1
H A7 A8 NC NC BA1 NC
J CLK CKE A9 BA0 CS RAS
K DQM1 NC NC CAS WE DQM0
L VDDQ DQ8 VSS VDD DQ7 VSSQ
M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 VSS VDD DQ0 DQ2
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 3/46
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
CS Chip Select Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0~3.
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A10 Address Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
BA0 , BA1 Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
DQM0~3 Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ DQ31 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC No Connection This pin is recommended to be left No Connection on the device.
DQM 0~3
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decoder
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Output
Buffer
Address
Clock
Generator
CLK
CKE
Command Decoder
CS
RAS
CAS
WE
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 4/46
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT
Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 CΒ°
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 CΒ°)
PARAMETER SYMBOL MIN TYP MAX UNIT NOTE
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 - VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current IIL -10 - 10 ΞΌA 3
Output leakage current IOL -10 - 10 ΞΌA 4
Note: 1. VIH(max) = 4.6V AC for pulse width ≀ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≀ 10ns acceptable.
3. Any input 0V ≀ VIN
≀
VDDQ+0.3, all other pins are not under test = 0V.
4. Dout is disabled , 0V ≀ VOUT ≀ VDDQ.
CAPACITANCE (VDD = 3.3V, TA = 25 CΒ°, f = 1MHZ)
PARAMETER SYMBOL MIN MAX UNIT
Input capacitance (A0 ~ A10, BA0 ~ BA1) CIN1 - 4 pF
Input capacitance
(CLK, CKE, CS , RAS , CAS , WE & DQM)
CIN2 - 4 pF
Data input/output capacitance (DQ0 ~ DQ31) COUT - 6 pF
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 5/46
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 C°
Version
Parameter Symbol Test Condition CAS
Latency -6 -7 Unit Note
Operating Current
(One Bank Active) ICC1 Burst Length = 1
tRC β‰₯ tRC (min), tCC β‰₯ tCC (min), IOL= 0mA 100 100 mA 1
ICC2P CKE ≀VIL(max), tCC =15ns 1 mA
Precharge Standby
Current in power-down
mode ICC2PS CKE ≀VIL(max), CLK
≀
VIL(max), tCC =
∞
0.5 mA
ICC2N CKE β‰₯VIH(min), CS β‰₯VIH(min), tCC =10ns
Input signals are changed one time during 20ns
20 mA
Precharge Standby
Current in non
power-down mode
ICC2NS
CKE β‰₯VIH(min), CLK
≀
VIL(max), tCC =
∞
Input signals are stable 6 mA
ICC3P CKE ≀VIL(max), tCC =15ns 6
Active Standby Current
in power-down mode ICC3PS CKE ≀ VIL(max), CLK
≀
VIL(max), tCC =
∞
6
mA
ICC3N CKE β‰₯VIH(min), CS β‰₯ VIH(min), tCC=15ns
Input signals are changed one time during 2clks
All other pins β‰₯ V
DD-0.2V or ≀ 0.2V
30 mA
Active Standby Current
in non power-down
mode
(One Bank Active)
ICC3NS CKE β‰₯VIH (min), CLK
≀
VIL(max), tCC=
∞
Input signals are stable 25 mA
Operating Current
(Burst Mode) ICC4
IOL= 0mA, Page Burst
All Band Activated, tCCD = tCCD (min) 200 180
mA 1
Refresh Current ICC5 tRC β‰₯tRC(min) 200 180
mA 2
TCSR range 70 CΒ°
4 Banks 420
2 Bank 380
1 Bank 350
Self Refresh Current I
CC6
CKE ≀0.2V
1/2 Bank 320
uA
Deep Power Down
Current ICC7 CKE ≀0.2V 200 uA
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 6/46
AC OPERATING TEST CONDITIONS (VDD=3.3V Β±0.3V,TA= 0 CΒ° ~ 70CΒ°)
Parameter Value Unit
Input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig.2
OPERATING AC P A RAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter Symbol -6 -7 Unit Note
Row active to row active delay tRRD(min) 12 14 ns 1
RAS to CAS delay tRCD(min) 18 21 ns 1
Row precharge time tRP(min) 18 21 ns 1
tRAS(min) 40 42 ns 1
Row active time
tRAS(max) 100 us -
@Operating tRC(min) 58 63 ns 1
Row cycle time
@Auto refresh tRFC(min) 60 70 ns 1 , 5
Last data in to new col. Address delay tCDL(min) 1 CLK 2
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. Address to col. Address delay tCCD(min) 1 CLK 3
Mode Register command to Active or Refresh Command tMRD(min) 2 CLK -
CAS latency=3 2
Number of valid output data
CAS latency=2 1
ea 4
Refresh period(4K cycle) tREF(max) 64 ms 6
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM,and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6ΞΌs.)
Output
870
VOH (DC) =2.4V , IOH = -2 mA
VOL (DC) =0.4V , IOL = 2 mA Output
50pF
Z0 =50
50pF
50
Vtt = 1.4V
3.3V
1200Ω
Ω
Ω
Ω
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 7/46
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-6 -7
Parameter Symbol Min Max Min Max Unit Note
CAS Latency =3 6 7
1000 CAS Latency =2 TCC 10 1000 10 1000 ns 1
CAS Latency =3 5.5 6
CLK to valid
output delay CAS Latency =2 TSAC 6 6
ns 1
Output data hold time tOH 2.5 2.5 ns 2
CLK high pulse width tCH 2.5 2.5 ns 3
CLK low pulse width tCL 2.5 2.5 ns 3
Input setup time tSS 1.5 1.5 ns 3
Input hold time tSH 1 1 ns 3
CLK to output in Low-Z tSLZ 0 0 ns 2
CAS Latency =3 5.5 6 CLK to output in
Hi-Z CAS Latency =2 tSHZ 6 6
ns -
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 8/46
SIMPLIFIED TRUTH TABLE
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0
BA1 A10/AP A9~A0 Note
Mode Register set
Register Extended Mode Register
set
H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry H L L L L H X X 3
L H H H X 3
Refresh Self
Refresh
Exit L H H X X X X X 3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column Address Auto Precharge Enable
H X L H L H X V
H
Column
Address
(A0~A7) 4,5
Auto Precharge Disable L 4
Write &
Column Address Auto Precharge Enable
H X L H L L X V
H
Column
Address
(A0~A7) 4,5
Burst Stop H X L H H L X X 6
Bank Selection V L
Precharge
All Banks
H X L L H L X
X H
X
H X X X
Entry H L
L V V V
X
Clock Suspend or
Active Power Down
Exit L H
X X X X X
X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power Down Mode
Exit L H
L V V V
X
X
DQM H X V X 7
H X X X
No Operating Command H X L H H H X X
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note : 1.OP Code : Operating Code
A0~A10 & BA0~BA1 : Program keys. (@ MRS). BA1=0 for MRS and BA1=1 for EMRS
2.MRS/EMRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS/EMRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by β€œAuto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are β€œLow” at read ,write , row active and precharge ,bank A is selected.
If both BA0 is β€œLow” and BA1 is β€œHigh” at read ,write , row active and precharge ,bank B is selected.
If both BA0 is β€œHigh” and BA1 is β€œLow” at read ,write , row active and precharge ,bank C is selected.
If both BA0 and BA1 are β€œHigh” at read ,write , row active and precharge ,bank D is selected
If A10/AP is β€œHigh” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 9/46
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address BA0 BA1 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function 0 0 0 0 0 0 CAS Latency BT Burst Length
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1
0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 Reserved 0 1 0 2 0 1 0 4 4
1 1 Reserved 0 1 1 3
0 1 1 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved
1 1 1 Full Page Reserved
Full Page Length : 256
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 10/46
BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1 0 0 0 0 0 DS TCSR PASR Extended Mode Register Set
A2-A0 Self Refresh Coverage
000 4Bank
001 2 Bank (BankA& BankB) or
(BA1=0)
010 1 Bank (BankA) or
(BA0=BA1=0)
011 R
100 R
101 1/2 Bank (BankA) or
A10=BA0=BA1=0
PASR
111 R
A6-A5 Driver Strength
00 Full Strength
01 1/2 Strength
10 1/4 Strength
DS
11 R
Remark R : Reserved
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores for selecting PASR;TCSR;DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS,RAS,CAS,WE and high on
BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more
register). The state of address pins
A0~An in the same cycle as CS,RAS,CAS,WE going low is written in the extended mode register. Refer to the table for specific
codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as long
as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks
refreshed.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 11/46
BURST SEQUENCE (BURST LENGTH = 4)
Initial Adrress
A1 A0 Sequential Interleave
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial
A2 A1 A0 Sequential Interleave
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 12/46
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of setup and hold time around positive edge
of the clock for proper functionality and Icc specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least β€œ1CLK + tSS” before the high going edge of the clock,
then the SDRAM becomes active from the same clock edge
accepting all the input commands.
BANK A DDRESSES (BA0~BA1)
This SDRAM is organized as four independent banks of
524,288 words x 32 bits memory arrays. The BA0~BA1
inputs are latched at the time of assertion of RAS and
CAS to select the bank to be used for the operation. The
banks addressed BA0~BA1 are latched at bank active, read,
write, mode register set and precharge operations.
ADDRESS INPUTS (A0~A10)
The 19 address bits are required to decode the 524,288
word locations are multiplexed into 12 address input pins
(A0~A10). The 12 row addresses are latched along with
RAS and BA0~BA1 during bank active command. The 8 bit
column addresses are latched along with CAS , WE and
BA0~BA1 during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high, The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock cycle like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting CS high. CS high disables
the command decoder so that RAS , CAS , WE and all
the address inputs are ignored.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and WE (The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A10
and BA0~BA1 in the same cycle as CS , RAS , CAS
and WE going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all banks
are in the idle state. The mode register is divided into
various fields into depending on functionality. The burst
length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
test mode use A7~A8, vendor specific options use A9,
A10 and BA1~BA0. A7~A8, A10/AP and BA0~BA1 must
be set to low for normal SDRAM operation. Refer to the
table for specific codes for various burst length, burst
type and CAS latencies.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 13/46
DEVICE OPERATIONS (Continued)
BANK ACTIVATE
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank address, a row access is initiated. The
read or write operation can occur after a time delay of tRCD
(min) from the time of bank activation. tRCD is the internal
timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock
cycles required between bank activate and read or write
command should be calculated by dividing tRCD (min) with
cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in
the same chip and shares part of the internal circuitry to
reduce chip area, therefore it restricts the activation of four
banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. tRRD (min) specifies the minimum time required
between activating different bank. The number of clock
cycles required between different bank activation must be
calculated similar to tRCD specification. The minimum time
required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
tRAS (min). Every SDRAM bank activate command must satisfy
tRAS (min) specification before a precharge command to that
active bank can be asserted. The maximum time any bank
can be in the active state is determined by tRAS (max) and tRAS
(max) can be calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
CS and RAS with WE being high on the positive edge
of the clock. The bank must be active for at least tRCD (min)
before the burst read command is issued. The first output
appears in CAS latency number of clock cycles after the
issue of burst read command. The burst length, burst
sequence and latency from the burst read command is
determined by the mode register which is already
programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the
initial address does not start from a boundary such that
number of outputs from each I/O are equal to the burst
length programmed in the mode register. The output goes
into high-impedance at the end of burst, unless a new burst
read was initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive
clock cycles in adjacent addresses depending on burst
length
and burst sequence. By asserting low on CS , CAS
and WE with valid column address, a write burst is
initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be
completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst
write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst
can also be terminated by using DQM for blocking data
and procreating the bank tRDL after the last data input to
be written into the active row. See DQM OPERATION
also.
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM
signal is important during burst interrupts of write with
read or precharge in the SDRAM. Due to asynchronous
nature of the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when the
complete burst write is required. Please refer to DQM
timing diagram also.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank
activate and CS , RAS , WE and A10/AP with valid
BA0~BA1 of the bank to be procharged. The precharge
command can be asserted anytime after tRAS (min) is
satisfy from the bank active command in the desired
bank. tRP is defined as the minimum number of clock
cycles required to complete row precharge is calculated
by dividing tRP with clock cycle time and rounding up to
the next higher integer. Care should be taken to make
sure that burst write is completed or DQM is used to
inhibit writing before precharge command is asserted.
The maximum time any bank can be active is specified
by tRAS (max). Therefore, each bank activate command. At
the end of precharge, the bank enters the idle state and
is ready to be activated again. Entry to power-down,
Auto refresh, Self refresh and Mode register set etc. is
possible only when all banks are in idle state.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 14/46
DEVICE OPERATIONS (Continued)
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS (min) and β€œtRP” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
ALL BANKS PRECHARGE
All banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS , and
WE with high on A10/AP after all banks have satisfied tRAS
(min) requirement, performs precharge on all banks. At the
end of tRP after performing precharge all, all banks are in idle
state.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
and WE . The auto refresh command can only be asserted
with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by tRFC (min). The minimum number of clock cycles
required can be calculated by driving tRFC with clock cycle
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered
from all banks idle state by asserting low on CS ,
RAS , CAS and CKE with high on WE . Once the self
refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of tRFC before the SDRAM
reaches idle state to begin normal operation.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 15/46
COMMANDS
Mode register set command
(CS ,RAS ,CAS ,WE , BA1, BA0 = Low)
The device has a mode register that defines how the device operates. In this
command, A0 through BA0 are the data input pins. After power on, the mode register
set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state. During 2CLK
(tMRD) following this command, the device cannot accept any other commands.
Extended Mode register set command
( CS , RAS , CAS , WE , BA0 = Low ; BA1= High)
The device has a extended mode register that defines how to set PASR, TCSR,
DS.
Activate command
(CS , RAS = Low, CAS , WE = High)
The device has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A10.
This command corresponds to a conventional DRAM’s RAS falling.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 16/46
Precharge command
(CS , RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the device can’t accept the activate command to the
precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
Write command
( CS , CAS , WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
(CS , CAS = Low, RAS , WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 17/46
CBR (auto) refresh command
(CS , RAS , CAS = Low, WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh address is
generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a row
activate command.
During tRC period (from refresh command to refresh or activate command), the device
cannot accept any other command.
Self refresh entry command
(CS , RAS , CAS , CKE = Low , WE = High)
After the command execution, self refresh operation continues while CKE remains low.
When CKE goes to high, the device exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed internally,
so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
(CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 18/46
No operation
( CS = Low , RAS , CAS , WE = High)
This command is not a execution command. No operations begin or terminate by this
command.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 19/46
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
2. DQM Operation
*Note :1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
CLK
CMD
DQM
DQ(CL2)
DQ(CL3)
RD
Q0 Q2 Q3
Q1 Q2 Q3D0 D1 D3
D1 D3
D0
WR
Mask ed b y DQM
Mas ke d b y DQM
CLK
CMD
DQM
DQ(CL2)
DQ(CL3)
CKE
RD
Q0 Q2 Q4
Hi-Z Hi-Z Hi-Z
Q6 Q7 Q8
Q5 Q6 Q7
Q1 Q3
Hi-Z Hi-Z Hi-Z
Hi-Z
Hi-Z
1)Write Mask (BL=4) 2)Read Mask (BL=4)
DQM to Data-in Mask=0 DQM to Data-out Mask=2
3)DQM with clcok suspended (Full Page Read)
*Note2
Internal
CLK
Q9
Q8
CLK
CMD
CK E
Internal
CLK
DQ (C L2)
DQ (C L3)
RD
Q2Q0 Q1 Q3
Q0 Q1 Q3D0 D1 D2 D3
D1 D2 D3
D0
WR
Masked by CKE
1) Cl ock Su sp end ed D urin g W ri
t
e(B
L
=4) 2 ) C lo c k Su spe nd ed D uri ng R ead ( BL =4 )
Not Written Suspended Dout
Q2
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 20/46
3. CAS Interrupt (I)
*Note : 1. By β€œinterrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
CLK
CMD
ADD
DQ(CL2)
DQ(CL3)
RD
QB0 QB2
QA0
CLK
CMD
ADD
DQ
WR
DA 0 DB0 DB 1
RD
AB
QB1 QB3
QB0 QB2
QA0 QB3
QB1
tCCD
*Note 2
WR
tCCD *Note 2
AB
tCD L
*Note 3
WR RD
tCC D * No t e 2
AB
DA0 DB0 DB1
tCD L
*Note 3
DA0 DB 0 DB1
DQ (C L3 )
DQ(CL2)
1) Re ad i nte rr upt ed b y R ea d (BL= 4)
2)W rite inte rrup ted by W r it e ( BL= 2) 3)Writ e i nte rr upte d b y Rea d ( BL= 2)
*N
o
t
e1
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 21/46
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
CLK
i)CMD
DQM
DQ D1 D3
D0 D2
WR
ii)CMD
DQM
DQ
iii)CMD
DQM
DQ
iv)CMD
DQM
DQ
D1 D3
D0 D2
RD WR
RD WR
D1 D3
D0 D2
D1 D3
D0 D2
RD WR
Hi-Z
Q0
*Note1
Hi-Z
Hi-Z
Hi-Z
(a)CL=2,BL=4
RD
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 22/46
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
CLK
CMD
DQM
DQ D0 D1 D2
WR
*Note3
*Note2
Mask ed b
y
DQM
D3
CLK
i)CMD
ii)CMD
iii)CMD
iv)CMD
DQM
DQM
DQM
DQM
DQ
DQ
DQ
DQ
D1 D3
D1
D0 D2
D3
D0 D2
WR
(b)CL=3,BL=4
RD WR
RD WR
D1 D3
D0 D2
D1 D3
D0 D2
RD WR
Hi-Z
D1 D3
D0 D2
Q0
*Note1
v)CMD
DQM
DQ
RD WR
Hi-Z
RD
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 23/46
6. Precharge
.
7. Auto Precharge
*Note : 1. tRDL : Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
CLK
CMD
DQ D0 D1 D2 D3
WR
tRDL
*Note1
CLK
CMD
CMD
DQ(CL2) Q0 Q1 Q2 Q3
RD PRE
DQ(CL3) Q0 Q1 Q2 Q3
PRE
1)No
r
mal W
r
ite (BL=4) 2)Normal Read (BL=4)
CL=2
PRE CL=3
*Note2
*Note2
CLK
CMD
DQ D0 D1 D2 D3
WR
CLK
CMD
DQ(CL2) D0 D1 D2 D3
RD
DQ(CL3)
*Note3
Auto Precharge starts
D0 D1 D2 D3
*Note3
Auto Precharge starts
1
)
No
mal W
ite
(
BL=4
)
2
)
No
mal Read
(
BL=4
)
tRDL (min)
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 24/46
8. Burst Stop & Interrupted by Precharge
9. MRS
*Note: 1. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
3. Write burst is terminated. tRDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.
6. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
CLK
CMD
DQ (C L2 )
DQ(CL3)
CLK
CMD
DQM
DQ D0 D1 D2 D3
WR STOP
*N ote1
Q0 Q1
Q0 Q1
RD STOP
*Note2
1)W ri
t
eBurs
t
S
t
o
p
(BL=8)
2)Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
CLK
CMD
DQ M
DQ D0 D1 Mask Mask
WR
Q0 Q1
RD PRE
1)W ri
t
ein
t
erru
p
t
ed
b
y
p
recharge (BL=4)
2)Read interrupted by precharge (BL=4)
*Note2
PRE
*Note4
*Note3
DQ(CL3)
*N ote5
Q2
Q1 Q2 Q3
Q0
tRDL
tBDL
D4 D5
Q3
CLK
CMD PRE
*N o t e6
MRS ACT
tRP 2CLK
1)M
o
de Regis
t
er Se
t
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 25/46
10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
*Note : 1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
CLK
CKE
Internal
CLK
CMD RD
tSS
*Note1
CLK
CKE
Internal
CLK
CMD ACT
tSS
*Note2
NOP
1)Clock Suspen d(=
A
ctive Powe
r
Down)Exit 2)Powe
r
Down (=P
r
echa
r
ge Powe
r
Down )
CLK
CMD PRE AR
CKE
CMD
tRP tRFC
*Note5
*N ote4
CLK
CMD PRE SR
CKE
CMD
tRP tRFC
*N ote4
1)Auto Refresh & Self Refre sh
2)Self Refresh
*N
o
t
e
3
*Note6
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 26/46
12. About Burst Type Control
Sequential Counting
At MRS A3 = β€œ0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Basic
MODE
Interleave Counting At MRS A3 = β€œ1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Random
MODE
Random Column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
1 At MRS A210 = β€œ000”
At auto precharge . tRAS should not be violated.
2 At MRS A210 = β€œ001”
At auto precharge . tRAS should not be violated.
4 At MRS A210 = β€œ010”
8 At MRS A210 = β€œ011”
Basic
MODE
Full Page At MRS A210 = β€œ111”
At the end of the burst length , burst is warp-around.
Random
MODE Burst Stop t
BDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
RAS Interrupt
(Interrupted by
Precharge)
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
t
RDL = 2clk with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 27/46
FUNCTION TURTH TABLE (TABLE 1)
Current
State CS RAS CAS WE BA ADDR ACTION Note
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
IDLE L H L X BA CA, A10/AP ILLEGAL 2
L L H H BA RA Row (&Bank) Active ; Latch RA
L L H L BA A10/AP NOP 4
L L L H X X Auto Refresh or Self Refresh 5
L L L L OP code OP code Mode Register Access 5
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
Row L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP
Active L H L L BA CA, A10/AP Begin Write ; latch CA ; determine AP
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Precharge
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End Γ† Row Active)
L H H H X X NOP (Continue Burst to End Γ† Row Active)
L H H L X X Term burst Γ† Row active
Read L H L H BA CA, A10/AP Term burst, New Read, Determine AP
L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term burst, Precharge timing for Reads
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End Γ† Row Active)
L H H H X X NOP (Continue Burst to End Γ† Row Active)
L H H L X X Term burst Γ† Row active
Write L H L H BA CA, A10/AP Term burst, New Read, Determine AP 3
L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term burst, Precharge timing for Writes 3
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End Γ† Row Active)
Read with L H H H X X NOP (Continue Burst to End Γ† Row Active)
Auto L H H L X X ILLEGAL
Precharge L H L X BA CA, A10/AP ILLEGAL
L L H X BA RA, RA10 ILLEGAL 2
L L L X X X ILLEGAL
H X X X X X NOP (Continue Burst to End Γ† Row Active)
Write with L H H H X X NOP (Continue Burst to End Γ† Row Active)
Auto L H H L X X ILLEGAL
Precharge L H L X BA CA, A10/AP ILLEGAL
L L H X BA RA, RA10 ILLEGAL 2
L L L X X X ILLEGAL
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 28/46
Current
State CS RAS CAS WE BA ADDR ACTION Note
H X X X X X NOP Γ† Idle after tRP
L H H H X X NOP Γ† Idle after tRP
Precharging L H H L X X ILLEGAL 2
L H L X BA CA ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP NOP Γ† Idle after tRP 4
L L L X X X ILLEGAL
H X X X X X NOP Γ† Row Active after tRCD
L H H H X X NOP Γ† Row Active after tRCD
Row L H H L X X ILLEGAL 2
Activating L H L X BA CA ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP ILLEGAL 2
L L L X X X ILLEGAL
H X X X X X NOP Γ† Idle after tRFC
L H H X X X NOP Γ† Idle after tRFC
Refreshing L H L X X X ILLEGAL
L L H X X X ILLEGAL
L L L X X X ILLEGAL
H X X X X X NOP Γ† Idle after 2clocks
Mode L H H H X X NOP Γ† Idle after 2clocks
Register L H H L X X ILLEGAL
Accessing L H L X X X ILLEGAL
L L X X X X ILLEGAL
Abbreviations : RA = Row Address BA = Bank Address
NOP = No Operation Command CA = Column Address AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 29/46
FUNCTION TRUTH TABLE (TABLE2)
Current
State CKE
( n-1 ) CKE
n CS RAS CAS WE ADDR ACTION Note
H X X X X X X INVALID
L H H X X X X Exit Self Refresh Γ† Idle after tRFC (ABI) 6
Self L H L H H H X Exit Self Refresh Γ† Idle after tRFC (ABI) 6
Refresh L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self Refresh)
H X X X X X X INVALID
All L H H X X X X Exit Self Refresh Γ† ABI 7
Banks L H L H H H X Exit Self Refresh Γ† ABI 7
Precharge L H L H H L X ILLEGAL
Power L H L H L X X ILLEGAL
Down L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Low Power Mode)
H H X X X X X Refer to Table1
H L H X X X X Enter Power Down 8
H L L H H H X Enter Power Down 8
H L L H H L X ILLEGAL
All H L L H L X X ILLEGAL
Banks H L L L H H RA Row (& Bank) Active
Idle H L L L H H X NOP
H L L L L L X Enter Self Refresh 8
H L L L L L OP Code Mode Register Access
L L X X X X X NOP
Any State H H X X X X X Refer to Operations in Table 1
other than H L X X X X X Begin Clock Suspend next cycle 9
Listed L H X X X X X Exit Clock Suspend next cycle 9
above L L X X X X X Maintain Clock Suspend
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 30/46
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 31/46
Note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA1 BA0 Active & Read/Write
0 0 Bank A
0 1 Bank B
1 0 Bank C
1 1 Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP BA1 BA0 Operating
0 0 Disable auto precharge, leave A bank active at end of burst.
0 1 Disable auto precharge, leave B bank active at end of burst.
1 0 Disable auto precharge, leave C bank active at end of burst.
0
1 1 Disable auto precharge, leave D bank active at end of burst.
0 0 Enable auto precharge , precharge bank A at end of burst.
0 1 Enable auto precharge , precharge bank B at end of burst.
1 0 Enable auto precharge , precharge bank C at end of burst.
1
1 1 Enable auto precharge , precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP BA1 BA0 Precharge
0 0 0 Bank A
0 0 1 Bank B
0 1 0 Bank C
0 1 1 Bank D
1 X X All Banks
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 32/46
Power Up Sequence
0123456789
CLOCK
CKE
CS
RAS
CAS
ADDR
WE
DQ
DQM
A10/AP
t
RP
Key Key
BA1
BA0
High-Z
Precharge
(All Banks)
Auto Refresh Auto Refresh Mode Register Set
Extended Mode
Register Set
: Don't care
t
RFC
t
RFC
High level is necessary
High level is necessary
10 11 12 13 14 15 16 17 18 19 20
RA
BS
BS
RA
Row Active
t
MRD
t
MRD
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ
- Apply VDDQ
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK,CLK),apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS..
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 33/46
Read & Write Cycle at Same Bank @ Burst Length = 4
CLOCK
CKE
CS
RAS
CAS
ADDR
WE
DQ
DQM
A10/AP
BA1
BA0
CL =2
CL =3
Row Active
( A - Bank )
Read
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Precharge
(A - Bank)
:Don't Care
Qa1 Qa2 Qa3 Qb1 Qb2 Qb3Qb0Qa0
Ra
*Note2
Rb Cb0
Ra Ca0
HIGH
t
RCD
t
RDL
0123456789
10 11 12 13 14 15 16 17 18 19
Rb
*Note3
Qa1 Qa2 Qa3 Qb1 Qb2 Qb3Qb0Qa0
t
RDL
*Note3
Precharge
(A-Bank)
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 34/46
Page Read & Write Cycle at Same Bank @ Burst Length = 4
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid
bus contention.
2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 35/46
Page Read Cycle at Different Bank @ Burst Length = 4
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 36/46
Page Write Cycle at Different Bank @ Burst Length = 4
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 37/46
Read & Write Cycle at Different Bank @ Burst Length = 4
*Note : 1. tCDL should be met to complete write.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 38/46
Read & Write cycle with Auto Precharge @ Burst Length = 4
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 39/46
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
*Note : 1. DQM is needed to prevent bus contention
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 40/46
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of β€œFull page write burst stop cycles”.
2. Burst stop is valid at every burst length.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 41/46
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 42/46
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
*Note: 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 43/46
Self Refresh Entry & Exit Cycle
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays β€œLow”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. Burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 44/46
Mode Register Set Cycle Extended Mode Register Set Cycle
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal
mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 45/46
PACKING DIMENSIONS
90-BALL SDRAM ( 8x13 mm )
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A
1.00
0.039
A1 0.30 0.35 0.40 0.012 0.014 0.016
A2
0.586 0.023
ΓΈb 0.40 0.45 0.50 0.016 0.018 0.020
D 7.90 8.00 8.10 0.311 0.315 0.319
E 12.90 13.00 13.10 0.508 0.512 0.516
D1
6.40
0.252
E1
11.20 0.441
e
0.80
0.031
Controlling dimension : Millimeter.
ESMT
M52L64322A
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2008
Revision: 1.1 46/46
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