E ADVANCE INFORMATION
June 1997 Order Number: 290609-001
n
Two 32-Byte Write Buffers
2 µs per Byte Effective
Programming Time
n
Operating Voltage
5V VCC
5V VPP
n
70 ns Read Access Time (16 Mbit)
90 ns Read Access Time (32 Mbit)
n
High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n
System Performance Enhancements
STS Status Output
n
Industry-Standard Packaging
SSOP and TSOP (16 Mbit)
SSOP (32 Mbit)
n
Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n
100,000 Block Erase Cycles
n
Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n
Configurable x8 or x16 I/O
n
Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n
ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-c ost, nonvolatile, read/ write storage
solutions for a wide range of applications. The word-wide memories are available at various densities in the
same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly
flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend
capabilities provide an ideal solution for code or data storage applications. For secure code storage
applicat ions, such as networki ng, where code is eit her direc tly exec uted out of f las h or downloaded to DRA M,
the word-wide memori es off er three levels of protec tion: abs olute protec tion wit h VPP at GND, select ive bloc k
locking, and program/erase lockout during power transitions. These alternatives give designers ultimate
control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead
TSOP package.
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S5, 28F320S5
Includes Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property ri ghts is granted by this document. Except as provided in Intel ’s Terms and Condi tions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property ri ght. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F160S5 and 28F320S5 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.
E28F160S5, 28F320S5
3
ADVANCE INFORMATION
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.1 New Features...............................................5
1.2 Product Overview.........................................5
1.3 Pinout and Pin Description...........................6
2.0 PRINCIPLES OF OPERATION .......................9
2.1 Data Protection ..........................................10
3.0 BUS OPERATION.........................................11
3.1 Read..........................................................11
3.2 Output Disable...........................................11
3.3 Standby......................................................11
3.4 Deep Power-Down.....................................11
3.5 Read Query Operation...............................11
3.6 Read Identifier Codes Operation................12
3.7 Write ..........................................................12
4.0 COMMAND DEFINITIONS............................12
4.1 Read Array Command................................16
4.2 Read Query Mode Command.....................16
4.2.1 Query Structure Output .......................16
4.2.2 Query Structure Overview ...................18
4.2.3 Block Status Register..........................19
4.2.4 CFI Query Identification String.............20
4.2.5 System Interface Information..............21
4.2.6 Device Geometry Definition.................22
4.2.7 Intel-Specific Extended Query Table ...23
4.3 Read Identifier Codes Command...............24
4.4 Read Status Register Command................24
4.5 Clear Status Register Command................25
4.6 Block Erase Command ..............................25
4.7 Full Chip Erase Command.........................25
4.8 Write to Buffer Command...........................26
4.9 Byte/Word Write Command........................26
4.10 STS Configuration Command...................27
4.11 Block Erase Suspend Command..............27
4.12 Program Suspend Command...................27
4.13 Set Block Lock-Bit Commands.................28
4.14 Clear Block Lock-Bits Command..............28
5.0 DESIGN CONSIDERATIONS........................38
5.1 Three-Line Output Control..........................38
5.2. STS and WSM Polling...............................38
5.3 Power Supply Decoupling ..........................38
5.4 VPP Trace on Printed Circuit Boards...........38
5.5 VCC, VPP, RP# Transitions..........................38
5.6 Power-Up/Down Protection........................38
6.0 ELECTRICAL SPECIFICATIONS..................39
6.1 Absolute Maximum Ratings........................39
6.2 Operating Conditions..................................39
6.2.1 Capacitance.........................................40
6.2.2 AC Input/Output Test Conditions .........40
6.2.3 DC Characteristics...............................41
6.2.4 AC Characteristics - Read-Only
Operations..........................................43
6.2.5 AC Characteristics - Write Operations .45
6.2.6 Reset Operations.................................47
6.2.7 Erase, Program, and Lock-Bit
Configuration Performance.................48
APPENDIX A: Device Nomenclature and
Ordering Information ..................................49
APPENDIX B: Additional Information...............50
28F160S5, 28F320S5 E
4ADVANCE INFORMATION
REVISION HISTORY
Number Description
-001 Original version
E28F160S5, 28F320S5
5
ADVANCE INFORMATION
1.0 INTRODUCTION
This datasheet contains Word-Wide FlashFile™
memory (28F160S5, 28F320S5) specifications.
Section 1 provides a flash memory overview.
Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications for extended temperature
product offerings.
1.1 New Features
The Word-Wide FlashFile memory family maintains
basic compatibility with Intel’s 28F016SA and
28F016SV. Key enhancements include:
•Common Flash Interface (CFI) Support
• Scaleable Command Set (SCS) Support
• S5 Technology
•Enhanced Suspend Capabilities
They share a compatible Status Register, basic
software commands, and pinout. These similarities
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note
the following differences:
•Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
•New software commands.
•To take advantage of the 5V t echnology on the
28F160S5 and 28F320S5, allow VPP
connection to VCC. The 28F160S5 and
28F320S5 FlashFile memories do not support a
12V VPP option.
1.2 Product Overview
The Word-Wide FlashFile memory family provides
density upgrades with pinout compatibility for the
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty-
four 64-Kbyte blocks that can be erased, locked,
and unlocked in-system. Figure 1 shows the block
diagram, and Figure 4 illustrates the memory
organization.
Specifically designed for 5V systems, the
28F160S5 and 28F320S5 support read and write
operation with VCC equal to VPP. Coupled with this
capability, high programming performance is
achieved through small, highly-optimized write
buffer operations. Additionally, the dedicated VPP
pin gives complete data protection when VPP ≤
VPPLK.
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
families of dev ic es. This allows devic e-independent ,
JEDEC ID-independent, and forward- and
backward-compatible software support for the
specified flash device families. Flash vendors can
standardize their existing interfaces for long-term
compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, S IMM, or direct -to-board placement).
Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal device operation. A valid command
sequence written to the CUI initiates device
automati on. An internal Wri te St ate Mac hi ne (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within tWHQV2/EHQV2
independent of other blocks. Each block can be
independently erased 100,000 times. Block erase
suspend allows system software to suspend block
erase to read or write data from any other block.
Data is programmed in byte, word or page
increments. Program suspend mode enables the
system to read data or execute c ode from any ot her
flash memory array location.
The device incorporates two Write Buffers of 32
bytes (16 words) to allow optimum-performance
data programming. This feature can improve
system program performance by up to eight times
over non-buffer programming.
28F160S5, 28F320S5 E
6ADVANCE INFORMATION
Indivi dual bloc k loc k ing uses a com binati on of bloc k
lock-bits to lock and unlock blocks. Block lock-bits
gate block eras e, full chi p erase, program and write
to buffer operations. Lock-bit configuration
operations (Set Block Lock-Bit and Clear Block
Lock-Bits commands) set and clear lock-bits.
The Status Register and the STS pin in RY/BY#
mode indicate whether or not the device is busy
executing an operation or ready for a new
command. Polling the Status Register, system
software retrieves WSM feedback. STS in RY/BY#
mode gives an additional indicator of WSM activity
by providing a hardware status signal. Like the
Status Register, RY/BY#-low indicates that the
WSM is performi ng a block eras e, program, or loc k-
bit operation. RY/BY#-high indicates that the WSM
is ready for a new command, block erase is
suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode with address A0 selecting between the low
byte and high byte. BYTE# at logic high enables
16-bit operation with address A1 becoming the
lowest order addres s. A ddress A0 is not used in 16-
bit mode.
When one of the CEX# pins (CE0#, CE 1#) and RP#
pins are at VCC, the component enters a CMOS
standby mode. Dri ving RP # to GND enabl es a deep
power-down mode which significantly reduces
power consumption, provides write protection,
resets the device, and c lears t he Status Register. A
reset time (tPHQV) is required from RP# switching
high until outputs are valid. Likewise, the device
has a wake time (tPHEL) from RP#-high until writes
to the CUI are recognized.
1.3 Pinout and Pin Description
The 16-Mbit device is available in the 56-lead
TSOP and 56-lead SSOP. The 32- Mb device is
available in the 56-lead SSOP. The pinouts are
shown in Figures 2 and 3.
16-Mbit: Thirty-two
32-Mbit: Sixty-four
64-Kbyte Blocks
Input Buffer
Output
Multiplexer
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output Buffer
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
WP#
BYTE#
Command
User
Interface
16-Mbit: A
0
- A
20
32-Mbit: A
0 -
A
21
DQ
0
- DQ
15
V
CC
Write Buffer
Write State
Machine
Multiplexer
Query
STS
0608_01
Figure 1. 28F320S5 and 28F160S5 Block Diagram
E28F160S5, 28F320S5
7
ADVANCE INFORMATION
Table 1. Pin Descriptions
Sym Type Name and Function
A0–A21 INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally
latched during a write cycle. A0 selects high or low byte when operating in x8 mode.
In x16 mode, A0 is not used; input buffer is off.
16-Mbit → A0–A20 32-Mbit → A0–A21
DQ
0
–
DQ15 INPUT/
OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, Status Register, query and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CE0#,
CE1#INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. With CE0# or CE1# high, the device is deselected and power
consumption reduces to standby levels. Both CE0# and CE1# must be low to select
the device. Device selection occurs with the latter falling edge of CE0# or CE1#. The
first rising edge of CE0# or CE1# disables the device.
RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during system power transitions, puts the device in
deep power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
STS OPEN
DRAIN
OUTPUT
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up
resistor.
WP# INPUT WRITE PROTECT: Master control for block locking. When VIL, locked blocks
cannot be erased or programmed, and block lock-bits cannot be set or cleared.
BYTE# INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
Necessary voltage to perform block erase, program, and lock-bit configuration
operations. Do not float any power pins.
VCC SUPPLY DEVICE POWER SUPPLY: Do not float any power pins.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
28F160S5, 28F320S5 E
8ADVANCE INFORMATION
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
56-LEAD TSOP
STANDARD PINOUT
14 mm x 20 mm
TOP VIEW
Highlights pinout changes.
WP#
WE#
OE#
RY/BY#
DQ
15
DQ
7
DQ
14
DQ
6
GND
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
GND
DQ
11
DQ
3
DQ
10
DQ
2
V
CC
DQ
9
DQ
1
DQ
8
DQ
0
A
0
BYTE#
NC
NC
28F016SA
28F016SV
RY/BY#
3/5#
CE
1
#
NC
A
20
A
19
A
18
A
17
A
16
V
CC
A
15
A
14
A
13
A
12
CE
0
#
V
PP
RP#
A
11
A
10
A
9
A
8
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
28F016SA
28F016SV
3/5# NC
CE
1
#
NC
A
20
A
19
A
18
A
17
A
16
V
CC
A
15
A
14
A
13
A
12
CE
0
#
V
PP
RP#
A
11
A
10
A
9
A
8
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
28F160S3
28F160S5
WP#
WE#
OE#
STS
DQ
15
DQ
7
DQ
14
DQ
6
GND
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
GND
DQ
11
DQ
3
DQ
10
DQ
2
V
CC
DQ
9
DQ
1
DQ
8
DQ
0
A
0
BYTE#
NC
NC
28F160S3
28F160S5
0608_02
Figure 2. 28F160S5 TSOP 56-Lead Pinout
E28F160S5, 28F320S5
9
ADVANCE INFORMATION
Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout
2.0 PRINCIPLES OF OPERATION
The Word-Wide FlashFile memories include an
on-chip Write State Machine (WSM) to manage
block erase, program, and lock-bit configuration
functions. It allows for: 100% TTL-level control
inputs, fi xed power s upplies during bloc k erasure,
programming, lock-bit configuration, and minimal
processor overhead with RAM-like interface
timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device def aults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.
28F160S5, 28F320S5 E
10 ADVANCE INFORMATION
Read Array, S tatus Register, query, and ident ifier
codes can be accessed through the CUI
independent of the VPP voltage. Proper
programming voltage on VPP enables successful
block erasure, program, and lock-bit
configuration. All functions associated with
altering memory contents —block erase, program,
lock-bit configuration, status, and identifier
codes—are accessed via the CUI and verified
through the Status Register.
Commands are written using standard micro-
processor write timings. The CUI contents serve
as input to the WSM that controls the block
erase, programming, and lock-bit configuration.
The internal algorithms are regulated by the
WSM, including pulse repetition, internal
verification, and margining of data. Addresses
and data are internally latched during write
cycles. Writing the appropriate c ommand outputs
array data, identifier codes, or Status Register
data.
Interface software that initiates and polls
progress of block erase, programming, and lock-
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM during flash memory updates. After
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
2.1 Data Protection
Depending on the application, the system
designer may choose to make the VPP power
supply switchable or hardwired to VPPH. The
device supports either design practice, and
encourages optimization of the processor-
memory interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. When high voltage is applied to VPP, the
two-step block erase, program, or lock-bit
configuration command sequences provide
protection from unwanted operations. All write
functi ons are disabled when V CC voltage is below
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability
provides additional protection from inadvertent
code or data alteration.
0608_05
Figure 4. Memory Map
E28F160S5, 28F320S5
11
ADVANCE INFORMATION
3.0 BUS OPERATION
The local CP U reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard mi croprocessor bus
cycles.
3.1 Read
Block information, query information, identifier
codes and Status Registers can be read
independent of the VPP voltage.
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component . CE0#, CE1# and OE# mus t be driv en
active to obtain data at the outputs. CE0# and
CE1# are the device selection controls, and,
when both are active, enable the selected
memory device. OE# is the data output (DQ0–
DQ15) control: When active it drives the selected
memory data onto the I/O bus. WE# must be at
VIH and RP# must be at VIH. Figure 16 illustrates
a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.3 Standby
CE0# or CE1# at a logic-high level (VIH) places
the device in standby mode, substantially
reducing device power consumption. DQ0–DQ15
(or DQ0– DQ7 in x8 mode) outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time tPLPH. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the Status
Register is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data may be partially corrupted after
programming or parti ally altered af ter an erase or
lock-bit conf igurati on. Time t PHWL is required aft er
RP# goes to logic-high (VIH) before another
command can be written.
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash memory. Automated flash memories
provide st atus information when acces sed during
block erase, programming, or lock-bit
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not oc cur bec ause t he fl ash m emory m ay be
providing s tat us inf ormat ion ins tead of array dat a.
Intel’s Flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.5 Read Query Operation
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
28F160S5, 28F320S5 E
12 ADVANCE INFORMATION
3.6 Read Identifier Codes
Operation
The read-identifier codes operation outputs the
manufacturer code, device code, and block lock
configuration codes for each block configuration
(see Figure 5). Using the manufacturer and
device codes, the system software can
automatically match the device with its proper
algorithms. The block-lock configuration codes
identify each block’s lock-bit setting.
0608_06
Figure 5. Device Identifier Code Memory Map
3.7 Write
Writing commands to t he CUI enables reading of
device data, query, identifier codes, inspection
and clearing of the Status Register. Additionally,
when VPP = VPPH, block erasure, programming,
and lock-bit configuration can also be performed.
The Block Erase command requires appropriate
command data and an address within the block
to be erased. The Byte/Word Write command
requires the command and address of the
location to be written. Set Block Lock-Bit
commands require the command and address
within the block to be locked. The Clear Block
Lock-Bits command requires the command and
an address within the device.
The CUI does not occupy an addressable
memory location. It is written when WE#, CE0#,
and CE1# are act ive and OE # = VIH. The addres s
and data needed to execute a command are
latched on the rising edge of WE# or CEX#
(CE0#, CE1#), whichever goes high first.
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0 COMMAND DEFINITIONS
VPP voltage ≤ V
PPLK enables read operations
from the Status Register, identifier codes, or
memory blocks. Placing VPPH on VPP enables
successful block erase, programming, and lock-
bit configuration operations.
Device operat ions are selec ted by wri ting s pecif ic
commands into the CUI. Table 2 and Table 3
define these commands.
E28F160S5, 28F320S5
13
ADVANCE INFORMATION
Table 2. Bus Operations
Mode Notes RP# CE0#CE
1
# OE#(11) WE#(11) Address VPP DQ(8) STS(3)
Read 1,2 VIH VIL VIL VIL VIH XXD
OUT X
Output Disable VIH VIL VIL VIH VIH X X High Z X
Standby VIH VIL
VIH
VIH
VIH
VIL
VIH
X X X X High Z X
Reset/Power-
Down Mode 10 VIL X X X X X X High Z High Z(9)
Read Identifier
Codes 4V
IH VIL VIL VIL VIH See
Figure 5 XD
OUT High Z(9)
Read Query 5 VIH VIL VIL VIL VIH See Table 6 X DOUT High Z(9)
Write 3,6,7 VIH VIL VIL VIH VIL XV
PPH DIN X
NOTES:
1. Refer to Table 19. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH for VPP. See Table 19, for VPPLK and VPPH
voltages.
3. STS in RY/BY# mode (default) is VOL when the WSM is executing internal block erase, programming, or lock-bit
configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive),
program suspend mode, or deep power-down mode.
4. See Section 4.3 for read identifier code data.
5. See Section 4.2 for read query data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when V
PP = VPPH and
VCC = VCC1/2 (see Section 6.2).
7. Refer to Table 3 for valid DIN during a write operation.
8. DQ refers to DQ0–7 if BYTE# is low and DQ0–15 if BYTE# is high.
9. High Z will be VOH with an external pull-up resistor.
10. RP# at GND ± 0.2V ensures the lowest deep power-down current.
11. OE# = VIL and WE# = VIL concurrently is an undefined state and should not be attempted.
28F160S5, 28F320S5 E
14 ADVANCE INFORMATION
Table 3. Word-Wide FlashFile™ Memory Command Set Definitions(13)
Command Scaleable
or Basic
Command
Set(14)
Bus
C
y
cles
Req'd
Notes First Bus Cycle Second Bus Cycle
Oper(1) Addr(2) Data(3,4) Oper(1) Addr(2) Data(3,4)
Read Array SCS/BCS 1 Write X FFH
Read Identifier Codes SCS/BCS ≥2 5 Write X 90H Read IA ID
Read Query SCS ≥ 2 Write X 98H Read QA QD
Read Status Register SCS/BCS 2 Write X 70H Read X SRD
Clear Status Register SCS/BCS 1 Write X 50H
Write to Buffer SCS > 2 8, 9, 10 Write BA E8H Write BA N
Word/Byte Program SCS/BCS 2 6,7 Write X 40H
or
10H
Write PA PD
Block Erase SCS/BCS 2 6,10 Write X 20H Write BA D0H
Block Erase, Word/Byte
Program Suspend SCS/BCS 1 6 Write X B0H
Block Erase, Word/Byte
Program Resume SCS/BCS 1 6 Write X D0H
STS pin Configuration SCS 2 Write X B8H Write X CC
Set Block Lock-Bit SCS 2 11 Write X 60H Write BA 01H
Clear Block Lock-Bits SCS 2 12 Write X 60H Write X D0H
Full Chip Erase SCS 2 10 Write X 30H Write X D0H
E28F160S5, 28F320S5
15
ADVANCE INFORMATION
NOTES:
1. Bus operations are defined in.Table 2.
2. X = Any valid address within the device.
BA = Address within the block being erased or locked.
IA = Identifier Code Address: see Table 12.
QA = Query database Address.
PA = Address of memory location to be programmed.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code. (See Table 14.)
4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
Section 4.3 for read identifier code data.
6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and
suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V
IL
will fail.
7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1
byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the
correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write
cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the
buffer boundary causes unexpected results and should be avoided.
10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.
Confirm also reactivates suspended operations.
11. A block lock-bit can be set only while WP# is VIH.
12. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.
13. Commands other than those shown above are reserved for future use and should not be used.
14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
28F160S5, 28F320S5 E
16 ADVANCE INFORMATION
4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is writ ten. Once t he internal WSM has s tarted block
erase, program, or lock-bi t c onfigurati on, t he devic e
will not recognize the Read Array command until
the WSM c ompletes its operation—unl ess the WS M
is suspended via an Erase-Suspend or Program-
Suspend command. The Read Array command
functions independently of the VPP voltage.
4.2 Read Query Mode Command
This section defines the data structure or
“database” returned by the Common Flash I nterface
(CFI) Query command. System software should
parse this structure to gain critical information such
as block size, density, x8/x16, and electrical
specifications. Once this information has been
obtained, the software will know which command
sets t o use to enable fl ash writes, block erases, and
otherwise control the flash component. The Query
is part of an overall specification for multiple
command set and control interface descriptions
called Common Flash Interface, or CFI.
4.2.1 QUERY STRUCTURE OUTPUT
The Query “database” allows system software to
gain critical information for controlling the flash
component. This section describes the device’s
CFI-compliant interface that allows the host system
to access Query data.
Query data are always presented on the lowest-
order data outputs (DQ0-7) only. The numerical
offset v alue i s the address relati ve to the maximum
bus width supported by the device. On this device,
the Query table device starting address is a 10h
word address, since the maximum bus width is x16.
For this word-wide (x16) device, the first two bytes
of the Query structure, “Q” and ”R” in ASCII, appear
on the low byte at word addresses 10h and 11h.
This CFI-compliant device outputs 00H data on
upper bytes. Thus, the device outputs ASCII “Q” in
the low byte (DQ0-7) and 00h in the high byte
(DQ8-15).
Since the device is x8/x16 capable, the x8 data is
still presented in word-relative (16-bit) addresses.
However, the “fill data” (00h) is not the same as
driven by the upper bytes in the x16 mode. As in
x16 mode, the byte address (A0) is ignored for
Query output so that the “odd byte address” (A0
high) repeats the “ev en byt e address ” data (A0 low).
Therefore, in x8 mode using byte addressing, the
device will output the sequence “Q”, “Q”, “R”, “R”,
“Y”, “Y”, and so on, beginning at byte-relative
address 20h (whic h is equiv alent to word of fset 10h
in x16 mode).
At Query addresses containing two or more bytes
of information, the least significant data byte is
presented at the lower address, and the most
significant data byte is presented at the higher
address.
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ADVANCE INFORMATION
Table 4. Summary of Query Structure Output as a Function of Device and Mode
Device Type/Mode Word Addressing Byte Addressing
Location Quer
y
Data
Hex, ASCII Location Quer
y
Data
Hex, ASCII
x16 device/
x16 mode 10h
11h
12h
0051h “Q”
0052h “R”
0059h “Y”
20h
21h
22h
51h “Q”
00h null
52h “R”
x16 device/
x8 mode N/A(1) N/A 20h
21h
22h
51h “Q”
51h “Q”
52h “R”
NOTE:
1. The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8
mode. Therefore, word addressing where lower addresses are not toggled by the system is “Not Applicable” for x8-
configured devices.
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device
Device
Address Word Addressin
g
:
Query Data B
y
te
Address
Byte Addressing:
Query Data
A16–A1D15–D0A7–A0D7–D0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
0051h “Q”
0052h “R”
0059h “Y”
P_IDLO PrVendor
P_IDHI ID #
PLO PrVendor
PHI TblAdr
A_IDLO AltVendor
A_IDHI ID #
...
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
51h “Q”
51h “Q”
52h “R”
52h “R”
59h “Y”
59h “Y”
P_IDLO PrVendor
P_IDLO ID #
P_IDHI “
...
28F160S5, 28F320S5 E
18 ADVANCE INFORMATION
4.2.2 QUERY STRUCTURE OVERVIEW
The Query command causes the flash component
to displ ay the Common Flas h Interface (CFI ) Query
structure or “database.” The structure sub-sections
and address locations are summarized in Table 8.
The following s ections des cribe the Query s tructure
sub-sections in detail.
Table 6. Query Structure(1)
Offset Sub-Section Name Description
00h Manufacturer Code
01h Device Code
(BA+2)h(2) Block Status Register Block-specific information
04-0Fh
Reserved Reserved for vendor-specific information
10h CFI Query Identification String Command set ID and vendor data offset
1Bh System Interface Information Device timing & voltage information
27h Device Geometry Definition Flash device layout
P(3) Primary Intel-specific Extended Query
table Vendor-defined additional information
specific to the Primary Vendor Algorithm
NOTES:
1. Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode.
2. BA = The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is
32 Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
E28F160S5, 28F320S5
19
ADVANCE INFORMATION
4.2.3 BLOCK STATUS REGISTER
The Block Status Register indicates whether an
erase operation completed successfully or whether
a given bloc k is loc ked or c an be acc ess ed for f lash
program/erase operations.
Block Erase Status (BSR.1) allows system software
to determine the success of the last block erase
operation. B SR.1 can be used j ust after power-up to
verify that the VCC supply was not accidentally
removed during an erase operation. This bit is only
reset by issuing another erase operation to the
block. The Block Status Register is accessed from
word address 02h within each block.
Table 7. Block Status Register
Offset Len
g
th
(bytes) Description 28F32/160S5
x16 Device/Mode
(BA+2)h(1) 01h Block Status Register BA+2: 0000h or
0001h
BSR.0 = Block Lock Status
1 = Locked
0 = Unlocked
BA+2 (bit 0): 0 or 1
BSR.1 = Block Erase Status
1 = Last erase operation did not complete
successfully
0 = Last erase operation completed successfully
BA+2 (bit 1): 0 or 1
BSR 2-7 Reserved for future use
BA+2 (bits 2-7): 0
NOTE:
1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)
28F160S5, 28F320S5 E
20 ADVANCE INFORMATION
4.2.4 CFI QUERY IDENTIFICATION STRING
The Identification String provides verification that
the component supports the Common Flash
Interface specification. Additionally, it indicates
which version of the spec and which vendor-
specified command set(s) is (are) supported.
Table 8. CFI Identification
Offset Len
g
th
(Bytes) Description 28F32/160S5
10h 03h Query-Unique ASCII string “QRY“ 10: 0051h
11: 0052h
12: 0059h
13h 02h Primary Vendor Command Set and Control Interface ID Code
16-bit ID Code for Vendor-Specified Algorithms 13: 0001h
14: 0000h
15h 02h Address for Primary Algorithm Extended Query Table
Offset value =
P
= 31h 15: 0031h
16: 0000h
17h 02h Alternate Vendor Command Set and Control Interface ID Code
Second Vendor-Specified Algorithm Supported
Note: 0000h means none exists
17: 0000h
18: 0000h
19h 02h Address for Secondary Algorithm Extended Query Table
Note: 0000h means none exists 19: 0000h
1A: 0000h
E28F160S5, 28F320S5
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ADVANCE INFORMATION
4.2.5 SYSTEM INTERFACE INFORMATION
The following device information can be useful in
optimizing system interface software.
Table 9. System Interface Information
Offset Len
g
th
(bytes) Description 28F32/160S5
1Bh 01h VCC Logic Supply Minimum Program/Erase Voltage
bits 7–4 BCD volts
bits 3–0 BCD 100 mv
1B: 0030h
1Ch 01h VCC Logic Supply Maximum Program/Erase Voltage
bits 7–4 BCD volts
bits 3–0 BCD 100 mv
1C: 0055h
1Dh 01h VPP [Programming] Supply Minimum Program/Erase
Voltage
bits 7–4 HEX volts
bits 3–0 BCD 100 mv
1D: 0030h
1Eh 01h VPP [Programming] Supply Maximum Program/Erase
Voltage
bits 7–4 HEX volts
bits 3–0 BCD 100 mv
1E: 0055h
1Fh 01h Typical Time-Out per Single Byte/Word Program, 2N µ-
sec 1F: 0003h
20h 01h Typical Time-Out for Max. Buffer Write, 2N µ-sec 20: 0006h
21h 01h Typical Time-Out per Individual Block Erase, 2N m-sec 21: 000Ah
22h 01h Typical Time-Out for Full Chip Erase, 2N m-sec 22: 000Fh
23h 01h Maximum Time-Out for Byte/Word Program,
2N Times Typical 23: TBD
24h 01h Maximum Time-Out for Buffer Write, 2N Times Typical 24: TBD
25h 01h Maximum Time-Out per Individual Block Erase,
2N Times Typical 25: TBD
26h 01h Maximum Time-Out for Chip Erase, 2N Times Typical 26: TBD
28F160S5, 28F320S5 E
22 ADVANCE INFORMATION
4.2.6 DEVICE GEOMETRY DEFINITION
This fi eld provides critic al detail s of the flas h devi ce
geometry.
Table 10. Device Geometry Definition
Offset Len
g
th
(bytes) Description 28F32/160S5
27h 01h Device Size = 2N in Number of Bytes 27: 0015h
(16 Mbit)
27: 0016h
(32 Mbit)
28h 02h Flash Device Interface Description
value meaning
0002h x8/x16 asynchronous
28: 0002h
29: 0000h
2Ah 02h Maximum Number of Bytes in Write Buffer = 2N2A: 0005h
2B: 0000h
2Ch 01h Number of Erase Block Regions within Device:
bits 7–0 = x = # of Erase Block Regions
2C: 0001h
2Dh 04h Erase Block Region Information
bits 15–0 = y, Where y+1 = Number of Erase Blocks of
Identical Size within Region
bits 31–16 = z, Where the Erase Block(s) within This
Region are (z) × 256 Bytes
y: 32 Blocks
(16 Mbit)
2D: 001Fh
2E: 0000h
y: 64 Blocks
(32 Mbit)
2D: 003Fh
2E: 0000h
z: (64-KB)
2F: 0000h
30: 0001h
E28F160S5, 28F320S5
23
ADVANCE INFORMATION
4.2.7 INTEL-SPECIFIC EXTENDED QUERY
TABLE
Certain flash features and commands are optional.
The Intel-Specific Extended Query table specifies
this and other similar types of information.
Table 11. Primary-Vendor Specific Extended Query
Offset(1) Len
g
th
(bytes) Description Data
(P)h 03h Primary Extended Query Table
Unique ASCII String “PRI“ 31: 0050h
32: 0052h
33: 0049h
(P+3)h 01h Major Version Number, ASCII 34: 0031h
(P+4)h 01h Minor Version Number, ASCII 35: 0030h
(P+5)h 04h Optional Feature & Command Support
bit 0 Chip Erase Supported (1=yes, 0=no)
bit 1 Suspend Erase Supported (1=yes, 0=no)
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bits 5–31 Reserved for future use; undefined bits
are “0”
36: 000Fh
37: 0000h
38: 0000h
39: 0000h
(P+9)h 01h Supported Functions after Suspend
Read Array, Status, and Query are always supported
during suspended Erase or Program operation. This field
defines other operations supported.
bit 0 Program Supported after Erase Suspend
(1=yes, 0=no)
bits 1-7 Reserved for future use; undefined bits are “0”
3A: 0001h
(P+A)h 02h Block Status Register Mask
Defines which bits in the Block Status Register section of
Query are implemented.
bit 0 Block Status Register Lock-Bit [BSR.0] active
(1=yes, 0=no)
bit 1 Block Erase Status Bit [BSR.1] active
(1=yes, 0=no)
bits 2-15 Reserved for future use; undefined bits
are “0”
3B: 0003h
3C: 0000h
NOTES:
1. The variable P is a pointer which is defined at offset 15h in Table 8.
28F160S5, 28F320S5 E
24 ADVANCE INFORMATION
Table 11. Primary-Vendor Specific Extended Query (Continued)
Offset Len
g
th
(bytes) Description Data
(P+C)h 01h VCC Logic Supply Optimum Program/Erase voltage
(highest performance)
bits 7–4 BCD value in volts
bits 3–0 BCD value in 100 mv
3D: 0050h
(P+D)h 01h VPP [Programming] Supply Optimum Program/Erase
voltage
bits 7–4 HEX value in volts
bits 3–0 BCD value in 100 mv
3E: 0050h
(P+E)h
reserved Reserved for future use
Table 12. Identifier Codes
Code Address(2) Data
Manufacturer Code 000000 B0
Device Code 16 Mbit 000001 D0
32 Mbit 000001 D4
Block Lock Configuration X0002(1)
• Block is Unlocked DQ0 = 0
• Block is Locked DQ0 = 1
• Reserved for Future Use DQ2-7
Block Erase Status x0002(1)
• Last erase completed
successfully DQ1 = 0
• Last erase did not
complete successfully DQ1 = 1
• Reserved for Future Use DQ2-7
NOTES:
1. X selects the specific block lock configuration code.
See Figure 5 for the device identifier code memory
map.
2. A0 should be ignored in this address. The lowest order
address line is A1 in both word and byte mode.
4.3 Read Identifier Codes
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command writ e, read cycles from addresses shown
in Figure 5 retrieve the manufacturer, device, block
lock configuration, and block erase status codes
(see Table 12 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage. Following the
Read Identifier Codes command, the information in
Table 12 can be read.
4.4 Read Status Register
Command
The Status Register may be read to determine
when programming, block erasure, or lock-bit
configurat ion is com plete and whet her the operat ion
complet ed successf ully. It may be read at any time
by writing the Read Status Register command.
After writing this command, all subsequent read
operations output data from the Status Register
until another valid command is written. The Status
Register contents are latched on the falling edge of
OE#, CE0#, or CE1# whichever occ urs last. OE# or
CEX# must toggle to VIH to update the Status
Register latc h. The Read St atus Regis ter comm and
functions independently of the VPP voltage.
E28F160S5, 28F320S5
25
ADVANCE INFORMATION
Following a program, bl ock erase, s et bloc k lock-bit,
or clear block lock-bits command sequence, only
SR.7 is valid until the Write State Machine
completes or suspends the operation. Device I/O
pins DQ0-6 and DQ8-15 are invalid. When the
operation completes or suspends (SR.7 = 1), all
contents of the Status Register are valid when read.
The eXtended Status Register (XSR) may be read
to determine Write Buffer availability (see Table 16).
The XSR may be read at any time by writing the
Write to Buffer command. After writing this
command, all subsequent read operations output
data from the XSR, until another valid command is
written. The content s of the X SR are lat ched on the
falling edge of OE# or CEX# whichever occurs last
in the read cycle. Write to buffer command must be
re-issued to update the XSR latch.
4.5 Clear Status Register
Command
Status Register bits SR.5, SR.4, SR.3, and SR.1
are set to “1”s by the WSM and can only be reset
by the Clear Status Register command. These bits
indicate various failure conditions (see Table 15).
By allowing system software to reset these bits,
several operat ions (such as cumulativ ely erasing or
locking multiple blocks or programming several
bytes/words in sequence) may be performed. The
Status Register may be polled to determine if an
error occurred during the sequence.
To clear the Status Register, the Clear Status
Register command is written. It functions
independently of the applied VPP voltage. This
command is not functional during block erase or
program suspend modes.
4.6 Block Erase Command
Block Erase is executed one block at a time and
initiated by a two-cycle command. A Block Erase
Setup command is written first, followed by a
Confirm command. This command sequence
requires appropriate sequencing and an address
within the block to be erased (erase changes all
block data to FFH). Block preconditioning, erase,
and verify are handled internally by the WSM
(invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs S tat us Regi st er data when read (see Figure
9). The CPU can detect block erase completion by
analyzing STS in level RY/BY# mode or Status
Register bit SR.7. Toggle OE#, CE0#, or CE1# to
update the Status Register.
When the block erase is complete, Status Register
bit SR. 5 should be check ed. If a block erase error is
detected, the Status Register should be cleared
before system software attempts corrective actions.
The CUI remains in read St atus Regis ter mode unt il
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both Status
Register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
VCC = VCC1/2 and VPP = VPPH. In the absence of
these voltages, block contents are protected
against erasure. If block erase is attempted while
VPP ≤ V
PPLK, SR.3 and SR.5 will be set to “1.”
Successful block erase requires that the
corresponding block lock-bit be cleared, or WP# =
VIH. If block erase is attempted when the
corresponding block lock-bit is set and WP# = VIL,
the block erase will fail and SR.1 and SR.5 will be
set to “1.”
4.7 Full Chip Erase Command
The Full Chip Erase command followed by a
Confirm c ommand erases all unlock ed blocks. After
the Confirm command is written, the device erases
all unlocked blocks from block 0 to block 31 (or 63)
sequentially. Block preconditioning, erase, and
verify are handled internally by the WSM. After the
Full Chip Erase command sequence is written to
the CUI, the device automatic al l y outputs t he S tatus
Register data when read. The CPU can detect full
chip erase completion by polling the STS pin in
level RY/BY# mode or Status Register bit SR.7.
When the full chip erase is complete, Status
Register bit SR.5 should be checked to see if the
operation completed successfully. If an erase error
occurred, the Status Register should be cleared
before issuing the next command. The CUI remains
in read Status Regi ster mode until a new command
is issued. If an error is detected while erasing a
block during a full chip erase operation, the WSM
skips the rem aining c ells in t hat bloc k and proc eeds
to erase the next block. Reading the block valid
status code by issuing the Read Identifier Codes
command or Query command informs the user of
which block(s) failed to erase.
28F160S5, 28F320S5 E
26 ADVANCE INFORMATION
This two-s tep command s equence of set up f ol l owed
by execution ensures that block contents are not
accidentally erased. An invalid Full Chip Erase
command sequence will result in both Status
Register bits SR.4 and SR.5 being set to 1. Also,
reliable full chip erasure can only occur when
VCC = VCC1/2 and V PP = VPPH. In t he absence these
voltages, block contents are protected against
erasure.
If full chip erase is attempted while VPP ≤
VPPLK, SR.3 and S R.5 will be s et to 1. When WP# =
VIL, only unlocked blocks are erased. Full chip
erase cannot be suspended.
4.8 Write to Buffer Command
To program the flash device via the writ e buffers, a
Write to Buffer command sequence is initiated. A
variable number of bytes or words, up to the buffer
size, can be wri tt en into the buf fer and program med
to the flash device. First, the Write to Buffer setup
command is issued along with the Block Address.
At this point, the eXtended Status Register
information is loaded and XSR.7 reverts to the
“buffer available” status. If XSR.7 = 0, no write
buffer is available. To retry, continue monitoring
XSR.7 by issuing the Write to Buffer setup
command with the Block Address until XSR.7 = 1.
When XSR.7 transit ions to a “1,” the buf fer is ready
for loading.
Now a Word/Byte count is issued at an address
within the block. On the next write, a device start
address is given along with the write buffer data.
For maximum programm ing performance and lower
power, align the start address at the beginni ng of a
Write Buffer boundary. Subsequent writes must
supply additional device addresses and data,
depending on the count. All subsequent addresses
must lie within the start address plus the count.
After the final buffer data is given, a Write Confirm
command is issued. This initiates the WS M to begi n
copying the buffer data to the flash memory. If a
command other than Write Conf irm is written t o the
device, an “Invalid Command/Sequence” error will
be generated and Status Register bits SR.5 and
SR.4 will be set to “1.” For additional buffer writes,
issue another Write to Buffer setup command and
check XSR.7. The write buf fers can be l oaded while
the WSM is bus y as long as X SR.7 indicat es that a
buffer is available. Refer to Fi gure 6 for the Write t o
Buffer flowchart.
If an error occurs while writing, the device will stop
programming, and Status Register bit SR.4 will be
set to a “1” to indicate a program fail ure. Any t ime a
media failure occurs during a program or an erase
(SR.4 or SR.5 is set), the device will not accept any
more Write to Buffer commands. Additionally, if the
user attempts to wri te past an erase bloc k boundary
with a Write to Buffer command, the device will
abort programming. This will generate an “Invalid
Command/S equence” error and Status Register bits
SR.5 and SR.4 will be set to “1.” To clear SR.4
and/or SR.5, issue a Clear Status Register
command.
Reliable buffered programming can only occur
when VCC = VCC1/2 and VPP = VPPH. If programm ing
is attempted while VPP ≤ VPPLK, Status Regis ter bit s
SR.4 and SR.5 will be set to “1.” Programming
attempts with invalid VCC and VPP voltages produc e
spurious results and should not be attempted.
Finally, successful programming requires that the
corresponding B lock Lock -Bit be cleared, or WP# =
VIH. If a buffered write is attempted when the
corresponding B lock Loc k-Bit is s et and WP# = VIL,
SR.1 and SR.4 will be set to “1.”
4.9 Byte/Word Program Command
Byte/Word programming is executed by a two-cycle
command sequence. Byte/Word Program setup
(standard 40H or alternate 10H) is written, followed
by a second write that specifies the address and
data (latched on t he risi ng edge of WE #). The WSM
then takes over, controlling the program and verify
algorithms internally. After the write sequence is
written, the device automatically outputs Status
Register data when read. The CPU can detect the
completion of the program event by analyzing STS
in level RY/BY# mode or Status Register bit SR.7.
When programming is c omplete, Status Register bi t
SR.4 should be checked. If a programming error is
detected, the Status Register should be cleared.
The internal WSM verify onl y detects errors for “1”s
that do not successfully program to “0”s. The CUI
remains in read Status Register mode until it
receives another command. Refer to Figure 7 for
the Word/Byte Program flowchart.
Also, Reliable byte/word programming can only
occur when VCC = VCC1/2 and VPP = VPPH. In the
absence of thi s high v olt age, c ontent s are prot ect ed
against programming. If a byte/word program is
E28F160S5, 28F320S5
27
ADVANCE INFORMATION
attempted while VPP ≤ VPPLK, Status Register bits
SR.4 and SR.3 will be set to “1.” Successful
byte/word programming requires that the
corresponding block lock-bit be cleared. If a
byte/word program is attempted when the
corresponding block lock-bit is set and WP# = VIL,
SR.1 and SR.4 will be set to “1.”
4.10 STS Configuration Command
The Status (STS) pin can be c onfigured to different
states using the STS pin Configuration command.
Once the STS pin has been configured, it remains
in that configuration until another configuration
command is issued or RP# i s low. Init ially, the STS
pin defaults to level RY/BY# operation where STS
low indicates that the state machine is busy. STS
high indicates that the state machine is ready for a
new operation or suspended.
To reconfigure t he Status (STS) pin to other modes,
the STS pin Configuration command is issued
followed by the desired configuration code. The
three alternate c onfigurations are all puls e mode for
use as a system interrupt as described in Table 14.
For these configurations, bit 0 controls Erase
Complete interrupt pulse, and bit 1 controls Write
Complete interrupt pulse. When the device is
configured in one of the pulse modes, the STS pin
pulses low with a typical pulse width of 250 ns.
Supplying the 00h configuration code with the
Configuration command resets the STS pin to the
default RY/BY# level mode. Refer to Table 14 for
configuration coding definitions. The Configuration
command may only be giv en when the dev ice i s not
busy or suspended. Check SR.7 for device status.
An invalid configuration code will result in both
Status Register bits SR.4 and SR.5 being set to “1.”
4.11 Block Erase Suspend
Command
The Block Erase Suspend command allows
block-erase interruption to read or program data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs Status Register
data when read after the Block Erase Suspend
command is written. Polling Status Register bits
SR.7 can determine when the block eras e operation
has been sus pended. When SR.7 = 1, SR. 6 should
also be set to “1”, indic ati ng that the devi ce is in t he
erase suspend mode. STS in level RY/BY# mode
will also transition to VOH. Specification tWHRH2
defines the block erase suspend latency.
At thi s point , a Read A rray c omm and can be writ ten
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.12), a program operation
can also be suspended. During a program operat i on
with block erase suspended, Status Register bit
SR.7 will return to “0” and STS in RY/BY # mode will
transition to VOL. However, SR.6 will remain “1” to
indicate block erase suspend status.
The only other v alid c omm ands whil e block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and STS in RY/BY# mode will return to VOL. After
the Erase Resume command is written, the device
automatically outputs Status Register data when
read (see Figure 10). V PP must remain at VPPH and
VCC must remain at VCC1/2 (the same VPP and VCC
levels used for block erase) while block erase is
suspended. RP# mus t al so remai n at VIH (the s ame
RP# level us ed for block erase). Bloc k erase cannot
resume until program operations initiated during
block erase suspend have completed.
4.12 Program Suspend Command
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the programming process starts,
writing the Program Suspend command requests
that the WSM suspend the program sequence at a
predetermined point in the algorithm. The device
continues to output St atus Regist er data when read
after the Program Suspend command is written.
Polling Status Register bits SR.7 can determine
when the programming operation has been
suspended. When SR.7 = 1, SR.2 should also be
set to “1”, indicating that the device is in the
program suspend mode. STS in level RY/BY#
mode will also transition to VOH. Specification
tWHRH1 defines the program suspend latency.
At thi s point , a Read A rray c omm and can be writ ten
to read data from locations other than that which is
28F160S5, 28F320S5 E
28 ADVANCE INFORMATION
suspended. The only other valid commands while
programming is suspended are Read Status
Register and Program Resume. After a Program
Resume command is written, the WSM will
continue t he programming process . Status Register
bits SR.2 and SR.7 will automatically c lear and STS
in RY/BY# mode will return to VOL. After the
Program Resume command is written, the device
automatically outputs Status Register data when
read. VPP must remain at VPPH and VCC must
remain at VCC1/2 (the same VPP and VCC levels used
for programming) while in program suspend mode.
RP# must also remain at VIH (the same RP# level
used for programming). Refer to Figure 8 for the
Program Suspend/Resume flowchart.
4.13 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits. The
block lock-bits gate program and erase operations.
With WP# = VIH, individual block lock-bits can be
set using the Set Block Lock-Bit command.
Set block lock-bit is initiated using a two-cycle
command sequence. The Set Block Lock-Bit setup
along with appropriate block or device address is
written followed by the Set Block Lock-Bit Confirm
and an address within the block to be locked. The
WSM then controls the set lock-bit algorithm. After
the sequence is written, the device automatically
outputs Status Register data when read. The CPU
can detect the completion of the set lock-bit event
by analyzing STS in level RY/BY# mode or Status
Register bit SR.7.
When the set l ock-bit operation is complet e, Status
Register bit SR.4 should be checked. If an error is
detected, the Status Register should be cleared.
The CUI will remain in read Status Register mode
until a new command is issued.
This two-step sequence of setup followed by
execut ion ensures t hat loc k-bi ts are not ac cident all y
set. An invalid Set Block Lock-Bit command will
result in Status Register bits SR.4 and SR.5 being
set to “1.” Also, rel iable operations oc cur only when
VCC = VCC1/2 and V PP = VPPH. In the absenc e these
voltages, lock-bit contents are protected against
alteration.
A successful set block lock-bit operation requires
that WP# = VIH. If it is attempted with WP# = VIL,
the operation will fail and S R.1 and SR.4 will be set
to “1.” See Tabl e 13 for write protec tion alternati ves.
Refer to Figure 11 for the Set Block Lock-Bit
flowchart.
4.14 Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. This command is
valid only when WP# = VIH.
The clear bloc k lock-bits operation is initiat ed using
a two-cycle command sequence. A Clear Block
Lock-Bits setup command is written followed by a
Confirm command. Then, the device automatically
outputs S tat us Regi st er data when read (see Figure
12). The CPU can detect completion of the clear
block lock-bits event by analyzing STS in level
RY/BY# mode or Status Register bit SR.7.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in Status
Register bits SR.4 and SR.5 being set to “1.” Also,
a reliable clear block lock-bits operation can only
occur when V CC = VCC1/2 and V PP = VPPH. If a clear
block lock-bits operation is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to “1.” In the
absence of these voltages, the block lock-bits
contents are protected against alteration. A
successful clear block lock-bits operation requires
that WP# = VIH.
If a cl ear block loc k-bits operati on is aborted due t o
VPP or VCC transiti oning out of vali d range or RP# or
WP# active transition, block lock-bit values are left
in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit
contents to known values.
When the operation i s compl ete, St atus Regis ter bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the Status Register should be
cleared. The CUI will remain in read S tatus Regis ter
mode until another command is issued.
E28F160S5, 28F320S5
29
ADVANCE INFORMATION
Table 13. Write Protection Alternatives
Operation Bloc
k
Lock-
Bit WP# Effect
Program and 0 VIL or VIH Block erase and programming enabled
Block Erase 1 VIL Block is locked. Block erase and programming disabled
VIH Block Lock-Bit override. Block erase and programming enabled
Full Chip Erase 0,1 VIL All unlocked blocks are erased
XV
IH Block Lock-Bit override. All blocks are erased
Set or Clear X VIL Set or clear block lock-bit disabled
Block Lock-Bit VIH Set or clear block lock-bit enabled
Table 14. Configuration Coding Definitions
Reserved Pulse on
Write
Complete
Pulse on
Erase
Complete
bits 7–2 bit 1 bit 0
DQ7–DQ2 = Reserved
DQ1/DQ0 = STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Flash Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high
when the operation indicated by the given
configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits D7–D2 to 00h) are as
follows:
Default RY/BY# level mode B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Flash-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
DQ7–DQ2 are reserved for future use.
default (DQ1/DQ0 = 00) RY/BY#, level mode
-----used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
configuration 01 ER INT, pulse mode(1)
-----used to generate a system interrupt pulse when
any flash device in an array has completed a block
erase or sequence of queued block erases. Helpful
for reformatting blocks after file system free space
reclamation or ‘cleanup’
configuration 10 PR INT, pulse mode(1)
-----used to generate a system interrupt pulse when
any flash device in an array has complete a
program operation. Provides highest performance
for servicing continuous buffer write operations.
configuration ER/PR INT, pulse mode(1)
-----used to generate system interrupts to trigger
servicing of flash arrays when either erase or flash
program operations are completed when a common
interrupt service routine is desired.
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
28F160S5, 28F320S5 E
30 ADVANCE INFORMATION
Table 15. Status Register Definition
WSMS ESS ECLBS BWSLBS VPPS BWSS DPS R
765 4 3210
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check STS in RY/BY# mode or SR.7 to determine
block erase, programming, or lock-bit configuration
completion. SR.6-0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUSPEND STATUS
1 = Block erase suspended
0 = Block erase in progress/completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in block erasure or clear lock-bits
0 = Successful block erase or clear lock-bits
If both SR.5 and SR.4 are “1”s after a block erase
or lock-bit configuration attempt, an improper
command sequence was entered.
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in program or block lock-bit
0 = Successful program or set block lock-bit
SR.3 = V
PP
STATUS
1 = V
PP
low detect, operation abort
0 = VPP OK
SR.3 does not provide a continuous indication of
VPP level. The WSM interrogates and indicates the
VPP level only after a block erase, program, or lock-
bit configuration operation. SR.3 reports accurate
feedback only when VPP = VPPH.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program suspended
0 = Program in progress/completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or
RP# lock detected, operation abort
0 = Unlock
SR.1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bit, and WP# only after a block erase,
program, or lock-bit configuration operation. It
informs the system, depending on the attempted
operation, if the block lock-bit is set.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS SR.0 is reserved for future use and should be
masked when polling the Status Register.
Table 16. Extended Status Register Definition
WBS R R R R R R R
765 4 3210
NOTES:
XSR.7 = WRITE BUFFER STATUS
1 = Write to buffer available
0 = Write to buffer not available
After a Write to buffer command, XSR.7 indicates
that another Write to buffer command is possible.
XSR.6 = RESERVED FOR FUTURE
ENHANCEMENTS SR.6–0 are reserved for future use and should be
masked when polling the status register
E28F160S5, 28F320S5
31
ADVANCE INFORMATION
Bus
O
p
eration Command Comments
Write Write to
Buffer Data = E8h
Addr = Block Address
Read XSR.7=valid
Addr = X
Standby Check XSR.7
1 = Write buffer available
0 = Write buffer not available
Write
(
Note 1
,
2
)
Data = N = word/byte count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(
Note 3
,
4
)
Data = write buffer data
Addr = device start address
Write
(
Note 5
,
6
)
Data = write buffer data
Addr = device address
Write Buffer
write to flash
confirm
Data = D0h
Addr = X
Read Status Register data
CE# & OE# low updates SR
Addr = X
Standby Check SR.7
1 = WSM ready
0 = WSM busy
1. Byte- or word-count values on DQ0-7 are loaded into
the Count register.
2. The device now outputs the Status Register when
read (XSR is no longer available).
3. Write Buffer contents will be programmed at the
device start address or destination flash address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance.
5. The device aborts the Write to Buffer command if the
current address is outside of the original block
address.
6. The Status Register indicates an “improper command
sequence” if the Write to Buffer command is aborted.
Follow this with a Clear Status Register command.
Full status check can be done after all Erase and
Write sequences complete. Write FFh after the last
operation to reset the device to Read Array mode.
Start
Write Word or Byte
Count, Block Address
Write Buffer Data,
Start Address
X = 0
X = X + 1
Write Next Buffer Data,
Device Address
Abort Buffer
Write
Command?
X = N
Another
Buffer
Write?
Read
Status Register
SR.7 =
Buffer Write to
Flash Complete
Read Extended
Status Register
XSR.7 =
1
No
Yes
No
No
1
Buffer Write to
Flash Aborted
Yes
No
Yes
Full Status
Check if Desired
Buffer Write to Flash
Confirm D0H
Issue Write Command
E8H, Block Address
Write to Another
Block Address
Write Buffer
Time-Out?
0
Yes
Suspend
Write?
Yes
Suspend
Write Loop
Set Time-Out
Issue Read
Status Command
No
0
0608_07
Figure 6. Write to Buffer Flowchart
28F160S5, 28F320S5 E
32 ADVANCE INFORMATION
0608_08
Figure 7. Single Byte/Word Program Flowchart
E28F160S5, 28F320S5
33
ADVANCE INFORMATION
0608_09
Figure 8. Program Suspend/Resume Flowchart
28F160S5, 28F320S5 E
34 ADVANCE INFORMATION
Bus
O
p
eration Command Comments
Write Erase Block Data = 28h or 20h
Addr = Block Addre ss
Read XSR.7=valid
Addr = X
Standby Check XSR.7
1 = Eras e queue avail able
0 = No Erase queue available
Write Erase Block Data = 28H
Addr = Block Addre ss
Read SR. 7= v al id; SR .6-0=X
With the device en abled,
OE# low updates SR
Addr = X
Standby Check XSR.7
1 = Eras e queue avail able
0 = No Erase queue available
Write
(Note 1) Erase
Confirm Data = D0H
Addr = X
Read St atus Register dat a
With the device en abled,
OE# low updates SR
Addr = X
Standby Check SR.7
1 = WSM ready
0 = WSM busy
1. The Eras e C onf ir m b
y
te must follow Erase Setup when
the Eras e Queue sta tus (X SR .7)= 0.
Full status check ca n be done a fte r all Era se and Write
sequences complete. Write FFh after the last
operation to reset the device to Read Array mo de.
Erase Block
Time-Out?
Start
Read
Status Register
SR.7 =
Erase Flash
Block(s) Complete
0
1
No
Full Status
Check if Desired
Suspend
Erase
No
Yes
Device
Supports
Queuing
Issue Block Queue
Erase Command 28H,
Block Address
Read Extended Status
Register
Is Queue
Available?
XSR.7=
Another
Block
Erase?
Issue Erase Command
28H Block Address
Read Extended
Status Register
Write Confirm D0H
Block Address
Another
Block
Erase?
Is Queue
Full?
XSR.7=
0=Yes
1=No
Yes
No
1=Yes
Yes
Issue Single Block
Erase Command 20H,
Block Address
No
0=No
No
Suspend
Erase Loop
Yes
Yes
Write Confirm D0H
Block Address
Set Time-Out
Issue Read
Status Command
Queued Erase Section
(Include this section for compatibility
with future SCS-compliant devices)
0609_10
Figure 9. Block Erase Flowchart
E28F160S5, 28F320S5
35
ADVANCE INFORMATION
SR.7 = 0
1
Start
Write B0H
Read
Status Register
Write D0H
Block Erase Resumed
Bus
Operation Command Comments
Write Erase
Suspend
Read
Data = B0H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Status Register Data
Addr = X
Standby
SR.6 = Block Erase Completed
Write FFH
Read Array Data
0
1
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Standby
Data = D0H
Addr = X
Write Erase
Resume
Read Array
Data Write
Loop
Read or
Write? WriteRead
Done?
Yes
No
Figure 10. Block Erase Suspend/Resume Flowchart
28F160S5, 28F320S5 E
36 ADVANCE INFORMATION
SR.7 = 0
1
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Full Status
Check if Desired
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read
Status Register
Voltage Range Error
Bus
Operation Command Comments
Standby
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set
before full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Bus
Operation
Command Comments
Write
Write
Set
Block/Master
Lock-Bit Setup
Data = 01H (Block),
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Read
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Standby
SR.3 =
SR.4 = Set Lock-Bit Error
Set Lock-Bit Successful
Set
Block or Master
Lock-Bit Confirm
Status Register Data
Standby Check SR.4
1 = Set Lock-Bit Error
0
1
Device Protect Error
SR.1 =
1
0
SR.4,5 = Command Sequence
Error
Check SR.4,5
Both 1 = Command Sequence Error
Standby
Check SR.1
1 = Device Protect Detect
RST# = V
(Set Master Lock-Bit Operation)
RST# = V , Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
IH
IH
Check SR.3
1 = Programming Voltage Error
Detect
Figure 11. Set Block Lock-Bit Flowchart
E28F160S5, 28F320S5
37
ADVANCE INFORMATION
SR.7 = 0
1
Start
Write 60H
Write D0H
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read Status
Register
Voltage Range Error
1
0
Command Sequence
Error
SR.3 =
SR.5 =
SR.4,5 =
Clear Block Lock-Bits
Error
Bus
Operation Command Comments
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.5
1 = Clear Block Lock-Bits Error
Standby
Bus
Operation Command Comments
Write
Write
Clear Block
Lock-Bits Setup
Read
Data = 60H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the Clear Block Lock-Bits operation to place device
to read array mode.
Status Register Data
Standby
Clear Block
Lock-Bits Confirm Data = D0H
Addr = X
Clear Block Lock-Bits
Successful
Standby
0
1Device Protect ErrorSR.1=
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.1
1 = Device Protect Detect
RST# = V , Master Lock-Bit Is Set
IH
Figure 12. Clear Block Lock-Bits Flowchart
28F160S5, 28F320S5 E
38 ADVANCE INFORMATION
5.0 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
Intel provides three control inputs to accommodate
multiple memory connections: CEX# (CE0#, CE1#),
OE#, and RP#. Three-line control provides for:
a. Lowest possible memory power dissipation;
b. Data bus contention avoidance.
To use these control inputs efficiently, an address
decoder should enable CEx# while OE# should be
connected to all memory devices and the system’s
READ# cont rol line. Thi s ass ures that only selec ted
memory devices have active outputs, while de-
selected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 STS and WSM Polling
STS is an open drain output that should be
connected to VCC by a pull-up resistor to provide a
hardware form of detecting block erase, program,
and lock-bit configuration completion. In default
mode, it transitions low during execution of these
commands and returns to VOH when the WSM has
finished executing the internal algorithm. For
alternate STS pin configurations, see Section 4.10.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also VOH when the device
is in block erase suspend (with programming
inactive) or in reset/power-down mode.
5.3 Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. Standby current
levels, active current levels and transient peaks
produced by falling and rising edges of CEX# and
OE# are areas of interest. Two-line control and
proper decoupling capacitor selection will suppress
transient voltage peaks . Each dev ice s hould have a
0.1 µF ceramic capacitor connected between its
VCC and GND and VPP and GND. These high-
frequency, low-inductance capacitors should be
placed as close as possible to package leads.
Additionally, for every eight devices, a 4.7 µF
electrol y tic capacitor shoul d be pl aced at t he array’s
power supply connection between VCC and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
5.4 VPP Trace on Printed Circuit
Boards
Updating target-system resident flash memories
requires that the printed circuit board designer pay
attention to VPP power supply traces. The VPP pin
supplies the memory cell current for programming
and block erasing. Use similar trace widths and
layout considerations given to the VCC power bus.
Adequate VPP supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
5.5 VCC, VPP, RP# Transitions
Block erase, program, and lock -bit c onfi guration are
not guaranteed if RP# ≠ VIH, or if VPP or VCC fall
outside of a valid voltage range (VCC1/2 and VPPH).
If VPP error is detected, Status Register bit SR.3
and SR.4 or SR.5 are set to “1.” If RP# transitions
to VIL during block erase, program, or lock-bit
configuration, STS in level RY/BY# mode will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. Because the aborted
operation may leave data partially altered, the
command s equence must be repeated aft er normal
operation is restored.
5.6 Power-Up/Down Protection
The device offers protection against accidental
block erase, programming, or lock-bit configuration
during power transitions.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Sinc e both WE# and CEX# m ust be low f or a
command writ e, dri vi ng either i nput s ignal t o VIH will
inhibit writes. The CUI’s two-step command
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. RP# = VIL disables
the device regardless of its control inputs states.
E28F160S5, 28F320S5
39
ADVANCE INFORMATION
6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings
Temperature under Bias................ –40°C to +85°C
Storage Temperature................... –65°C to +125°C
Voltage On Any Pin
(except VCC and VPP )
....................................–0.5V to + VCC +0.5V(1)
VCC Supply Voltage ............–0.2V to + VCC+0.5V(1)
VPP Update Voltage during
Block Erase, Flash Write, and
Lock-Bit Configuration ........... –0.2V to +7.0V(2)
Output Short Circuit Current.....................100 mA(3)
NOTICE: This datasheet contains information on products
in the design phase of development. Do not finalize a
design with this information. Revised information will be
published when the product is available. Verify with your
local Intel Sales office that you have the latest datasheet
before finalizing a design
*
WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device
reliability.
NOTES:
1. All specified voltages are with respect to GND. Minimum
DC voltage is –0.5V on input/output pins and –0.2V on
VCC and VPP pins. During transitions, this level may
undershoot to –2.0V for periods <20 ns. Maximum DC
voltage on input/output pins and VCC is VCC +0.5V
which, during transitions, may overshoot to VCC +2.0V
for periods <20 ns.
2. Maximum DC voltage on VPP may overshoot to +7.0V
for periods <20 ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
4. Operating temperature is for extended product defined
by this specification.
6.2 Operating Conditions
Table 17. Temperature and VCC Operating Conditions (1)
Symbol Parameter Notes Min Max Unit Test Condition
TAOperating Temperature -40 +85 °C Ambient Temperature
VCC1 VCC Supply Voltage (5V ± 5%) 4.75 5.25 V
VCC2 VCC Supply Voltage (5V ± 10%) 4.50 5.50 V
NOTES:
1. Device operations in the VCC voltage ranges not covered in the table produce spurious results and should not be
attempted.
28F160S5, 28F320S5 E
40 ADVANCE INFORMATION
6.2.1 CAPACITANCE Table 18. Capacitance(1), TA = +25°C, f = 1 MHz
Symbol Parameter Typ Max Unit Condition
CIN Input Capacitance 6 8 pF VIN = 0.0V
COUT Output Capacitance 8 12 pF VOUT = 0.0V
NOTE:
1. Sampled, not 100% tested.
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
TEST POINTSINPUT OUTPUT
1.5
3.0
0.0
1.5
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 5.0V ± 5%
(High Speed Testing Configuration)
TEST POINTS
INPUT OUTPUT
2.0
0.8 0.8
2.0
2.4
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 5.0V ± 10%
(Standard Testing Configuration)
DEVICE
UNDER
TEST
1.3V
1N914
C
L
OUT
R = 3.3 k
L
Ω
C Includes Jig
Capacitance
L
Figure 15. Transient Equivalent Testing
Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration CL (pF)
VCC = 5.0V ± 5% 30
VCC = 5.0V ± 10% 100
E28F160S5, 28F320S5
41
ADVANCE INFORMATION
6.2.3 DC CHARACTERISTICS
Table 19. DC Characteristics, TA = –40oC to +85oC
Sym Parameter Notes Typ Max Unit Conditions
ILI Input Load Current 1 ±1µAV
CC = VCC Max
VIN = VCC or GND
ILO Output Leakage Current 1 ±10 µAV
CC = VCC Max
Vout = VCC or GND
ICCS VCC Standby Current 1,3,6 25 100 µA CMOS Inputs
VCC = VCC Max
CEX# = RP# = VCC ± 0.2V
0.4 2 mA TTL Inputs
VCC = VCC Max
CEX# = RP# = VIH
ICCD VCC Deep Power-Down Current 1 20 µA RP# = GND ± 0.2V
IOUT (RY/BY#) = 0 mA
ICCR VCC Read Current 1,5,6 50 mA CMOS Inputs
VCC = VCC Max
CEX# = GND
f = 8 MHz, IOUT = 0 mA
65 mA TTL Inputs
VCC = VCC Max
CEX# = VIL
f = 8 MHz, IOUT = 0 mA
ICCW VCC Programming and Set Lock-
Bit Current 1,7 35 mA VPP = VPPH
ICCE VCC Block Erase or Clear Block
Lock-Bits Current 1,7 30 mA VPP = VPPH
ICCWS
ICCES
VCC Program Suspend or Block
Erase Suspend Current 1,2 10 mA CEX# = VIH
IPPS
IPPR
VPP Standby or VPP Read
Current 1 ± 2 ± 15 µA VPP ≤ VCC
10 200 µA VPP ≥ VCC
IPPD VPP Deep Power-Down Current 1 0.1 5 µA RP# = GND ± 0.2V
IPPW V
PP
Program or Set Lock-Bit
Current 1,7 80 mA VPP = VPPH
IPPE V
PP
Block Erase or Clear Block
Lock-Bits Current 1,7 40 mA VPP = VPPH
IPPWS
IPPES
V
PP
Program Suspend or Block
Erase Suspend Current 1 10 200 µA VPP = VPPH
28F160S5, 28F320S5 E
42 ADVANCE INFORMATION
Table 19. DC Characteristics (Continued)
Sym Parameter Notes Min Max Unit Conditions
VIL Input Low Voltage 7 –0.5 0.8 V
VIH Input High Voltage 7 2.0 VCC + 0.5 V
VOL Output Low Voltage 3,7 0.45 V VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage (TTL) 3,7 2.4 V VCC = VCC Min
IOH = –2.5 mA
VOH2 Output High Voltage (CMOS) 3,7 0.85 ×
VCC VV
CC = VCC Min
IOH = –2.5 mA
VCC – 0.4 V VCC = VCC Min
IOH = –100 µA
VPPLK VPP Lockout Voltage 4,7 1.5 V
VPPH VPP Voltage 4 4.5 5.5 V
VLKO VCC Lockout Voltage 8 2.0 V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
2. ICCWS and ICCES are specified with the device de-selected. If read or programmed while in erase suspend mode, the
device’s current is the sum of ICCWS or ICCES and ICCR or ICCW.
3. Includes STS in level RY/BY# mode.
4. Block erase, program, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range between
VPPLK (max) and VPPH (min), and above VPPH (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5V VCC static operation.
6. CMOS inputs are either VCC ± 0.2V or GND ± 0.2V. TTL inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. With VCC ≤ VLKO flash memory writes are inhibited.
E28F160S5, 28F320S5
43
ADVANCE INFORMATION
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
Table 20. AC Read Characteristics (1,5), TA = –40oC to +85oC
Versions(4) 5V ± 5% VCC -70/-90
(All units in ns unless otherwise noted) 5V ± 10% VCC -80/-100 -100/-110
# Sym Parameter Notes Min Max Min Max Min Max
R1 tAVAV Read/Write Cycle Time 16 Mbit 1 70 80 100
32 Mbit 1 90 100 110
R2 tAVQV Address to Output Delay 16 Mbit 1 70 80 100
32 Mbit 1 90 100 110
R3 tELQV CEX# to Output Delay 16 Mbit 2 70 80 100
32 Mbit 2 90 100 110
R4 tPHQV RP# High to Output Delay 400 400 400
R5 tGLQV OE# to Output Delay 2 30 35 40
R6 tELQX CEX# to Output in Low Z 3 0 0 0
R7 tEHQZ CEX# High to Output in High Z 3 25 30 35
R8 tGLQX OE# to Output in Low Z 3 0 0 0
R9 tGHQZ OE# High to Output in High Z 3 10 10 15
R10 tOH Output Hold from Address, CEX#, or
OE# Change, Whichever Occurs First 3000
R11 tELFL
tELFH
CEX# Low to BYTE# High or Low 3 5 5 5
R12 tFLQV
tFHQV
BYTE# to Output Delay 16 Mbit 3 70 80 100
32 Mbit 3 90 100 110
R13 tFLQZ BYTE# to Output in High Z 3 25 30 30
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact on tELQV.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Figures 13 through 15 for testing characteristics.
28F160S5, 28F320S5 E
44 ADVANCE INFORMATION
Note: CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.
0608_17
Figure 16. AC Waveform for Read Operations
E28F160S5, 28F320S5
45
ADVANCE INFORMATION
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
Table 21. Write Operations(1,6), TA = –40°C to +85°C
Versions(6) 5V ± 5%
5V ± 10% VCC Valid for All
Speeds
#Sym Parameter Notes Min Max Unit
W1 tPHWL (tPHEL)RP# High Recovery to WE# (CEX# ) Going Low 2 1 µs
W2 tELWL CEX# Setup to WE# Going Low 10 ns
(tWLEL)(WE# Setup to CEX# Going Low) 0 ns
W3 tWLWH WE# Pulse Width 40 ns
(tELEH)(CEX# Pulse Width) 50 ns
W4 tDVWH (tDVEH)Data Setup to WE# (CEX# ) Going High 3 40 ns
W5 tAVWH (tAVEH)Address Setup to WE# (CEX# ) Going High 3 40 ns
W6 tWHEH CEX# Hold from WE# High 10 ns
(tEHWH)(WE# Hold from CEX# High) 0 ns
W7 tWHDX (tEHDX)Data Hold from WE# (CEX# ) High 5 ns
W8 tWHAX (tEHAX)Address Hold from WE# (CEX# ) High 5 ns
W9 tWHWL WE# Pulse Width High 30 ns
(tEHEL)(CEX# Pulse Width High) 25 ns
W10 tSHWH (tSHEH)WP# VIH Setup to WE# (CEX# ) Going High 100 ns
W11 tVPWH (tVPEH)VPP Setup to WE# (CEX# ) Going High 2 100 ns
W12 tWHGL (tEHGL)Write Recovery before Read 0 ns
W13 tWHRL (tEHRL)WE# High to STS in RY/BY# Low 90 ns
W14 tQVSL WP# VIH Hold from Valid SRD 2,4 0 ns
W15 tQVVL VPP Hold from Valid SRD, STS in RY/BY# High 2,4 0 ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration.
4. VPP should be at VPPH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Figures 13 through 15 for testing characteristics.
28F160S5, 28F320S5 E
46 ADVANCE INFORMATION
NOTES:
A. VCC power-up and standby.
B. Write block erase or program setup.
C. Write block erase confirm or valid address and data..
D. Automated erase or program delay.
E. Read Status Register data.
F. Write Read Array command.
CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.
0608_18
Figure 17. AC Waveform for Write Operations
E28F160S5, 28F320S5
47
ADVANCE INFORMATION
6.2.6 RESET OPERATIONS
Figure 18. AC Waveform for Reset Operation
Table 22. Reset AC Specifications(1)
# Sym Parameter Notes Min Max Unit
P1 tPLPH RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable) 100 ns
P2 tPLRH RP# Low to Reset during Block Erase, Program, or Lock-
Bit Configuration 2,3 12 µs
P3 t5VPH VCC at 4.5V to RP# High 50 µs
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complete
within tPLPH.
3. A reset time, tPHQV, is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.
28F160S5, 28F320S5 E
48 ADVANCE INFORMATION
6.2.7 ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE
Table 23. Erase/Write/Lock Performance(3,4)
5V ± 5%,
5V ± 10% VCC
Version 5V VPP
# Sym Parameter Notes Typ(1) Max Units
W16 Byte/word program time (using write buffer) 5 2 TBD µs
W16 tWHQV1
tEHQV1
Per byte program time (without write buffer) 2 9.24 TBD µs
W16 tWHQV1
tEHQV1
Per word program time (without write buffer) 2 9.24 TBD µs
W16 Block program time (byte mode) 2 0.5 TBD sec
W16 Block program time (word mode) 2 0.38 TBD sec
W16 Block program time (using write buffer) 2 0.13 TBD sec
W16 tWHQV2
tEHQV2
Block erase time 2 0.34 TBD sec
W16 Full chip erase time 16 Mbit 10.7 sec
32 Mbit 21.4 sec
W16 tWHQV3
tEHQV3
Set Lock-Bit time 2 9.24 TBD µs
W16 tWHQV4
tEHQV4
Clear block lock-bits time 2 0.34 TBD sec
W16 tWHRH1
tEHRH1
Program suspend latency time to read 5.6 7 µs
W16 tWHRH2
tEHRH2
Erase suspend latency time to read 9.4 13.1 µs
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled but not 100% tested.
5. Uses whole buffer.
E28F160S5, 28F320S5
49
ADVANCE INFORMATION
APPENDIX A
DEVICE NOMENCLATURE AND ORDERING
INFORMATION
Product line designator for all Intel Flash products
Package
DT = Extended Temp.
56-Lead SSOP
TE = Extended Temp.
56-Lead TSOP Device Type
5 = 5V VCC, 5V VPP
E28F1 06 S5 -7
Access Speed (ns)
0
70 ns (5V, 30 pF), 80 ns (5V)
Product Family
S = FlashFile™ Memory
Device Density
160 = 16-Mbit
320 = 32-Mbit
T
0609_20
Order Code by Density Valid Operational Combinations
16 Mb 32 Mb 10% VCC
100 pF load
(16 Mb / 32 Mb)
5% VCC
30
p
F load
(16 Mb / 32 Mb)
E28F160S5-70 E28F320S5-90 -80 / -100 -70 / -90
E28F160S5-100 E28F320S5-110 -100 / -110
DA28F160S5-70 DA28F320S5-90 -80 / -100 -70 / -100
DA28F160S5-100 DA28F320S5-110 -100 / -110
28F160S5, 28F320S5 E
50 ADVANCE INFORMATION
APPENDIX B
ADDITIONAL INFORMATION(1,2)
Order Number Document/Tool
290608
Word-Wide FlashFile™Memory Family 28F160S3, 28F320S3
Datasheet
292203
AP-645 28F160S3/S5 Compatibility with 28F016SA/SV
292204
AP-646 Common Flash Interface and Command Sets
290528
28F016SV 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory
Datasheet
290489
28F016SA 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile™ Memory
Datasheet
297372
16-Mbit Flash Product Family User’s Manual
292123
AP-374 Flash Memory Write Protection Techniques
292144
AP-393 28F016SV Compatibility with 28F016SA
292159
AP-607 Multi-Site Layout Planning with Intel’s FlashFile™ Components,
Including ROM Capability
292163
AP-610 Flash Memory In-System Code and Data Update Techniques
Contact Intel/Distribution
Sales Office
CFI - Common Flash Interface Reference Code
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.
