LM27222M/NOPB - NATIONAL SEMICONDUCTOR

VCC

LEN

GND

LM27222 1

(to controller)

VCC

4V to 6.85V

D1 C2

0.33 PF

C1 Q1

VIN

VOUT

C4 +

up to 30V

0.5V to

Vin - 0.5V

LM27222

www.ti.com

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

LM27222 High-Speed 4.5A Synchronous MOSFET Driver

Check for Samples: LM27222

1FEATURES DESCRIPTION

The LM27222 is a dual N-channel MOSFET driver

2• Adaptive Shoot-through Protection designed to drive MOSFETs in push-pull

• 10ns Dead Time configurations as typically used in synchronous buck

• 8ns Propagation Delay regulators. The LM27222 takes the PWM output from

a controller and provides the proper timing and drive

• 30ns Minimum On-time levels to the power stage MOSFETs. Adaptive shoot-

• 0.4ΩPull-down and 0.9ΩPull-up Drivers through protection prevents damaging and efficiency

• 4.5A Peak Driving Current reducing shoot-through currents, thus ensuring a

robust design capable of being used with nearly any

• MOSFET Tolerant Design MOSFET. The adaptive shoot-through protection

• 5µA Quiescent Current circuitry also reduces the dead time down to as low

• 30V Maximum Input Voltage in Buck as 10ns, ensuring the highest operating efficiency.

Configuration The peak sourcing and sinking current for each driver

of the LM27222 is about 3A and 4.5Amps

• 4V to 6.85V Operating Voltage respectively with a Vgs of 5V. System performance is

• SOIC-8 and WSON Packages also enhanced by keeping propagation delays down

to 8ns. Efficiency is once again improved at all load

APPLICATIONS currents by supporting synchronous, non-

synchronous, and diode emulation modes through the

• High Current Buck And Boost Voltage LEN pin. The minimum output pulse width realized at

Converters the output of the MOSFETs is as low as 30ns. This

• Fast Transient DC/DC Power Supplies enables high operating frequencies at very high

• Single Ended Forward Output Rectification conversion ratios in buck regulator designs. To

support low power states in notebook systems, the

• CPU And GPU Core Voltage Regulators LM27222 draws only 5µA from the 5V rail when the

IN and LEN inputs are low or floating.

Typical Application

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LEN

Shoot-through

Protection

VCC

GND

Logic

150k

Level

Shifter

10k

VCC

LEN

GND

SW 1

LM27222

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

www.ti.com

Connection Diagram

Figure 1. Top View

SOIC-8 (Package # D0008A) θJA = 172°C/W

WSON-8 (Package # NGT0008A) θJA = 39°C/W

PIN DESCRIPTIONS

Pin # Pin Name Pin Function

1 SW High-side driver return. Should be connected to the common node of high and low-side MOSFETs.

2 HG High-side gate drive output. Should be connected to the high-side MOSFET gate. Pulled down internally to

SW with a 10K resistor to prevent spurious turn on of the high-side MOSFET when the driver is off.

3 CB Bootstrap. Accepts a bootstrap voltage for powering the high-side driver.

4 IN Accepts a PWM signal from a controller. Active High. Pulled down internally to GND with a 150K resistor to

prevent spurious turn on of the high-side MOSFET when the controller is inactive.

5 LEN Low-side gate enable. Active High. Pulled down internally to GND with a 150K resistor to prevent spurious

turn-on of the low-side MOSFET when the controller is inactive.

6 VCC Connect to +5V supply.

7 LG Low-side gate drive output. Should be connected to low-side MOSFET gate. Pulled down internally to GND

with a 10K resistor to prevent spurious turn on of the low-side MOSFET when the driver is off.

8 GND Ground.

Block Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM27222

LM27222

www.ti.com

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

Absolute Maximum Ratings (1)

VCC to GND -0.3V to 7V

CB to GND -0.3V to 36V

CB to SW -0.3V to 7V

SW to GND (2) -2V to 36V

LEN, IN, LG to GND -0.3V to VCC + 0.3V ≤7V

HG to GND -0.3V to 36V

Junction Temperature +150°C

Power Dissipation (3) 720mW

Storage Temperature −65° to 150°C

ESD Susceptibility

Human Body Model 2kV

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which

the device operates correctly. Operating Ratings do not imply ensured performance limits.

(2) The SW pin can have -2V to -0.5 volts applied for a maximum duty cycle of 10% with a maximum period of 1 second. There is no duty

cycle or maximum period limitation for a SW pin voltage range of -0.5V to 30 Volts.

(3) Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal

resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated

using: PMAX = (TJMAX-TA) / θJA. The junction-to-ambient thermal resistance, θJA, for the LM27222M, it is 165°C/W. For a TJMAX of 150°C

and TAof 25°C, the maximum allowable power dissipation is 0.76W. The θJA for the LM27222SD is 42°C/W. For a TJMAX of 150°C and

TA of 25°C, the maximum allowable power dissipation is 3W.

Operating Ratings (1)

VCC 4V to 6.85V

Junction Temperature Range −40° to 125°C

CB (max) 33V

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which

the device operates correctly. Operating Ratings do not imply ensured performance limits.

Product Folder Links: LM27222

LM27222

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

www.ti.com

Electrical Characteristics (1)

VCC = CB = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA= TJ=

+25°C. Limits appearing in boldface type apply over the entire operating temperature range (-40°C ≤TJ≤125°C).

Symbol Parameter Conditions Min Typ Max Units

POWER SUPPLY

Iq_op Operating Quiescent Current IN = 0V, LEN = 0V 5 15 µA

IN = 0V, LEN = 5V 500 540 650 µA

825

HIGH-SIDE DRIVER

Peak Pull-up Current 3 A

RH-pu Pull-up Rds_on ICB = IHG = 0.3A 0.9 2.5 Ω

Peak Pull-down Current 4.5 A

RH-pd Pull-down Rds_on ISW = IHG = 0.3A 0.4 1.5 Ω

t4Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns

t6Fall Time Timing Diagram, CLOAD = 3.3nF 12 ns

t3Pull-up Dead Time Timing Diagram 9.5 ns

t5Pull-down Delay Timing Diagram 16.5 ns

ton_min Minimum Positive Output 30 ns

Pulse Width

LOW-SIDE DRIVER

Peak Pull-up Current 3.2 A

RL-pu Pull-up Rds_on IVCC = ILG = 0.3A 0.9 2.5 Ω

Peak Pull-down Current 4.5 A

RL-pd Pull-down Rds_on IGND = ILG = 0.3A 0.4 1.5 Ω

t8Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns

t2Fall Time Timing Diagram, CLOAD = 3.3nF 14 ns

t7Pull-up Dead Time Timing Diagram 11.5 ns

t1Pull-down Delay Timing Diagram 7.7 ns

PULL-DOWN RESISTANCES

HG-SW Pull-down Resistance 10k Ω

LG-GND Pull-down 10k Ω

Resistance

LEN-GND Pull-down 150K Ω

Resistance

IN-GND Pull-down Resistance 150K Ω

LEAKAGE CURRENTS

Ileak_IN IN pin Leakage Current IN = 0V, Source Current 50 nA

IN = 5V, Sink Current 33 µA

Ileak_LEN LEN pin Leakage Current LEN = 0V, Source Current 200 nA

LEN = 5V, Sink Current 33 µA

LOGIC

VIH_LEN LEN Low to High Threshold Low to High Transition 65 % of VCC

VIL_LEN LEN High to Low Threshold High to Low Transition 30 % of VCC

VIH_IN IN Low to High Threshold Low to High Transition 65 % of VCC

VIL_IN IN High to Low Threshold High to Low Transition 30 % of VCC

Threshold Hysteresis 0.7 V

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

Product Folder Links: LM27222

LEN

400 ns/DIV

HG-SW

40 ns/DIV

HG-SW

40 ns/DIV

HG-SW

0.9V

t1t5t7t8

LM27222

www.ti.com

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

Timing Diagram

Typical Waveforms

Figure 2. PWM Low-to-High Transition at IN Input Figure 3. PWM High-to-Low Transition at IN Input

Figure 4. LEN Operation

The typical waveforms are from a circuit similar to Typical Application with:

Q1: 2 x Si7390DP

Q2: 2 x Si7356DP

L1: 0.4 µH

VIN: 12V

Product Folder Links: LM27222

20 40 60 80 100 120 140

tON (ns)

100

120

tON_SW (ns)

20 ns/DIV

HG-SW

LM27222

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

www.ti.com

APPLICATION INFORMATION

GENERAL

The LM27222 is designed for high speed and high operating reliability. The driver can handle very narrow, down

to zero, PWM pulses in a specified, deterministic way. Therefore, the HG and LG outputs are always in

predictable states. No latches are used in the HG and LG control logic so the drivers cannot get "stuck" in the

wrong state. The driver design allows for powering up with a pre-biasing voltage being present at the regulator

output. To reduce conduction losses in DC-DC converters with low duty factors the LM27222 driver can be

powered from a 6.5V ±5% power rail.

It is recommended to use the same power rail for both the controller and driver. If two different power rails are

used, never allow the PWM pulse magnitude at the IN input or the control voltage at the LEN input to be above

the driver VCC voltage or unpredictable HG and LG outputs pulse widths may result.

MINIMUM PULSE WIDTH

As the input pulse width to the IN pin is decreased, the pulse width of the high-side gate drive (HG-SW) also

decreases. However, for input pulse widths 60ns and smaller, the HG-SW remains constant at 30ns. Thus the

minimum pulse width of the driver output is 30ns. Figure 5 shows an input pulse at the IN pin 20ns wide, and the

output of the driver, as measured between the nodes HG and SW is a 30ns wide pulse. Figure 6 shows the

variation of the SW node pulse width vs IN pulse width. At the IN pin, if a falling edge is followed by a rising edge

within 5ns, the HG may ignore the rising edge and remain low until the IN pin toggles again. If a rising edge is

followed by a falling edge within 5ns, the pulse may be completely ignored.

Figure 5. Min On Time Figure 6.

ADAPTIVE SHOOT-THROUGH PROTECTION

The LM27222 prevents shoot-through power loss by ensuring that both the high- and low-side MOSFETs are not

conducting at the same time. When the IN signal rises, LG is first pulled down. The adaptive shoot-through

protection circuit waits for LG to reach 0.9V before turning on HG. Similarly, when IN goes low, HG is pulled

down first, and the circuit turns LG on only after the voltage difference between the high-side gate and the switch

node, i.e., HG-SW, has fallen to 0.9V.

It is possible in some applications that at power-up the driver's SW pin is above 3V in either buck or boost

comverter applications. For instance, in a buck configuration a pre-biasing voltage can be either a voltage from

anothert power rail connected to the load, or a leakage voltage through the load, or it can be an output capacitor

pre-charged above 3V while no significant load is present. In a boost application it can be an input voltage rail

above 3V.

Product Folder Links: LM27222

P = QG-H

fSW x VCC

RH-pu

RH-pu + RG-H +RH-pd

RH-pd + RG-H

+QG-L RL-pu

RL-pu + RG-L

RL-pd

RL-pd + RG-L

LM27222

www.ti.com

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

In the case of insufficient initial CB-SW voltage (less than 2V) such as when the output rail is pre-biased, the

shoot-through protection circuit holds LG low for about 170ns, beginning from the instant when IN goes high.

After the 170ns delay, the status of LG is dictated by LEN and IN. Once LG goes high and SW goes low, the

bootstrap capacitor will be charged up (assuming SW is grounded for long enough time). As a result, CB-SW will

be close to 5V and the LM27222 will now fully support synchronous operation.

The dead-time between the high- and low-side pulses is kept as small as possible to minimize conduction

through the body diode of the low-side MOSFET(s).

POWER DISSIPATION

The power dissipated in the driver IC when switching synchronously can be calculated as follows:

where

• where fSW = switching frequency

• VCC = voltage at the VCC pin

• QG_H = total gate charge of the (parallel combination of the) high-side MOSFET(s)

• QG_L = total gate charge of the (parallel combination of the) low-side MOSFET(s)

• RG_H = gate resistance of the (parallel combination of the) high-side MOSFET(s)

• RG_L = gate resistance of the (parallel combination of the) low-side MOSFET(S)

• RH_pu = pull-up RDS_ON of the high-side driver

• RH_pd = pull-down RDS_ON of the high-side driver

• RL_pu = pull-up RDS_ON of the low-side driver

• RL_pd = pull-down RDS_ON of the low-side driver (1)

PC BOARD LAYOUT GUIDELINES

1. Place the driver as close to the MOSFETs as possible.

2. HG, SW, LG, GND: Run short, thick traces between the driver and the MOSFETs. To minimize parasitics,

the traces for HG and SW should run parallel and close to each other. The same is true for LG and GND.

3. Driver VCC: Place the decoupling capacitor close to the VCC and GND pins.

4. The high-current loop between the high-side and low-side MOSFETs and the input capacitors should be as

small as possible.

5. There should be enough copper area near the MOSFETs and the inductor for heat dissipation. Vias may

also be added to carry the heat to other layers.

Product Folder Links: LM27222

GND

OUT1

CMP1

CMPREF

CMP2

VREF

VDD

LM27212

L1 R8

L2 R9

+C6

+C7

VCC5VIN

LM27222

SYNC1

SYNC2

OUT2

R2 R3

VCC

LEN

GND

VCC

LEN

GND

10:

0.1 PF

1.5:

121:

60.4:

1 PF,

6.3V

1 PF,

6.3V 0.33 PF

0.6 PH

30A 1 m:

270 PF x 3

ESR = 9 m:

/cap

VOUT

VIN

0.6 PH

30A

0.33 PF

10 PF x 6

1 m:

LM27222

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

www.ti.com

TYPICAL APPLICATION CIRCUIT DESCRIPITON

The Application Example on the following page shows the LM27222 being used with the LM27212, a 2-phase

hysteretic current mode controller. Although this circuit is capable of operating from 5V to 28V, the components

are optimized for an input voltage range of 9V to 28V. The high-side FET is selected for low gate charge to

reduce switching losses. For low duty cycles, the average current through the high-side FET is relatively small

and thus we trade off higher conduction losses for lower switching losses. The low-side FET is selected solely on

RDS_ON to minimize conduction losses. If the input voltage range were 4V to 6V, the MOSFET selection should

be changed. First, much lower voltage FETs can be used, and secondly, high-side FET RDS_ON becomes a larger

loss factor than the switching losses. Of course with a lower input voltage, the input capacitor voltage rating can

be reduced and the inductor value can be reduced as well. For a 4V to 6V application, the inductor can be

reduced to 200nH to 300nH. The switching frequency of the LM27212 is determined by the allowed ripple current

in the inductor. This circuit is set for approximately 300kHz. At lower input voltages, higher frequencies are

possible without suffering a significant efficiency loss. Although the LM27222 can support operating frequencies

up to 2MHz in many applications, the LM27212 should be limited to about 1MHz. The control architecture of the

LM27212 and the low propagation times of the LM27222 potentially gives this solution the fastest transient

response in the industry.

Application Example

* Q1, Q3: 2 x Si7390DP

** Q2, Q4: 2 x Si7356DP

Product Folder Links: LM27222

LM27222

www.ti.com

SNVS306B –SEPTEMBER 2004–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision A (March 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 8

Product Folder Links: LM27222

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM27222M NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 27222

LM27222M/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 27222

LM27222MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 27222

LM27222SD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L27222S

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM27222MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM27222SD/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM27222MX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM27222SD/NOPB WSON NGT 8 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

8X 0.35

0.25

3 0.05

2.4

2.6 0.05

6X 0.8

0.8 MAX

0.05

0.00

8X 0.5

0.3

A4.1

3.9 B

4.1

3.9

(0.2) TYP

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

PIN 1 ID 0.1 C A B

0.05 C

THERMAL PAD

EXPOSED

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

8X (0.3)

(3)

(3.8)

6X (0.8)

(2.6)

( 0.2) VIA

TYP (1.05)

(1.25)

8X (0.6)

(R0.05) TYP

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SYMM 9

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

(1.31)

(0.675)

8X (0.3)

8X (0.6)

(1.15)

(3.8)

(0.755)

6X (0.8)

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

METAL

TYP

SYMM 9

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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