11-/14-Bit, 5.7 GSPS,
RF Digital-to-Analog Converter
Data Sheet
AD9119/AD9129
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013-2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
DAC update rate: up to 5.7 GSPS
Direct RF synthesis at 2.85 GSPS data rate
DC to 1.425 GHz in baseband mode
DC to 1.0 GHz in 2× interpolation mode
1.425 GHz to 4.2 GHz in Mix-Mode
Bypassable 2× interpolation
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
8 QAM carriers: ACLR > 65 dBc
Industry-leading single/multicarrier IF or RF synthesis
4-carrier W-CDMA ACLR at 2457.6 MSPS
fOUT = 900 MHz, ACLR = 71 dBc (baseband mode)
fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode)
fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode)
Dual-port LVDS and DHSTL data interface
Up to 1.425 GSPS operation
Source synchronous DDR clocking with parity bit
Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS)
APPLICATIONS
Broadband communications systems
CMTS/VOD
Wireless infrastructure: W-CDMA, LTE, point-to-point
Instrumentation, automatic test equipment (ATE)
Radar, jammers
FUNCTIONAL BLOCK DIAGRAM
SDO
SDIO
SCLK
CS
DCI_x
DATA ASSEM BL ER
SPI
RESET
Tx DAC
CORE
DATA
LATCH
IOUTP
IOUTN
IRQ
4× FI FO
2×
BASEBAND
MODE
MIX-
MODE
FRM_x
(FRAME/
PARITY)
AD9129
CLOCK
DISTRIBUTION
VREFI250U
LVDS DDR
RECEIVER
LVDS DDR
RECEIVER
P1_D[13:0]P,
P1_D[13:0]N
P0_D[13:0]P,
P0_D[13:0]N
DLL
1.2V
PLL
DCO_x
NORMAL
11149-001
DACCLK_x
DCR
Figure 1.
GENERAL DESCRIPTION
The AD9119/AD9129 are high performance, 11-/14-bit RF digital-
to-analog converters (DACs) supporting data rates up to 2.85
GSPS. The DAC core is based on a quad-switch architecture that
enables dual-edge clocking operation, effectively increasing the
DAC update rate to 5.7 GSPS when configured for Mix-Mode™
or 2× interpolation. The high dynamic range and bandwidth
enable multicarrier generation up to 4.2 GHz.
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the AD9119/AD9129 can reconstruct
RF carriers in the second and third Nyquist zone while still
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
current can be programmed over a range of 9.5 mA to 34.4 mA.
The AD9119/AD9129 include several features that may further
simplify system integration. A dual-port, source synchronous
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
optimize timing between different clock domains.
A serial peripheral interface (SPI) configures the AD9119/
AD9129 and monitors the status of readback registers. The
AD9119/AD9129 are manufactured on a 0.18 µm CMOS
process and operates from +1.8 V and −1.5 V supplies. It is
supplied in a 160-ball chip scale package ball grid array.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
support RF signal synthesis of up to 4.2 GHz.
2. Dual-port interface with double data rate (DDR) LVDS
data receivers supports 2850 MSPS maximum conversion rate.
3. Manufactured on a CMOS process; a proprietary switching
technique enhances dynamic performance.
AD9119/AD9129 Data Sheet
Rev. B | Page 2 of 66
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
LVDS Digital Specifications ........................................................ 4
HSTL Digital Specifications ........................................................ 4
Serial Port and CMOS Pin Specifications ................................. 5
AC Specifications .......................................................................... 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 12
AD9119 ........................................................................................ 12
AD9129 ........................................................................................ 22
Terminology .................................................................................... 35
Serial Communications Port Overview ....................................... 36
Serial Peripheral Interface (SPI) ............................................... 36
General Operation of the SPI.................................................... 36
Instruction Mode (8-Bit Instruction) ...................................... 36
Serial Peripheral Interface Pin Descriptions .......................... 36
MSB/LSB Transfers .................................................................... 37
Serial Port Configuration .......................................................... 37
Theory of Operation ...................................................................... 38
LVDS Data Port Interface .......................................................... 39
Digital Datapath Description ................................................... 42
Reset ............................................................................................. 47
Interrupt Requests ...................................................................... 47
Interface Timing Validation .......................................................... 48
Sample Error Detection (SED) Operation .............................. 48
SED Example............................................................................... 48
Analog Interface Considerations .................................................. 49
Analog Modes of Operation ..................................................... 49
Clock Input.................................................................................. 50
PLL ............................................................................................... 50
Voltage Reference ....................................................................... 51
Analog Outputs .......................................................................... 51
Start-Up Sequence ...................................................................... 54
Device Configuration Registers .................................................... 55
Device Configuration Register Map ........................................ 55
Device Configuration Register Descriptions .......................... 56
Outline Dimensions ....................................................................... 66
Ordering Guide .......................................................................... 66
REVISION HISTORY
6/2017—Rev. A to Rev. B
Changes to Table 8 ............................................................................ 9
Changes to Table 9 .......................................................................... 11
Changes to Figure 87 ...................................................................... 27
Added Reset Section ....................................................................... 47
Changes to Figure 149 .................................................................... 51
Changes to Figure 156 .................................................................... 53
Changes to Bits[2:1] Description, Table 29 ................................. 59
Change to Bit 5 Access, Table 37 .................................................. 61
9/2013—Rev. 0 to Rev. A
Changes to Product Title ............................................................................ 1
Changes to Features Section and General Description Section ....... 1
Changes to Table 1 ........................................................................... 3
Changes to Table 2 and Table 3 ....................................................... 4
Changes to Dynamic Performance Parameter, Table 5 ............... 6
Changes to Figure 10 and Figure 13 ............................................. 13
Changes to Figure 21and Figure 23 .............................................. 15
Changes to Figure 24 and Figure 27 ............................................. 16
Changes to Figure 35 and Figure 37 ............................................. 18
Changes to Figure 62, Figure 65, and Figure 67 ......................... 23
Changes to Figure 76 and Figure 79 ............................................ 25
Changes to Figure 84, Figure 85, and Figure 87 ......................... 27
Changes to Figure 90 and Figure 92 ............................................ 28
Changes to Figure 95 and Figure 97 ............................................ 29
Changes to Figure 118 ................................................................... 33
Change to Serial Communications Port Overview Section .......... 36
Changes to Theory of Operation Section.................................... 38
Changes to LVDS Data Port Interface Section ........................... 39
Changes to Multiple DAC Synchronization Section ................. 44
Change to PLL Section .................................................................. 50
Change to Voltage Reference Section .......................................... 51
Change to Register 0x01, Table 16 ............................................... 54
Changes to Table 17 ....................................................................... 55
Changes to Bit 6, Table 37 ............................................................. 61
Changes to Table 49, Table 50, Table 51, and Table 52 .............. 63
Changes to Table 53, Table 54, Table 55, Table 56, and Table 57 ... 64
1/2013—Revision 0: Initial Version
Data Sheet AD9119/AD9129
Rev. B | Page 3 of 66
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C.
Table 1.
AD9119 AD9129
Parameter Min Typ Max Min Typ Max Unit
RESOLUTION 11 14 Bits
ACCURACY
Integral Nonlinearity (INL) 0.2 1.4 LSB
Differential Nonlinearity (DNL)
0.15
1.1
LSB
ANALOG OUTPUTS
Gain Error (with Internal Reference) +2.5 +2.5 %
Full-Scale Output Current Maximum 33.4 34.2 34.9 33.4 34.2 34.9 mA
Full-Scale Output Current Minimum
9.1
9.4
9.6
9.4
9.6
mA
Output Compliance Range 1.5 2.5 1.5 2.5 V
Output Impedance1
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
0.4
1
2
1
2
V
Common-Mode Voltage 1.2 1.2 V
TEMPERATURE DRIFT
Gain 60 60 ppm/°C
Reference Voltage 20 20 ppm/°C
REFERENCE
Internal Reference Voltage 1.0 1.0 V
Output Resistance 5 5 kΩ
ANALOG SUPPLY VOLTAGES
VDDA 1.70 1.80 1.90 1.70 1.80 1.90 V
FIR40 Enabled, DACCLK > 2600 MSPS 1.8 1.9 2.0 1.8 1.9 2.0 V
VSSA −1.4 −1.5 −1.6 −1.4 −1.5 −1.6 V
DIGITAL SUPPLY VOLTAGES
VDD
1.70
1.8
1.90
1.8
1.90
V
FIR40 Enabled, DACCLK > 2600 MSPS 1.8 1.9 2.0 1.8 1.9 2.0 V
SUPPLY CURRENTS AND POWER DISSIPATION, 2.3 GSPS
(NORMAL MODE)
IVDDA 202 209 202 209 mA
IVSSA 53 54 53 54 mA
IDVDD 307 327 307 327 mA
Power Dissipation
Normal Mode 1.0 1.05 1.0 1.05 W
FIR25 Enabled 1.17 1.24 1.17 1.24 W
FIR40 Enabled 1.3 1.4 1.3 1.4 W
Reduced Power Mode, Power-Down Enabled
(Register 0x01 = 0xEF)
I
VDDA
7.6
7.6
mA
IVSSA 6 6 µA
IVDD 0.4 0.4 mA
SUPPLY CURRENTS AND POWER DISSIPATION, 2.8 GSPS
(NORMAL MODE)
IVDDA 230 230 mA
IVSSA 53 53 mA
IDVDD 336 336 mA
Power Dissipation (Normal Mode) 1.1 1.1 W
1 For more information about output impedance, see the Output Stage Configuration section.
AD9119/AD9129 Data Sheet
Rev. B | Page 4 of 66
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE
Standard 1596.3-1996, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
LVDS DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N, FRM_P, FRM_N)
Px_DxP = VIA, Px_DxN = VIB
Input Voltage Range VIA, VIB 825 1575 mV
Input Differential Threshold VIDTH −100 +100 mV
Input Differential Hysteresis
V
IDTHH
− V
IDTHL
20
mV
Receiver Differential Input Impedance RIN 80 120 Ω
LVDS Input Rate 1425 MSPS
Input Capacitance 1.2 pF
LVDS CLOCK INPUTS (DCI_P, DCI_N) DCI_P = VIA, DCI_N = VIB
Input Voltage Range VIA, VIB 825 1575 mV
Input Differential Threshold VIDTH −225 +225 mV
Input Differential Hysteresis VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance RIN 80 120 Ω
Maximum Clock Rate 712.5 MHz
LVDS CLOCK OUTPUTS (DCO_P, DCO_N) DCO_P = VOA, DCO_N = VOB,
100 Ω termination
Output Voltage High VOA, VOB 1375 mV
Output Voltage Low VOA, VOB 1025 mV
Output Differential Voltage |VOA|, |VOB| Register 0x7C[7:6] = 01b (default) 200 225 250 mV
Output Offset Voltage VOS 1150 1250 mV
Output Impedance, Single-Ended RO 80 100 120 Ω
RO Mismatch Between A and B ∆RO 10 %
Change in |VOD| Between Setting 0 and Setting 1 |∆VOD| 25 mV
Change in VOS Between Setting 0 and Setting 1 ∆VOS 25 mV
Output Current
Driver Shorted to Ground ISA, ISB 20 mA
Drivers Shorted Together ISAB 4 mA
Power-Off Output Leakage |IXA|, |IXB| 10 µA
Maximum Clock Rate 712.5 MHz
HSTL DIGITAL SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC
JESD8-6 standard, unless otherwise noted.
Table 3.
Parameter Symbol Test Comments/Conditions Min Typ Max Unit
HSTL DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N,
P0_D[13:0]P, P0_D[13:0]N, FRM_P, FRM_N)
Px_DxP = VIA, Px_DxN = VIB
Common-Mode Input Voltage Range VIA, VIB 0.68 0.9 V
Differential Input Voltage 200 mV
Receiver Differential Input Impedance RIN 80 120 Ω
HSTL Input Rate 1425 MSPS
Input Capacitance 1.2 pF
HSTL CLOCK INPUT (DCI_P, DCI_N) DCI_P = VIA, DCI_N = VIB
Common-Mode Input Voltage Range VIA, VIB 0.68 0.9 mV
Differential Input Voltage 450 mV
Receiver Differential Input Impedance RIN 80 120 Ω
Maximum Clock Rate 712.5 MHz
Data Sheet AD9119/AD9129
Rev. B | Page 5 of 66
SERIAL PORT AND CMOS PIN SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C.
Table 4.
Parameter Symbol Test Comments/Conditions Min Typ Max Unit
WRITE OPERATION See Figure 126
SCLK Clock Rate fSCLK, 1/tSCLK 20 MHz
SCLK Clock High tHIGH 20 ns
SCLK Clock Low tLOW 20 ns
SDIO to SCLK Setup Time tDS 10 ns
SCLK to SDIO Hold Time tDH 5 ns
CS to SCLK Setup Time tS 10 ns
SCLK to CS Hold Time tH 5 ns
READ OPERATION See Figure 127
SCLK Clock Rate fSCLK, 1/tSCLK 20 MHz
SCLK Clock High tHIGH 20 ns
SCLK Clock Low tLOW 20 ns
SDIO to SCLK Setup Time tDS 10 ns
SCLK to SDIO Hold Time tDH 5 ns
CS to SCLK Setup Time tS 10 ns
SCLK to SDIO (or SDO) Data Valid Time tDV 10 ns
CS to SDIO (or SDO) Output Valid to High-Z tEZ 2
INPUTS (SDI, SDIO, SCLK, CS)
Voltage In High VIH 1.2 1.8 V
Voltage In Low VIL 0 0.4 V
Current In High IIH +75 µA
Current In Low IIL −150 µA
OUTPUTS (SDIO, SYNC)
Voltage Out High VOH 1.3 2.0 V
Voltage Out Low VOL 0 0.3 V
Current Out High IOH 4 mA
Current Out Low IOL 4 mA
AD9119/AD9129 Data Sheet
Rev. B | Page 6 of 66
AC SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
AD9119 AD9129
Parameter Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
DAC Update Rate (DACCLK_x Inputs)
Normal Mode, FIR25 Enabled, or FIR40 Enabled with VDD = 1.9 V 1400 2850 1400 2850 MSPS
FIR40 Filter Enabled, VDD = 1.8 V 1400 2600 1400 2600 MSPS
Adjusted DAC Update Rate1 1400 2850 1400 2850 MSPS
Output Settling Time to 0.1% 13 13 ns
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 2600 MSPS
fOUT = 100 MHz −76 −76 dBc
fOUT = 350 MHz −65 −65 dBc
fOUT = 550 MHz −63 −64 dBc
f
OUT
= 950 MHz
−55
−55
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 2600 MSPS, fOUT2 = fOUT1 + 1.4 MHz
fOUT = 100 MHz −82 −86 dBc
fOUT = 350 MHz −78 −85 dBc
fOUT = 550 MHz −73 −83 dBc
fOUT = 950 MHz −67 −76 dBc
NOISE SPECTRAL DENSITY (NSD)
Single Tone, fDAC = 2800 MSPS
fOUT = 100 MHz −157 −166 dBm/Hz
fOUT = 350MHz −157 −162 dBm/Hz
fOUT = 550 MHz −155 −158 dBm/Hz
fOUT = 850 MHz −154 −157 dBm/Hz
DOCSIS ACLR PERFORMANCE (50 MHz to 1000 MHz) at ≥6 MHz OFFSET
fDAC = 2782 MSPS
8 Contiguous Carriers 64 64 dBc
16 Contiguous Carriers 62 63 dBc
32 Contiguous Carriers 60 61 dBc
W-CDMA ACLR (SINGLE CARRIER)
Adjacent Channel
fDAC = 2605.056 MSPS, fOUT = 750 MHz 75 75 dBc
fDAC= 2605.056 MSPS, fOUT = 950 MHz 74 74 dBc
f
DAC
= 2605.056 MSPS, f
OUT
= 1700 MHz (Mix-Mode)
73.5
73.5
dBc
fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode) 69 69 dBc
Alternate Adjacent Channel
fDAC = 2605.056 MSPS, fOUT = 750 MHz 80 80 dBc
fDAC = 2605.056 MSPS, fOUT = 950 MHz 78 78 dBc
fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode) 74 74 dBc
fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode) 72 72 dBc
1 Adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9119/AD9129, the minimum interpolation factor is 1.
Thus, with fDAC = 2850 MSPS, fDAC adjusted = 2850 MSPS.
Data Sheet AD9119/AD9129
Rev. B | Page 7 of 66
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
DCI, DCO to VSS −0.3 V to VDD + 0.3 V
LVDS Data Inputs to VSS
−0.3 V to VDD + 0.3 V
IOUTP, IOUTN to VSSA VSSA − 0.3V to +2.5V
I250U, VREF to VSSA VSSA − 0.3 V to VDDA + 0.3 V
IRQ, CS, SCLK, SDO, SDIO, RESET,
SYNC to VSS
−0.3 V to VDD + 0.3 V
Junction Temperature 150°C
Operating Temperature Range
−40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θJA θJC Unit
160-Ball CSP_BGA 31.2 7.0 °C/W1
1 With no airflow movement.
ESD CAUTION
AD9119/AD9129 Data Sheet
Rev. B | Page 8 of 66
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VREF
VSSA
VDDA SH IOUTP IOUTN VDDA SH VDDA VDDA VDDA VSSC VSSC VSSC
VDDA
I250U
VSSA VSSA
VSSA
VDDA SH VDDA
DACCLK_N
VSS VSS VSS VSS
VSS VSS VSS VSS
CSSCLK DCI_P DCI_N FRM_P FRM_N
P1_D0P P1_D1P P1_D2P P1_D3P P1_D4P P1_D5P P1_D6P P1_D7P P1_D8P P1_D9P P1_D10P
VSSA VSSA
VSSCVDDA VDDA VSSC
VDDAVDDA VDDA
VSSA VDDA SH
VSSVSSCVDDA VDDA VSSC VSS
VSS VSS VSSVSSCVDDA VDDA
VSSC
VSSC
VSSC VSSCVSSC VSSCVSSC
DACCLK_P
VDDAVDDA VSSC
VSS VDD VDD VDD
VDD VDD VDD
VDD VDD VDD
VDD
VDD
VSSC
VSS VSSVSS
IRQRESET VSS VSS
VDD VDDSDOSDIO
P1_D0N P1_D1N P1_D2N P1_D3N P1_D4N P1_D5N P1_D6N P1_D7N P1_D8N P1_D9N P1_D10N
P0_D0P P0_D1P P0_D2P P0_D3P P0_D4P P0_D5P P0_D6P P0_D7P P0_D8P P0_D9P P0_D10P
P0_D0N P0_D1N P0_D2N P0_D3N P0_D4N P0_D5N P0_D6N P0_D7N P0_D8N P0_D9N P0_D10N
VDDAVDDA
VSSA VDDA
VDDAVDDA
VSSC VSSC
VSSC
DCO_P DCO_N
AD9119
NOTES
1. NC = NO CO NNE CT. DO NO T CO NNE CT TO T HIS PIN.
SYNC
NC NC NC
NC NC NC
NC NC NC
NC NC NC
11149-002
Figure 2. AD9119 Pin Configuration
Table 8. AD9119 Pin Function Descriptions
Pin No. Mnemonic Description
A1 I250U Nominal 1.0 V Reference. Tie this pin to VSSA via a 4.0 kΩ resistor to generate
a 250 µA reference current.
A2 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor.
A3, A4, B3, B4, B5, C4, C5, C6 VSSA −1.5 V Analog Supply Voltage Input.
A5, A8, B6, B7 VDDA SH +1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC.
A9, A10, A11, B1, B2, B8, B9, B10,
B11, C2, C3, C7, C8, C9, C10, D2,
D3, D4, D7, E1, E2
VDDA
+1.8 V Analog Supply Voltage Input.
Data Sheet AD9119/AD9129
Rev. B | Page 9 of 66
Pin No. Mnemonic Description
G12, G13, G14, H11, H12, H13,
H14, J3, J4, J11, J12, J13, J14
VDD +1.8 V Digital Supply Voltage Input.
C13, C14, D12, D13, D14, E11,
E12, E13, E14, F11, F12, F13, F14,
G1, G2, G3, G11, H3, H4
VSS +1.8 V Digital Supply Return.
A12, A13, A14, B12, B13, C11,
C12, D5, D6, D8, D9, D10, D11,
E3, E4, F1, F2, F3, F4, G4
VSSC Analog Supply Return.
A6 IOUTP DAC Positive Current Output Source.
A7 IOUTN DAC Negative Current Output Source.
B14 SYNC Synchronization Signal Output.
C1, D1 DACCLK_N, DACCLK_P Negative/Positive DAC Clock Input.
H1 RESET Reset Input. Active high. If unused, tie this pin to VSS.
H2 IRQ Interrupt Request Open Drain Output. Active high. Pull up this pin to VDD
with a 1 kΩ resistor.
J1 SDIO Serial Port Data Input/Output.
J2 SDO Serial Port Data Output.
K1 SCLK Serial Port Clock Input.
K2 CS Serial Port Enable Input.
K3, K4 DCI_P, DCI_N Positive, Negative Data Clock Input (DCI).
K11, K12 D CO _ P, DCO_N Positive, Negative Data Clock Output (DCO).
K13, K14 FRM_P, FRM_N Positive, Negative Data Frame/Parity Signal (FRAME/PARITY).
L1, M1 NC, NC No Connect. Do not connect to this pin.
L2, M2 NC, NC No Connect. Do not connect to this pin.
L3, M3 NC, NC No Connect. Do not connect to this pin.
L4, M4 P1_D0P, P1_D0N Data Port 1 Positive/Negative Data Input Bit 0. LSB.
L5, M5 P1_D1P, P1_D1N Data Port 1 Positive/Negative Data Input Bit 1.
L6, M6 P1_D2P, P1_D2N Data Port 1 Positive/Negative Data Input Bit 2.
L7, M7 P1_D3P, P1_D3N Data Port 1 Positive/Negative Data Input Bit 3.
L8, M8 P1_D4P, P1_D4N Data Port 1 Positive/Negative Data Input Bit 4.
L9, M9 P1_D5P, P1_D5N Data Port 1 Positive/Negative Data Input Bit 5.
L10, M10 P1_D6P, P1_D6N Data Port 1 Positive/Negative Data Input Bit 6.
L11, M11 P1_D7P, P1_D7N Data Port 1 Positive/Negative Data Input Bit 7.
L12,M12 P1_D8P, P1_D8N Data Port 1 Positive/Negative Data Input Bit 8.
L13, M13 P1_D9P, P1_D9N Data Port 1 Positive/Negative Data Input Bit 9.
L14, M14 P1_D10P, P1_D10N Data Port 1 Positive/Negative Data Input Bit 10. MSB.
N1, P1 NC, NC No Connect. Do not connect to this pin.
N2, P2 NC, NC No Connect. Do not connect to this pin.
N3, P3 NC, NC No Connect. Do not connect to this pin.
N4, P4 P0_D0P, P0_D0N Data Port 0 Positive/Negative Data Input Bit 0. LSB.
N5, P5 P0_D1P, P0_D1N Data Port 0 Positive/Negative Data Input Bit 1.
N6, P6 P0_D2P, P0_D2N Data Port 0 Positive/Negative Data Input Bit 2.
N7, P7 P0_D3P, P0_D3N Data Port 0 Positive/Negative Data Input Bit 3.
N8, P8 P0_D4P, P0_D4N Data Port 0 Positive/Negative Data Input Bit 4.
N9, P9 P0_D5P, P0_D5N Data Port 0 Positive/Negative Data Input Bit 5.
N10, P10 P0_D6P, P0_D6N Data Port 0 Positive/Negative Data Input Bit 6.
N11, P11 P0_D7P, P0_D7N Data Port 0 Positive/Negative Data Input Bit 7.
N12, P12 P0_D8P, P0_D8N Data Port 0 Positive/Negative Data Input Bit 8.
N13, P13
P0_D9P, P0_D9N
Data Port 0 Positive/Negative Data Input Bit 9.
N14, P14 P0_D10P, P0_D10N Data Port 0 Positive/Negative Data Input Bit 10. MSB.
AD9119/AD9129 Data Sheet
Rev. B | Page 10 of 66
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VREF
VSSA
VDDA SH IOUTP IOUTN VDDA SH VDDA VDDA VDDA VSSC VSSC VSSC
VDDA
I250U
VSSA VSSA
VSSA
VDDA SH VDDA
DACCLK_N
VSS VSS VSS VSS
VSS VSS VSS VSS
SCLK DCI_P DCI_N FRM_P FRM_N
P1_D3P P1_D4P P1_D5P P1_D6P P1_D7P P1_D8P P1_D9P P1_D10P P1_D11P P1_D12P P1_D13P
VSSA VSSA
VSSCVDDA VDDA VSSC
VDDAVDDA VDDA
VSSA VDDA SH
VSSVSSCVDDA VDDA VSSC VSS
VSS VSS VSSVSSCVDDA VDDA
VSSC
VSSC
VSSC VSSCVSSC VSSCVSSC
DACCLK_P
VDDAVDDA VSSC
VSS VDD VDD VDD
VDD VDD VDD
VDD VDD VDD
VDD
VDD
VSSC
VSS VSSVSS
IRQRESET VSS VSS
VDD VDDSDOSDIO
P1_D3N P1_D4N P1_D5N P1_D6N P1_D7N P1_D8N P1_D9N P1_D10N P1_D11N P1_D12N P1_D13N
P0_D3P P0_D4P P0_D5P P0_D6P P0_D7P P0_D8P P0_D9P P0_D10P P0_D11P P0_D12P P0_D13P
P0_D3N P0_D4N P0_D5N P0_D6N P0_D7N P0_D8N P0_D9N P0_D10N P0_D11N P0_D12N P0_D13N
VDDAVDDA
VSSA VDDA
VDDAVDDA
VSSC VSSC
VSSC
DCO_P DCO_N
AD9129
SYNC
P1_D0P P1_D1P P1_D2P
P1_D0N P1_D1N P1_D2N
P0_D0P P0_D1P P0_D2P
P0_D0N P0_D1N P0_D2N
11149-003
CS
Figure 3. AD9129 Pin Configuration
Table 9. AD9129 Pin Function Descriptions
Pin No. Mnemonic Description
A1 I250U Nominal 1.0 V Reference. Tie this pin to VSSA via a 4.0 kΩ resistor to generate
a 250 µA reference current.
A2 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor.
A3, A4, B3, B4, B5, C4, C5, C6 VSSA −1.5 V Analog Supply Voltage Input.
A5, A8, B6, B7 VDDA SH +1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC.
A9, A10, A11, B1, B2, B8, B9, B10,
B11, C2, C3, C7, C8, C9, C10, D2,
D3, D4, D7, E1, E2
VDDA
+1.8 V Analog Supply Voltage Input.
G12, G13, G14, H11, H12, H13,
H14, J3, J4, J11, J12, J13, J14
VDD +1.8 V Digital Supply Voltage Input.
C13, C14, D12, D13, D14, E11,
E12, E13, E14, F11, F12, F13, F14,
G1, G2, G3, G11, H3, H4
VSS +1.8 V Digital Supply Return.
Data Sheet AD9119/AD9129
Rev. B | Page 11 of 66
Pin No. Mnemonic Description
A12, A13, A14, B12, B13, C11,
C12, D5, D6, D8, D9, D10, D11,
E3, E4, F1, F2, F3, F4, G4
VSSC Analog Supply Return.
A6 IOUTP DAC Positive Current Output Source.
A7
IOUTN
DAC Negative Current Output Source.
B14 SYNC Synchronization Signal Output.
C1, D1 DACCLK_N, DACCLK_P Negative/Positive DAC Clock Input.
H1 RESET Reset Input. Active high. If unused, tie this pin to VSS.
H2 IRQ Interrupt Request Open-Drain Output. Active high. Pull up this pin to VDD
with a 1 kΩ resistor.
J1 SDIO Serial Port Data Input/Output.
J2 SDO Serial Port Data Output.
K1 SCLK Serial Port Clock Input.
K2 CS Serial Port Enable Input.
K3, K4 DCI_P, DCI_N Positive, Negative Data Clock Input (DCI).
K11, K12
D CO _ P, DCO_N
Positive, Negative Data Clock Output (DCO).
K13, K14 FRM_P, FRM_N Positive, Negative Data Frame/Parity Signal (FRAME/PARITY).
L1, M1 P1_D0P, P1_D0N Data Port 1 Positive/Negative Data Input Bit 0. LSB.
L2, M2 P1_D1P, P1_D1N Data Port 1 Positive/Negative Data Input Bit 1.
L3, M3 P1_D2P, P1_D2N Data Port 1 Positive/Negative Data Input Bit 2.
L4, M4 P1_D3P, P1_D3N Data Port 1 Positive/Negative Data Input Bit 3.
L5, M5 P1_D4P, P1_D4N Data Port 1 Positive/Negative Data Input Bit 4.
L6, M6 P1_D5P, P1_D5N Data Port 1 Positive/Negative Data Input Bit 5.
L7, M7 P1_D6P, P1_D6N Data Port 1 Positive/Negative Data Input Bit 6.
L8, M8 P1_D7P, P1_D7N Data Port 1 Positive/Negative Data Input Bit 7.
L9, M9 P1_D8P, P1_D8N Data Port 1 Positive/Negative Data Input Bit 8.
L10, M10 P1_D9P, P1_D9N Data Port 1 Positive/Negative Data Input Bit 9.
L11, M11 P1_D10P, P1_D10N Data Port 1 Positive/Negative Data Input Bit 10.
L12,M12 P1_D11P, P1_D11N Data Port 1 Positive/Negative Data Input Bit 11.
L13, M13 P1_D12P, P1_D12N Data Port 1 Positive/Negative Data Input Bit 12.
L14, M14 P1_D13P, P1_D13N Data Port 1 Positive/Negative Data Input Bit 13. MSB.
N1, P1 P0_D0P, P0_D0N Data Port 0 Positive/Negative Data Input Bit 0. LSB.
N2, P2
P0_D1P, P0_D1N
Data Port 0 Positive/Negative Data Input Bit 1.
N3, P3 P0_D2P, P0_D2N Data Port 0 Positive/Negative Data Input Bit 2.
N4, P4 P0_D3P, P0_D3N Data Port 0 Positive/Negative Data Input Bit 3.
N5, P5 P0_D4P, P0_D4N Data Port 0 Positive/Negative Data Input Bit 4.
N6, P6 P0_D5P, P0_D5N Data Port 0 Positive/Negative Data Input Bit 5.
N7, P7 P0_D6P, P0_D6N Data Port 0 Positive/Negative Data Input Bit 6.
N8, P8 P0_D7P, P0_D7N Data Port 0 Positive/Negative Data Input Bit 7.
N9, P9 P0_D8P, P0_D8N Data Port 0 Positive/Negative Data Input Bit 8.
N10, P10 P0_D9P, P0_D9N Data Port 0 Positive/Negative Data Input Bit 9.
N11, P11 P0_D10P, P0_D10N Data Port 0 Positive/Negative Data Input Bit 10.
N12, P12 P0_D11P, P0_D11N Data Port 0 Positive/Negative Data Input Bit 11.
N13, P13 P0_D12P, P0_D12N Data Port 0 Positive/Negative Data Input Bit 12.
N14, P14 P0_D13P, P0_D13N Data Port 0 Positive/Negative Data Input Bit 13. MSB.
AD9119/AD9129 Data Sheet
Rev. B | Page 12 of 66
TYPICAL PERFORMANCE CHARACTERISTICS
AD9119
Static Linearity
IOUTFS = 28 mA, nominal supplies, TA = 25°C, unless otherwise noted.
CODE
INL (LSB)
–0.2
–0.1
0
0.1
0.2
0.3
0200 400 600 800 1000 1200 1400 1600 1800 2000
11149-004
Figure 4. Typical INL, 11 mA at 25°C
INL (LSB)
–0.2
–0.1
0
0.1
0.2
0.3
CODE
0200 400 600 800 1000 1200 1400 1600 1800 2000
11149-005
Figure 5. Typical INL, 22 mA at 25°C
INL (LSB)
–0.2
–0.1
0
0.1
0.2
0.3
CODE
0200 400 600 800 1000 1200 1400 1600 1800 2000
11149-006
Figure 6. Typical INL, 33 mA at 25°C
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
CODE
DNL (LSB)
0200 400 600 800 1000 1200 1400 1600 1800 2000
11149-007
Figure 7. Typical DNL, 11 mA at 25°C
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
CODE
DNL (LSB)
0200 400 600 800 1000 1200 1400 1600 1800 2000
11149-008
Figure 8. Typical DNL, 22 mA at 25°C
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
CODE
DNL (LSB)
0200 400 600 800 1000 1200 1400 1600 1800 2000
11149-009
Figure 9. Typical DNL, 33 mA at 25°C
Data Sheet AD9119/AD9129
Rev. B | Page 13 of 66
AC (Normal Mode)
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–95 START 20M Hz
RES BW 20kHz VBW 20kHz SWEEP 7.78s (1001 p t s)
REF 5dBm ATTEN: 24dB
10dB/DIV
STOP 2.6GHz
–85
–75
–65
–55
–45
–35
–25
–5
–15
5
11149-011
Figure 10. Single-Tone Spectrum at fOUT = 70 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 0200 400 600 800 1000 1200 1400
SFDR ( dBc)
f
OUT
(MHz)
1400MSPS
1600MSPS
2200MSPS
2600MSPS
2800MSPS
11149-013
Figure 11. SFDR vs. fOUT over fDAC
–145
–150
–155
–160
–165
–170 0200 400 600 800 1000 1200 1400
NSD (d Bm/Hz)
f
OUT
(MHz)
1600MSPS
2200MSPS
2800MSPS
11149-015
Figure 12. Single-Tone NSD vs. fOUT
–95 START 20M Hz
RES BW 20kHz VBW 20kHz SWEEP 7.78s (1001 p t s)
REF 5dBm AT TEN: 20dB
STOP 2.6GHz
–85
–75
–65
–55
–45
–35
–25
–5
–15
5
11149-012
10dB/DIV
Figure 13. Single-Tone Spectrum at fOUT = 1000 MHz
–55
–60
–65
–70
–75
–80
–85
–90 0200 400 600 800 1000 1200 1400
IMD (dBc)
f
OUT (MHz)
1600MSPS
2200MSPS
2600MSPS
2800MSPS
11149-014
Figure 14. IMD vs. fOUT over fDAC
–150
–155
–160
–165
–170 0200 400 600 800 1000 1200
NSD (d Bm/Hz)
f
OUT
(MHz)
1600MSPS
2200MSPS
2800MSPS
11149-016
Figure 15. W-CDMA NSD vs. fOUT
AD9119/AD9129 Data Sheet
Rev. B | Page 14 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–45
–50
–55
–60
–65
–70
–75
–80 0200 400 600 800 1000 1200 1400
SFDR ( dBc)
f
OUT
(MHz)
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-017
Figure 16. SFDR vs. fOUT over Digital Full Scale
–40
–50
–60
–70
–80
–90
–100 0200 400 600 800 1000 1200 1400
IMD (dBc)
f
OUT (MHz)
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-020
Figure 17. IMD vs. fOUT over Digital Full Scale
–30
–40
–50
–60
–70
–80
–90 0200 400 600 800 1000 1200 1400
SFDR ( dBc)
f
OUT (MHz)
11mA
22mA
33mA
11149-021
Figure 18. SFDR vs. fOUT over DAC IOUTFS
0200 400 600 800 1000 1200 1400
f
OUT (MHz)
11mA
22mA
33mA
–55
–60
–65
–70
–75
–80
–85
–90
IMD (dBc)
11149-022
Figure 19. IMD vs. fOUT over DAC IOUTFS
Data Sheet AD9119/AD9129
Rev. B | Page 15 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0200 400 600 800 1000 1200 1400
NSD (d Bm/Hz)
fOUT
(MHz)
–145
–150
–155
–160
–165
–170
–40°C
+25°C
+85°C
11149-025
Figure 20. Single-Tone NSD vs. fOUT over Temperature
CENT ER 877.5MHz
VBW 3kHz
10dB/DIV
SPAN 53. 84M Hz
SWEEP 1.485s
–20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
25MHz
INT EG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–74.97
–77.99
–78.68
–78.79
–76.81
dBm
–85.68
–88.69
–89.38
–89.50
–87.52
dBc
–75.24
–78.44
–78.94
–78.58
–77.20
dBm
–85.95
–89.14
–89.65
–89.29
–87.91
FILTER
OFF
OFF
OFF
OFF
OFF
TOTAL CARRIER POWER –10.705dBm/3. 84M Hz
UPPERLOWER
11149-027
Figure 21. Single-Carrier W-CDMA at 877.5 MHz
0200 400 600 800 1000 1200
fOUT
(MHz)
NSD (d Bm/Hz)
–150
–155
–160
–165
–170
–40°C
+25°C
+85°C
11149-026
Figure 22. W-CDMA NSD vs. fOUT over Temperature
CENT ER 877.5MHz
VBW 3kHz
10dB/DIV
SPAN 58. 84M Hz
SWEEP 1.623s
–20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
25MHz
INT EG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–71.62
–74.36
–74.35
–72.89
–67.34
dBm
–85.23
–87.96
–87.95
–86.50
–80.95
dBc
–71.61
–74.94
–74.91
–74.53
–73.68
dBm
–85.22
–88.55
–88.52
–88.14
–87.29
FILTER
OFF
OFF
OFF
OFF
OFF
UPPERLOWER
TOTAL CARRIER POWER –10.646dBm/7. 68M Hz
11149-028
Figure 23. Two-Carrier W-CDMA at 877.5 MHz
AD9119/AD9129 Data Sheet
Rev. B | Page 16 of 66
AC (Mix-Mode)
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–100 START 20M Hz
RES BW 20kHz VBW 20kHz SWEEP 7.78s (1001 p t s)
REF 0dBm ATTEN: 20dB
10dB/DIV
STOP 2.6GHz
–90
–80
–70
–60
–50
–40
–30
–10
–20
0
11149-029
Figure 24. Single Tone Spectrum at fOUT = 2350 MHz
500 1000 1500 2000 2500 3000
SFDR ( dBc)
f
OUT
(MHz)
1600MSPS
2200MSPS
2800MSPS
–40
–50
–60
–70
–80
–90
11149-031
Figure 25. SFDR vs. fOUT over fDAC
1000 1500 2000 350035002500 4000 4500
NSD (d Bm/Hz)
f
OUT
(MHz)
–145
–150
–155
–160
–165
–170
11149-033
Figure 26. Single-Tone NSD vs. fOUT
–95 START 20M Hz
RES BW 20kHz VBW 20kHz SWEEP 7.78s (1001 p t s)
REF 5dBm ATTEN: 20dB
STOP 2.6GHz
–85
–75
–65
–55
–45
–35
–25
–5
–15
5
11149-030
10dB/DIV
Figure 27. Single-Tone Spectrum at fOUT = 1600 MHz
500 1000 1500 2000 2500 3000
f
OUT (MHz)
1600MSPS
2200MSPS
2800MSPS
IMD (dBc)
–50
–55
–60
–65
–70
–75
–80
–85
11149-032
Figure 28. IMD vs. fOUT over fDAC
1500 2000 2500 3000 3500 4000
f
OUT (MHz)
NSD (d Bm/Hz)
–145
–150
–155
–160
–165
–170
11149-034
Figure 29. W-CDMA NSD vs. fOUT
Data Sheet AD9119/AD9129
Rev. B | Page 17 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
1000 1500 2000 2500 3000 3500 4000
f
OUT
(MHz)
SFDR (dBc)
–25
–55
–60
–45
–50
–35
–40
–30
–65
–70
11149-035
SECO ND NY QUI S T ZONE
THIRD NYQUIST ZONE
–16dBFS
–12dBFS
–6dBFS
0dBFS
Figure 30. SFDR vs. fOUT over Digital Full Scale
1000 1500 2000 2500 3000 3500 4000
f
OUT
(MHz)
IM D ( dBc)
–45
–65
–70
–55
–60
–50
–75
–80
11149-036
SECO ND NY QUI S T ZONE
THIRD NYQUIST ZONE
–16dBFS
–12dBFS
–6dBFS
0dBFS
Figure 31. IMD vs. fOUT over Digital Full Scale
1000 1500 2000 350035002500 4000
f
OUT (MHz)
SFDR ( dBc)
–25
–55
–60
–45
–50
–35
–40
–30
–65
–70
11149-039
SECO ND NY QUI S T ZONE
THIRD NYQUIST ZONE
11mA
22mA
33mA
Figure 32. SFDR vs. fOUT over DAC IOUTFS
1000 1500 25002000 3000 3500 4000
f
OUT (MHz)
IM D ( dBc)
–45
–50
–55
–60
–65
–80
–75
–70
11149-040
SECO ND NY QUI S T ZONE
THIRD NYQUIST ZONE
11mA
22mA
33mA
Figure 33. IMD vs. fOUT over DAC IOUTFS
AD9119/AD9129 Data Sheet
Rev. B | Page 18 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
1000 1500 2000 350035002500 4000
f
OUT
(MHz)
–145
NSD (d Bm/Hz)
–150
–155
–160
–165
–170
11149-043
–40°C
+25°C
+85°C
Figure 34. Single-Tone NSD vs. fOUT over Temperature
CENT ER 1.888G Hz
VBW 3kHz
10dB/DIV
SPAN 53. 84M Hz
SWEEP 1.485s
–20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
25MHz
INT EG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–70.25
–74.47
–75.55
–76.03
–76.62
dBm
–80.37
–84.60
–85.68
–86.15
–86.75
dBc
–70.38
–74.54
–75.72
–76.25
–76.70
dBm
–80.50
–84.66
–85.85
–86.37
–86.83
FILTER
OFF
OFF
OFF
OFF
OFF
TOTAL CARRIER POWER –10.125dBm/3. 84M Hz
UPPERLOWER
11149-045
Figure 35. Single-Carrier W-CDMA at 1887.5 MHz
1500 25002000 3000 3500 3500
fOUT (MHz)
NSD (d Bm/Hz)
–145
–150
–155
–160
–165
11149-044
–40°C
+25°C
+85°C
Figure 36. W-CDMA NSD vs. fOUT over Temperature
CENT ER 1.98G Hz
VBW 3kHz
10dB/DIV
SPAN 58. 84M Hz
SWEEP 1.623s
–20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
INT EG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–65.84
–67.02
–68.05
–69.07
dBm
–82.06
–83.23
–84.27
–85.29
dBc
–65.79
–66.75
–67.99
–69.03
dBm
–82.01
–82.97
–84.21
–85.25
FILTER
OFF
OFF
OFF
OFF
UPPERLOWER
TOTAL CARRIER POWER –10.251dBm/15. 36M Hz
11149-046
Figure 37. Four-Carrier W-CDMA at 1980 MHz
Data Sheet AD9119/AD9129
Rev. B | Page 19 of 66
DOCSIS Performance (Normal Mode)
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–120 START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 pts)
REF –20dBm
10dB/DIV
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–3.819dBm
(Δ) –74.107dB
(Δ) –74.148dB
X
70MHz
(Δ) 70MHz
(Δ) 140MHz
FUNCTION
VALUE
–3.819dBm
(Δ) –74.24dB
(Δ) –74.17dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
1
2Δ1 3Δ1
11149-049
Figure 38. Single Carrier at 70 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–12.143dBm
(Δ) –70.38dB
(Δ) –67.78dB
X
79MHz
(Δ) 61MHz
(Δ) 131MHz
FUNCTION
VALUE
–12.142dBm
(Δ) –70.351dB
(Δ) –67.775dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
1
2Δ1 3Δ1
11149-050
10dB/DIV
Figure 39. Four Carrier at 70 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 20kHz SWEEP 27.9s ( 1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–15.295dBm
(Δ) –66.768dB
(Δ) –66.821dB
X
91MHz
(Δ) 49MHz
(Δ) 117.9MHz
FUNCTION
VALUE
–15.294dBm
(Δ) –66.669dB
(Δ) –66.833dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
2Δ1 3Δ1
1
11149-051
10dB/DIV
Figure 40. Eight Carrier at 70 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–6.351dBm
(Δ) –66.696dB
(Δ) –70.598dB
X
950MHz
(Δ) –68MHz
(Δ) –882MHz
FUNCTION
VALUE
–6.349dBm
(Δ) –66.696dB
(Δ) –70.598dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
1
2Δ1
3Δ1
11149-052
10dB/DIV
Figure 41. Single Carrier at 950 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–14.282dBm
(Δ) –64.535dB
(Δ) –68.529dB
X
959MHz
(Δ) –77MHz
(Δ) –891MHz
FUNCTION
VALUE
–14.264dBm
(Δ) –64.535dB
(Δ) –68.597dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
2Δ1
3Δ1
1
11149-053
10dB/DIV
Figure 42. Four Carrier at 950 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s ( 1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–14.632dBm
(Δ) –62.657dB
(Δ) –66.131dB
X
971MHz
(Δ) –89MHz
(Δ) –903MHz
FUNCTION
VALUE
–18.397dBm
(Δ) –62.657dB
(Δ) –66.195dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
1
2Δ1
3Δ1
11149-054
10dB/DIV
Figure 43. Eight Carrier at 950 MHz Output
AD9119/AD9129 Data Sheet
Rev. B | Page 20 of 66
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
00.2 0.4 0.80.6 1.0
f
OUT (GHz)
IN-BAND S E COND HARMONIC ( dBc)
–40
–50
–80
–70
–60
–90
11149-055
Figure 44. Second Harmonic vs. fOUT Performance for One DOCSIS Carrier
00.2 0.4 0.80.6 1.0
f
OUT (GHz)
IN-BAND S E COND HARMONIC ( dBc)
–40
–50
–80
–70
–60
–90
11149-056
Figure 45. Second Harmonic vs. fOUT Performance for Four DOCSIS Carriers
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
IN-BAND S E COND HARMONI C ( dBc)
–40
–80
–70
–60
–50
–90
11149-057
Figure 46. Second Harmonic vs. fOUT Performance for Eight DOCSIS Carriers
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
IN-BAND THI RD HARM ONI C ( dBc)
–40
–80
–70
–60
–50
–90
11149-058
Figure 47. Third Harmonic vs. fOUT Performance for One DOCSIS Carrier
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
IN-BAND THI RD HARM ONI C ( dBc)
–40
–80
–70
–60
–50
–90
11149-059
Figure 48. Third Harmonic vs. fOUT Performance for Four DOCSIS Carriers
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
IN-BAND THI RD HARM ONI C ( dBc)
–40
–80
–70
–60
–50
–90
11149-060
Figure 49. Third Harmonic vs. fOUT Performance for Eight DOCSIS Carriers
Data Sheet AD9119/AD9129
Rev. B | Page 21 of 66
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
ACPR (d Bc)
–50
–55
–65
–80
–70
–75
–85
–60
–90
11149-167
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 50. Single-Carrier ACPR vs. fOUT
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
ACPR (d Bc)
–50
–55
–65
–80
–70
–75
–85
–60
–90
11149-168
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 51. Four-Carrier ACPR vs. fOUT
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
ACPR (d Bc)
–50
–75
–80
–65
–70
–60
–55
–85
–90
11149-169
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 52. Eight-Carrier ACPR vs. fOUT
00.2 0.4 0.80.6 1.0
fOUT
(GHz)
ACPR (d Bc)
–50
–75
–80
–65
–70
–60
–55
–85
–90
11149-170
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 53. 16-Carrier ACPR vs. fOUT
0.1 0.2 0.40.3 0.5 0.7 0.80.6 0.9
f
OUT
(MHz)
ACPR (d Bc)
–50
–75
–80
–65
–70
–60
–55
–85
–90
11149-171
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 54. 32-Carrier ACPR vs. fOUT
–120 CENTE R 77M Hz
RES BW 10kHz VBW 1kHz SWEEP 6.08s (1001 pt s)
REF –20dBm
SPAN 60MHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
11149-172
10dB/DIV
Figure 55. Gap Channel ACPR at 77 MHz
AD9119/AD9129 Data Sheet
Rev. B | Page 22 of 66
AD9129
Static Linearity
IOUTFS = 28 mA, nominal supplies, TA = 25°C, unless otherwise noted.
–1.5
–1.0
–0.5
0
INL (LSB)
0.5
1.0
1.5
2.0
02000 4000 6000 8000
CODE 10000 12000 14000 16000
11149-065
Figure 56. Typical INL, 11 mA at 25°C
–1.5
–1.0
–0.5
0
INL (LSB)
0.5
1.0
1.5
2.0
02000 4000
6000 8000
CODE 10000 12000 14000 16000
11149-066
Figure 57. Typical INL, 22 mA at 25°C
02000 4000 6000 8000
CODE
10000 12000 14000 16000
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL (LSB)
11149-067
Figure 58. Typical INL, 33 mA at 25°C
CODE
02000 4000 6000 8000 10000 12000 14000 16000
–1.5
–1.0
–0.5
0
0.5
1.0
DNL (LSB)
11149-068
Figure 59. Typical DNL, 11 mA at 25°C
CODE
02000 4000 6000 8000 10000 12000 14000 16000
DNL (LSB)
–1.5
–1.0
–0.5
0
0.5
1.0
11149-069
Figure 60. Typical DNL, 22 mA at 25°C
CODE
02000 4000 6000 8000 10000 12000 14000 16000
–1.5
–1.0
–0.5
0
0.5
1.0
DNL (LSB)
11149-070
Figure 61. Typical DNL, 33 mA at 25°C
Data Sheet AD9119/AD9129
Rev. B | Page 23 of 66
AC (Normal Mode)
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–95 START 20M Hz
RES BW 20kHz
REF 5dBm ATTEN: 24dB
STOP 2.6GHz
–85
–75
–65
–55
–45
–35
–25
–15
–5
5
11149-071
VBW 20kHz SWEEP 7.78s (1001 p t s)
10dB/DIV
Figure 62. Single-Tone Spectrum at fOUT = 70 MHz
0200 400 600 800
f
OUT (MHz)
SFDR ( dBc)
1000 1200 1400
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1400MSPS
1600MSPS
2200MSPS
2600MSPS
2800MSPS
11149-073
Figure 63. SFDR vs. fOUT over fDAC
0200 400 600 800
f
OUT (MHz)
NSD (d Bm/Hz)
1000 1200 1400
–145
–150
–155
–160
–165
–170
1600MSPS
2200MSPS
2800MSPS
11149-075
Figure 64. Single-Tone NSD vs. fOUT
–95 START 20M Hz
RES BW 20kHz
REF 5dBm ATTEN: 24dB
STOP 2.6GHz
–85
–75
–65
–55
–45
–35
–25
–15
–5
5
11149-072
VBW 20kHz SWEEP 7.78s (1001 p t s)
10dB/DIV
Figure 65. Single-Tone Spectrum at fOUT = 1000 MHz
0200 400 600 800
f
OUT (MHz)
IMD (dBc)
1000 1200 1400
–40
–50
–60
–70
–80
–90
–100
1600MSPS
2200MSPS
2600MSPS
2800MSPS
11149-074
Figure 66. IMD vs. fOUT over fDAC
0200 400 600 800
fOUT
(MHz)
NSD (dBm/Hz )
1000 1200
–150
–155
–160
–165
–170
11149-076
1600MSPS
2200MSPS
2800MSPS
Figure 67. W-CDMA NSD vs. fOUT
AD9119/AD9129 Data Sheet
Rev. B | Page 24 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0200 400 600 800
f
OUT
(MHz)
SF DR ( dBc)
1000 14001200
–45
–50
–55
–60
–65
–70
–75
–80
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-077
Figure 68. SFDR vs. fOUT over Digital Full Scale
0200 400 600 800
f
OUT (MHz)
IN-BAND S E COND HARMONIC (dBc)
1000 14001200
–40
–50
–60
–70
–80
–90
–100
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-078
Figure 69. SFDR for Second Harmonic vs. fOUT over Digital Full Scale
–40
–50
–60
–70
–80
–90
–100
0200 400 600 800
fOUT
(MHz)
IN- BAND THIRD HARM ONI C ( dBc)
1000 14001200
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-079
Figure 70. SFDR for Third Harmonic vs. fOUT over Digital Full Scale
0200 400 600 800
f
OUT (MHz)
IMD (dBc)
1000 14001200
–40
–50
–60
–70
–80
–90
–100
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-080
Figure 71. IMD vs. fOUT over Digital Full Scale
0200 400 600 800
f
OUT
(MHz)
SFDR ( dBc)
1000 14001200
–30
–40
–50
–60
–70
–80
–90
11mA
22mA
33mA
11149-081
Figure 72. SFDR vs. fOUT over DAC IOUTFS
0200 400 600 800
f
OUT (MHz)
IMD (dBc)
1000 14001200
–55
–60
–65
–70
–75
–80
–85
–90
11mA
22mA
33mA
11149-082
Figure 73. IMD vs. fOUT over DAC IOUTFS
Data Sheet AD9119/AD9129
Rev. B | Page 25 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0 200 400 600 800
f
OUT
(MHz)
SFDR (dBc)
1000 14001200
–
50
–55
–60
–65
–70
–75
–80
–40°C
+25°C
+85°C
11149-083
Figure 74. SFDR vs. fOUT over Temperature
0 200 400 600 800
f
OUT
(MHz)
IMD (dBc)
1000 14001200
–
60
–65
–70
–75
–80
–85
–40°C
+25°C
+85°C
11149-084
Figure 75. IMD vs. fOUT over Temperature
CENTER 877.5MHz
VBW 3kHz
10dB/DI
V
SPAN 53.84MHz
SWEEP 1.485s
–
20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
25MHz
INTEG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–76.29
–80.60
–81.37
–81.76
–79.29
dBm
–87.08
–91.39
–92.16
–92.56
–90.08
dBc
–75.85
–79.88
–81.09
–81.89
–80.89
dBm
–86.64
–90.68
–91.89
–92.68
–91.69
FILTER
OFF
OFF
OFF
OFF
OFF
TOTAL CARRIER POWER –10.794dBm/3.84MHz
11149-087
Figure 76. Single-Carrier W-CDMA at 877.5 MHz
0 200 400 600 800
f
OUT
(MHz)
NSD (dBm/Hz)
1000 1200
–
150
–155
–160
–165
–170
–40°C
+25°C
+85°C
11149-086
Figure 77. W-CDMA NSD vs. fOUT over Temperature
0 200 400 600 800
f
OUT
(MHz)
NSD (dBm/Hz)
1000 14001200
–
145
–150
–155
–160
–165
–170
–40°C
+25°C
+85°C
11149-085
Figure 78. Single-Tone NSD vs. fOUT over Temperature
CENTER 877.5MHz
VBW 3kHz
10dB/DI
V
SPAN 58.84MHz
SWEEP 1.623s
–
20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
25MHz
INTEG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–72.33
–75.18
–74.76
–72.69
–65.42
dBm
–85.89
–88.74
–88.32
–86.25
–78.99
dBc
–72.37
–75.19
–74.92
–74.60
–73.53
dBm
–85.93
–88.75
–88.48
–88.16
–87.09
FILTER
OFF
OFF
OFF
OFF
OFF
TOTAL CARRIER POWER –10.599dBm/7.68MHz
11149-088
Figure 79. Two-Carrier W-CDMA at 875 MHz
AD9119/AD9129 Data Sheet
Rev. B | Page 26 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
700 750 800 850 900
f
OUT (MHz)
ACLR ( dBc)
950 1000
–60
–75
–70
–65
–80
–85
–90
FI RS T ACL R ( dBc)
SECO ND ACLR (dBc)
11149-089
Figure 80. Single-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
f
OUT (MHz)
ACLR (dBc)
–60
–75
–70
–65
–80
–85
–90
11149-090
THI RD ACLR (dBc)
FO URTH ACL R ( dBc)
FI FT H ACLR (dBc)
700 750 800 850 900 950 1000
Figure 81. Single-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
f
OUT
(MHz)
ACLR (dBc)
–60
–75
–70
–65
–80
–85
–90
11149-091
FI RS T ACL R ( dBc)
SECO ND ACLR (dBc)
700 750 800 850 900 950
Figure 82. Two-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
f
OUT (MHz)
ACLR (dBc)
–60
–75
–70
–65
–80
–85
–90
11149-092
THI RD ACLR (dBc)
FO URTH ACL R ( dBc)
FI FT H ACLR (dBc)
700 750 800 850 900 950
Figure 83. Two-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
Data Sheet AD9119/AD9129
Rev. B | Page 27 of 66
AC (Mix-Mode)
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–100
–90
START 20M Hz
RES BW 20kHz VBW 20kHz SWEEP 7.78s (1001 p t s)
REF 0dBm ATTEN: 20dB
STOP 2.6GHz
–80
–70
–60
–50
–40
–30
–20
–10
0
11149-093
10dB/DIV
Figure 84. Single-Tone Spectrum at fOUT = 2350 MHz
–90500 15001000 2000 2500
f
OUT
(MHz)
SF DR ( dBc)
3000
–70
–80
–50
–60
–40
1600MSPS
2200MSPS
2800MSPS
11149-095
Figure 85. SFDR vs. fOUT over fDAC
–170
1000 20001500 2500 3500 40003000
fOUT
(MHz)
NSD (d Bm/Hz)
4500
–160
–165
–150
–155
–145
11149-097
Figure 86. Single-Tone NSD vs. fOUT
–95 START 20M Hz
RES BW 20kHz VBW 20kHz SWEEP 7.78s (1001 p t s)
REF 5dBm ATTEN: 20dB
STOP 2.6GHz
–85
–75
–65
–55
–45
–35
–25
–5
–15
5
11149-094
10dB/DIV
Figure 87. Single-Tone Spectrum at fOUT = 1600 MHz
–85500 15001000 2000 2500
f
OUT
(MHz)
IM D ( dBc)
3000
–65
–70
–80
–75
–60
–55
–50
1600MSPS
2200MSPS
2800MSPS
11149-096
Figure 88. IMD vs. fOUT over fDAC
–170
1500 25002000 3000 3500
fOUT (MHz)
NSD (d Bm/Hz)
4000
–160
–165
–150
–155
–145
11149-098
Figure 89. W-CDMA NSD vs. fOUT
AD9119/AD9129 Data Sheet
Rev. B | Page 28 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–70
1000 20001500 2500 3500
f
OUT
(MHz)
SF DR ( dBc)
40003000
–50
–55
–65
–60
–45
–40
–35
–30
–25 SECO ND NY QUI S T Z ONE
THIRD NYQUIST ZONE
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-099
Figure 90. SFDR vs. fOUT over Digital Full Scale
–80
1000 20001500 2500 35003000
f
OUT (MHz)
IMD (dBc)
4000
–60
–65
–70
–75
–50
–55
–45 SECO ND NY QUI S T ZONE
THIRD NYQUIST ZONE
–16dBFS
–12dBFS
–6dBFS
0dBFS
11149-100
Figure 91. IMD vs. fOUT over Digital Full Scale
–90
1000 1500 25002000 3000 3500
fOUT
(MHz)
SF DR ( dBc)
4000
–10
–20
–30
–40
–50
–60
–70
–80
0SECO ND NY QUI S T Z ONE
THIRD NYQUIST ZONE
11mA
22mA
33mA
11149-101
Figure 92. SFDR vs. fOUT over DAC IOUTFS
–90
1000 20001500 2500 35003000
fOUT (MHz)
IM D ( dBc)
4000
–60
–70
–80
–50
–40
–30
11149-193
SECO ND NY QUI S T ZONE
THIRD NYQUIST ZONE
11mA
22mA
33mA
Figure 93. IMD vs. fOUT over DAC IOUTFS
Data Sheet AD9119/AD9129
Rev. B | Page 29 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–170
1000 20001500 2500 35003000
f
OUT (MHz)
NSD (d Bm/Hz)
4000
–160
–165
–150
–155
–145
11149-105
–40°C
+25°C
+85°C
Figure 94. Single-Tone NSD vs. fOUT over Temperature
CENT ER 1.888G Hz
VBW 3kHz
10dB/DIV
SPAN 53. 84M Hz
SWEEP 1.485s
–20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
25MHz
INT EG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–73.71
–77.40
–78.04
–78.13
–78.01
dBm
–83.15
–86.84
–87.48
–87.57
–87.46
dBc
–74.00
–77.31
–77.85
–78.51
–78.43
dBm
–83.45
–86.75
–87.30
–87.96
–87.87
FILTER
OFF
OFF
OFF
OFF
OFF
TOTAL CARRIER POW ER – 9 .44 5d Bm /3 .84MHz
11149-107
UPPERLOWER
Figure 95. Single-Carrier W-CDMA at 1887.5 MHz
–165
1500 25002000 3000 3500
f
OUT
(MHz)
NSD (d Bm/Hz)
–150
–155
–160
–145 –40°C
+25°C
+85°C
11149-106
Figure 96. W-CDMA NSD vs. fOUT over Temperature
CENT ER 1.98G Hz
VBW 3kHz
10dB/DIV
SPAN 58. 84M Hz
SWEEP 1.623s
–20
–30
–50
–40
–80
–70
–60
–90
–120
–110
–100
OFFSET FREQ
5MHz
10MHz
15MHz
20MHz
INT EG BW
3.84MHz
3.84MHz
3.84MHz
3.84MHz
dBc
–69.05
–69.86
–70.81
–71.03
dBm
–85.24
–86.05
–87.00
–87.22
dBc
–69.03
–69.71
–70.52
–70.91
dBm
–85.22
–85.90
–86.71
–87.10
FILTER
OFF
OFF
OFF
OFF
UPPERLOWER
TOTAL CARRIER POW ER – 1 0 .211dBm/15.36MHz
11149-108
Figure 97. Four-Carrier W-CDMA at 1980 MHz
AD9119/AD9129 Data Sheet
Rev. B | Page 30 of 66
IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
1.4 1.6 1.8 2.0 2.2
f
OUT (GHz)
ACLR (dBc)
2.4 2.6
–50
–60
–75
–70
–55
–65
–80
–85
–90
FI RS T ACL R ( dBc)
SECO ND ACLR (dBc)
11149-109
Figure 98. Single-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
1.4 1.6 1.8 2.0 2.2
fOUT
(GHz)
ACLR (dBc)
2.4 2.6
–50
–60
–75
–70
–55
–65
–80
–85
–90
11149-110
THI RD ACLR (dBc)
FO URTH ACL R ( dBc)
FI FT H ACLR (dBc)
Figure 99. Single-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
1.4 1.6 1.8 2.0 2.2
f
OUT
(GHz)
ACLR ( dBc)
2.4 2.6
–50
–60
–75
–70
–55
–65
–80
–85
–90
FI RS T ACL R ( dBc)
SECO ND ACLR (dBc)
11149-111
Figure 100. Four-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
1.4 1.6 1.8 2.0 2.2
fOUT (GHz)
ACLR ( dBc)
2.4 2.6
–50
–60
–75
–70
–55
–65
–80
–85
–90
11149-112
THI RD ACLR (dBc)
FO URTH ACL R ( dBc)
FI FT H ACLR (dBc)
Figure 101. Four-Carrier W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
Data Sheet AD9119/AD9129
Rev. B | Page 31 of 66
DOCSIS Performance (Normal Mode)
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–120 START 0Hz
RES BW 20kHz VBW 20kHz SWEEP 27.9s ( 1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–3.611dBm
(Δ) –72.929dB
(Δ) –74.629dB
X
70MHz
(Δ) 70MHz
(Δ) 140MHz
FUNCTION
VALUE
–3.612dBm
(Δ) –72.903dB
(Δ) –74.583dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f (Δ)
f (Δ)
2Δ1
1
3Δ1
11149-113
10dB/DIV
Figure 102. Single Carrier at 70 MHz Output
–120
–20
START 0Hz
RES BW 20kHz VBW 20kHz SWEEP 27.9s (1001 pt s)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
Y
–11.506dBm
(Δ) –71.473dB
(Δ) –69.109dB
X
79MHz
(Δ) 61MHz
(Δ) 131MHz
FUNCTION
VALUE
–11.506dBm
(Δ) –71.606dB
(Δ) –69.155dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f (Δ)
f (Δ)
2Δ1
1
3Δ1
11149-114
10dB/DIV
Figure 103. Four Carrier at 70 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 20kHz SWEEP 27.9s ( 1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–15.917dBm
(Δ) –66.430dB
(Δ) –67.401dB
X
91MHz
(Δ) 49MHz
(Δ) 117.9MHz
FUNCTION
VALUE
–15.919dBm
(Δ) –66.658dB
(Δ) –67.436dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f (Δ)
f (Δ)
1
2Δ1 3Δ1
11149-115
10dB/DIV
Figure 104. Eight Carrier at 70 MHz Output
11149-211
–120
–30
START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–20
–40
Y
–6.221dBm
(Δ)–68.115dB
(Δ)–71.783dB
X
950MHz
(Δ) –68MHz
(Δ)–882MHz
FUNCTION
VALUE
–6.223dBm
(Δ) –68.115dB
(Δ)–71.783dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
2Δ1
1
3Δ1
10dB/DIV
Figure 105. Single Carrier at 950 MHz Output
–120
–30
START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 pts)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–20
–40
Y
–14.583dBm
(Δ) –65.064dB
(Δ) –71.759dB
X
959MHz
(Δ) –77MHz
(Δ) –891MHz
FUNCTION
VALUE
–14.584dBm
(Δ) –65.064dB
(Δ) –71.759dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
2Δ1
1
3Δ1
11149-117
10dB/DIV
Figure 106. Four Carrier at 950 MHz Output
–120 START 0Hz
RES BW 20kHz VBW 2kHz SWEEP 27.9s (1001 p t s)
REF –20dBm
STOP 1.1GHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
Y
–18.364dBm
(Δ) –63.858dB
(Δ) –70.065dB
X
971MHz
(Δ) –89MHz
(Δ) –903.0MHz
FUNCTION
VALUE
–18.364dBm
(Δ) –63.858dB
(Δ) –70.065dB
FUNCTION
WIDTH
6MHz
6MHz
6MHz
FUNCTION
BAND POWER
BAND POWER
BAND POWER
MODE
N
Δ1
Δ1
TRC
1
1
1
SCL
f
f
f
2Δ1
1
3Δ1
11149-118
10dB/DIV
Figure 107. Eight Carrier at 950 MHz Output
AD9119/AD9129 Data Sheet
Rev. B | Page 32 of 66
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
00.2 0.4
f
OUT (GHz)
IN- BAND SE COND HARMONI C ( dBc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-119
Figure 108. Second Harmonic vs. fOUT Performance for One DOCSIS Carrier
00.2 0.4
f
OUT
(GHz)
IN- BAND SE COND HARMONI C ( dBc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-120
Figure 109. Second Harmonic vs. fOUT Performance for Four DOCSIS Carriers
00.2 0.4
f
OUT
(GHz)
IN-BAND S E COND HARMONI C ( dBc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-121
Figure 110. Second Harmonic vs. fOUT Performance for Eight DOCSIS Carriers
00.2 0.4
f
OUT (GHz)
IN- BAND THIRD HARM ONI C ( dBc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-122
Figure 111. Third Harmonic vs. fOUT Performance for One DOCSIS Carrier
00.2 0.4
fOUT
(GHz)
IN-BAND THI RD HARM ONI C ( dBc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-123
Figure 112. Third Harmonic vs. fOUT Performance for Four DOCSIS Carriers
00.2 0.4
fOUT (GHz)
IN-BAND THI RD HARM ONI C ( dBc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-124
Figure 113. Third Harmonic vs. fOUT Performance for Eight DOCSIS Carriers
Data Sheet AD9119/AD9129
Rev. B | Page 33 of 66
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
00.2 0.4
fOUT
(GHz)
ACPR (d Bc)
0.6 1.00.8
–50
–55
–65
–75
–85
–60
–70
–80
–90
11149-219
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 114. Single-Carrier ACPR vs. fOUT
00.2 0.4
fOUT
(GHz)
ACPR (d Bc)
0.6 1.00.8
–50
–55
–65
–75
–85
–60
–70
–80
–90
11149-220
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 115. Four-Carrier ACPR vs. fOUT
00.2 0.4
fOUT
(GHz)
ACPR (d Bc)
0.6 1.00.8
–50
–55
–65
–75
–85
–60
–70
–80
–90
11149-221
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 116. Eight-Carrier ACPR vs. fOUT
00.2 0.4
fOUT
(GHz)
ACPR (d Bc)
0.6 1.00.8
–50
–55
–65
–75
–85
–60
–70
–80
–90
11149-222
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 117. 16-Carrier ACPR vs. fOUT
0.1 0.2 0.3 0.5 0.70.4
f
OUT
(GHz)
ACPR (dBc)
0.6 0.90.8
–50
–55
–65
–75
–85
–60
–70
–80
–90
11149-223
ACP1
ACP2
ACP3
ACP4
ACP5
Figure 118. 32-Carrier ACPR vs. fOUT
AD9119/AD9129 Data Sheet
Rev. B | Page 34 of 66
IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–120 CENTE R 77M Hz
RES BW 10kHz V BW 1kHz SWEEP 6.08s (1001 pts)
REF –20dBm
SPAN 60MHz
–110
–100
–90
–80
–70
–60
–50
–30
–40
–20
11149-125
10dB/DIV
Figure 119. Gap Channel ACLR at 77 MHz
00.2 0.4
fOUT
(GHz)
ACLR I N GAP CHANNEL (d Bc)
0.6 1.00.8
–40
–50
–60
–70
–80
–90
11149-225
Figure 120. Gap Channel ACLR vs. fOUT
Data Sheet AD9119/AD9129
Rev. B | Page 35 of 66
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
The maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from zero to
full scale.
Differential Nonlinearity (DNL)
The measure of the variation in analog value, normalized to full
scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero.
For IOUTP, 0 mA output is expected when the inputs are all 0s.
For IOUTN, 0 mA output is expected when all inputs are set to 1.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1 minus the output when all inputs are set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Specified as the maximum change from the ambient (25°C) value
to the value at either TMIN or TMAX. For offset and gain drift, the
drift is reported in ppm of full-scale range (FSR) per degree
Celsius (°C). For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Spurious-Free Dynamic Range
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal. It is expressed as
a percentage or in decibels (dB).
Noise Spectral Density (NSD)
The converter noise power per unit of bandwidth. This is
usually specified in dBm/Hz in the presence of a 0 dBm full-
scale signal.
Adjacent Channel Leakage Ratio (ACLR)
The ratio, in dBc, between the measured power within a channel
relative to its adjacent channels.
Adjacent Channel Power Ratio (ACPR)
The ratio, in dBc, between the total power of an adjacent channel
(intermodulation signal) to the main channel's power (useful
signal).
Modulation Error Ratio (MER)
A measure of the discrepancy between the average output
symbol magnitude and the rms error magnitude of the individual
symbol. Modulated signals create a discrete set of output values
referred to as a constellation, and each symbol creates an output
signal corresponding to one point on the constellation.
Intermodulation Distortion (IMD)
The result of two or more signals at different frequencies mixing
together. Many products are created according to the formula
aF1 ± bF2, where a and b are integer values.
AD9119/AD9129 Data Sheet
Rev. B | Page 36 of 66
SERIAL COMMUNICATIONS PORT OVERVIEW
The AD9119/AD9129 are 11-bit/14-bit DACs that operate at an
update rate of up to 2.85 GSPS. Due to internal timing
requirements, the minimum allowable sample rate is 1400
MSPS. Input data is sampled through two 11-/14-bit LVDS
ports that are internally multiplexed. Each port has its own data
inputs, but both ports share a common data clock input (DCI).
The LVDS inputs meet the IEEE-1596 specification with the
exception of input hysteresis, which is not guaranteed over all
process corners. Each DCI input runs at one-quarter the input
data rate in a double data rate (DDR) format. Each edge of the
DCI is used to transfer data into the AD9119/AD9129.
The DACCLK_N and DACCLK_P inputs directly drive the
DAC core to minimize clock jitter. The DACCLK signal is
divided by 4 and then output as the DCO for each port. The
DCO signal can be used to clock the data source. The DAC
expects DDR LVDS data (P0_D[13:0]x, P1_D[13:0]x), with
each channel aligned with the single DDR DCI signal.
Control of the AD9119/AD9129 functions is via a SPI.
SERIAL PERIPHERAL INTERFACE (SPI)
The AD9119/AD9129 SPI is a flexible, synchronous serial
communications port, allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer formats,
including the Motorola® SPI and the Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9119/AD9129. Most significant bit first (MSB-first) or
least significant bit first (LSB-first) transfer formats are supported.
The AD9119/AD9129 serial interface port can be configured as
a single I/O pin (SDIO) or two unidirectional pins for input/
output (SDIO and SDO).
SDO ( P IN J2)
SDIO (P IN J1)
SCLK ( P IN K1)
CS (PIN K2)
AD9119/
AD9129
SPI PORT
11149-126
Figure 121. AD9119/AD9129 SPI Port
GENERAL OPERATION OF THE SPI
There are two phases to a communication cycle with the AD9119/
AD9129. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9119/AD9129, coincident with
the first eight SCLK rising edges. The instruction byte provides
the AD9119/AD9129 serial port controller with information
about the data transfer cycle, which is Phase 2 of the communi-
cation cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write and the starting register
address for the first byte of the data transfer. The first eight SCLK
rising edges of each communication cycle are used to write the
instruction byte into the AD9119/AD9129.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9119/
AD9129 and the system controller. Phase 2 of the communication
cycle is a transfer of one byte only. Single-byte data transfers are
useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte. CS (chip select) can be raised after
each sequence of eight bits (except the last byte) to stall the bus.
The serial transfer resumes when CS is lowered. Stalling on
nonbyte boundaries resets the SPI.
INSTRUCTION MODE (8-BIT INSTRUCTION)
The instruction byte is shown in the following table.
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0
R/W A6 A5 A4 A3 A2 A1 A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation, the data transfer cycle. A6 to A0 (Bit 6 through Bit 0
of the instruction byte) determine which register is accessed
during the data transfer portion of the communications cycle.
SERIAL PERIPHERAL INTERFACE PIN
DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9119/AD9129 and to run the internal state machines. The
maximum frequency of SCLK is 20 MHz. All data input to the
AD9119/AD9129 is registered on the rising edge of SCLK. All
data is driven out of the AD9119/AD9129 on the rising edge
of SCLK.
CS—Chip Select
Active low input starts and gates a communication cycle. It allows
more than one device to be used on the same serial communi-
cations lines. The SDO and SDIO pins go to a high impedance
state when this input is high. Chip select should stay low during
the entire communication cycle.
SDIO—Serial Data I/O
Data is always written into the AD9119/AD9129 on this pin.
However, this pin can be used as a bidirectional data line. The
configuration of this pin is controlled by Register 0x00, Bit 7
(SDIO_DIR). The default is Logic 1, which configures the SDIO
pin as bidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. When the AD9119/AD9129
are operating in a single bidirectional I/O mode, this pin does
not output data and is set to a high impedance state.
Data Sheet AD9119/AD9129
Rev. B | Page 37 of 66
MSB/LSB TRANSFERS
The AD9119/AD9129 serial port can support both MSB-first
and LSB-first data formats. This functionality is controlled by
the LSB/MSB bit, Bit 6 in Register 0x00. The default is MSB first
(LSB/MSB = 0). When the MSB-first data format is selected, the
instruction and data bytes must be written from the most
significant bit to the least significant bit.
When LSB/MSB = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most
significant bit.
SERIAL PORT CONFIGURATION
The AD9119/AD9129 serial port configuration is controlled
by Register 0x00, Bits[7:5]. Note that the configuration changes
immediately upon writing to the last bit of the register. When
setting the software reset bit (SoftReset in Register 0x00, Bit 5),
all registers are set to their default values except Register 0x00,
which remains unchanged.
In the event of unexpected programming sequences, the
AD9119/AD9129 SPI can become inaccessible. For example,
if user code inadvertently changes the LSB/MSB bit, the bits that
follow experience unexpected results. The SPI can be returned
to a known state by writing an incomplete byte (1 to 7 bits) of
all 0s, followed by three bytes of 0x00. This returns to the MSB-
first instructions (Register 0x00 = 0x00) so that the device can
be reinitialized.
R/W A6 A5 A4 A3 A2 A1 A0 D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
CS
11149-127
Figure 122. Serial Register Interface Timing, MSB-First Write
R/W A6 A5 A4 A3 A2 A1 A0
D7
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
SDO
D7
CS
11149-128
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
Figure 123. Serial Register Interface Timing, MSB-First Read
A0 A1 A2 A3 A4 A5 A6R/W
SCLK
SDIO
CS
INSTRUCTION CYCLE D
A
TA TRANSFER CYCLE
11149-129
D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D4
0
Figure 124. Serial Register Interface Timing, LSB-First Write
A0 A1 A2 A3 A4 A5 A6R/W
D0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
SDO
D0
CS
11149-130
D7
N
D6
N
D5
N
D1
0
D2
0
D4
0
D7
N
D6
N
D5
N
D1
0
D2
0
D4
0
Figure 125. Serial Register Interface Timing, LSB-First Read
INSTRUCTION BIT 6INSTRUCTION BIT 7
SCLK
SDIO
t
DS
t
DS
t
DH
t
SCLK
CS
11149-131
Figure 126. Timing Diagram for an SPI Register Write
I1 I0 D7 D6 D5
t
DV
t
DNV
SCLK
SDIO
CS
11149-132
Figure 127. Timing Diagram for an SPI Register Read
After the last instruction bit is written to the SDIO pin, the
driving signal must be set to a high impedance in time for the
bus to turn around. The serial output data from the AD9119/
AD9129 is enabled by the falling edge of SCLK. This causes the
first output data bit to be shorter than the remaining data bits,
as shown in Figure 127. To assure proper reading of data, read
the SDIO pin or the SDO pin before changing SCLK from low
to high. Due to the more complex multibyte protocol, multiple
AD9119/ AD9129 devices cannot be daisy-chained on the SPI bus.
Control multiple DACs by using independent CS signals.
AD9119/AD9129 Data Sheet
Rev. B | Page 38 of 66
THEORY OF OPERATION
The AD9119/AD9129 are 11-bit/14-bit DACs that are capable of
reconstructing signal bandwidths up to 1.425 GHz while
operating with an input data rate up to 2.85 GSPS. Figure 128
shows a top level functional diagram of the AD9119/AD9129.
A high perfor-mance NMOS DAC delivers a signal dependent,
differential current to a balanced external load referenced a
nominal 1.8 V analog supply. The current source array of the
DAC is referenced to an external −1.5 V supply, and its full-scale
current, IOUTFS, can be adjusted over a 9.5 mA to 34.4 mA span.
11149-133
SDO
SDIO
SCLK
CS
DCI_x
DATA ASSEM BL ER
SPI
RESET
Tx DAC
CORE
DATA
LATCH
IOUTP
IOUTN
IRQ
4× FI FO
2×
BASEBAND
MODE
MIX-
MODE
FRM_x
(FRAME/
PARITY)
AD9129
CLOCK
DISTRIBUTION
VREFI250U
LVDS DDR
RECEIVER
LVDS DDR
RECEIVER
P1_D[13:0]P,
P1_D[13:0]N
P0_D[13:0]P,
P0_D[13:0]N
DLL
1.2V
PLL
DCO_x
NORMAL
DACCLK_x
DCR
Figure 128. Functional Block Diagram of the AD9119/AD9129
A low jitter differential clock receiver is used to square up the
signal appearing at the DACCLK_x input that sets the update
rate of the DAC. The differential clock receiver can accept
sinusoidal signals with negligible noise spectral density degra-
dation if the input signal level is maintained above 0 dBm.
A +1 dB degradation occurs at a −5 dBm input, and degradation
increases as the signal approaches −10 dBm and its associated
+2 dB additional degradation. A duty cycle restorer (DCR),
following the clock receiver, ensures near 50% duty-cycle to the
subsequent circuitry. The output of the DCR serves as the
master clock and is routed directly to the DAC, as well as to a
clock distribution block that generates all critical internal and
external clocks. The clock source quality, as defined by its phase
noise characteristics, jitter, and drive capability, is an important
consideration in maintaining optimum ac performance.
The AD9119/AD9129 supports a source synchronous, LVDS
double data-rate (DDR) data interface to the host processor.
Two 11-bit/14-bit LVDS data ports (P0_DxP, P0_DxN and
P1_Dx P, P 1 _ D x N ) are used to sample de-interleaved data from
the host on the rising and falling edge of the host DCI clock.
This effectively reduces the bus interface speed to ½ the data
rate (for example, fDATA/2) with the DCI clock operating at fDATA/4.
An optional parity bit can also be sent along with the data to
enhance the robustness of the interface. In this case, a counter
is available to count parity errors and generate an interrupt
request (IRQ) when a programmable threshold is exceeded.
The AD9119/AD9129 provide the host with a DCO clock that is
equal to the DCI clock frequency to establish synchronous opera-
tion. A delay locked loop (DLL) with programmable phase offset
is used to generate an internal sampling clock with optimum edge
placement for the input data latches of the LVDS DDR receivers.
When data is latched into the AD9119/AD9129, an eight-sample-
deep FIFO is used to hand off the data between the host and the
AD9119/AD9129 clock domains. The FIFO can be reset with an
external synchronization signal, fSYNC, to ensure consistent pipeline
latency. The pipeline delay, from a sample being latched into the
data port to when it appears at the DAC output, varies depending
on the chosen configuration (see the Pipeline Delay (Latency)
section).
The de-interleaved data is reassembled into its original data stream
after passing into the internal clock domain of the AD9119/
AD9129. Because the quad-switch architecture of the DAC
updates its output on both the rising and falling edge (for example,
dual edge clocking) of the DACCLK signal, the following two
additional modes of operation are available:
•A 2× interpolation filter can be selected to increase the
effective DAC update rate (fDAC) to be 2× the input data
rate, hence simplifying the analog postfiltering require-
ments and reducing the effects of alias harmonics in the
desired baseband region.
•A Mix-Mode option essentially generates the complement
sample on the falling edge such that the original Nyquist
spectrum is shifted to fDACCLK, with the sinc null of the DAC
falling at 2 × fDACCLK.
The digital handoff between the digital domain and mixed signal
domain of a high speed DAC is critical in preserving its output
dynamic range. A phase locked loop (PLL) with programmable
phase offset is used to optimize the timing handoff between these
two clock domains. State machines are used to initialize both the
DLL and the PLL during the initial boot sequence after receiving
a stable DACCLK signal. Following initialization of the two loops,
they maintain optimum timing alignment over temperature, time,
and power supply variation. The AD9119/AD9129 also provide
IRQ capability to monitor the DLL, the PLL, and other internal
circuitry.
Data Sheet AD9119/AD9129
Rev. B | Page 39 of 66
LVDS DATA PORT INTERFACE
The AD9119/AD9129 can operate with input data rates of up to
2.85 GSPS. A source synchronous LVDS interface is used
between the host and the AD9119/AD9129 to achieve these high
data rates, while simplifying the interface. As shown in Figure
129, the host feeds the AD9119/AD9129 with de-interleaved
input data into two 11-bit/14-bit LVDS data ports (P0_DxP,
P0_DxN and P1_DxP, P1_DxN) at ½ the DAC clock rate (that
is, fDACCLK/2). Along with the input data, the host provides an
embedded DDR data clock input (DCI_x) at fDACCLK/4.
A DLL circuit that is designed to operate with DCI clock rates
of between 350 MHz and 712.5 MHz is used to generate a phase
shifted version of DCI, called the data sampling clock (DSC),
to register the input data on both the rising and falling edges.
As shown in Figure 130, the DCI clock edges must be coincident
with the data bit transitions with minimum skew and jitter. The
nominal sampling point of the input data occurs in the middle
of the DCI clock edges because this point corresponds to the
center of the data eye. This is also equivalent to a nominal phase
shift of 90°of the DCI clock.
The data timing requirements are defined by a minimum data
valid margin that is dependent on the data clock input skew,
input data jitter, and the variations of the DLL delay line across
delay settings. This margin is defined by subtracting from the
data period any data skew, data jitter, and the keep-out window
(KOW) that is defined by the sum of the set and hold times, as
follows:
tDATA VALID MARGIN = tDATA PERIOD − tDATA SKEW − tDATA JITTER − (tH + tS)
The keep-out window, which is the sum of the set and hold times,
is the area where data transitions should not occur. The timing
margin allows tuning of the DLL delay setting, either automatically
or in manual mode (see Figure 130).
Figure 130 shows that the ideal location for the DSC signal is 90°
out of phase from the DCI input. However, due to skew of the DCI
relative to the data, it may be necessary to change the DSC phase
offset to sample the data at the center of its eye diagram. The
sampling instance can be varied in discrete increments by offsetting
the nominal DLL phase shift value of 90° via Register 0x0A,
Bits[3:0]. The following equation defines the phase offset
relationship:
Phase Offset = 90° ± n × 11.25°, |n| < 8
LVDS DDR
RECEIVER
DCI
DCO CLOCK
DISTRIBUTION
DELAY
LOCK
LOOP
LVDS DDR
RECEIVER
P1_D[13:0]x P0_D[13:0]x
AD9129
HOST
PROCESSOR
LVDS DDR DRIVE R
14 × 2
14 × 2
1 × 2
1 × 2
DATA DE- INT E RLEAV ER
f
DATA
= f
DACCLK
/2
f
DCO
= f
DACCLK
/4
f
DCI
= f
DACCLK
/4
f
DACCLK
EVEN DATA
SAMPLES
ODD DAT A
SAMPLES
OPTIONAL PARITY
COMBINED
ODD/EVEN
PARITY BIT
11149-134
Figure 129. Recommended Digital Interface Between the AD9119/AD9129 and the Host Processor
INPUT DAT A[ 13: 0]
DCI
DLL P HAS E
DELAY
t
DATA PERI OD
t
DATA SKEW
t
DSC SETUP AND HOLD
t
DATA JI T TE R
DATA SAM P LE CLOCK
DATA EY E
11149-135
Figure 130. LVDS Data Port Timing Requirements
AD9119/AD9129 Data Sheet
Rev. B | Page 40 of 66
Figure 131 shows the DSC set and hold times with respect to
the DCI signal and data signals.
11149-238
DCI
DATA
DSC
t
S
t
H
Figure 131. LVDS Data Port Set and Hold Times
Table 11 shows the typical times for various DAC clock frequencies
that are required to calculate the data valid margin. The amount
of margin that is available for tuning of the DSC sampling point
can be determined using Table 11.
Table 10 lists the values that are guaranteed over the operating
conditions. These values were taken with 50% duty cycle and
DCI swing of 450 mV p-p. For best performance, the duty cycle
variation should be kept below ±5%, and the DCI input should
be as high as possible, up to 800 mV p-p.
Table 10. Data Port Set and Hold Time Window (Guaranteed)
Frequency,
fDAC (MHz) Time (ps)
Data Port Set and Hold Times (ps)
at DLL Phase
−3 0 +3
1600 tS −272 −489 −683
tH 682 911 1120
2300 tS −168 −292 −420
tH 564 705 839
2800 tS −88 −185 −285
tH 457 559 652
Table 11. Data Port Set and Hold Time Window (Typical)
Frequency,
fDAC1 (MHz)
Time
(ps)
Data Port Set and Hold Times (ps) at DLL Phase
−6 −5 −4 −3 −2 −1 0 +1 +2 +3 +4 +5 +6
1400 tS −106 −205 −274 −353 −436 −523 −604 −680 −798 −906 −993 −1064 −1131
tH 426 499 571 651 730 813 900 977 1069 1152 1235 1303 1387
1500 tS −124 −197 −291 −351 −453 −524 −600 −670 −732 −815 −908 −982 −1071
tH 427 490 556 637 713 795 870 942 1025 1100 1181 1241 1320
1600 tS −120 −191 −252 −335 −402 −495 −552 −626 −704 −776 −847 −902 −978
tH 421 485 550 619 689 760 836 910 989 1049 1128 1195 1250
1700 tS −111 −184 −226 −301 −370 −442 −528 −580 −641 −719 −784 −822 −895
tH 382 429 489 549 619 700 762 825 907 970 1032 1095 1151
1800
t
S
−93
−133
−209
−265
−326
−401
−475
−524
−596
−646
−709
−765
−823
tH 400 442 492 555 617 677 754 816 883 950 1003 1061 1122
1900 tS −90 −139 −182 −254 −298 −359 −430 −496 −547 −593 −663 −700 −765
t
H
398
443
488
535
593
664
717
778
849
900
963
1021
1070
2000 tS −82 −122 −170 −220 −272 −346 −399 −452 −517 −565 −607 −660 −713
tH 389 423 468 522 571 625 683 733 789 854 908 958 1015
2100 tS −87 −133 −161 −206 −274 −331 −384 −443 −488 −540 −586 −623 −675
tH 370 409 451 491 536 592 636 696 751 794 855 911 954
2200 tS −94 −143 −182 −245 −283 −334 −378 −427 −487 −521 −565 −604 −659
tH 415 453 487 523 571 622 673 722 778 818 859 908 956
2300 tS −93 −131 −182 −227 −270 −312 −357 −388 −439 −485 −531 −570 −623
tH 390 422 456 500 542 595 644 686 731 778 821 858 902
2400 tS −130 −156 −196 −244 −277 −313 −366 −404 −457 −496 −534 −560 −615
tH 426 459 494 529 567 607 653 698 731 769 815 862 911
2500 tS −73 −106 −142 −177 −216 −258 −308 −348 −394 −430 −458 −486 −535
tH 370 407 433 467 502 546 582 619 662 702 740 780 828
2600 tS −43 −76 −115 −145 −184 −228 −275 −306 −351 −375 −402 −443 −491
tH 338 369 396 430 466 503 535 567 614 652 690 725 766
2700 tS −54 −77 −108 −144 −179 −228 −277 −305 −336 −354 −400 −424 −471
tH 316 340 372 406 441 475 499 539 580 622 654 685 729
2800 tS −36 −72 −101 −143 −175 −208 −243 −287 −320 −347 −382 −408 −463
tH 335 355 379 404 442 480 511 545 575 607 638 676 717
1 Table 11 shows characterization data for selected fDAC frequencies. Other frequencies are possible, and Table 11 can be used to estimate performance.
Data Sheet AD9119/AD9129
Rev. B | Page 41 of 66
Maximizing the opening of the eye in both the DCI and data
signals improves reliability of the data port interface. Use differ-
ential controlled impedance traces of equal length (that is, delay)
between the host processor and the AD9119/AD9129 input. To
ensure coincident transitions with the data bits, implement the
DCI as an additional data line with an alternating (010101…)
bit sequence from the same output drivers that are used for
the data.
For synchronous operation between the host and the AD9119/
AD9129, the AD9119/AD9129 provide a data clock output, DCO,
to the host at the same rate as DCI (that is, fDACCLK/4). Note that
the DCI signal can have arbitrary phase alignment with respect to
the DCO because the DLL of the AD9119/AD9129 ensures proper
data hand-off between the two clock domains (that is, the host
processors and the internal digital core of the AD9119/AD9129).
The default reset state of the AD9119/AD9129 is to have the
DCO signal disabled. To enable it, write a 1b to Register 0x0C,
Bit 6. The DCO output level is controlled in Register 0x7C,
Bits[7:6]. The default setting is 01b, or 2.8 mA, but it can be
increased to as high as 4 mA (11b) if higher swing is necessary.
The DCI signal is ac-coupled internally; therefore, a possibility
exists that removing the DCI signal can cause DAC output chatter
due to randomness on the DCI input. To avoid this chatter, it is
recommended that the DAC output be disabled when the DCI
signal is not present. To do this, program the DAC output current
power-down bit in Register 0x01, Bit 6, to 1b. When the DCI signal
is again present, the DAC output can be enabled by programming
Register 0x01, Bit 6, to 0b. The DAC output powers up in ~2 µs.
The status of the DLL can be polled by reading the data status
register at Address 0x0E. Bit 0 indicates that the DLL is running
and attempting lock, and Bit 7 is set to 1b when the DLL is locked.
Bit 2 is set to 1b when a valid data clock is detected. The warning
bits in Address 0x0E, Bits[6:4] can be used as indicators that the
DAC may be operating in a nonideal location in the delay line.
Note that these bits are read at the SPI port speed, which is much
slower than the actual speed of the DLL. This means that these
bits can show only a snapshot of what is happening, rather than
giving real-time feedback.
Temperature Effects
The length of the delay line varies slightly across the operating
temperature range, as the amount of delay through a delay cell
expands or contracts slightly due to the temperature change.
This can introduce a situation where the DLL may lock at one
temperature extreme and then approach an unlocked state as
the temperature changes (see Figure 132).
In the example shown in Figure 132, the DLL can lock at Phase
Setting 0 at 90° in a cold temperature. As the temperature gets
hotter, the delay line changes length, and the controller adjusts
the DLL control voltage to keep the 90° offset. In this case, a voltage
beyond the acceptable control voltage range is required to hold
the 90° phase offset.
Before losing lock, the DLL controller issues a DLL warning by
setting Register 0x0E, Bit 6, to 1b and setting either Bit 5 or Bit 4
to 1b. This setting indicates that the DLL is near to losing lock. If
the DLL is going to reach the beginning of the delay line soon,
the controller issues a start warning by setting Register 0x0E, Bit 5
and Bit 6 to 1b. This setting indicates that the DLL is at the start
of the delay line, and losing lock is imminent.
D0 D1
USER DCI
USER DAT A
DATA
SAMPLE CLK
90°
DELAY LI NE – COLD
DELAY LI NE
–
HOT
11149-236
Figure 132. Example of DLL Length Variation Across Temperature
A similar situation can happen at the end of the delay line, in
which case a DLL warning and a DLL end is issued. DLL end is
indicated when Register 0x0E, Bit 4 and Bit 6 are set to 1b.
In case of a DLL warning, action must be taken to prevent loss
of lock. On a start warning, reduce the minimum delay of the
delay line by removing one or several of the delay cells. This
can be accomplished by setting the bits in Registers 0x70 and
Register 0x71 to 0b. Begin by setting Bit 0 of Register 0x70 to 0b,
then Bit 1, and so on. In some cases, up to three delay cells may
need to be disabled. It is possible to disable up to six delay cells.
However, in most cases, none of the cells need to be disabled.
The situation varies, depending on the temperature range needed,
as well as the DACCLK signal rate used. The end warning case
is a theoretical possibility, but practical conditions normally
dictate that it is not reachable. If the end warning is reached, the
DLL must be relocked immediately. When doing initial lock (or
relock) of the DLL, all delay cells must be active, with all delay cell
bits in Register 0x70 and Register 0x71 set to 1b.
Parity
The data interface can be continuously monitored by enabling
the parity bit feature in Register 0x5C, Bit 7, and configuring
the FRM_P, FRM_N pins (Pin K13 and Pin K14) as parity pins
by setting Register 0x07, Bits[1:0] = 1 dec. When this pin con-
figuration is used, the host sends a parity bit along with each data
sample. This bit is set according to the following formulas,
where n is the data sample that is being checked.
For even parity on the AD9129,
XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n),
P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 0.
For odd parity on the AD9129,
XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n),
P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 1.
AD9119/AD9129 Data Sheet
Rev. B | Page 42 of 66
For the AD9119, the data port is 11-bit instead of 14-bit, so
P0_D11, P0_D12, P0_D13, P1_D11, P1_D12, and P1_D13 are
not used in the calculation of the parity bit. Thus, the parity bit
is calculated over 29 bits (including the frame/parity bit) for the
AD9129 and over 23 bits for the AD9119.
If a parity error occurs, the parity error counter (Register 0x5D
or Register 0x5E) is incremented. Parity errors on the bits that
are sampled by the rising edge of DCI increment the parity
rising edge error counter (Register 0x5D) and set the parity
error rising edge bit (Register 0x5C, Bit 0). Parity errors on the
bits that are sampled by the falling edge of DCI increment the
parity falling edge error counter (Register 0x5E) and set the
parity error falling edge bit (Register 0x5C, Bit 1). The parity
counter continues to accumulate until it is cleared, or until it
reaches a maximum value of 255. The count can be cleared by
writing 1b to Register 0x5C, Bit 5.
An IRQ can be enabled to trigger when a parity error occurs by
writing 1b to Register 0x04, Bit 2 for rising edge-based parity
detection or to Register 0x04, Bit 3 for falling edge-based parity.
The status of IRQ can be measured via Register 0x06, Bit 2 or
Register 0x06, Bit 3 or by using the IRQ pin. When using the IRQ
pin and more than one IRQ is enabled, check Register 0x06,
Bits[3:2] when an IRQ event occurs to determine whether the
IRQ was caused by a parity error. The IRQ can also be cleared
by writing 1b to Register 0x06, Bit 2 or Register 0x06, Bit 3.
The parity bit feature can also be used to validate the interface
timing. As described previously, the host provides a parity bit
with the data samples and configures the AD9119/AD9129 to
generate an IRQ. The user can then sweep the sampling instance
of the AD9119/AD9129 input registers to determine at what
point a sampling error occurs.
DIGITAL DATAPATH DESCRIPTION
Figure 133 provides a more detailed diagram of the AD9119/
AD9129 digital datapath. The 22-bit/28-bit datapath with
internal DDR clocking interfaces with the dual 11-bit/14-bit
input data ports. Because two 11-bit/14-bit samples are captured
on each clock edge of DCI, four consecutive samples are captured
per DCI clock cycle. Samples captured on the rising edge of DCI
propagate through the upper section at a rate of DACCLK/2
(DDR), and those captured on the falling edge propagate through
the lower section.
14
14
14
14
14
14
28
PARITY/
SED LOGIC
INPUT
LATCH
INPUT
LATCH
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
RESET
LOGIC
FRAME
SPI FIFO ALIGN REQUEST
REG 0x11[7]
SPI FIFO ALIGN ACKNOWLEDGE
REG 0x11[6]
FIFO WRITE POINTEROFFSET
REG 0x12[2:0]
RD PTR
RESET
WR P TR
RESET
RD PTR
RESET
DACCLK/4
WR P TR
RESET
DACCLK/ 4 DIST. DACCLK/4
DLLDCI
DATA
FRAME/
PARITY FRAME
14
14
14 BIT S
28
1
28
1
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
FIFO PH3
PARITY/
SED LOGIC
DATA ASS E M BLER
TO DAC
DECODE
MIX-MODE
FIFO PH1
FIFO PH2
FIFO PH0
11149-136
2×
Figure 133. Digital Datapath of the AD9119/AD9129
Data Sheet AD9119/AD9129
Rev. B | Page 43 of 66
After the input data has been captured, the data is passed through a
logic block that monitors and/or determines the signal integrity
of the high speed digital data interface. The optional parity check
is used to continuously monitor the digital interface on a sample-
per-sample basis, and the sample error detection (SED) can be
used to validate the input data interface for system debug/test
purposes. Note that the FRAME and PARITY signals share the
same pin assignment because the FRAME signal is typically
used during system initialization (for FIFO synchronization
purposes), and parity is used in normal operation.
FIFO Description
The next functional block in the datapath is a set of four FIFOs
that are eight registers deep. The dual port data is clocked into
the FIFOs on both the rising and the falling edge of the DCI signal.
The FIFO acts as a buffer that absorbs timing variations between
the data source and DAC, such as the clock-to-data variation of
an FPGA or ASIC. For the greatest timing margin, maintain the
FIFO level near half full (that is, a difference of four between the
write and read pointers). The value of the write pointer determines
the FIFO register into which the input data is written, and the
value of the read pointer determines the register from which data
is read and fed into the data assembler. The write and read pointers
are updated every time new data is loaded and removed,
respectively, from the FIFO.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. Note that an overflow or
empty condition of the FIFO is the same as the write pointer and
read pointer being equal. When both pointers are equal, an
attempt is made to simultaneously read and write a single FIFO
register. This simultaneous register access leads to unreliable
data transfer through the FIFO and must be avoided by ensuring
that data is written to the FIFO at the same rate that data is read
from the FIFO, keeping the data level in the FIFO constant.
This condition must be met by ensuring that DCI is equal to
DACCLK/4 (or equivalently, DCO).
Resetting the FIFO Data Level
FIFO initialization is required to ensure a four-sample spacing
and a deterministic pipeline latency. If the clocks are running
at power-up, the FIFO initializes to 50% full. The AD9119/
AD9129 has an internal delay that effectively offsets the FIFO
pointers by 2, such that the optimal FIFO data level of 4 (center)
reads back as 2 (0000011b) from Register 0x13 to Register 0x16.
To achieve this level, set Register 0x12 to 0x20 (hexadecimal) before
resetting the FIFO. This sets the read pointer to Level 2 and the
write pointer to Level 0.
To maximize the timing margin between the DCI input and the
internal DAC data rate clock, initialize the FIFO data level before
beginning data transmission. The value of the FIFO data level
can be initialized in three ways: by resetting the device, by strobing
the FRM_x input, and via a write sequence to the serial port.
The two preferred methods are use of the FRAME signal and
via a write sequence to the serial port. Before initializing the
FIFO data level, the LVDS DLL and the DAC clock PLL must be
locked.
The FRM_x input can be used to initialize the FIFO data level
value. First, set up the FRM_N and FRM_P pins for frame mode
(Register 0x07, Bits[1:0] = 2). Next, assert the FRAME signal
high for at least one DCI clock cycle. When the FRAME signal is
asserted in this manner, the write pointer is set to 4 (by default
or to the FIFO start level (Register 0x12, Bits[2:0])) the next
time the read pointer becomes 0 (see Figure 134).
01 2 3 4 5670123
34 5 6 7 0 1 2 4567
FIFO WRITE RESETS
READ
POINTER
FRAME
WRITE
POINTER
11149-137
Figure 134. Timing of the Frame Input vs. Write Pointer Value
To initialize the FIFO data level through the serial port, toggle
Bit 7 of Register 0x11 from 0b to 1b. When the write to the
register is complete, the FIFO data level is initialized.
The recommended procedure for a serial port FIFO data level
initialization is as follows:
1. Request FIFO level reset by setting Register 0x11, Bit 7,
to 1b.
2. Verif y that the part acknowledges the request by ensuring
that Register 0x11, Bit 6, is set to 1b.
3. Remove the request by setting Register 0x11, Bit 7, to 0b.
4. Verif y that the part drops the acknowledge signal by
ensuring that Register 0x11, Bit 6, is set to 0b.
Monitoring the FIFO Status
The relative FIFO data levels can be read from Register 0x13
through Register 0x16 at any time. The FIFO data level reported
by the serial port is denoted as a 7-bit thermometer code of the
write counter state, relative to the absolute read counter being at 0.
For example, the FIFO data level of 2 is reported as a value of
0000011b in the status register. Adding the internal delay of 2 to
this value makes the reported FIFO level equal to 4. It should be
noted that, depending on the timing relationship between DCI
and the main DACCLK signal, the FIFO level value can be off by
a count of ±1. Therefore, it is important that the difference
between the read and write pointers be maintained at ≥2.
Multiple DAC Synchronization
Synchronization of multiple AD9119/AD9129s implies that all
of the DAC outputs are time aligned to the same phase when all
devices are fed with the same data pattern (along with DCI) at
the same instance of time. FIFO initialization ensures that the
initial pipeline latency in the FIFO is set to four samples and
remains at this level, assuming that no process, voltage, or tem-
perature variations occur between the host and the AD9119/
AD9129 clock domains.
AD9119/AD9129 Data Sheet
Rev. B | Page 44 of 66
Figure 136 shows an example of two AD9119/AD9129 devices
that are synchronized to the same host (that is, FPGA or ASIC).
Note that, when the same resources are used to generate these out-
put signals, synchronization to a single host IC ensures minimum
data and DCI time skew between devices.
Synchronization within a data sample requires insight into the
difference between the read pointers of the master and slave
devices, as well as the ability to vary the delay of the slave device(s)
within the host to compensate for initial offsets between devices.
It is possible to calculate how many data samples the slave device(s)
is offset from the master device for the following reasons:
•The pipeline delay of each device is the same after FIFO
initialization (FIFO reset).
•The read counter of each device is derived from the same
phase aligned DACCLK source.
•The state of the read counters of each device is sampled at
the same instance in time via the FRAME signal.
•The readback value (Register 0x12[6:4]) is normalized to
a data sample (that is, a DACCLK period).
By calculating the difference between the read pointer settings
of the master and slave devices, the user can advance or delay
the data stream of the slave device within the FPGA. Because
this difference can be up to ±4 data samples, the FPGA must
provide this adjustment range for DAC synchronization alone.
Note that additional range must be added to compensate for any
other system delay variation.
In addition to synchronizing to the data sample level, the AD9119/
AD9129 can enable synchronization to the DACCLK level (see
Figure 135). A 1.8 V CMOS output pin, SYNC, can be used to
provide a DACCLK/8 signal. Using the SYNC output from each
DAC, enabled by Register 0x1A, Bit 4 = 1, the user can create
a simple phase detector with an external XOR gate.
DAC 1
SYNC
DAC 2
SYNC
XOR
11149-139
Figure 135. Example of Synchronization of Two DACs to
±1 DACCLK Accuracy
By adjusting the internal delay (incrementing or decrementing
by one DACCLK cycle with each write to Register 0x1A, Bit 7 or
Bit 6, respectively), the user can align the DACCLKs inside the two
DACs to within ±1 DACCLK cycle, when errors from the external
phase detector, low-pass filter, and delay differences are taken
into account. The existing phase position can be read from
Register 0x1A, Bits[2:0]. The value of each DAC in Register 0x1A
Bits[2:0] can be different when the DACs are synchronized. Align
the SYNC outputs first, then reset the FIFOs on each DAC to
ensure that proper sync is achieved.
This calibration must be performed at each power-up because
the FIFOs can be reset to any of four levels based on the divide-
by-4 output of the clock distribution block (see Figure 133). For
example, a FIFO reset to Level 2 could have an actual FIFO level
of 1.5, 1.75, 2, or 2.25, based on the location of the div-by-4 clock
edge. Adjusting the SYNC signals to align with each other
eliminates this ambiguity. As with the Sync register (0x1A
Bits[2:0]), the FIFO levels on each DAC do not have to match
(i.e., can be different) when the DACs are synchronized.
The FIFO set or reset level is always a whole number (the
recommended value is 2). Because of this, there is a possibility
that the FIFO can be reset on the border of a rollover from a
fractional level to a whole level (as in 1.75 to 2.0). In this case,
an effect can occur that causes the FIFO Read level to increment
before the final read, thereby shifting the level from 1.75 to 2.75
and thus effectively setting the level to 3 instead of 2. This can
be noticed by a seeming 4 DAC sample offset in the output.
To avoid this issue (setting the FIFO before emptying its last
read), the FIFO must be reset and then read back to understand
its level. If it is a whole number, it is recommended that the DCI
is advanced or delayed by 1 DACCLK cycle relative to the FIFO.
This must be done in the FPGA if DCO is used as the timing
reference for DCI. If this is not possible in the FPGA, then it is
recommended that the DCO NOT be used to generate DCI, in
order to decouple the two clocks and enable this necessary phase
shift. If the DCI is generated independently from the DCO,
then the 1 DACCLK delay or advance can be accomplished by
incrementing or decrementing by 1 the SYNC output of both
DACs in the same direction.
When the two DACs are aligned, the drift over temperature and
supply voltage of the SYNC signal of one DAC, relative to
another DAC, is expected to be no more than 450 ps.
The DCO signal is derived from the SYNC signal such that if
the SYNC signal is adjusted by a DACCLK cycle, the DCO
signal will also be adjusted by the same amount.
When all adjustments of the SYNC signal are complete, it is
recommended to disable the SYNC output by programming
Register 0x1A, Bit 4 = 0, to eliminate a possible source of clock
spurious signals.
Data Sheet AD9119/AD9129
Rev. B | Page 45 of 66
AD9129
MASTER
DACCLK
MATCHED
DELAYS
DCI ADCLK925
1.4GHz
TO
2.8GHz
COMMON
CLOCK
SOURCE
DCO_x
FPGA
DCI_x
FRM_x
AD9129
SLAVE
DACCLK
DCO_x
DCI_x
FRM_x
0+ dBm
0+ dBm
11149-138
Figure 136. Example of Synchronization of Two DACs to One FPGA
Data Assembler and Signal Processing Modes
The data assembler reconstructs the original sample sequence.
It consists of a 4:1 multiplexer operating at fDACCLK. Each of the
four FIFOs provides a sample that is now referenced to the
internal clock domain of the AD9119/AD9129, fDACCLK. The
reconstructed sample sequence can be directed to the DAC
decode logic or undergo additional signal processing. In 2×
interpolation mode, a FIR filter is used to generate a new data
sample that is inserted between each sample, such that it can
update the DAC decode logic on the falling edge of DACCLK.
In Mix-Mode, the complement of each data sample is generated
and inserted after it, such that it also updates the DAC in a similar
manner. The 2× interpolator can be used with Mix-Mode enabled.
2× Digital Filter
The AD9119/AD9129 include a bypassable 2× half-band
interpolation filter to help simplify the analog reconstruction
filter. The filter has the potential benefit of minimizing the
impact of folded back harmonics in the desired baseband
region. The filter operates in a dual-edge clocking mode, where
it generates a new interpolated sample value for every alternate
DACCLK edge. This effectively increases the DAC update rate
to 2 × fDACCLK with the DAC’s sinc response null moving from
fDACCLK to 2 × fDACCLK.
There are two different filters, FIR25 and FIR40, that can be
chosen using Register 0x18, Bit 5, when the 2× interpolator is
enabled with Register 0x18, Bit 7.
The FIR25 half-band filter provides 25 dB of stop-band rejection.
Its response is shown in Figure 137. Coefficients were optimized
for practical implementation purposes with the notion that the
±0.5 dB pass-band ripple effects on a multicarrier application
(for example, DOCSIS) can be compensated by the digital host
adjusting individual channel powers. Note that the worst-case
tilt across any 6 MHz channel is less than −0.05 dB.
The FIR40 half-band filter provides 40 dB of stop-band rejection,
and its response is shown in Figure 139. Coefficients were
chosen to reduce pass-band ripple and increase out-of-band
rejection for multicarrier applications (for example, DOCSIS).
As a result, the frequency response has a flatter in-band response
and a sharper transition region, and the trade-off is a higher phase
count, leading to higher pipeline delay and higher power
consumption. The two filters are compared in Table 12.
Table 12. Features of the Two 2× Interpolation Filters
Filter Ripple (dB) Attenuation (dB) Power (mW)
FIR25 ±0.5 25 150
FIR40 ±0.1 40 450
A duty cycle restore circuit follows the DACCLK clock receiver
to minimize impact of duty cycle errors on image rejection.
0500 1000 1500 2000 2500
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
FREQUENCY (MHz)
MAGNITUDE ( Normalized to 0dB)
11149-140
Figure 137. FIR25 2× Interpolation Filter Plot, Complete Frequency Response;
fDAC = 2.5 GHz
AD9119/AD9129 Data Sheet
Rev. B | Page 46 of 66
0200 400 600 800 1000 1200
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY (MHz)
MAGNIT UDE ( Normal ized t o 0d B)
11149-141
Figure 138. FIR25 2× Interpolation Filter Plot, Pass-Band Ripple; fDAC = 2.5 GHz
00.90.80.70.60.50.40.30.20.1 1.0
–60
–50
–55
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
NORM ALIZED FREQ UE NCY ( × π RAD/Sample)
MAGNITUDE ( dB)
11149-142
Figure 139. FIR40 2× Interpolation Filter Plot, Complete Frequency Response
00.450.400.350.300.250.200.150.100.05 0.50
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
NORMALI ZED F RE QUENCY ( × π RAD/Sample)
MAGNITUDE ( dB)
11149-143
Figure 140. FIR40 2× Interpolation Filter Plot, Pass-Band Ripple
Pipeline Delay (Latency)
The pipeline delay, or latency, of the AD9129 varies, based on
the configuration that is chosen and can be calculated using the
following formula:
Pipeline_Total = Pipeline_Delay + 2×_Delay
+ Group_Delay + FIFO_Level
The values listed in Table 13 can be used, depending on the
mode of operation that is selected.
Table 13. Pipeline Delay Values for Each Block
Mode
Pipeline
Delay
(fDAC cycles)
Group
Delay
(fDAC cycles)
Total
Pipeline
(fDAC cycles)
Total
Delay
(fDAC cycles)
No 2× filter 74 N/A 74 74
With FIR25 43 2 117 119
With FIR40 67 9 141 150
The terms used in Table 13 are defined as follows:
•Pipeline delay is the time from DAC code latched until the
DAC output begins to move.
•Group delay is the time for the maximum amplitude pulse
to reach the DAC output, as compared to the first time the
output moves.
•No 2× filter is the base pipeline delay, including data
interface, analog circuitry (six cycles), and data FIFO at
half-full/Position 3.
•FIR25 is the 2× interpolator with 25 dB of out-of-band
rejection.
•FIR40 is the 2× interpolator with 40 dB of out-of-band
rejection.
Note that the values for pipeline delay apply in both normal
mode and Mix-Mode. After the total delay through the digital
blocks is calculated, add the FIFO level to that delay to find the
total pipeline delay. Note that the pipeline delay can be considered
fixed, with the only ambiguity being the FIFO state. The FIFO
state can be initialized as part of the startup sequence to ensure
a four sample spacing and, therefore, a fixed pipeline delay, or
deterministic latency (see the Resetting the FIFO Data Level
section for more information).
To ensure repeatable pipeline delay over multiple power-up cycles,
the SYNC output of the DAC must be aligned with a known system
sync reference. Follow a calibration process that is similar to the
multiple DAC sync process (see the Multiple DAC Synchronization
section for more information) after each power-up event to align
the DAC to the system sync reference.
Power-Up Time
The AD9119/AD9129 have a power-down register (Register 0x01)
that enables the user to power down various portions of the DAC.
The power-up time for several usage cases is shown in Table 14.
The recommended way to power up the AD9119/AD9129 is
to power up all parts of the circuit with IREF disabled (by setting
Register 0x01, Bit 6 = 1b), and then enable IREF by programming
Register 0x01, Bit 6 = 0b.
Table 14. Power-Up Times for Several Usage Cases
State Register State Time (µs)
Power-Up From 0x01 = 0xEF to 0x01 = 0x08 250
Clock Path Up From 0x01 = 0x0C to 0x01 = 0x08 220
Wake-Up From 0x01 = 0x48 to 0x01 = 0x08 2
Data Sheet AD9119/AD9129
Rev. B | Page 47 of 66
RESET
The hardware reset pin (Pin H1) is active high and resets all
registers on the device. The software reset bit in Register 0x00
(Bit 5) performs the same reset function, except that it preserves
the current contents of Register 0x00.
INTERRUPT REQUESTS
The AD9119/AD9129 can provide the host processor with an
interrupt request output signal (IRQ), indicating that one or
more of the following events has occurred:
•One of the clock controllers has established or lost lock.
•A parity error has occurred.
•A sample error detection status or result is ready.
•The FIFO is nearing an overwrite status.
The IRQ output signal is an active low output signal that is available
on the IRQ pin (Pin H2). If used, connect the output to VDD via
a 10 kΩ pull-up resistor.
Each IRQ is enabled by setting the enable bits in Register 0x03 and
Register 0x04 that have the same bit mapping as the IRQ status bits
in Registers 0x05 and Register 0x06. If an interrupt bit is not
enabled, a read request of that bit shows a direct readback of the
current state of the source. Thus, a read request of either register
shows the current state of all eight interrupts in that register,
regardless of whether each individual bit is actually enabled to
generate an interrupt. When an interrupt bit is enabled, it captures
a rising edge of the interrupt source and holds it, even if the source
subsequently returns to its zero state. It is possible, for example, for
the retimer lost interrupt enable and retimer lock interrupt enable
status bits (Register 0x03[1:0], respectively) to be set when a
controller temporarily loses lock but then reestablishes lock before
the IRQ is serviced by the host. In such a case, the host should
validate the present status of the suspect block by reading back its
current status bits. Based on the status of these bits, the host can
take appropriate action, if required.
The IRQ pin responds only to those interrupts that are enabled. To
clear an IRQ, it is necessary to write a 1b to the bit in Register 0x05
or Register 0x06 that caused the interrupt. See Figure 141 for
a detailed diagram of the interrupt circuitry.
The IRQ can also be used during the AD9119/AD9129
initialization phase after power-up to determine when the
retimer PLL and data receiver controllers achieve lock. For
example, before enabling the retimer PLL, the retimer lock
interrupt enable bit (Register 0x03[0]) can be set, and the IRQ
output signal can be monitored to determine when lock is
established, before continuing in a similar manner with the data
receiver controller. Clear the relevant lock bit, after locking, before
continuing to the next controller. When all of the controllers are
locked, set the appropriate lost lock enable bits in Register 0x03
to continuously monitor the controllers for loss of lock.
R
QD
WRITE1b TO
REQUE S T BI T
IRQ E NABLE
SOURCE IRQ RE QUEST
IRQ E NABLE
IRQ E NABLE
IRQ PIN
OT HE R IRQ
BITS
SINGLE IRQ BIT
11149-144
Figure 141. Interrupt Request Circuitry
Table 15. Interrupt Request Registers
Addr (Hex) Bit Bit Name Description
0x05 7 FIFO_Warn2 interrupt status Indicates that the FIFO is within two slots of overwrite
6 FIFO_Warn1 interrupt status Indicates that the FIFO is within one slot of overwrite
5 SPIFrmAck interrupt status Indicates acknowledgement that the SFrmReq bit has changed from 0b to 1b
4 Reserved Reserved
3 DLL warn interrupt status Indicates that the DLL is close to coming unlocked and action is needed
2 DLL lock interrupt status Indicates that the DLL is now locked
1 Retimer lost interrupt status Indicates that the retimer PLL is no longer locked
0 Retimer lock interrupt status Indicates that the retimer PLL is now locked
0x06 7 Reserved Reserved
6 AED pass interrupt status Indicates that the AED logic has captured eight valid samples
5 AED fail interrupt status Indicates that the AED logic has detected a miscompare
4 SED fail interrupt status Indicates that the SED logic has detected a miscompare
3 Parity error falling edge status Indicates a parity fault due to data captured on the falling edge
2 Parity error rising edge status Indicates a parity fault due to data captured on the rising edge
1 Reserved Reserved
0 Reserved Reserved
AD9119/AD9129 Data Sheet
Rev. B | Page 48 of 66
INTERFACE TIMING VALIDATION
The AD9119/AD9129 provide on-chip sample error detection
(SED) circuitry that simplifies verification of the input data
interface. The SED compares the input data samples captured
at the digital input pins with a set of comparison values. The
comparison values are loaded into registers through the SPI port.
Differences between the captured values and the comparison
values are detected and stored.
SAMPLE ERROR DETECTION (SED) OPERATION
The SED circuitry operates on a data set made up of eight
11-bit/14-bit input words, denoted as R0L, R1L, R0H, R1H,
F0L, F1L, F0H, and F1H. These represent the rising edge and
falling edge data of Data Port 0 and Data Port 1. (The AD9119/
AD9129 use both edges of the DCI clock to sample data on each
input port.) To properly align the input samples, the rising edge
data-words of the data ports (that is, RxL and RxH) are indicated
by asserting the FRAME signal for a minimum of two complete
input samples.
Figure 142 shows the input timing of the interface in word mode.
The FRAME signal can be issued once at the start of the data
transmission, or it can be asserted repeatedly at intervals coinciding
with the RxL and RxH data-words.
11149-249
FRAME
P0[7:0]
P0[13:8]
DCI
R0L
R0H
F0L
F0H
P1[7:0]
P1[13:8]
R1L
R1H
F1L
F1H
Figure 142. Timing Diagram of FRAME Signal Required to Align Input Data
for SED
The SED has three flag bits (Register 0x50, Bit 0, Bit 1, and Bit 2)
that indicate the results of the input sample comparisons. The
SED fail bit (Register 0x50, Bit 0) is set when an error is detected
and remains set until cleared. The SED also provides registers that
indicate which input data bits experienced errors (Register 0x51
through Register 0x58). These bits are latched and indicate the
accumulated errors detected until cleared. To cl ear the SED
registers, write 1b to Register 0x50, Bit 6.
The autosample error detection (AED) mode is an autoclear
mode that has the following two effects:
•AED mode activates the AED fail bit and the AED pass bit
(Register 0x50, Bit 1 and Bit 2).
•AED mode changes the behavior of Register 0x51 through
Register 0x58.
The compare pass bit is set if the last comparison indicates that
the sample is error free. The compare fail bit is set if an error is
detected. The compare fail bit is automatically cleared by the
reception of eight consecutive error-free comparisons. When
autoclear mode is enabled, Register 0x51 through Register 0x58
accumulate errors as previously described but reset to all 0s after
eight consecutive error-free sample comparisons are made.
The sample error, compare pass, and compare fail flags can be
configured to trigger an IRQ when active, if desired. This is
accomplished by enabling the appropriate bits in the event flag
register (Register 0x06, Bit 4, Bit 5, and Bit 6).
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of an IRQ
when a single error is detected.
1. Write to the following registers to load the comparison values:
a) Register 0x51: SED Patt/Err R0L, Bits[7:0].
b) Register 0x52: SED Patt/Err R0H, Bits[13:8].
c) Register 0x53: SED Patt/Err R1L, Bits[7:0].
d) Register 0x54: SED Patt/Err R1H, Bits[13:8].
e) Register 0x55: SED Patt/Err F0L, Bits[7:0].
f) Register 0x56: SED Patt/Err F0H, Bits[13:8].
g) Register 0x57: SED Patt/Err F1L, Bits[7:0].
h) Register 0x58: SED Patt/Err F1H, Bits[13:8].
i) Comparison values can be chosen arbitrarily;
however, choosing values that require frequent
bit toggling provides the most robust test.
2. Enable the SED error detect flag to assert the IRQ pin.
a) Register 0x04: set to 0x10.
3. Begin transmitting the input data pattern.
4. Write three times to Register 0x50 to enable the SED.
a) Register 0x50: set to 0x80.
b) Register 0x50: set to 0xC0.
c) Register 0x50: set to 0x80.
If IRQ is asserted, read Register 0x50 and Register 0x51 through
Register 0x58 to verify that a SED error is detected and determine
which input bits are in error. The bits in Register 0x51 through
Register 0x58 are latched. This means that the bits indicate any
errors that occur on those bits throughout the test and not just
the errors that caused the error detected flag to be set.
Data Sheet AD9119/AD9129
Rev. B | Page 49 of 66
ANALOG INTERFACE CONSIDERATIONS
ANALOG MODES OF OPERATION
The AD9119/AD9129 use the quad-switch architecture shown in
Figure 143. Only one pair of switches is enabled during a half-clock
cycle, thus requiring each pair to be clocked on alternative clock
edges. A key benefit of the quad-switch architecture is that it masks
the code-dependent glitches that occur in the conventional two-
switch DAC architecture.
V
G
1
V
SSA
IOUTP IOUTN
V
G
1 V
G
2 V
G
3 V
G
4
DACCLK_xCLK
LATCHES
Px_D[13:0]x
V
G
2
V
G
3
V
G
4
11149-146
Figure 143. Quad-Switch Architecture
In two-switch architecture, when a switch transition occurs and
D1 and D2 are in different states, a glitch occurs. But, if D1 and
D2 happen to be at the same state, the switch transitions, and no
glitches occur. This code-dependent glitching causes an increased
amount of distortion in the DAC. In quad-switch architecture
(no matter what the codes are), there are always two switches
that are transitioning at each half-clock cycle, thus eliminating
the code-dependent glitches but, in the process, creating a constant
glitch at 2 × DACCLK. For this reason, a significant clock spur
at 2 × fDACCLK is evident in the DAC output spectrum.
INPUT
DATA
DACCLK_x
TWO-SWITCH
DAC OUTPUT
FOUR-SWITCH
DAC OUTPUT
(NORMAL MODE)
t
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
6
D
7
D
8
D
9
D
10
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
1
D
2
D
3
D
4
D
5
t
11149-147
Figure 144. Two-Switch and Quad-Switch DAC Waveforms
As a consequence of the quad-switch architecture enabling
updates on each half-clock cycle, it is possible to operate that
DAC core at 2× the DACCLK rate if new data samples are latched
into the DAC core on both the rising and falling edge of the
DACCLK. This notion serves as the basis when operating the
AD9119/AD9129 in either Mix-Mode or with the 2× interpo-
lation filter enabled. In each case, the DAC core is presented
with new data samples on each clock edge, albeit in Mix-Mode;
the falling edge sample is simply the complement of the rising
edge sample value.
When Mix-Mode is used, the output is effectively chopped at
the DAC sample rate. This has the effect of reducing the power
of the fundamental signal while increasing the power of the
images centered around the DAC sample rate, thus improving
the dynamic range of these images.
INPUT
DATA
DACCLK_x
FOUR-SWITCH
DAC OUTPUT
(
f
S
MIX-MODE)
–D
6
–D
7
–D
8
–D
9
–D
10
D
6
D
7
D
8
D
9
D
10
–D
1
–D
2
–D
3
–D
4
–D
5
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
1
D
2
D
3
D
4
D
5
t
11149-148
Figure 145. Mix-Mode Waveform
This ability to change modes provides the user the flexibility to
place a carrier anywhere in the first three Nyquist zones, depending
on the operating mode selected. Switching between baseband
and Mix-Mode reshapes the sinc roll-off inherent at the DAC
output. In baseband mode, the sinc null appears at fDACCLK
because the same sample latched on the rising clock edge is also
latched again on the falling clock edge, thus resulting in the
same ubiquitous sinc response of a traditional DAC. In Mix-
Mode, the complement sample of the rising edge is latched on
the falling edge, therefore pushing the sinc null to 2 × fDACCLK.
Figure 146 shows the ideal frequency response of both modes
with the sinc roll-off included.
NORMALIZED FREQUENCY RELATIVE T O
f
DACCLK
(Hz)
0 1.501.251.000.750.500.25
–35
–30
–25
–20
–15
–10
–5
0
FIRST
NYQUIST ZONE SECOND
NYQUIST ZONE THIRD
NYQUIST ZONE
MIX-MODE
dBFS
BASEBAND
MODE
11149-149
Figure 146. Sinc Roll-Off for Baseband Mode and Mix-Mode Operation
The quad-switch can be configured via SPI (Register 0x19, Bit 0)
to operate in either baseband mode (0b) or Mix-Mode (1b).
AD9119/AD9129 Data Sheet
Rev. B | Page 50 of 66
CLOCK INPUT
The AD9119/AD9129 contain a low jitter, differential clock
receiver that is capable of interfacing directly to a differential
or single-ended clock source. Because the input is self-biased to
a nominal midsupply voltage of 1.25 V with a nominal impedance
of 10 kΩ//2 pF, it is recommended that the clock source be
ac-coupled to the DACCLK_x input pins with an external
differential load of 100 Ω. When the nominal differential input
span is 1 V p-p, the clock receiver can operate with a span that
ranges from 250 mV p-p to 2.0 V p-p.
DACCLK_PTO DAC
AND DLL
DACCLK_N
1.25V
5kΩ 5kΩ
50kΩ
25µA
DUTY CY CLE
RESTORER
11149-150
Figure 147. Clock Input
The quality of the clock source, as well as its interface to the
AD9119/AD9129 clock input, directly impacts ac performance.
Select the phase noise and spur characteristics of the clock source
to meet the target application requirements. Phase noise and
spurs at a given frequency offset on the clock source are directly
translated to the output signal. It can be shown that the phase noise
characteristics of a reconstructed output sine wave are related to
the clock source by 20 × log10 (fOUT/fCLK) when the DAC clock
path contribution is negligible. (The wideband noise is not
dominated by the thermal and quantization noise of the DAC.)
Figure 148 shows a clock source based on the ADF4350 low phase
noise/jitter PLL. The ADF4350 can provide output frequencies
from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms. Its
squared-up output level can be varied from −4 dBm to +5 dBm,
allowing further optimization of the clock drive level.
A clock control register exists at Address 0x30. This register can
be used to enable automatic duty cycle correction (Bit 1), enable
zero-crossing control (Bit 6), and set the zero-crossing point
(Bits[5:2]). Recommended settings for this register are listed in
the recommended start-up sequence section (see the Start-Up
Sequence section).
PLL
The DACCLK_x input goes to a high frequency PLL to ensure
robust locking of the DAC sample clock to the input clock. The
PLL is enabled by default such that the PLL locks upon power-up.
The PLL (or DAC clock retimer) control registers are located at
Register 0x33 and Register 0x34. Register 0x33 enables the user
to set the phase detector phase offset level (Bits[7:4]), clear the PLL
lost lock status bit (Bit 3), choose the PLL divider for optimum per-
formance (Bit 2), and choose the phase detector mode (Bits[1:0]).
These settings are determined during product characterization
and are given in the recommended start-up sequence (see the
Start-Up Sequence section). It is not normally necessary to change
these values, nor is the product characterization data valid on
any settings other than the recommended ones. Register 0x34 is
used to reset the PLL, should that become necessary.
At DACCLK = 2.85 GSPS, the lock time is about 10 µs. In most
situations, no action is required with the PLL. If the DACCLK
is changed and, especially, if it is changed multiple times, as in
a frequency hopping application, a phase slip or glitch may be
caused by the change in frequency, and it may become necessary
to reset the PLL. This can be checked by reading the PLL retimer
lost lock bit (Register 0x35, Bit 6). If that is the case, toggle the
PLL reset bit by programming Register 0x34, Bit 3, high and then
low. In addition, clear the PLL retimer lost lock bit by writing 0b
to Register 0x35, Bit 6. PLL lock can be verified by reading the
PLL lock bit at Register 0x35, Bit 7. It is possible to use the IRQ
registers to set an interrupt for these events. See the Interrupt
Requests section for more details.
VCO
PLL
ADF4350
f
REF
0.8GHz TO 2. 8GHz
1V p-p
2.4nF
2.4nF
AD9129
100Ω
DACCLK_P
DACCLK_N
DIV-BY-2
N
N = 0 – 4
11149-151
Figure 148. Possible Signal Chain for DACCLK_x Input
Data Sheet AD9119/AD9129
Rev. B | Page 51 of 66
VOLTAGE REFERENCE
The AD9119/AD9129 output current is set by a combination of
digital control bits and the I250U reference current, as shown in
Figure 149.
CURRENT
SCALING
FSC[9:0]
AD9129
DAC
I
FULLSCALE
4kΩ
1nF
VREF
I250
–1.5V
I250U
V
BG
1.0V
+
–
11149-153
Figure 149. Voltage Reference Circuit
The reference current is obtained by forcing the band gap
voltage across an external 4.0 kΩ resistor from I250U (Pin A1)
to VSSA. The 1.0 V nominal band gap voltage (VREF) generates a
250 µA reference current in the 4.0 kΩ resistor. Note the
following constraints when configuring the voltage reference
circuit:
•Both the 4.0 kΩ resistor and 1 nF bypass capacitor are
required for proper operation.
•Adjusting the DAC output full-scale current, IOUTFS, from
its default setting of 20 mA should be performed digitally.
•The AD9119/AD9129 are not multiplying DACs. Modula-
tion of the reference current, I250U, with an ac signal is not
supported.
•The band gap voltage appearing at the VREF pin must be
buffered for use with an external circuitry because its output
impedance is approximately 7.5 kΩ.
•An external reference can be used to overdrive the internal
reference by connecting it to the VREF pin.
As mentioned, the IOUTFS can be adjusted digitally over a 9.4 mA
to 34.2 mA range by the FSC_x[9:0] bits (Register 0x20, Bits[7:0]
and Register 0x21, Bits[1:0]). The following equation relates
IOUTFS to the FSC_x[9:0] bits, which can be set from 0 to 1023.
IOUTFS = 24.21875 mA × FSC_x[9:0]/1000 + 9.4 mA (1)
Note that the default value of 0x200 generates 21.937 mA full scale,
but most of the characterization presented in this datasheet uses
33 mA, unless noted otherwise.
ANALOG OUTPUTS
Equivalent DAC Output and Transfer Function
The AD9119/AD9129 provide complementary current outputs,
IOUTP and IOUTN, that sink current from an external load
that is referenced to the 1.8 V VDDA supply. Figure 150 shows
an equivalent output circuit for the DAC. Compared to most
current output DACs of this type, the outputs of the AD9119/
AD9129 exhibit a slight offset current (that is, IOUTFS/17), and the
peak differential ac current is slightly below IOUTFS/2 (that is,
8/17 × IOUTFS).
(9/17) × I
OUTFS
I
PEAK
=
(8/17) × I
OUTFS
I
OUTFS
=9.5mA – 34mA
(9/17) × I
OUTFS
AC
11149-154
Figure 150. Equivalent DAC Output Circuit
The example shown in Figure 150 can be modeled as a pair of
dc current sources that source a current of 9/17 × IOUTFS to each
output. A differential ac current source, IPEAK, is used to model
the signal (that is, a digital code) dependent nature of the DAC
output. The polarity and signal dependency of this ac current
source is related to the digital code (F) by the following equation:
F (code) = (DACCODE − 8192)/8192 (2)
−1 < F (code) < +1 (3)
where DACCODE = 0 to 16,383 (decimal).
Because IPEAK can swing ±(8/17) × IOUTFS, the output currents
that are measured at IOUTP and IOUTN can span from
IOUTFS/17 to IOUTFS. However, because the ac signal-dependent
current component is complementary, the sum of the two
outputs is always constant (that is, IOUTP + IOUTN =
(18/17) × IOUTFS).
The code-dependent current that is measured at the IOUTP
(and IOUTN) output is as follows:
IOUTP = (9/17) × IOUTFS (mA) + (8/17) × IOUTFS (mA)
× F (code) (4)
IOUTN = (9/17) × IOUTFS (mA) − (8/17) × IOUTFS (mA)
× F (code)
Figure 151 shows the IOUTP vs. DACCODE transfer function
when IOUTFS is set to 19.65 mA.
20
18
10
12
14
16
OUTPUT CURRENT (mA)
8
6
4
2
00 4096 8192 12,288
DAC CODE 16,384
11149-155
Figure 151. Gain Curve for FSC_x[9:0] = 512, DAC Offset = 1.228 mA
AD9119/AD9129 Data Sheet
Rev. B | Page 52 of 66
Peak DAC Output Power Capability
The maximum peak power capability of a differential current
output DAC is dependent on its peak differential ac current,
IPEAK, and the equivalent load resistance it sees. In the case of a
1:1 balun with 50 Ω source termination, the equivalent load that
is seen by the DAC ac current source is 25 Ω. If the AD9119/
AD9129 is programmed for an IOUTFS = 20 mA, its peak ac current
is 9.375 mA and its peak power, delivered to the equivalent
load, is 2.2 mW (that is, P = I2R). Because the source and load
resistance seen by the 1:1 balun are equal, this power is shared
equally. Hence, the output load receives 1.1 mW, or 0.4 dBm
peak power.
To calculate the rms power delivered to the load, consider the
following:
•Peak-to-rms of digital waveform
•Any digital backoff from digital full scale
•DAC sinc response and nonideal losses in the external
network
For example, a reconstructed sine wave with no digital backoff
ideally measures −2.6 dBm because it has a peak-to-rms ratio of
3 dB. If a typical balun loss of 0.4 dBm is included, the user would
expect to measure −3 dBm of actual power in the region where
the sinc response of the DAC has negligible influence. Increasing
the output power is best accomplished by increasing IOUTFS.
Output Stage Configuration
The AD9119/AD9129 are intended to serve high dynamic range
applications that require wide signal reconstruction bandwidth
(that is, a DOCSIS cable modem termination system (CMTS))
and/or high IF/RF signal generation. Optimum ac performance
can be realized only if the DAC output is configured for differential
(that is, balanced) operation with its output common-mode
voltage biased to a stable, low noise 1.8 V nominal analog supply
(VDDA). The ADP150 LDO can be used to generate a clean 1.8
V supply.
The output network used to interface to the DAC should provide
a near 0 Ω dc bias path to VDDA. Any imbalance in the output
impedance over frequency between the IOUTP and IOUTN pins
degrades the distortion performance (mostly even order) and
noise performance. Component selection and layout are critical
in realizing the performance potential of the AD9119/AD9129.
Most applications that require balanced-to-unbalanced conversion
from 10 MHz to 1 GHz can take advantage of the Mini-Circuits
JTX series of transformers that offer impedance ratios of both
2:1 and 1:1.
Figure 152 shows the AD9119/AD9129 interfacing to the JTX-2-
10T transformer. This transformer provides excellent amplitude/
phase balance (that is, <1 dB/1°) up to 1 GHz while providing
a 0 Ω D dc bias path to VDDA. If filtering of the DAC images
and clock components is required, applying an analog LC filter
on the single-ended side has the advantage of preserving the
balance of the transformer.
JTX-2-10T+
MINI-CIRCUITS
50Ω
50Ω
IOUTP
IOUTN
VDDA
2:1
11149-156
Figure 152. Recommended Transformer for Wideband Applications with
Upper Bandwidths of up to 2.2 GHz
Figure 153 shows an interface that can be considered when
interfacing the DAC output to a self-biased differential gain block.
The inductors (L) shown serve as RF chokes that provide the
dc bias path to AGND. Its value, along with the dc blocking
capacitors, determines the lower cut-off frequency of the
composite pass-band response. (The dc blocking capacitors
form a high-pass response with the input resistance of the RF
differential gain stage.)
100Ω
IOUTP
IOUTN
L
L
RF DIFF_
AMP
C
C
VDDA
11149-157
Figure 153. Interfacing the DAC Output to Self-Biased,
Differential Gain Stage
Many RF differential amplifiers consist of two single-ended
amplifiers with matched gain, thus providing no common-mode
rejection while possibly degrading the balance, due to poor
matching characteristics. Also, depending on the component
tolerances, differential LC filters can further degrade the balance
in a differential signal path. In both cases, the use of a balun could
be advantageous in rejecting the common-mode distortion and
noise components from the RF DAC prior to filtering or further
amplification.
Data Sheet AD9119/AD9129
Rev. B | Page 53 of 66
For applications that operate the AD9119/AD9129 in Mix-Mode
with output frequencies extending beyond 2.2 GHz, the user may
want to consider the circuit shown in Figure 154. This circuit
uses a wideband balun (for example, −3 dB at 4.0 GHz), with a
configuration that is similar to the example shown in Figure 152,
to provide a dc bias path for the DAC outputs. This circuit was
implemented on an evaluation board, and the frequency response
was measured to compare it with the ideal curve in Figure 146.
The result is shown in Figure 155.
50Ω
50Ω
L
L
MINI-CIRCUITS
TCI-1-13M+
TCI-1-33M+
IOUTP
IOUTN C
C
VDDA
11149-158
Figure 154. Recommended Mix-Mode Configuration Offering Extended RF
Bandwidth Using TC1-1-13M+ Balun
–36
–33
–30
–27
–24
–21
–18
–15
–12
–9
–6
–3
0
3
0500 1000 1500 2000 2500 3000 3500 4000 4500 5000
POWER ( dBc)
FREQUENCY (MHz)
NORMAL MODE
MIX-MODE
MEASURE D NORMAL
MEASURED MI X-MO DE
11149-257
Figure 155. Measured vs. Ideal DAC Output Response; fDAC = 2.6 GSPS
To assist in matching the AD9119/AD9129 output, a Smith chart
is provided in Figure 156. The plot was taken using the circuit
in Figure 154, with the balun and the coupling capacitors
removed, and L = 270 nH. For the measured vs. ideal response of
the DAC output, see Figure 155, which illustrates that a nonideal
response occurs in the second half of the second Nyquist zone.
This area corresponds to the low impedance area between 2 GHz
and 3 GHz, as shown in the Smith chart in Figure 156. Output
matching can be used to compensate for this nonideal response;
the possible reduction in signal bandwidth must be considered if
such matching is used.
1. 300kHz 3.1341Ω 710.55mΩ 376.96nH
2. 1G Hz 54.333Ω –44.210Ω 3.5999pF
3. 2G Hz 13.113Ω –11.207Ω 7.1006pF
4. 3G Hz 13.022Ω –14.259Ω 756.48pH
1
2
3
4
11149-256
Figure 156. Measured Smith Chart Showing the DAC Output Impedance;
fDAC = 2.6 GSPS
AD9119/AD9129 Data Sheet
Rev. B | Page 54 of 66
START-UP SEQUENCE
A small number of steps is required to program the AD9119/AD9129 to the proper operating state after the device is powered up. This
sequence is listed in Table 16, along with an explanation of the purpose of each step.
Table 16. Start-Up Sequence After Power-Up
Register Value Description
0x00 0x00 4-wire SPI, MSB-first packing, short addressing mode
0x30
0x5C
Enable cross control, cross location = 7 dec, duty cycle correction off
0x0C 0x64 Set DLL minimum delay = 4 dec, enable DCO
0x0B 0x39 Set clock divider to DCI/512
0x01
0x68
Set bias power-down
0x34 0x6D or 0x5D Set PLL mode for normal or 2× mode; normal mode or FIR25 on = 0x6D, FIR40 on = 0x5D
0x01 0x48 Enable bias
0x33 0x13 Initialize PLL to phase step = 1 dec
0x33 0xF8 or 0xD8 Select PFD, set PLL phase step, keep PLL lost bit cleared; phase step is as follows: normal mode or
FIR25 on = 0xF8, FIR40 on = 0xD8
0x33 0xF0 or 0xD0 Deassert the PLL lost bit, keeping the phase step; normal mode or FIR25 on = 0xF0, FIR40 on = 0xD0
0x0D 0x06 Set duty correction bandwidth to lowest
0x0A 0xC0 Enable DLL
0x18 0xm0 Select data mode, filter mode to set value of m; for example: 0x40, unsigned data, interpolator off
0x20 0xC6 Set full-scale current (FSC) to 33 mA
0x21 0x03 Complete the setting of FSC
0x30 0x46 Enable cross control, cross location = 1 dec, enable duty cycle correction
0x12 0x20 Set the FIFO pointers
0x11
0x81
Assert FIFO reset
0x11 0x01 Deassert FIFO reset
0x01 0x08 Enable IREF (DAC output)
Data Sheet AD9119/AD9129
Rev. B | Page 55 of 66
DEVICE CONFIGURATION REGISTERS
DEVICE CONFIGURATION REGISTER MAP
The blank bits in Table 17 are reserved and should be programmed to their default values. A setting of 1 or 0 indicates the required
programming for the bit.
Table 17. Device Configuration Register Map
Register Name
Address
Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Hex Dec
Mode 0x00 0 R/W SDIO_DIR LSB/MSB SoftReset 0 0 SoftReset LSB/MSB SDIO_DIR 0x81
Power-Down 0x01 1 R/W BG_PD IREF_PD BIAS_PD 1 CLKPATH_PD Retimer_PD DLL_PD 0x48
IRQ Enable 0 0x03 3 R/W FIFO_Warn2 FIFO_Warn1 SPIFrmAck DLL warn DLL lock Retimer lost Retimer lock 0x00
IRQ Enable 1 0x04 4 R/W AED pass AED fail SED fail Parity err fall Parity err rise 0x00
IRQ Request 0 0x05 5 R/W FIFO_Warn2 FIFO_Warn1 SPIFrmAck DLL warn DLL lock Retimer lost Retimer lock 0x00
IRQ Request 1 0x06 6 R/W AED pass AED fail SED fail Parity err fall Parity err rise 0x00
Frame Pin Usage 0x07 7 R/W ParUsage FrmUsage FRM_x pin usage mode, Bits[1:0] 0x00
Reserved_0 0x08 8 R/W Must maintain default (reset) value of 0x58 0x58
Data Ctrl 0 0x0A 10 R/W DLL enable Duty cycle
correction
enable
Phase offset, Bits[3:0] 0x40
Data Ctrl 1 0x0B 11 R/W Warn clear Lock delay
divider
Controller clock divider,
Bits[1:0]
Delay line middle set, Bits[3:0] 0x29
Data Ctrl 2 0x0C 12 R/W DCO enable Maximum delay set, Bits[2:0] Minimum delay set, Bits[2:0] 0x23
Data Ctrl 3 0x0D 13 R/W Duty correction BW, Bits[1:0] 0x04
Data Status 0 0x0E 14 R DLL lock DLL warn DLL delay line
start warning
DLL delay line
end warning
DLL correct
phase
DCI on DLL lock phase DLL running N/A
FIFO Ctrl 0x11 17 R/W SPIFrmReq SPIFrmAck Enable pin
framing
Phase report
enable
0x00
FIFO Offset 0x12 18 R/W RdPtrOff, Bits[2:0] WtPtrOff, Bits[2:0] 0x04
FIFO Ph0 Thrm 0x13 19 R Phz0Thrm, Bits[6:0] N/A
FIFO Ph1 Thrm 0x14 20 R Phz1Thrm, Bits[6:0] N/A
FIFO Ph2 Thrm 0x15 21 R Phz2Thrm, Bits[6:0] N/A
FIFO Ph3 Thrm 0x16 22 R Phz3Thrm, Bits[6:0] N/A
Data Mode Ctrl 0x18 24 R/W Filter enable Binary select FILT_SEL 0x00
Decode Ctrl 0x19 25 R/W Mix-Mode en 0x00
Sync 0x1A 26 R/W Inc latency Dec latency Sync enable Sync done Phase readback, Bits[2:0] 0x00
FSC_1 0x20 32 R/W Full-scale current, Bits[7:0] 0x00
FSC_2 0x21 33 R/W Full-scale current, Bits[9:8] 0x02
ANA_CNT1 0x22 34 R/W 0x00
ANA_CNT2 0x23 35 R/W 0x0C
CLK REG1 0x30 48 R/W 0 Cross enable Cross location, Bits[3:0] Duty enable 0 0x00
Retimer Ctrl 0 0x33 51 R/W Phase step, Bits[3:0] Clear lost PLL divider Retimer mode, Bits[1:0] 0x30
Retimer Ctrl 1 0x34 52 R/W PLL reset_Z 0x55
Retimer Stat 0 0x35 53 R PLL lock PLL lost N/A
SED Control 0x50 80 R/W SED enable SED error clear AED enable 0 0 AED pass AED fail SED fail 0x00
SED Patt/Err R0L 0x51 81 R/W SED Data Port 0 rising edge low part error, Bits[7:0] N/A
SED Patt/Err R0H 0x52 82 R/W SED Data Port 0 rising edge high part error, Bits[13:8] N/A
SED Patt/Err R1L 0x53 83 R/W SED Data Port 1 rising edge low part error, Bits[7:0] N/A
SED Patt/Err R1H 0x54 84 R/W SED Data Port 1 rising edge high part error, Bits[13:8] N/A
SED Patt/Err F0L 0x55 85 R/W SED Data Port 0 falling edge low part error, Bits[7:0] N/A
SED Patt/Err F0H 0x56 86 R/W SED Data Port 0 falling edge high part error, Bits[13:8] N/A
SED Patt/Err F1L 0x57 87 R/W SED Data Port 1 falling edge low part error, Bits[7:0] N/A
SED Patt/Err F1H 0x58 88 R/W SED Data Port 1 falling edge high part error, Bits[13:8] N/A
Parity Control 0x5C 92 R/W Parity enable Parity even Parity error
clear
Parity error
falling edge
Parity error
rising edge
0x00
Parity Err Rising 0x5D 93 R Parity rising edge error count, Bits[7:0] N/A
Parity Err Falling 0x5E 94 R Parity falling edge error count, Bits[7:0] N/A
Delay Ctrl 0 0x70 112 R/W Enable delay cell, Bits[7:0] 0xFF
Delay Ctrl 1 0x71 113 R/W Enable delay cell, Bits[10:8] 0x67
Drive Strength 0x7C 124 R/W DCO drive strength, Bits[1:0] 0x7C
Part ID 0x7F 127 R Part ID, Bits[7:0] 0x07 or
0x87
AD9119/AD9129 Data Sheet
Rev. B | Page 56 of 66
DEVICE CONFIGURATION REGISTER DESCRIPTIONS
SPI Communications Control Register
Address: 0x00, Reset: 0x81, Name: Mode
Table 18. Bit Descriptions for Mode
Bits Bit Name Description Reset Access
7 SDIO_DIR Selects 3-wire or 4-wire mode
1: 3-wire bidirectional
0: 4-wire unidirectional
1 R/W
6 LSB/MSB LSB/MSB data packing
1: LSB-first packing
0: MSB-first packing
0 R/W
5 SoftReset 1: performs a software-based reset 0 R/W
4 Reserved Must be set to 0; reserved (short addressing mode) 0 R/W
3 Reserved Mirror Bit 4 for safety 0 R
2 SoftReset Mirror Bit 5 for safety 0 R
1 LSB/MSB Mirror Bit 6 for safety 0 R
0 SDIO_DIR Mirror Bit 7 for safety 1 R
Power Control Register
Address: 0x01, Reset: 0x48, Name: Power-Down
Table 19. Bit Descriptions for Power-Down
Bits Bit Name Description Reset Access
7 BG_PD Band gap power-down
1: band gap is powered down
0: band gap is active
0 R/W
6 IREF_PD IREF power-down
1: FSC is 0 mA
0: FSC is as programmed
1 R/W
5 BIAS_PD Bias power-down
1: all bias currents are off
0: all bias currents are on
0 R/W
4 Reserved Reserved 0 R/W
3 Reserved Must be set to 1; reserved 1 R/W
2 CLKPATH_PD Clock path power-down
1: DAC clock is powered down
0: DAC clock is active
0 R/W
1 Retimer_PD 1: PLL is powered down 0 R/W
0 DLL_PD DLL (data receiver) power-down
1: DLL (data receiver) is powered down
0 R/W
Data Sheet AD9119/AD9129
Rev. B | Page 57 of 66
Interrupt Enable Register 0
Address: 0x03, Reset: 0x00, Name: IRQ Enable 0
Table 20. Bit Descriptions for IRQ Enable 0
Bits Bit Name Description Reset Access
7 FIFO_Warn2 interrupt enable Enables the FIFO warning within two slots of overwrite interrupt 0 R/W
6 FIFO_Warn1 interrupt enable Enables the FIFO warning within one slot of overwrite interrupt 0 R/W
5 SPIFrmAck interrupt enable Enables the FIFO SPI-based calibration acknowledgement of SPIFrmReq
(Address 0x11, Bit 7) going from 0b to1b
0 R/W
4 Reserved Reserved 0 R
3 DLL warn interrupt enable Enables the DLL warning flag that the data receiver is no longer locked 0 R/W
2 DLL lock interrupt enable Enables the DLL warning flag that the data receiver is now locked 0 R/W
1 Retimer lost interrupt enable Enables the retimer lost interrupt indication 0 R/W
0 Retimer lock interrupt enable Enables the retimer lock interrupt indication 0 R/W
Interrupt Enable Register 1
Address: 0x04, Reset: 0x00, Name: IRQ Enable 1
Table 21. Bit Descriptions for IRQ Enable 1
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R/W
6 AED pass interrupt enable Enables the AED pass interrupt reporting saying that eight valid samples captured 0 R/W
5 AED fail interrupt enable Enables the AED fail interrupt reporting that a miscompare occurred 0 R/W
4 SED fail interrupt enable Enables the SED fail interrupt reporting that a miscompare occurred 0 R/W
3 Parity error falling edge enable Enables the parity fail due to a falling edge-based parity detected error 0 R/W
2
Parity error rising edge enable
Enables the parity fail due to a rising edge-based parity detected error
0
R/W
1 Reserved Reserved 0 R
0 Reserved Reserved 0 R
Interrupt Status Register 0
Address: 0x05, Reset: 0x00, Name: IRQ Request 0
Table 22. Bit Descriptions for IRQ Request 0
Bits Bit Name Description Reset Access
7 FIFO_Warn2 interrupt status Indicates that the FIFO is within two slots of overwrite 0 R
6 FIFO_Warn1 interrupt status Indicates that the FIFO is within one slot of overwrite 0 R
5 SPIFrmAck interrupt status Indicates acknowledgement of SPIFrmReq has changed from 0b to1b 0 R
4 Reserved Reserved 0 R
3 DLL warn interrupt status Indicates that the DLL (data receiver) is close to coming unlocked and action is
needed
0 R
2 DLL lock interrupt status Indicates that the DLL (data receiver) is now locked 0 R
1 Retimer lost interrupt status Indicates that the retimer PLL is no longer locked 0 R
0 Retimer lock interrupt status Indicates that the retimer PLL is now locked 0 R
AD9119/AD9129 Data Sheet
Rev. B | Page 58 of 66
Interrupt Status Register1
Address: 0x06, Reset: 0x00, Name: IRQ Request 1
Table 23. Bit Descriptions for IRQ Request 1
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R/W
6 AED pass interrupt status Indicates that the AED logic has captured eight valid samples 0 R/W
5 AED fail interrupt status Indicates that the AED logic has detected a miscompare 0 R/W
4 SED fail interrupt status Indicates that the SED logic has detected a miscompare 0 R/W
3 Parity error falling edge status Indicates a parity fault due to data captured on the falling edge 0 R/W
2 Parity error rising edge status Indicates a parity fault due to data captured on the rising edge 0 R/W
1 Reserved Reserved 0 R/W
0 Reserved Reserved 0 R/W
Frame Pin Usage Register
Address: 0x07, Reset: 0x00, Name: Frame Pin Usage
Table 24. Bit Descriptions for Frame Pin Usage
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R/W
6
Reserved
Reserved
0
R/W
5 ParUsage 1: FRM_x pin is in parity mode, and parity is enabled
Note that parity must be enabled, and the type must be chosen in Register 0x5C[7:6]
0 R
4 FrmUsage 1: FRM_x pin is in frame mode and enable pin framing (Register 0x11[5] = 1b) is
enabled
0 R
3 Reserved Reserved 0 R
2 Reserved Reserved 0 R
[1:0] FRM_x pin usage mode 3: reserved
2: frame
1: parity
0: no effect
0x0 R/W
Reserved_0 Register
Address: 0x08, Reset: 0x58, Name: Reserved_0
Table 25. Bit Descriptions for Reserved_0
Bits Bit Name Description Reset Access
[7:0]
Reserved
Must keep default (reset) value; reserved
0x58
R
Data Receiver Control 0 Register
Address: 0x0A, Reset: 0x40, Name: Data Ctrl 0
Table 26. Bit Descriptions for Data Ctrl 0
Bits Bit Name Description Reset Access
7 DLL enable 1: enables DLL
0: disables DLL
0 R/W
6 Duty cycle correction enable 1: enables duty cycle correction
0: disables duty cycle correction
1 R/W
5 Reserved Reserved 0 R/W
4
Reserved
Reserved
0
R/W
[3:0] Phase offset Locked phase = 90° ± n × 11.25°, where n is the 4-bit signed magnitude number 0x0 R/W
Data Sheet AD9119/AD9129
Rev. B | Page 59 of 66
Data Receiver Control 1 Register
Address: 0x0B, Reset: 0x29, Name: Data Ctrl 1
Table 27. Bit Descriptions for Data Ctrl 1
Bits Bit Name Description Reset Access
7 Warn clear 1: clears data receiver warning bit 0 R/W
6 Lock delay divider 1: long delay
0: short delay
0 R/W
[5:4] Controller clock divider Controller clock divider
00: DCI/4
01: DCI/16
10: DCI/64
11: DCI/512
0x2 R/W
[3:0] Delay line middle set Sets nominal delay line delay 0x9 R/W
Data Receiver Control 2 Register
Address: 0x0C, Reset: 0x23, Name: Data Ctrl 2
Table 28. Bit Descriptions for Data Ctrl 2
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R/W
6 DCO enable 1: enables DCO output driver 0 R/W
[5:3] Maximum delay set Sets maximum delay line delay (larger number = longer delay line) 0x2 R/W
[2:0] Minimum delay set Sets minimum delay line delay (larger number = smaller delay line) 0x3 R/W
Data Receiver Control 3 Register
Address: 0x0D, Reset: 0x04, Name: Data Ctrl 3
Table 29. Bit Descriptions for Data Ctrl 3
Bits Bit Name Description Reset Access
[7:3] Reserved Reserved. 0x00 R
[2:1] Duty correction BW set Sets the bandwidth of the duty cycle correction circuit.
00: highest BW.
01: higher BW.
10: lower BW.
11: lowest BW.
0x2 R/W
0 Reserved Reserved 0 R/W
Data Receiver Status 0 Register
Address: 0x0E, Reset: 0x00, Name: Data Status 0
Table 30. Bit Descriptions for Data Status 0
Bits Bit Name Description Reset Access
7 DLL lock 1: DLL lock 0 R
6 DLL warning 1: DLL near beginning/end of delay line 0 R
5 DLL delay line start warning 1: DLL at beginning of delay line 0 R
4 DLL delay line end warning 1: DLL at end of delay line 0 R
3 DLL correct phase 1: data is sampled on correct phase
0: data is sampled on incorrect phase.
0 R
2 DCI on 1: user has provided a clock > 100 MHz 0 R
1 DLL lock phase 1: DLL is locked on negative half of DCI.
0: DLL is locked on positive half of DCI
0 R
0 DLL running 1: closed loop DLL attempting to lock
0: delay fixed at middle of delay line
0 R
AD9119/AD9129 Data Sheet
Rev. B | Page 60 of 66
FIFO Control Register
Address: 0x11, Reset: 0x00, Name: FIFO Ctrl
Table 31. Bit Descriptions for FIFO Ctrl
Bits Bit Name Description Reset Access
7 SPIFrmReq Requests a SPI-based FIFO alignment (FIFO reset) 0 R/W
6 SPIFrmAck Acknowledges SPIFrmReq change (tracks SPIFrmReq setting) 0 R/W
5 Enable pin framing 1: enables hardware pin-based FIFO framing 0 R/W
[4:1] Reserved Reserved 0x0 R
0 Phase report enable 1: enables FIFO phase reporting 0 R/W
FIFO Offset Register
Address: 0x12, Reset: 0x04, Name: FIFO Offset
Table 32. Bit Descriptions for FIFO Offset
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:4] RdPtrOff[2:0] FIFO read pointer offset 0x0 R/W
3 Reserved Reserved 0 R
[2:0] WtPtrOff[2:0] FIFO write pointer offset 0x4 R/W
FIFO Thermometer for Phase 0 Status Register
Address: 0x13, Reset: 0x00, Name: FIFO PH0 THRM
Table 33. Bit Descriptions for FIFO PH0 THRM
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:0] Phz0Thrm Phase 0-based FIFO thermometer status. Phase 0 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
FIFO Thermometer for Phase 1 Status Register
Address: 0x14, Reset: 0x00, Name: FIFO PH1 THRM
Table 34. Bit Descriptions for FIFO PH1 THRM
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:0] Phz1Thrm Phase 1-based FIFO thermometer status. Phase 1 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
FIFO Thermometer for Phase 2 Status Register
Address: 0x15, Reset: 0x00, Name: FIFO PH2 THRM
Table 35. Bit Descriptions for FIFO PH2 THRM
Bits Bit Name Description Reset Access
7
Reserved
Reserved
0
R
[6:0] Phz2Thrm Phase 2-based FIFO thermometer status. Phase 2 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
FIFO Thermometer for Phase 3 Status Register
Address: 0x16, Reset: 0x00, Name: FIFO PH3 THRM
Table 36. Bit Descriptions for FIFO PH3 THRM
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:0] Phz3Thrm Phase 3-based FIFO thermometer status. Phase 3 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
Data Sheet AD9119/AD9129
Rev. B | Page 61 of 66
Data Mode Control Register
Address: 0x18, Reset: 0x00, Name: Data Mode Ctrl
Table 37. Bit Descriptions for Data Mode Ctrl
Bits Bit Name Description Reset Access
7 Filter enable 1: enables 2× interpolation filter
0: bypasses 2× interpolation filter
0 R/W
6 Binary select Selects input data format
1: unsigned
0: signed (Twos complement)
0 R/W
5 FILT_SEL 2× interpolator filter select
1: 40 dB OOB rejection
0: 25 dB out-of-band (OOB) rejection
0 R/W
[4:0]
Reserved
Reserved
0
R
Decoder Control (Program Thermometer Type) Register
Address: 0x19, Reset: 0x00, Name: Decode Ctrl
Table 38. Bit Descriptions for Decode Ctrl
Bits Bit Name Description Reset Access
[7:1] Reserved Reserved 0x00 R
0 Mix-Mode enable 1: Mix-Mode
0: normal
0 R/W
Sync Control Register
Address: 0x1A, Reset: 0x00, Name: Sync
Table 39. Bit Descriptions for Sync
Bits Bit Name Description Reset Access
7 Inc latency Increment delay by 1 0 R/W
6 Dec latency Decrement delay by 1 0 R/W
5 Reserved Reserved 0 R
4
Sync enable
1: multi-DAC sync output pin enabled
0: multi-DAC sync output pin disabled
0
R/W
3 Sync done 1: last increment or decrement request is complete 0 R
[2:0] Phase readback Readback of existing SYNC phase delay value 0 R
Full-Scale Current Adjust (Lower) Register
Address: 0x20, Reset: 0x00, Name: FSC_1
Table 40. Bit Descriptions for FSC_1
Bits Bit Name Description Reset Access
[7:0] Full-scale current, Bits[7:0] DAC gain adjust; DAC full-scale current (LSB) 0x00 R/W
Full-Scale Current Adjust (Upper) Register
Address: 0x21 Reset: 0x02, Name: FSC_2
Table 41. Bit Descriptions for FSC_2
Bits
Bit Name
Description
Reset
Access
7 Reserved Reserved 0 R/W
[6:2] Reserved Reserved 0 R
[1:0] Full-scale current, Bits[9:8] DAC gain adjust; DAC full-scale current (MSB) 0x02 R/W
AD9119/AD9129 Data Sheet
Rev. B | Page 62 of 66
Analog Control 1 Register
Address: 0x22, Reset: 0x00, Name: ANA_CNT1
Table 42. Bit Descriptions for ANA_CNT1
Bits Bit Name Description Reset Access
[7:0] Reserved Reserved 0x0 R/W
Analog Control 2 Register
Address: 0x23, Reset: 0x0C, Name: ANA_CNT2
Table 43. Bit Descriptions for ANA_CNT2
Bits Bit Name Description Reset Access
[7:0] Reserved Reserved 0x0C R/W
Clock Control 1 Register
Address: 0x30, Reset: 0x00, Name: CLK REG1
Table 44. Bit Descriptions for CLK REG1
Bits Bit Name Description Reset Access
7 Reserved Must be set to 0; reserved 0 R/W
6 Cross enable Enables zero-crossing control 0 R/W
[5:2] Cross location Adjusts zero-crossing control location (signed magnitude) 0 R/W
1 Duty enable Enables duty cycle correction 0 R/W
0 Select internal Must be set to 0 0 R/W
Retimer Control 0 Register
Address: 0x33, Reset: 0x30, Name: Retimer Ctrl 0
Table 45. Bit Descriptions for Retime Ctrl 0
Bits Bit Name Description Reset Access
[7:4] Phase step 4-bit signed magnitude; PFD phase step = n × 30° 0x3 R/W
3 Clear lost Clear lost status bit 0
2 PLL divider 1: divide-by-4
0: divide-by-8
0
[1:0] Retimer mode 0: enable PFD, normal mode
1: reserved
2: reserved
3: reserved
0x0
Retimer Control 1 Register
Address: 0x34, Reset: 0x55, Name: Retimer Ctrl 1
Table 46. Bit Descriptions for Retimer Ctrl 1
Bits Bit Name Description Reset Access
[7:4] Reserved Reserved 0x5 R/W
3 PLL reset_Z 1: normal operation for DAC clock PLL
0: resets the DAC clock PLL
0 R/W
[2:0] Reserved Reserved 0x5 R/W
Retimer Status 0 Register
Address: 0x35, Reset: 0x00, Name: Retimer Stat 0
Table 47. Bit Descriptions for Retimer Stat 0
Bits Bit Name Description Reset Access
7 PLL lock 1: retimer PLL locked 0 R
6 PLL lost 1: retimer PLL lost (can be sticky) 0 R
[5:4] Reserved Reserved 0x0 R
[3:0] Reserved Reserved 0x0 R
Data Sheet AD9119/AD9129
Rev. B | Page 63 of 66
Sample Error Detection (SED) Control Register
Address: 0x50, Reset: 0x00, Name: SED Control
Table 48. Bit Descriptions for SED Control
Bits Bit Name Description Reset Access
7 SED enable 1: setting this bit to 1 enables the SED compare logic 0 R/W
6 SED error clear 1: clears all SED reported error bits below 0 R/W
5 AED enable 1: enables the AED function (SED with autoclear after eight passing sets) 0 R/W
4 Reserved Must be set to 0; reserved 0 R
3 Reserved Must be set to 0; reserved 0 R
2 AED pass 1: signals eight true compare cycles 0 R/W
1
AED fail
1: signals a miscompare
0
R
0 SED fail 1: signals an SED miscompare (with SED or AED enabled) 0 R
Sample Error Detection (SED) Data Port 0 Rising Edge Status Low Register
Address: 0x51, Reset: 0x00, Name: SED Patt/Err R0L
Table 49. Bit Descriptions for SED Patt/Err R0L
Bits Bit Name Description Reset Access
[7:0] SED Data Port 0 rising edge low part error bits SED Data Port 0 rising edge error, Bits[7:0] 0x00 R/W
Sample Error Detection (SED) Data Port 0 Rising Edge Status High Register
Address: 0x52, Reset: 0x000, Name: SED Patt/Err R0H
Table 50. Bit Descriptions for SED Patt/Err R0H
Bits Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R
[5:0] SED Data Port 0 rising edge high part error bits SED Data Port 0 rising edge error, Bits[13:8] 0x00 R/W
Sample Error Detection (SED) Data Port 1 Rising Edge Status Low Register
Address: 0x53, Reset: 0x00, Name: SED Patt/Err R1L
Table 51. Bit Descriptions for SED Patt/Err R1L
Bits Bit Name Description Reset Access
[7:0] SED Data Port 1 rising edge low part error bits SED Data Port 1 rising edge error, Bits[7:0] 0x00 R/W
Sample Error Detection (SED) Data Port 1 Rising Edge Status High Register
Address: 0x54, Reset: 0x00, Name: SED Patt/Err R1H
Table 52. Bit Descriptions for SED Patt/Err R1H
Bits Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R
[5:0] SED Data Port 1 rising edge high part error bits SED Data Port 1 rising edge error, Bits[13:8] 0x00 R/W
AD9119/AD9129 Data Sheet
Rev. B | Page 64 of 66
Sample Error Detection (SED) Data Port 0 Falling Edge Status Low Register
Address: 0x55, Reset: 0x00, Name: SED Patt/Err F0L
Table 53. Bit Descriptions for SED Patt/Err F0L
Bits Bit Name Description Reset Access
[7:0] SED Data Port 0 falling edge low part error bits SED Data Port 0 falling edge error, Bits[7:0] 0x00 R/W
Sample Error Detection (SED) Data Port 0 Falling Edge Status High Register
Address: 0x56, Reset: 0x000, Name: SED Patt/Err F0H
Table 54. Bit Descriptions for SED Patt/Err F0H
Bits Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R
[5:0] SED Data Port 0 falling edge high part error bits SED Data Port 0 falling edge error, Bits[13:8] 0x00 R/W
Sample Error Detection (SED) Data Port 1 Falling Edge Status Low Register
Address: 0x57, Reset: 0x00, Name: SED Patt/Err F1L
Table 55. Bit Descriptions for SED Patt/Err F1L
Bits
Bit Name
Description
Reset
Access
[7:0] SED Data Port 1 falling edge low part error bits SED Data Port 1 falling edge error, Bits[7:0] 0x00 R/W
Sample Error Detection (SED) Data Port 1 Falling Edge Status High Register
Address: 0x58, Reset: 0x00, Name: SED Patt/Err F1H
Table 56. Bit Descriptions for SED Patt/Err F1H
Bits Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R
[5:0] SED Data Port 1 falling edge high part error bits SED Data Port 1 falling edge error, Bits[13:8] 0x00 R/W
Parity Control Register
Address: 0x5C, Reset: 0x00, Name: Parity Control
Table 57. Bit Descriptions for Parity Control
Bits Bit Name Description Reset Access
7 Parity enable 1: enables parity 0x00 R/W
6 Parity even 1: even parity. Even parity is defined as XOR[FRM(n), P0_D0(n),
P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n),
P1_D2(n), …, P1_D13(n)] = 0.
0: odd parity. Odd parity is defined as XOR[FRM(n), P0_D0(n),
P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n),
P1_D2(n), …, P1_D13(n)] = 1
Note that the parity bit must be enabled in Register 0x07.
0 R/W
5 Parity error clear 1: clears parity error counters 0 R/W
[4:2]
Reserved
Reserved
0x0
R
1 Parity error falling edge 1: signals detection of a falling edge parity error 0 R
0 Parity error rising edge 1: signals detection of a rising edge parity error 0 R
Parity Rising Edge Count Register
Address: 0x5D, Reset: 0x00, Name: Parity Err Rising
Table 58. Bit Descriptions for Parity Err Rising
Bits Bit Name Description Reset Access
[7:0] Parity rising edge error count Number of rising edge-based errors detected, clipped to 256 0x00 R
Parity Falling Edge Count Register
Address: 0x5E, Reset: 0x00, Name: Parity Err Falling
Data Sheet AD9119/AD9129
Rev. B | Page 65 of 66
Table 59. Bit Descriptions for Parity Err Falling
Bits Bit Name Description Reset Access
[7:0] Parity falling edge error count Number of falling edge-based errors detected, clipped to 256 0x00 R
Delay Control Register 0
Address: 0x70, Reset: 0xFF, Name: Delay Ctrl 0
Table 60. Bit Descriptions for Delay Ctrl 0
Bits Bit Name Description Reset Access
[7:0] Enable delay cell Sets each bit to enable or disable the delay cell, Bits[7:0]; delay cell number corresponds to bit
number
1: enables delay cell (default)
0: disables delay cell
0xFF R/W
Delay Control Register 1
Address: 0x71, Reset: 0x67, Name: Delay Ctrl 1
Table 61. Bit Descriptions for Delay Ctrl 1
Bits Bit Name Description Reset Access
[7:3] Reserved Reserved 0x60 R/W
[2:0] Enable delay cell Sets each bit to enable or disable the delay cell, Bits[10:8]; delay cell numbers are 10, 9,
and 8, which correspond to Bit 2, Bit 1, and Bit 0, respectively
1: enables delay cell (default)
0: disables delay cell
0x7 R/W
Drive Strength Register
Address: 0x7C, Reset: 0x7C, Name: Drive Strength
Table 62. Bit Descriptions for Drive Strength
Bits Bit Name Description Reset Access
[7:6] DCO drive strength Sets DCO drive strength
00: 2 mA
01: 2.8 mA (default)
10: 3.4 mA
11: 4 mA
0x1 R/W
[5:0] Reserved Reserved 0x3C R/W
Part ID Register
Address: 0x7F, Reset: 0x03 or 0x83, Name: Part ID
Table 63. Bit Descriptions for Part ID
Bits Bit Name Description Reset Access
[7:0] Part ID Version information
0x07 = the AD9129 (14-bit version)
0x87 = the AD9119 (11-bit version)
0x07
or
0x87
R
AD9119/AD9129 Data Sheet
Rev. B | Page 66 of 66
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
0.43 MAX
0.25 MIN
1.00 MAX
0.85 MIN
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14 13 12 1110 8 763219 54
1.40 MAX
0.55
0.50
0.45
10.40
BSC SQ
11-18-2011-A
COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1.
COPLANARITY
0.12
BALL DIAMETER
0.80
BSC
DETAIL A
A1 BALL
CORNER
A1 BALL
CORNER
DETAIL A
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
Figure 157. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-160-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9119BBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1
AD9119BBCZRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1
AD9119-EBZ Evaluation Board for Normal Mode Evaluation
AD9119-MIX-EBZ Evaluation Board for Mix-Mode Evaluation
AD9119-CBLTX-EBZ Evaluation Board for Cable Transmitter Evaluation
AD9129BBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1
AD9129BBCZRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1
AD9129BBC −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1
AD9129BBCRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1
AD9129-EBZ Evaluation Board for Normal Mode Evaluation
AD9129-MIX-EBZ Evaluation Board for Mix-Mode Evaluation
AD9129-CBLTX-EBZ Evaluation Board for Cable Transmitter Evaluation
1 Z = RoHS Compliant Part.
©2013-2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11149-0-6/17(B)