1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
■CMOS and TTL compatible I/O
■Automatic page write operation:
– 1 to 32 bytes in 5ms
– Page load timer
■End of write detection:
– Toggle bit
– DATADATA
DATADATA
DATA polling
■Hardware and software write protection
■100,000 program/erase cycles
■100 year data retention
CAT28LV64
64K-Bit CMOS PARALLEL EEPROM
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
The CAT28LV64 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
FEATURES
■3.0V to 3.6 V Supply
■Read access times:
– 150/200/250ns
■Low power CMOS dissipation:
– Active: 8 mA max.
– Standby: 100 µA max.
■Simple write operation:
– On-chip address and data latches
– Self-timed write cycle with auto-clear
■Fast write cycle time:
– 5ms max.
■Commercial, industrial and automotive
temperature ranges
Doc. No. 1010, Rev. D
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A5–A12
CE
OE
WE
A0–A4
I/O0–I/O7
I/O BUFFERS
8,192 x 8
E
2
PROM
ARRAY
32 BYTE PAGE
REGISTER
VCC
DATA POLLING
AND
TOGGLE BIT
H
A
L
O
G
E
N
F
R
E
E
TM
L
E
A
D
F
R
E
E
CAT28LV64
2
Doc. No. 1010, Rev. D
PIN FUNCTIONS
Pin Name Function Pin Name Function
A0–A12 Address Inputs WE Write Enable
I/O0–I/O7Data Inputs/Outputs VCC 3.0 to 3.6 V Supply
CE Chip Enable VSS Ground
OE Output Enable NC No Connect
PIN CONFIGURATION
SOIC Package (J, W) (K, X)DIP Package (P, L)
PLCC Package (N, G) TSOP Top View (8mm x 13.4mm) (T13, H13)
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
NC
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
NC
A8
I/O4
I/O3
16
15
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
NC
A12
A7
A6
A9
A11
28
27
26
25
VCC
WE
NC
A8
I/O4
I/O3
16
15
A
6
A
5
A
4
A
3
5
6
7
8
A
2
A
1
A
0
NC
9
10
11
12
I/O
0 13
A
8
A
9
A
11
NC
29
28
27
26
OE
A
10
CE
25
24
23
22 I/O
7
21
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
14151617181920
4321323130
A
7
A
12
NC
NC
V
CC
WE
NC
I/O
6
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O6
I/O5
I/O4
GND
I/O2
A1
A2
VCC
WE
A8
A9
A11
OE
A7
A6
A5
A4
A3
A10
I/O7
A12
16
15
CE
I/O3
I/O1
I/O0
A0
NC
NC
CAT28LV64
3Doc. No. 1010, Rev. D
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
NEND(1) Endurance 105Cycles/Byte MIL-STD-883, Test Method 1033
TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
MODE SELECTION
Mode CECE
CECE
CE WEWE
WEWE
WE OEOE
OEOE
OE I/O Power
Read L H L DOUT ACTIVE
Byte Write (WE Controlled) L H DIN ACTIVE
Byte Write (CE Controlled) L H DIN ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Test Max. Units Conditions
CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V
CIN(1) Input Capacitance 6 pF VIN = 0V
CAT28LV64
4
Doc. No. 1010, Rev. D
28LV64-15 28LV64-20 28LV64-25
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tRC Read Cycle Time 150 200 250 ns
tCE CE Access Time 150 200 250 ns
tAA Address Access Time 150 200 250 ns
tOE OEAccess Time 70 80 100 ns
tLZ(1) CE Low to Active Output 0 0 0 ns
tOLZ(1) OE Low to Active Output 0 0 0 ns
tHZ(1)(2) CE High to High-Z Output 50 50 55 ns
tOHZ(1)(2) OE High to High-Z Output 50 50 55 ns
Output Hold from
tOH(1) Address Change 0 0 0 ns
D.C. OPERATING CHARACTERISTICS
Vcc = 3.0V to 3.6V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC VCC Current (Operating, TTL) 8 mA CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
ISBC(3) VCC Current (Standby, CMOS) 100 µACE = VIHC,
All I/O’s Open
ILI Input Leakage Current –1 1 µAV
IN = GND to VCC
ILO Output Leakage Current –5 5 µAV
OUT = GND to VCC,
CE = VIH
VIH(3) High Level Input Voltage 2 VCC +0.3 V
VIL Low Level Input Voltage –0.3 0.6 V
VOH High Level Output Voltage 2 V IOH = –100µA
VOL Low Level Output Voltage 0.3 V IOL = 1.0mA
VWI Write Inhibit Voltage 2 V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) VIHC = VCC –0.3V to VCC +0.3V.
A.C. CHARACTERISTICS, Read Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
CAT28LV64
5Doc. No. 1010, Rev. D
28LV64-15 28LV64-20 28LV64-25
Symbol Parameter Min Max Min Max Min Max Units
tWC Write Cycle Time 5 5 5 ms
tAS Address Setup Time0 0 0 0 ns
tAH Address Hold Time 100 100 100 ns
tCS CE Setup Time 0 0 0 ns
tCH CE Hold Time 0 0 0 ns
tCW(2) CE Pulse Time 110 150 150 ns
tOES OE Setup Time 0 10 10 ns
tOEH OE Hold Time 0 10 10 ns
tWP(2) WE Pulse Width 110 150 150 ns
tDS Data Setup Time 60 100 100 ns
tDH Data Hold Time 0 0 0 ns
tINIT(1) Write Inhibit Period
After Power-up 5 10 5 10 5 10 ms
tBLC(1)(3) Byte Load Cycle Time 0.05 100 0.1 100 0.1 100 µs
DEVICE
UNDER
TEST
Vcc
1.8 K
OUTPUT
CL INCLUDES JIG CAPACITANCE
CL= 100 pF
1. 3K
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.6 V
V - 0.3 V
0.0 V
CC
Figure 1. A.C. Testing Input/Output Waveform(4)
Figure 2. A.C. Testing Load Circuit (example)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
CAT28LV64
6
Doc. No. 1010, Rev. D
Doc. No. 1010, Rev. A
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN DATA VALID
HIGH-Z
tCS
tAH
tCH
tWC
tOEH
tBLC
tDH
tDS
tOES tWP
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
DEVICE OPERATION
Read
Data stored in the CAT28LV64 is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architecture
can be used to eliminate bus contention in a system
environment.
ADDRESS
CE
OE
WE
tRC
DATA OUT DATA VALIDDATA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
CAT28LV64
7Doc. No. 1010, Rev. D
Doc. No. 1010, Rev. A
OE
CE
WE
ADDRESS
I/O
tWP tBLC
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
tWC
Page Write
The page write mode of the CAT28LV64 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte-write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 32 byte temporary buffer. The page
address where data is to be written, specified by bits A5
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A4
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that
existed in each addressed cell, and a write cycle, which
writes new data back into the cell. A page write will only
write data to the locations that were addressed and will
not rewrite the entire page.
Figure 5. Byte Write Cycle [CE Controlled]
Figure 6. Page Mode Write Cycle
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN DATA VALID
HIGH-Z
tAH
tWC
tOEH
tDH
tDS
tOES
tBLC
tCH
tCS
tCW
CAT28LV64
8
Doc. No. 1010, Rev. D
WE
CE
OE
I/O6
tOEH tOE tOES
tWC
(1) (1)
ADDRESS
CE
WE
OE
I/O7DIN = X DOUT = X DOUT = X
tOE
tOEH
tWC
tOES
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is
complete. Upon completion of the self-timed write cycle,
all I/O’s will output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
data from the device will result in I/O6 toggling between
one and zero. However, once the write is complete, I/O6
stops toggling and valid data can be read from the
device.
Figure 7. DATA Polling
Figure 8. Toggle Bit
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
CAT28LV64
9Doc. No. 1010, Rev. D
HARDWARE DATA PROTECTION
The following is a list of hardware data protection features
that are incorporated into the CAT28LV64.
(1) VCC sense provides for write protection when VCC
falls below 2.0V min.
(2) A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 2.40V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28LV64 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV64 is
in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC
Max., after SDP activation.
28LV64 F12
SOFTWARE DATA
PROTECTION ACTIVATED (1)
WRITE DATA: XX
WRITE LAST BYTE
TO
LAST ADDRESS
TO ANY ADDRESS
AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: A0
ADDRESS: 1555
WRITE DATA:
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: 80
ADDRESS: 1555
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: 20
ADDRESS: 1555
CAT28LV64
10
Doc. No. 1010, Rev. D
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
To allow the user the ability to program the device with
an EEPROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
Figure 12. Resetting Software Data Protection Timing
CE
WE
tWP
AA
1555
55
0AAA
A0
1555
DATA
ADDRESS
tBLC
tWC
BYTE OR
PAGE
WRITES
ENABLED
CE
WE
AA
1555
55
0AAA
DATA
ADDRESS
tWC
80
1555
AA
1555
55
0AAA
20
1555
SDP
RESET
DEVICE
UNPROTECTED
CAT28LV64
11 Doc. No. 1010, Rev. D
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT28LV64NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).
Prefix Device # Suffix
28LV64
Product
Number
CAT
Optional
Company
ID
NI T
Tape & Reel
Package
P: PDIP
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
-25
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)*
Speed
15: 150ns
20: 200ns
25: 250ns
* -40°C to +125°C is available upon request
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H13: TSOP (8mmx13.4mm) (Lead free, Halogen free)
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #: 1010
Revison: D
Issue date: 04/20/04
REVISION HISTORY
etaDnoisiveRstnemmoC
40/92/3C saerallanisegakcapneerGdeddA
40/02/40D noitangisedteehsatadeteleD
noitamrofnIgniredrOetadpU
yrotsiHnoisiveRetadpU
rebmuNveRetadpU