Data Sheet
V1.4 2018-09
Microcontrollers
XMC4100 / XMC4200
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Edition 2018-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG
All Rights Reserved.
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Data Sheet
V1.4 2018-09
Microcontrollers
XMC4100 / XMC4200
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
XMC4100 / XMC4200
XMC4000 Family
Data Sheet V1.4, 2018-09
XMC4[12]00 Data Sheet
Revision History: V1.4 2018-09
Previous Versions:
V1.3 2015-10
V1.2 2014-06
V1.1 2014-03
V1.0 2013-10
V0.6 2012-11
Page Subjects
43 Added RMS Noise parameter in VADC Parameters table.
12 Added a section listing the packages of the different markings.
14 Added BA marking variant.
14 Corrected SCU_IDCHIP value of XMC4100 EES-AA/ES-AA.
36 Added footnote explaining minimum VBAT requirements to start the
hibernate domain and/or oscillation of a crystal on RTC_XTAL.
37 Changed pull device definition to System Requirement (SR) to reflect that
the specified currents are defined by the characteristics of the external
load/driver.
37 Added information that PORST Pull-up is identical to the pull-up on
standard I/O pins.
42 Updated CAINSW, CAINTOT and RAIN parameters with improved values.
56 Added footnote on test configuration for LPAC measure m e n t.
58 Corrected parameter name of of USB pull device (upstream port receiving)
definition according to USB standard (referenced to DM instead of DP)
62 Relaxed RTC_XTAL VPPX parameter value and changed it to a system
requirement.
66 Added footnote on current consumption by enabling of fCCU.
67 Added Flash endurance parameter for 64 Kbytes Physical Sector PS4
NEPS4 for devices with BA marking.
many Added PG-TQFP-64-19 and PG-VQFN-48-71 package information.
89, 90 Added tables describing the differences between PG-LQFP-64-19 to PG-
TQFP-64-19 as well as PG-VQFN-48-53 to PG-VQFN-48-71 packages.
92 Updated to JEDEC standard J-STD-020D for the moisture sensitivity level
and added solder temperature parameter according to the same standard.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Data Sheet V1.4, 2018-09
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
We Listen to Your Comments
Is there any info rmation in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (includin g a reference to this document) to:
mcdocu.comments@infineon.com
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Table of Contents
Data Sheet 6 V1.4, 2018-09
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Package Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Pin Configuration and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.3 Digital to Analog Converters (DACx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.5 High Resolution PWM (HRPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.5.1 HRC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.5.2 CMP and 10-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.5.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.6 Low Power Analog Comparator (LPAC) . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.7 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.8 USB Device Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.9 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.2.10 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.11 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table of Contents
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Table of Contents
Data Sheet 7 V1.4, 2018-09
3.3.4 Phase Locked Loop (PLL) Characteristi cs . . . . . . . . . . . . . . . . . . . . . . 73
3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.8 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 79
3.3.8.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.3.8.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.3.9 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
About this Document
Data Sheet 8 V1.4, 2018-09
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of th e XMC4[12]00 series devices.
The document describes the characteristics of a superset of the XMC4[12]00 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4[12]00 throughout this manual.
XMC4000 Family User Documentation
The set of user documentation includes:
•Reference Manu al
– decribes the functionality of the superset of devices.
•Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about yo ur device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 9 V1.4, 2018-09
1 Summary of Features
The XMC4[12]00 devices are members of the XMC4000 Family of microcontrollers
based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high
performance and energy efficient microco ntrolle rs optimized for Industrial Connecti vity,
Industrial Control, Power Conversion, Sense & Control.
Figure 1 System Block Diagram
CPU Subsystem
•CPU Core
– High Performance 32-bit ARM Cortex-M4 CPU
– 16-bit and 32-bit Thumb2 instruction set
– DSP/MAC instructions
– System timer (SysTick) for Operating System support
• Floating Point Unit
• Memory Protection Unit
• Nested Vectored Interrupt Controller
• One General Purpose DMA with up-to 8 channels
• Event Request Unit (ERU) for programmable processing of external and internal
service requests
• Flexible CRC Engine (FCE) for multiple bit error detection
PMU
ROM & Flash
Bus Matri x
CPU
ARM®CortexTM-M4
DSRAM1PSRAM
FCE
GPDMA0 USB
Device
DCodeSystem ICode
Perip herals 0 Peripherals 1
PBA0
Data Code
WDT
RTC
ERU0
SCU
ERU1 VADC POSIF0 CCU40 CCU41
USIC0 CCU80 LEDTS0 PORTS DAC
USIC1 CAN
System
Masters System
Slaves
PBA1
HRPWM
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 10 V1.4, 2018-09
On-Chip Memories
• 16 KB on-chip boot ROM
• up to 16 KB on-chip high-speed program memory
• up to 24 KB on-chip high speed data memory
• up to 256 KB on-chip Flash Memory with 1 KB instruction cache
Communication Peripherals
• Universal Serial Bus, USB 2.0 de vice, with integrated PHY
• Controller Area Network i nterface (Mu lt iCAN), Ful l-CAN/Basic-CAN with two nodes,
64 message objects (MO), data rate up to 1 MBit/s
• Four Universal Serial Interface Channels (USIC), providing four serial channels,
usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
• LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
Analog Frontend Peripherals
• Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
• Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals
• Two Capture/Compare Units 4 (CCU4) for use as general purpose timers
• One Capture/Compare Units 8 (CCU8) for motor control and power conversion
• Four High Resoultion PWM (HRPWM) channels
• One Position Interface (POSIF) for servo motor positioning
• Window Watchdog Timer (WDT) for safety sensitive applications
• Die Temperature Sensor (DTS)
• Real Time Clock module with alarm support
• System Control Unit (SCU) for system configuration and control
Input/Output Li ne s
• Programmable port driver control module (PORTS)
• Individual bit addressability
• Tri-stated in input mode
• Push/pull or open drain output mode
• Boundary scan test support over JTAG interface
On-Chip Debug Suppo rt
• Full support for debug features: 8 breakpoin ts, CoreSight, trace
• Various interfaces: ARM-JTAG, SWD, single wire trace
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 11 V1.4, 2018-09
1.1 Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
• <DDD> the derivatives function set
• <Z> the package variant
–E: LFBGA
– F: LQFP, TQFP
–Q: VQFN
• <PPP> package pin count
• <T> the temperature range:
– F: -40°C to 85°C
– K: -40°C to 125°C
• <FFFF> the Fla sh me mo ry size.
For ordering codes for the XMC4[12]00 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4100 and XMC4200 series,
some descriptions may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4[12]00 is used for all derivatives throughout this document.
1.2 Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1 Synopsis of XMC4[12]00 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
Package Flash Kbytes SRAM Kbytes
XMC4200-F64x256 PG-yQFP-642)
2) y is a placeholder for the QFP package variant, LQFP or TQFP depen ding on the stepping, see Section 1.3.
256 40
XMC4200-Q48x256 PG-VQFN-48 256 40
XMC4100-F64x128 PG-yQFP-642) 128 20
XMC4100-Q48x128 PG-VQFN-48 128 20
XMC4104-F64x64 PG-yQFP-642) 64 20
XMC4104-Q48x64 PG-VQFN-48 64 20
XMC4104-F64x128 PG-yQFP-642) 128 20
XMC4104-Q48x128 PG-VQFN-48 128 20
XMC4108-F64x64 PG-yQFP-642) 64 20
XMC4108-Q48x64 PG-VQFN-48 64 20
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 12 V1.4, 2018-09
1.3 Package Variants
Different markings of the XMC4[12]00 use different package variants. Details of those
packages are given in the Package Parameters section of the Data Sheet.
1.4 Device Type Features
The following table lists the available features per device type.
Table 2 XMC4[12]00 Package Variants
Package Variant Marking Package
XMC4[12]00-F64 EES-AA, ES-AA, ES-AB, AB PG-LQFP-64-19
XMC4[12]00-Q48 PG-VQFN-48-53
XMC4[12]00-F64 BA PG-TQFP-64-19
XMC4[12]00-Q48 PG-VQFN-48-71
Table 3 Features of XMC4[12]0 0 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
LEDTS Intf. USB Intf. USIC Chan. MultiCAN
Nodes, MO
XMC4200-F64x256 1 1 2 x 2 N0, N1
MO[0..63]
XMC4200-Q48x256 1 1 2 x 2 N0, N1
MO[0..63]
XMC4100-F64x128 1 1 2 x 2 N0, N1
MO[0..63]
XMC4100-Q48x128 1 1 2 x 2 N0, N1
MO[0..63]
XMC4104-F64x64 1 −2 x 2 −
XMC4104-Q48x64 1 −2 x 2 −
XMC4104-F64x128 1 −2 x 2 −
XMC4104-Q48x128 1 −2 x 2 −
XMC4108-F64x64 −−2 x 2 N0, MO[0..31]
XMC4108-Q48x64 −−2 x 2 N0, MO[0..31]
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 13 V1.4, 2018-09
1.5 Definition of Feature Variants
The XMC4[12]00 types are offered with several memory size s and number of avai lable
VADC channels. Table 5 describes the location of the available Flash memory, Table 6
describes the location of the available SRAMs, Table 7 the available VADC channels.
Table 4 Features of XMC4[12]0 0 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
ADC
Chan. DAC
Chan. CCU4
Slice CCU8
Slice POSIF
Intf. HRPWM
Intf.
XMC4200-F64x256 10 2 2 x 4 1 x 4 1 1
XMC4200-Q48x256 9 2 2 x 4 1 x 4 1 1
XMC4100-F64x128 10 2 2 x 4 1 x 4 1 1
XMC4100-Q48x128 9 2 2 x 4 1 x 4 1 1
XMC4104-F64x64 10 2 2 x 4 1 x 4 1 1
XMC4104-Q48x64 9 2 2 x 4 1 x 4 1 1
XMC4104-F64x128 10 2 2 x 4 1 x 4 1 1
XMC4104-Q48x128 9 2 2 x 4 1 x 4 1 1
XMC4108-F64x64 10 2 2 x 4 1 x 4 1 −
XMC4108-Q48x64 9 2 2 x 4 1 x 4 1 −
Table 5 Flash Memory Ranges
Total Flash Size Cached Rang e Uncached Range
256 Kbytes 0800 0000H −
0803 FFFFH
0C00 0000H −
0C03 FFFFH
128 Kbytes 0800 0000H −
0801 FFFFH
0C00 0000H −
0C01 FFFFH
64 Kbytes 0800 0000H −
0800 FFFFH
0C00 0000H −
0C00 FFFFH
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 14 V1.4, 2018-09
1.6 Identification Registers
The identificati on registers allow software to identify the marking.
Table 6 SRAM Memory Ra nges
Total SRAM Size Program SRAM System Data SRAM
40 Kbytes 1FFF C000H −
1FFF FFFFH
2000 0000H −
2000 5FFFH
20 Kbytes 1FFF E000H −
1FFF FFFFH
2000 0000H −
2000 2FFFH
Table 7 ADC Channels1)
1) Some pins in a p ackage may be connected to more than one channel. For the detailed mapping see the Port
I/O Function tab l e.
Package VADC G0 VADC G1
LQFP-64, TQFP-64 CH0, CH3..CH7 CH0, CH1, CH3, CH6
PG-VQFN-48 CH0, CH3..CH7 CH0, CH1, CH3
Table 8 XMC4200 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 2001HEES-AA, ES-AA
SCU_IDCHIP 0004 2002HES-AB, AB
SCU_IDCHIP 0004 2003HBA
JTAG IDCODE 101D D083HEES-AA, ES-AA
JTAG IDCODE 201D D083HES-AB, AB
JTAG IDCODE 301D D083HBA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 15 V1.4, 2018-09
Table 9 XMC4100 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 2001HEES-AA, ES-AA
SCU_IDCHIP 0004 2002HES-AB, AB
SCU_IDCHIP 0004 1003HBA
JTAG IDCODE 101D D083HEES-AA, ES-AA
JTAG IDCODE 201D D083HES-AB, AB
JTAG IDCODE 301D D083HBA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 16 V1.4, 2018-09
2 General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC4[12]00 Logic Symbol PG-LQFP-64 and PG-TQFP-64
Port 0
12 bit
Port 1
10 bit
Port 2
12 bit
VAGND
VSSA
(1)
VAREF
VDDA
(1) VDDP
(3)
JTAG
3 bit
TCK SWD
1 bit
VDDC
(2)
XTAL1
XTAL2
USB_DP
USB_DM
Port 14
9 bit
TMS
PORST
via Port Pins
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
VBAT (1 )
(1) VSSO
Exp. Die Pad
(VSS)
VSS
(1)
Port 3
1 bit
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 17 V1.4, 2018-09
Figure 3 XMC4[12]00 Logic Symbol PG-VQFN-48
Port 0
9 bit
Port 1
6 bit
Port 2
6 bit
VAGND
VSSA
(1)
VAREF
VDDA
(1) VDDP
(3)
JTAG
3 bit
TCK SWD
1 bit
VDDC
(2)
XTAL1
XTAL2
USB_DP
USB_DM
Port 14
8 bit
TMS
PORST
via Port Pins
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
VBAT (1 ) Exp. Die Pad
(VSS)
VSS
(1)
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 18 V1.4, 2018-09
2.2 Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
Figure 4 XMC4[12]00 PG-LQFP-64 and PG-TQFP-64 Pin Configuration
(top view)
2P0.0 1P0.1
64 P0.2
63 P0.3
62 P0.4
61 P0.5
60 P0.6
58 P0.7
57 P0.8
4P0.9 3P0.10
59 P0.11
52 P1.0
51 P1.1
50 P1.2
49 P1.3
48 P1.4
47 P1.5
55 P1.7
54 P1.8
53 P1.9
46 P1.15
34 P2.0
33 P2.1
32P2.2 31P2.3 30P2.4 29P2.5
36 P2.6
35 P2.7
28P2.8 27P2.9 26P2.14 25P2.15
5P3.0
20P14.0 19P14.3 18P14.4 17P14.5
16P14.6 15P14.7
24P14.8 23P14.9
14P14.14
10HIB_IO_0
43 PORST
11RTC_XTAL1 12RTC_XTAL2
45 TCK
44 TMS
6USB_DM 7USB_DP
13VBAT
22VDDA/VAREF
9VDDC
42 VDDC
8VDDP
38 VDDP
56 VDDP
37 VSS
21VSSA/VAGND
41 VSSO
39 XTAL1
40 XTAL2
XMC4[12]00
(Top View)
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 19 V1.4, 2018-09
Figure 5 XMC4[12]00 PG-VQFN-48 Pin Configuration (top view)
2
P0.0 1P0.1
48 P0.2
47 P0.3
46 P0.4
45 P0.5
44 P0.6
42 P0.7
41 P0.8
4
3
43
P1.0
P1.1
P1.2
P1.3
36 P1.4
35 P1.5
39
38
37
34
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
24
23
22
21
5
16P14.0 15P14.3 14P14.4 13P14.5
P14.6
P14.7
20P14.8 19P14.9
10
HIB_IO_0 31 PORST
11
RTC_XTAL1
12
RTC_XTAL2
33 TCK
32 TMS
6
USB_DM
7
USB_DP
VBAT
18VDDA/VAREF
9
VDDC 30 VDDC
8
VDDP
26
VDDP
40 VDDP
25
VSS
17VSSA/VAGND
29
27
XTAL1
28
XTAL2
XMC4[12]00
(Top View)
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 20 V1.4, 2018-09
2.2.1 Package Pin Summary
The following general scheme is used to describe each pin:
The table is sorted by the “Fu nction” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the pa ckage pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the res pective pin/fu nction is given, i.e. deviatio ns
from the default configuration after reset. Pe r default the regu lar Port pins are c onfigured
as direct input with no internal pull device active.
Table 10 Package Pin Mapping Description
Function Package A Package B ... Pad
Type Notes
Name N Ax ... A1+
Table 11 Package Pin Mapping
Function LQFP-64
TQFP-64 VQFN-48 Pad Type Notes
P0.0 2 2 A1+
P0.1 1 1 A1+
P0.2 64 48 A1+
P0.3 63 47 A1+
P0.4 62 46 A1+
P0.5 61 45 A1+
P0.6 60 44 A1+
P0.7 58 43 A1+ After a system reset, via
HWSEL this pin selects the
DB.TDI function.
P0.8 57 42 A1+ After a system reset, via
HWSEL this pin selects the
DB.TRST function, with a
weak pull-down active.
P0.9 4 - A1+
P0.10 3 - A1+
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 21 V1.4, 2018-09
P0.11 59 - A1+
P1.0 52 40 A1+
P1.1 51 39 A1+
P1.2 50 38 A1+
P1.3 49 37 A1+
P1.4 48 36 A1+
P1.5 47 35 A1+
P1.7 55 - A1+
P1.8 54 - A1+
P1.9 53 - A1+
P1.15 46 - A1+
P2.0 34 26 A1+
P2.1 33 25 A1+ After a system reset, via
HWSEL this pin selects the
DB.TDO function.
P2.2 32 24 A1+
P2.3 31 23 A1+
P2.4 30 22 A1+
P2.5 29 21 A1+
P2.6 36 - A1+
P2.7 35 - A1+
P2.8 28 - A1+
P2.9 27 - A1+
P2.14 26 - A1+
P2.15 25 - A1+
P3.0 5 - A1+
P14.0 20 16 AN/DIG_IN
P14.3 19 15 AN/DIG_IN
P14.4 18 14 AN/DIG_IN
P14.5 17 13 AN/DIG_IN
P14.6 16 12 AN/DIG_IN
P14.7 15 11 AN/DIG_IN
P14.8 24 20 AN/DAC/DIG_IN
Table 11 Package Pin Mapping (cont’d)
Function LQFP-64
TQFP-64 VQFN-48 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 22 V1.4, 2018-09
P14.9 23 19 AN/DAC/DIG_IN
P14.14 14 - AN/DIG_IN
USB_DP 7 4 special
USB_DM 6 3 special
HIB_IO_0 10 7 A1 special At the first power-up and with
every reset of the hibernate
domain this pin is configured
as open-drain output and
drives "0".
As output the medium driver
mode is active.
TCK 45 34 A1 Weak pull-down active.
TMS 44 33 A1+ Weak pull-up active.
As output the strong-soft
driver mode is active.
PORST 43 32 special Strong pull-down controlled
by EVR.
Weak pull-up active while
strong pull-down is not active.
XTAL1 39 29 clock_IN
XTAL2 40 30 clock_O
RTC_XTAL1 11 8 clock_IN
RTC_XTAL2 12 9 clock_O
VBAT 13 10 Power When VDDP is supplied
VBAT has to be supplied as
well.
VDDA/VAREF 22 18 AN_Power/AN_
Ref Shared analog supply and
reference voltage pin.
VSSA/VAGND 21 17 AN_Power/AN_
Ref Shared analog supply and
reference ground pin.
VDDC 9 6 Power
VDDC 42 31 Power
VDDP 8 5 Power
VDDP 38 28 Power
VDDP 56 41 Power
VSS 37 27 Power
Table 11 Package Pin Mapping (cont’d)
Function LQFP-64
TQFP-64 VQFN-48 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 23 V1.4, 2018-09
VSSO 41 - Power
VSS Exp. Pad Exp. Pad Power Exposed Die Pad
The exposed die pad is
connected internally to VSS.
For proper operation, it is
mandatory to connect the
exposed pad directly to the
common ground on the
board.
For thermal aspects, please
refer to the Data Sheet.
Board layout examples are
given in an application note.
Table 11 Package Pin Mapping (cont’d)
Function LQFP-64
TQFP-64 VQFN-48 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 24 V1.4, 2018-09
2.2.2 Port I/O Functions
The following general scheme is used to describe each PORT pin:
Figure 6 Simp li fie d Port Stru cture
Pn.y is the port pin name , d efi ning the con t rol and d ata bits/registers associ ate d with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly drive n by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to mult iple peripherals. Most peripherals have an
input multip l exer to select betwe en di ff erent possible in put sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Table 12 Port I/O Function Description
Function Outputs Inputs
ALT1 ALTn HWO0 HWI0 Input Input
P0.0 MODA.OUT MODB.OUT MODB.INA MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
XMC4000
Pn.y
VDDP
GND
Pn.y
ALT1
...
ALTn
HWO0
HWO1
SW
Control Logic
Input 0
Input n
... PAD
HWI0
HWI1
MODB.OUT
MODB
MODA
MODA.INA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Data Sheet 28 V1.4, 2018-09
2.3 Power Connection Scheme
Figure 7. shows a reference power connection scheme for the XMC4[12]00.
Figure 7 Power Connection Sche me
Every power supply pin needs to b e connected. Different pins of the same supp ly need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 µF capacitor is connected to the VDDP nets and
an additional 4.7uF capacitor to the VDDC nets.
VBAT
M x VDDC
N x VDDP
VSS
VDDA / VAREF
Hibernate domain
RTC Hibernate
control
Retention
Memory
32 kHz
Clock
Core Domain
CPU
Dig.
Peripherals
Analog Domain
ADC DAC
GPIOs
Out-of-range comparator
PAD Domain
Level
shift.
FLASH
RAMs
100 nF x M
4.7 µF x 1
100 nF
3.3V
XMC4000
EVR
VSSA / VAGND
Exp. Die Pad
VSS
GND
GND
GND
GND
100 nF x N
10 µF x 1
3.3V
2.1...3.6 V
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Data Sheet 29 V1.4, 2018-09
The XMC4[12]00 has a common ground concep t, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
There are no dedicated connections for the analog reference VAREF and VAGND. Instead,
they share the same pins as the analog supply pins VDDA and VSSA.Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connecte d directly to VDDP.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 30 V1.4, 2018-09
3 Electrical Parameters
3.1 General Parameters
3.1.1 Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the
XMC4[12]00 and partly its requirements on the system. To aid interpreting the
parameters easily when evaluating them for a design, they are marked with an two-letter
abbreviation in column “Symbol”:
•CC
Such parameters indicate Controller Characte ristics, which are a distinctive fe ature
of the XMC4[12]00 and must be regarded for system design.
•SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4[12]00 is designed in.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 31 V1.4, 2018-09
3.1.2 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 14 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Storage temperature TST SR -65 – 150 °C–
Junction temperature TJ SR -40 −150 °C –
Voltage at 3.3 V power supply
pins with respect to VSS
VDDP SR – – 4.3 V –
Voltage on any Class A and
dedicated input pin with
respect to VSS
VIN SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Voltage on any analog input
pin with respect to VAGND
VAIN
VAREF SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Input current on any pin
during overload condition IIN SR -10 – +10 mA
Absolute maximum sum of all
input circuit currents for one
port group during overload
condition1)
1) The port groups are defined in Table 18.
ΣIIN SR -25 – +25 mA
Absolute maximum sum of all
input circuit currents during
overload condition
ΣIIN SR -100 – +100 mA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 32 V1.4, 2018-09
Figure 8 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in Section 3.1.3.
Figure 8 Absolute Maximum Input Voltage Ranges
V
4.3
V
SS
-1.0
A
A
B
Abs. max. input voltage V
IN
with V
DDP
> 3.3 V
Abs. max. input voltage V
IN
with V
DDP
≤ 3.3 V
V
V
DDP
+ 1.0
V
SS
-1.0
V
DDP
B
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 33 V1.4, 2018-09
3.1.3 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 15 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time is not exceeded
•Operating Co nditions are met for
– pad supply levels (VDDP or VDDA)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
parameters, then the parameters functionality of this pin as stated in the Operating
Conditions can no longer be guaranteed. Operation is still possible in most cases but
with relaxed parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations li ke short to battery.
Figure 9 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Table 15 Overload Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin
during overload condition IOV SR -5 – 5 mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
1) The port groups are defined in Table 18.
IOVG SR – – 20 mA Σ|IOVx|, for all
IOVx <0mA
––20mAΣ|IOVx|, for all
IOVx >0mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR – – 80 mA ΣIOVG
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 34 V1.4, 2018-09
Figure 9 Input Overload Current via ESD structures
Table 16 and Table 17 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as de fined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 16 PN-Junction Characteris itics for positive Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=150°C
A1 / A1+ VIN =VDDP +1.0V VIN =VDDP +0.75V
AN/DIG_IN VIN =VDDP +1.0V VIN =VDDP +0.75V
Table 17 PN-Junction Characterisiti cs for negative Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=150°C
A1 / A1+ VIN =VSS -1.0V VIN =VSS -0.75V
AN/DIG_IN VIN =VDDP -1.0V VIN =VDDP -0.75V
Table 18 Port Groups for Overl oad and Short-Circuit Current Sum
Parameters
Group Pins
1 P0.[12:0], P3.0
2 P14.[8:0]
3 P2.[15:0]
4 P1.[15:0]
Pn.y IOVx
GND
ESD Pad
GND
VDDP
VDDP
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 35 V1.4, 2018-09
3.1.4 Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 3.2.1.
Figure 10 Output Slopes with different Pad Driver Modes
Figure 10 is a qualitative display of the resulting output slope performance with
different output driver modes. The detailed input and output characteristics are listed in
Section 3.2.1.
Table 19 Pad Driver and Pad Classes Overview
Class Power
Supply Type Sub-Class Speed
Grade Load Termination
A3.3 V LVTTL
I/O,
LVTTL
outputs
A1
(e.g. GPIO) 6 MHz 100 pF No
A1+
(e.g. serial I/Os) 25 MHz 50 pF Series termination
recommended
V
VDDP
VSS
VOH
VOL
t
CDEF
C
D
E
F
Output High Voltage
Output Low Voltage
Weak drive strength
Medium drive strength
Stro ng – sl ow dri v e stre ngt h
Strong – soft drive strength
C D E F Class A1+ Pads
E F Class A1 Pads
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 36 V1.4, 2018-09
3.1.5 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4[12]00. All parameters specified in the following
tables refer to these operating conditions, unless noted otherwise.
Table 20 Operating Conditions Para meters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Ambient Temperature TA SR -40 −85 °C Temp. Range F
-40 −125 °C Temp. Ran ge K
Digital supply voltage VDDP SR 3.131)
1) See also the Supply Monitoring thresholds, Section 3.3.2.
3.3 3.632)
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime.
V
Core Supply Voltage VDDC
CC −1) 1.3 −V Generated
internally
Digital ground voltage VSS SR 0 −−V
ADC analog supply
voltage VDDA SR 3.0 3.3 3.62) V
Analog ground voltage for
VDDA
VSSA SR -0.1 0 0.1 V
Battery Supply Voltage
for Hiberna t e Do ma i n3)
3) Different limits apply for LPAC operation, Section 3.2.6
VBAT SR 1.954)
4) To start the hibernate domain it is requ ired that VBAT ≥2.1 V, for a reliable start of th e oscillation of RTC_XTAL
in crystal mode it is required that VBAT ≥3.0 V.
−3.63 V When VDDP is
supplied VBAT
has to be
supplied as well.
System Frequency fSYS SR −−80 MHz
Short circuit current of
digital outputs ISC SR -5 −5mA
Absolute sum of short
circuit currents per pin
group5)
5) The port groups are defined in Table 18.
ΣISC_PG
SR −−20 mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
SR −−100 mA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 37 V1.4, 2018-09
3.2 DC Parameters
3.2.1 Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
The pull-up characteristics (IPUH) and the input high and low voltage levels (VIH and VIL)
of the PORST pin are identical to the respective values of the standard digital
input/ou tput pins.
Table 21 Standard Pad Parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Max.
Pin capacitance (digital
inputs/outputs) CIO CC −10 pF
Pull-down current |IPDL|
SR 150 −μA1)VIN ≥0.6 × VDDP
1) Current required to override the pull device with the opposite logic level (“force current”).
With active pull device, at load currents between force and keep current the input state is undefined.
−10 μA2)VIN ≤0.36 × VDDP
2) Load current at which the pull device still maintains the valid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
Pull-up current |IPUH|
SR −10 μA2)VIN ≥0.6 × VDDP
100 −μA1)VIN ≤0.36 × VDDP
Input Hysteresis for
pads of all A classes3)
3) Hysteresis is implemented to avoid metastable st ates an d swit ching due to intern al g roun d bounce. It can n ot
be guaranteed that it suppresses switch ing due to external system noise.
HYSA
CC 0.1 ×
VDDP
−V
PORST spike filter
always blocked pulse
duration
tSF1 CC −10 ns
PORST spike filter
pass-through pulse
duration
tSF2 CC 100 −ns
PORST pull-down
current |IPPD|
CC 13 −mA Vi=1.0 V
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 38 V1.4, 2018-09
Figure 11 Pull Device Input Characteristics
Figure 11 visualizes the input characteristics with an active internal pull device:
• in the cases “A” the internal pull device is overridden by a strong external driver;
• in the cases “B” the internal pull device defines the input logical state against a weak
external load.
XMC4000 IN
I
PDL
AI
PDL
≥150 μA
BI
PDL
≤10 μA
V
DDP
GND
V
V
DDP
V
SS
0.6 x V
DDP
A
0.36 x V
DDP
B
Va lid High
Va lid Low
Inva lid di gi tal i nput
XMC4000
IN
I
PUH
AI
PUH
≥ 100 μA
BI
PUH
≤10 μA
V
V
DDP
V
SS
0.6 x V
DDP
B
0.36 x V
DDP
A
Va lid High
Va lid Low
Inva lid di gi tal i nput
Pull -down active
Pull-up active
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 39 V1.4, 2018-09
Table 22 Standard Pads Class_A1
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1 CC -500 500 nA 0 V ≤VIN ≤VDDP
Input high voltage VIHA1 SR 0.6 × VDDP VDDP + 0.3 V max . 3.6 V
Input low voltage VILA1 SR -0.3 0.36 × VDDP V
Output high voltage,
POD1) = weak VOHA1
CC VDDP - 0.4 −VIOH ≥-400 μA
2.4 −VIOH ≥-500 μA
Output high voltage,
POD1) = medium VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output low voltage VOLA1
CC −0.4 V IOL ≤500 μA;
POD1) = weak
−0.4 V IOL ≤2mA;
POD1) = medium
Fall time tFA1 CC −150 ns CL=20pF;
POD1) = weak
1) POD = Pin Out Driver
−50 ns CL=50pF;
POD1) = medium
Rise time tRA1 CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
Table 23 Standard Pads Class_A1 +
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1+ CC -1 1 μA0V≤VIN ≤VDDP
Input high voltage VIHA1+ SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V