AT24C16N-10SI-1.8 - Atmel - Product.Network

Features

•Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 5.5V)

•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),

1024 x 8 (8K) or 2048 x 8 (16K)

•2-wire Serial Interface

•Schmitt Trigger, Filtered Inputs for Noise Suppression

•Bi-directional Data Transfer Protocol

•100 kHz (1.8V) and 400 kHz (2.5V, 2.7V, 5V) Compatibility

•Write Protect Pin for Hardware Data Protection

•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

•Partial Page Writes are Allowed

•Self-timed Write Cycle (5 ms max)

•High-reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

•Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices

Available

•8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23,

8-lead TS SOP and 8-ball dBGA2™ Packages

Description

The AT24 C01A/02 /04/08/1 6 provides 10 24/2048/ 4096/81 92/16384 bits of ser ial ele c-

trically erasable and programmable read-only memor y (EEPROM) organized as

128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many

industrial and commercial applications where low-power and low-voltage operation

are essential. The AT24C01A/02/04/08/16 is availab le in space-saving 8-lead PDIP,

8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-

lead TSSOP and 8-ball dBGA2 packages and is accessed via a 2-wire serial interf ace.

In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)

versions.

2-wire

Serial EEPROM

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

16K (2048 x 8)

AT24C01A

AT24C02

AT24C04

AT24C08(1)

AT24C16(2)

0180R–SEEPR–4/04

Note: 1. This device is not recom-

mended for new designs.

Please refer to AT24C08A.

2. This device is not recom-

mended for new designs.

Please refer to AT24C16A.

Pin Configurations

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock In put

WP Write Protect

NC No Connect

GND Ground

VCC Power Supply

8-lead SO IC

GND

VCC

SCL

SDA

8-lead PDIP

GND

VCC

SCL

SDA

8-le ad MAP

Bottom View

VCC

SCL

SDA

GND

5-lead SOT23

SCL

GND

SDA

VCC

8-ball dBGA2

Bottom View

VCC

SCL

SDA

GND

8-lead TSSOP

GND

VCC

SCL

SDA

5-lead SOT23 Rotated (R)

(1k only)

SCL

GND

SDA

VCC

2AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Block Diag ram

Absolute Maxim u m Ratings

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. Th is is a stres s rat ing onl y and

funct ional ope rati on of the de vic e at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons for e xtended periods ma y affe ct devic e

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximu m Op er ati ng Volt age ............ ................. ..... ........ 6.25V

DC Output Current...................... ................. ...... ........... 5.0 mA

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Pin Description SERIAL CLOCK (SCL): The SC L input is used to posi tive edge clo ck data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DAT A (SDA): The SDA pin is bi-directional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open-

collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device

address input s that are hard wire d for the AT24C0 1A and the AT24C 02. As many as

eight 1K/2K dev ices may be addressed on a single bus system (de vice addressing is

discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K

devices may be addressed on a single bus system. The A0 pin is a no connect.

The AT24C 08 only uses the A2 inp ut for hardwire ad dressing and a total of two 8K

devices may be addressed on a single bus system. The A0 and A1 pins are no

connects.

The AT24C16 does not use the device address pins, which limits the number of devices

on a single bus to one. The A0, A1 and A2 pins are no connects.

WRITE PROT EC T (WP) : The AT24C01A/02/04/16 has a Write Protect pin that provides

hardware data protection. The Write Protect pin allows normal read/write operations

when con nected to groun d (G ND). When the W rite Pr otect pin i s conne cte d to V CC, the

write protection feature is enabled and operates as shown in the following table.

Notes: 1. This device is not recommended for new designs. Please refer to AT24C08A.

2. This device is not recommended for new designs. Pl ease refer to AT24C16A.

Memory Organization AT24C01A, 1 K S E RIAL EEPROM: Internally organized with 16 pages of 8 bytes each,

the 1K requires a 7-bit data word address for random word addressing.

AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,

the 2K requires an 8-bit data word address for random word addressing.

AT24C04, 4K SERIAL EEPROM: Interna lly organiz ed with 32 pages of 16 bytes each ,

the 4K requires a 9-bit data word address for random word addressing.

AT24C08, 8K SERIAL EEPROM: Interna lly organiz ed with 64 pages of 16 bytes each ,

the 8K requires a 10-bit data word address for random word addressing.

AT24C16, 16K SERIAL E EPROM: Internally o rganized with 128 pages of 16 b ytes

each, the 16K requires an 11-bit data word address for random word addressing.

WP Pin

Status

Part of the Array Protected

24C01A 24C02 24C04 24C08(1) 24C16(2)

At VCC Full (1K)

Array Full (2K)

Array Full (4K)

Array

Normal

Read/

Write

Operation

Upper

Half

(8K)

Array

At GND Normal Read/Write Operations

4AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Note: 1. This p arameter is characterized and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and are not tested.

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol Test Condition Max Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

DC Characteristics

Applic able over reco mmende d operati ng rang e from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V , TAE = -40°C to +125°C,

VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.8 5.5 V

VCC2 Supply Voltage 2.5 5.5 V

VCC3 Supply Voltage 2.7 5.5 V

VCC4 Supply Voltage 4.5 5.5 V

ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA

ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA

ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA

ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO Output Lea ka ge Cu rren t V OUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(1) -0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL2 Out put Lo w Level VCC = 3.0V IOL = 2.1 mA 0.4 V

VOL1 Out put Lo w Level VCC = 1.8V IOL = 0.15 mA 0.2 V

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Note: 1. The 24C01A/02/04 bearing the process letter “D” on the package (the mark is located in the lower right corner on the top

side of the package), guarantees 400 kHz (2.5 – 5.0V).

2. This parameter is characterized and is not 100% tested.

AC Characteristics

Appli cable over recommen ded operati ng rang e from TAI = -40°C to +8 5°C, VCC = +1.8V to +5.5V, TAE = -40°C to +125°C,

VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter

1.8-volt 2.5, 2.7, 5.0-volt

UnitsMin Max Min Max

fSCL Clo ck Fre que nc y, SCL 100 400(1) kHz

tLOW Clock Pulse Width Low 4.7 1.2 µs

tHIGH Clock Pulse Width High 4.0 0.6 µs

tINoise Supp ression Time(2) 100 50 ns

tAA Cloc k Lo w to Data Out Valid 0.1 4.5 0.1 0.9 µs

tBUF Time the bus must be free before

a new transmission can start(2) 4.7 1.2 µs

tHD.STA Start Hold Time 4.0 0.6 µs

tSU.STA Start Setup Time 4.7 0.6 µs

tHD.DAT Data In Hold Time 0 0 µs

tSU.DAT Data In Setup Time 200 100 ns

tRInputs Rise Time(2) 1.0 0.3 µs

tFInputs Fall Time(2) 300 300 ns

tSU.STO Stop Setup Time 4.7 0.6 µs

tDH Data Out Hold Time 100 50 ns

tWR Write Cycle Time 5 5 ms

Endurance(1) 5.0V, 25°C, Byte Mode 1M 1M Write

Cycles

6AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Device Operation CLOCK and DATA TRANSITI ONS: Th e SDA pin is normally pulled hig h with an ex ter-

nal devi ce . Data on th e SDA pin ma y ch a nge onl y duri ng SCL low ti me perio ds (ref er to

Data Validity timing diagram). Data changes during SCL high periods will indicate a start

or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (refer to Start and Stop Definition timing

diagram).

STOP CO NDI TION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has

received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode

which is enabled: ( a) upon power-up and (b) after the re ceipt of the STOP bit and the

completion of any internal operations.

MEMO RY R ESET : After an interruption in protocol, power loss or system reset, any 2-

wire part can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Bus Timing

SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

Note: 1. The write cyc le time tWR i s the tim e from a v alid stop co nditio n of a write se que nce to the end of the internal clea r/write cycle .

twr(1)

STOP

CONDITION START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

8AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Data Validity

Start and Stop Definition

Output Acknowledge

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Device Addressing The 1K, 2 K, 4K, 8K a nd 1 6K EE PRO M dev ic es al l r eq ui re an 8-bit d ev ic e a ddres s wor d

following a start condition to enable the chip for a read or write operation (refer to Figure

1).

The device address word consists of a mandatory one, zero sequence for the first four

most significant bits as shown. This is common to all the EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.

These 3 bits must compare to their corresponding hard-wired input pins.

The 4K EEPRO M on ly use s the A2 and A1 devi ce ad dres s bi ts with the thir d bi t bein g a

memory page address bit. The two device address bits must compare to their corre-

sponding hard-wired input pins. The A0 pin is no connect.

The 8K EEP ROM only us es the A2 device add ress bit with the next 2 bits bei ng for

memory page addressing. The A2 bit must compare to its corresponding hard-wired

input pin. The A1 and A0 pins are no connect.

The 16K does not use any devi ce addr ess bits but inst ead the 3 bits are us ed for mem-

ory page addressing. These page addressing bits on the 4K, 8K and 16K devices

should be considered the most significant bits of the data word address which follows.

The A0, A1 and A2 pins are no connect.

The eig hth bi t of the dev i ce add r ess is the r ead /write ope ra tio n s elec t bi t. A r ea d o pera-

tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a com pare of the dev ic e ad dres s, th e EE PRO M will ou tpu t a zero . If a compar e is

not made, the chip will return to a standby state.

Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the

device add ress word and ackn owledg ment. Upo n recei pt of thi s add ress, th e EEPR OM

will again respond with a zero and then clock in the first 8-bit dat a word. Follow ing

receipt of the 8-bit data word, the EEPROM will output a zero and the addressing

device , such a s a micr ocontrol ler, m ust termi nate the wr ite seque nce wi th a stop cond i-

tion. At this time the EEPROM enters an internally timed write cycle, tWR, to the

nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will

not respond until the write is complete (refer to Figure 2).

PAGE WRITE: The 1K/2K EE PR OM is c apa bl e of an 8- byte page write, and the 4K , 8K

and 16K devices are capable of 16-byte page writes.

A page wri te is in itiate d the same as a byte wr ite, but th e micr ocontro ller does not sen d

a stop condition after the first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcontroller can transmit up to seven

(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero

after each data word received. The microcontroller must terminate the page write

sequence with a stop condition (refer to Figure 3).

The data word address lower three (1K /2K) or four (4K, 8K, 16K) bits are i nternally

increm ent ed fol lowing the rec ei pt of eac h data wo rd. T h e h igh er d ata word add re ss b its

are not incr emented, retai ning the memor y page row locat ion. When the word address,

internally generated, reaches the page boundary, the following byte is placed at the

beginning of th e same page. If more than eigh t (1K/2K) or sixteen (4K, 8K, 16K ) data

words a re tran smitte d to th e EE PROM, the d ata wor d addr ess wi ll “r oll o ver” a nd prev i-

ous data will be overwritten.

10 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start co ndi tio n fol low ed by th e de vice address wor d. Th e re ad/ writ e b it is representat iv e of th e

operat ion desired. Only if the int ernal write cy cle has comp leted will the EEPR OM respon d

with a zero allowing the read or write sequence to continue.

Read

Operations Read ope ration s are init iated the sa me way as writ e operation s with the exce ption th at the

read/write select bit in the device address word is set to one. There are three read operations:

current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter main tains the last

address accessed during the last read or write operation, incremented by one. This address

stays valid between operations as long as the chip power is maintained. The address “roll

over” during read is from the last byte of the last memory page to the first byte of the first page.

The addres s “roll over” du ring writ e is from the l ast byte of the c urrent pa ge to the fir st byte of

the same page.

Once the device address with the read/write select bi t set to one is clocked in and acknowl-

edged by the EEPROM, the current address data word is serially clocked out. The

microcon tr oll er d oes not r es pon d w ith an i npu t z ero bu t d oes g ene ra te a fol low ing s top c ond i-

tion (refer to Figure 4).

RANDOM READ: A random rea d r eq ui re s a “d umm y” by te w ri te se que nc e t o l oa d i n the da ta

word address. Once the device address word and data word address are clocked in and

acknowledged by the EEPROM, the microcontroller must generate another start condition.

The micro con tr oll er now initiate s a cu rre nt add re ss rea d by sending a device add re ss with the

read/write select bit high. The EEPROM acknowledges the device address and serially clocks

out the data word. The microcontroller does not respond with a zero but does generate a fol-

lowing stop condition (refer to Figure 5).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-

dom address read. After the microcontroller receives a data word, it responds with an

acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment

the data word address and serially clock out sequential data words. When the memory

address limit is reached, the data word address will “roll over” and the sequential read will con-

tinue. Th e seque ntial rea d ope ration is termi nated whe n the micr ocontr olle r does not re spond

with a zero but does generate a following stop condition (refer to Figure 6).

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Figure 1. Device Address

Notes: 1. This device is not recommended for new designs. Please refer to AT24C08A.

2. This device is not recommended for new designs. Pl ease refer to AT24C16A.

Figure 2. Byte Write

Figure 3. Page Write

(* = DON’T CARE bit for 1K)

8K(1)

16K(2)

12 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Figure 4. Current Address Read

Figure 5. Random Read

(* = DON’T CARE bit for 1K)

Figure 6. Sequential Read

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.

AT24C01A Ordering Information

Orde ring Code P acka ge Operation Range

AT24C01A-10PI-2.7

AT24C01A-10SI-2.7

AT24C01A-10TI-2.7

AT24C01AY1-10YI-2.7

AT24C01A-10TSI-2.7

AT24C01AR-10TSI-2.7

AT24C01AU3-10UI-2.7

8P3

8S1

8A2

8Y1

5TS1

8U3-1

Industrial

(-40°C to 85°C)

AT24C01A-10PI-1.8

AT24C01A-10SI-1.8

AT24C01A-10TI-1.8

AT24C01AY1-10YI-1.8

AT24C01A-10TSI-1.8

AT24C01AU3-10UI-1.8

8P3

8S1

8A2

8Y1

5TS1

8U3-1

Industrial

(-40°C to 85°C)

AT24C01A-10SU-2.7

AT24C01A-10SU-1.8

AT24C01A-10TU-2.7

AT24C01A-10TU-1.8

8S1

8A2

Lead-free/Halogen-free/

Industrial Temperature

(-40°C to 85°C)

AT24C01A-10SE-2.7 8S1 High Grade/Ex tended Temp

(-40°C to 125°C)

AT24C01A-10SQ-2.7 8S1 Lead-free/Halogen-free/

High Gr a de/Ex tended Temp

(-40°C to 125°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1 8-ball, die Ball Grid Away Package (dBGA2)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 5.5V)

RRotated Pinout

14 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.

AT24C02 Ordering Info rmation

Ordering Code Package Operation Range

AT24C02-10PI-2.7

AT24C02N-10SI-2.7

AT24C02-10TI-2.7

AT24C02Y1-10YI-2.7

AT24C02-10TSI-2.7

AT24C02U3-10UI-2.7

8P3

8S1

8A2

8Y1

5TS1

8U3-1

Industrial

(-40°C to 85°C)

AT24C02-10PI-1.8

AT24C02N-10SI-1.8

AT24C02-10TI-1.8

AT24C02Y1-10YI-1.8

AT24C02-10TSI-1.8

AT24C02U3-10UI-1.8

8P3

8S1

8A2

8Y1

5TS1

8U3-1

Industrial

(-40°C to 85°C)

AT24C02N-10SU-2.7

AT24C02N-10SU-1.8

AT24C02-10TU-2.7

AT24C02-10TU-1.8

8S1

8A2

Lead-free/Halogen-free/

Industrial Temperature

(-40°C to 85°C)

AT24C02N-10SE-2.7 8S1 High Grade/Extended Temp

(-40°C to 125°C)

AT24C02N-10SQ-2.7 8S1 Lead-free/Halogen-free/

High Grade/Extended Temp

(-40°C to 125°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1 8-ball, die Ball Grid Away Package (dBGA2)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 5.5V)

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.

AT24C04 Ordering Info rmation

Orde ring Code Package Op erati on Range

AT24C04-10PI-2.7

AT24C04N-10SI-2.7

AT24C04-10TI-2.7

AT24C04Y1-10YI-2.7

AT24C04-10TSI-2.7

AT24C04U3-10UI-2.7

8P3

8S1

8A2

8Y1

5TS1

8U3-1

Industrial

(-40°C to 85°C)

AT24C04-10PI-1.8

AT24C04N-10SI-1.8

AT24C04-10TI-1.8

AT24C04Y1-10YI-1.8

AT24C04-10TSI-1.8

AT24C04U3-10UI-1.8

8P3

8S1

8A2

8Y1

5TS1

8U3-1

Industrial

(-40°C to 85°C)

AT24C04N-10SU-2.7

AT24C04N-10SU-1.8

AT24C04-10TU-2.7

AT24C04-10TU-1.8

8S1

8A2

Lead-free/Halogen-free/

Industrial Temperature

(-40°C to 85°C)

AT24C04N-10SE-2.7 8S1 High Grade/Extended Temp

(-40°C to 125°C)

AT24C04N-10SQ-2.7 8S1 Lead-free/Halogen-free/

High Grade/Extended Temp

(-40°C to 125°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)

5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

8U3-1 8-ball, die Ball Grid Away Package (dBGA2)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 5.5V)

16 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Notes: 1. For 2.7V devi ces used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC character isti cs table.

2. This device is not recommended for new designs. Please refer to AT24C08A.

AT24C08(2) Ordering Information

Orde ring Code Package Op erati on Range

AT24C08-10PI-2.7

AT24C08N-10SI-2.7

AT24C08-10TI-2.7

8P3

8S1

8A2

Industrial

(-40°C to 85°C)

AT24C08-10PI-1.8

AT24C08N-10SI-1.8

AT24C08-10TI-1.8

8P3

8S1

8A2

Industrial

(-40°C to 85°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 5.5V)

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

Notes: 1. For 2.7V devi ces used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC character isti cs table.

2. This device is not recommended for new designs. Please refer to AT24C16A.

AT24C16(2) Ordering Information

Orde ring Code Package Op erati on Range

AT24C16-10PI-2.7

AT24C16N-10SI-2.7

AT24C16-10TI-2.7

8P3

8S1

8A2

Industrial

(-40°C to 85°C)

AT24C16-10PI-1.8

AT24C16N-10SI-1.8

AT24C16-10TI-1.8

8P3

8S1

8A2

Industrial

(-40°C to 85°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 5.5V)

18 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

Packaging Information

8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

01/09/02

8P3 B

A2 A

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

A 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

Note:

10/7/03

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 B

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0˚ – 8˚

∅

Top View End View

Side View

20 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

8A2 – TS SOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End View

Top View

123

Pin 1 indicator

this corner

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

8Y1 – MAP

A – – 0.90

A1 0.00 – 0.05

D 4.70 4.90 5.10

E 2.80 3.00 3.20

D1 0.85 1.00 1.15

E1 0.85 1.00 1.15

b 0.25 0.30 0.35

e 0.65 TYP

L 0.50 0.60 0.70

PIN 1 INDEX AREA

A1 b

876

PIN 1 INDEX AREA

1234

Top View End View Bottom View

Side View

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package

(MAP) Y1 C

8Y1

2/28/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN NOM MAX

NOTE

22 AT24C01A/02/04/08/16 0180R–SEEPR–4/04

5TS1 – SOT23

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

PO5TS1 A

6/25/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink

Small Outline Package (SHRINK SOT)

A – – 1.10

A1 0.00 – 0.10

A2 0.70 0.90 1.00

c 0.08 – 0.20 4

D 2.90 BSC 2, 3

E 2.80 BSC 2, 3

E1 1.60 BSC 2, 3

L1 0.60 REF

e 0.95 BSC

e1 1.90 BSC

b 0.30 – 0.50 4, 5

NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing

MO-193, Variation AB, for additional information.

2. Dimension D does not include mold flash, protrusions, or gate burrs.

Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.

Dimension E1 does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.15 mm per side.

3. The package top may be smaller than the package bottom. Dimensions

D and E1 are determined at the outermost extremes of the plastic body

exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but

including any mismatch between the top and bottom of the plastic body.

4. These dimensions apply to the flat section of the lead between 0.08 mm

and 0.15 mm from the lead tip.

5. Dimension "b" does not include Dambar protrusion. Allowable Dambar

protrusion shall be 0.08 mm total in excess of the "b" dimension at

maximum material condition. The Dambar cannot be located on the lower

radius of the foot. Minimum space between protrusion and an adjacent lead

shall not be less than 0.07 mm.

End View

Seating

Plane

Side View

1Top View

AT24C01A/02/04/08/16

0180R–SEEPR–4/04

8U3-1 – dBGA2

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

PO8U3-1 A

6/24/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,

Small Die Ball Grid Array Package (dBGA2)

A 0.71 0.81 0.91

A1 0.10 0.15 0.20

A2 0.40 0.45 0.50

b 0.20 0.25 0.30

D 1.50 BSC

E 2.00 BSC

e 0.50 BSC

e1 0.25 REF

d 1.00 BSC

d1 0.25 REF

1. Dimension 'b' is measured at the maximum solder ball diameter.

This drawing is for general information only.

Bottom View

8 SOLDER BALLS

Top View

PIN 1 BALL PAD CORNER

Side View

PIN 1 BALL PAD CORNER

(e1)

(d1)

Printed on recycled paper.

0180R–SEEPR–4/04 xM

Disclaimer: Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in t he Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not author ized for use

as critical components in life suppor t devices or systems.

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