W25X32VSSIG - Winbond Electronics

W25X16, W25X32, W25X64

Publication Release Date:

- 1 - March 21, 2007, Revision F

16M-BIT, 32M-BIT, AND 64M-BIT

SERIAL FLASH MEMORY WITH

4KB SECTORS AND DUAL OUTPUT SPI

W25X16, W25X32, W25X64

- 2 -

Table of Contents

1. GENERAL DESCRIPTION......................................................................................................... 4

2. FEATURES................................................................................................................................. 4

3. PIN CONFIGURATION SOIC 208-MIL....................................................................................... 5

4. PIN CONFIGURATION WSON 6X5-MM.................................................................................... 5

5. PIN CONFIGURATION PDIP 300-MIL....................................................................................... 6

6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL, AND WSON 6X5-MM............................... 6

7. PIN CONFIGURATION SOIC 300-MIL....................................................................................... 7

8. PIN DESCRIPTION SOIC 300-MIL ............................................................................................ 7

8.1 Package Types............................................................................................................... 8

8.2 Chip Select (/CS)............................................................................................................ 8

8.3 Serial Data Output (DO) ................................................................................................. 8

8.4 Write Protect (/WP)......................................................................................................... 8

8.5 HOLD (/HOLD) ............................................................................................................... 8

8.6 Serial Clock (CLK).......................................................................................................... 8

8.7 Serial Data Input / Output (DIO) ..................................................................................... 8

9. BLOCK DIAGRAM...................................................................................................................... 9

10. FUNCTIONAL DESCRIPTION ................................................................................................. 10

10.1 SPI OPERATIONS ....................................................................................................... 10

10.1.1 SPI Modes....................................................................................................................10

10.1.2 Dual Output SPI............................................................................................................10

10.1.3 Hold Function ...............................................................................................................10

10.2 WRITE PROTECTION.................................................................................................. 11

10.2.1 Write Protect Features..................................................................................................11

11. CONTROL AND STATUS REGISTERS................................................................................... 12

11.1 STATUS REGISTER.................................................................................................... 12

11.1.1 BUSY............................................................................................................................12

11.1.2 Write Enable Latch (WEL)............................................................................................12

11.1.3 Block Protect Bits (BP2, BP1, BP0)..............................................................................12

11.1.4 Top/Bottom Block Protect (TB).....................................................................................12

11.1.5 Reserved Bits...............................................................................................................12

11.1.6 Status Register Protect (SRP)......................................................................................13

11.1.7 Status Register Memory Protection..............................................................................14

11.2 INSTRUCTIONS........................................................................................................... 16

11.2.1 Manufacturer and Device Identification.........................................................................16

11.2.2 Instruction Set...............................................................................................................17

11.2.3 Write Ensable (06h)......................................................................................................18

W25X16, W25X32, W25X64

Publication Release Date:

- 3 - March 21, 2007, Revision F

11.2.4 Write Disable (04h).......................................................................................................18

11.2.5 Read Status Register (05h)..........................................................................................19

11.2.6 Write Status Register (01h) ..........................................................................................20

11.2.7 Read Data (03h)...........................................................................................................21

11.2.8 Fast Read (0Bh)...........................................................................................................22

11.2.9 Fast Read Dual Output (3Bh).......................................................................................23

11.2.10 Page Program (02h)...................................................................................................24

11.2.11 Sector Erase (20h) .....................................................................................................25

11.2.12 Block Erase (D8h) ......................................................................................................26

11.2.13 Chip Erase (C7h)........................................................................................................27

11.2.14 Power-down (B9h)......................................................................................................28

11.2.15 Release Power-down / Device ID (ABh).....................................................................29

11.2.16 Read Manufacturer / Device ID (90h).........................................................................31

11.2.17 JEDEC ID (9Fh)..........................................................................................................32

12. ELECTRICAL CHARACTERISTICS (PRELIMINARY)............................................................. 33

12.1 Absolute Maximum Ratings.......................................................................................... 33

12.2 Operating Ranges......................................................................................................... 33

12.3 Endurance and Data Retention.................................................................................... 34

12.4 Power-up Timing and Write Inhibit Threshold.............................................................. 34

12.5 DC Electrical Characteristics........................................................................................ 35

12.6 AC Measurement Conditions........................................................................................ 36

12.7 AC Electrical Characteristics ........................................................................................ 37

12.8 AC Electrical Characteristics (Cont’d) .......................................................................... 38

12.9 Serial Output Timing..................................................................................................... 39

12.10 Input Timing................................................................................................................. 39

12.11 Hold Timing ................................................................................................................. 39

13. PACKAGE SPECIFICATION.................................................................................................... 40

13.1 8-Pin SOIC 208-mil (Package Code SS)...................................................................... 40

13.2 8-Pin PDIP 300-mil (Package Code DA)...................................................................... 41

13.3 8-contact 6x5 WSON.................................................................................................... 42

13.4 8-contact 6x5 WSON (Cont’d)...................................................................................... 43

13.5 16-Pin SOIC 300-mil (Winbond Package Code SF)..................................................... 44

14. ORDERING INFORMATION .................................................................................................... 45

15. REVISION HISTORY................................................................................................................ 47

W25X16, W25X32, W25X64

- 4 -

1. GENERAL DESCRIPTION

The W25X16 (16M-bit), W25X32 (32M-bit), and W25X64 (64M-bit) Serial Flash memories provide a

storage solution for systems with limited space, pins and power. The 25X series offers flexibility and

performance well beyond ordinary Serial Flash devices. They are ideal for code download applications

as well as storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply

with current consumption as low as 5mA active and 1µA for power-down. All devices are offered in

space-saving packages.

The W25X16/32/64 array is organized into 8,192/16,384/32,768 programmable pages of 256-bytes

each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can

be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase).

The W25X16/32/64 has 512/1024/2048 erasable sectors and 32/64/128 erasable blocks respectively.

The small 4KB sectors allow for greater flexibility in applications that require data and parameter

storage. (See figure 2.)

The W25X16/32/64 supports the standard Serial Peripheral Interface (SPI), and a high performance

dual output SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI

clock frequencies of up to 75MHz are supported allowing equivalent clock rates of 150MHz when

using the Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and

16-bit Parallel Flash memories.

A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control features,

provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and

device identification.

2. FEATURES

• Family of Serial Flash Memories

– W25X16: 16M-bit / 2M-byte (2,097,152)

– W25X32: 32M-bit / 4M-byte (4,194,304)

– W25X64: 64M-bit / 8M-byte (8,388,608)

– 256-bytes per programmable page

– Uniform 4K-byte Sect ors / 64K-byte Blocks

• SPI with Single or Dual Outputs

– Clock, Chip Select, Data I/O, Data Out

– Optional Hold function for SPI flexibility

• Data Transfer up to 150M-bits / second

– Clock operation to 75MHz

– Fast Read Dual Output instruction

– Auto-increment Read capability

• Flexible Architecture with 4KB sectors

– Sector Erase (4K-bytes)

– Block Erase (64K-byte)

– Page program up to 256 bytes <2ms

– Up to 100,000 erase/write cycles

– 20-year retention

• Low Power Consumption, Wide

Temperature Range

– Single 2.7 to 3.6V supply

– 5mA active current, 1µA Power-down (typ)

– -40° to +85°C operating range

• Software and Hardware Write Protection

– Write-Protect all or portion of memory

– Enable/Disable protection with /WP pin

– Top or bottom array protection

• Space Efficient Packaging

– 8-pin SOIC 208-mil (W25X16, X32)

– 8-pin PDIP 300-mil (W25X16, X32, X64)

– 16-pin SOIC 300-mil (W25X16, X32, X64)

– 8-pad WSON 6x5-mm (W25X16)

– 8-pad WSON 8x6-mm (W25X32, X64)

W25X16, W25X32, W25X64

Publication Release Date:

- 5 - March 21, 2007, Revision F

3. PIN CONFIGURATION SOIC 208-MIL

Figure 1a. W25X16 and W25X32 Pin Assignments, 8-pin SOIC (Package Code SS)

4. PAD CONFIGURATION WSON 6X5-MM

Figure 1b. W25X16 Pad Assignments, 8-pad WSON (Package Code ZP)

W25X16, W25X32, W25X64

- 6 -

5. PIN CONFIGURATION PDIP 300-MIL

Figure 1c. W25X16, W25X32, W25X64 Pin Assignments, 8-pin PDIP (Package Code DA)

6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL, AND WSON 6X5-MM

PIN NO. PIN NAME I/O FUNCTION

1 /CS I Chip Select Input

2 DO O Data Output

3 /WP I Write Protect Input

4 GND Ground

5 DIO I/O Data Input / Output

6 CLK I Serial Clock Input

7 /HOLD I Hold Input

8 VCC Power Supply

W25X16, W25X32, W25X64

Publication Release Date:

- 7 - March 21, 2007, Revision F

7. PIN CONFIGURATION SOIC 300-MIL

Figure 1d. W25X16, W25X32 and W25X64 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)

8. PIN DESCRIPTION SOIC 300-MIL

PIN NO. PIN NAME I/O FUNCTION

1 /HOLD I Hold Input

2 VCC Power Supply

3 N/C No Connect

4 N/C No Connect

5 N/C No Connect

6 N/C No Connect

7 /CS I Chip Select Input

8 DO O Data Output

9 /WP I Write Protect Input

10 GND Ground

11 N/C No Connect

12 N/C No Connect

13 N/C No Connect

14 N/C No Connect

15 DIO I/O Data Input / Output

16 CLK I Serial Clock Input

W25X16, W25X32, W25X64

- 8 -

8.1 Package Types

At the time this datasheet was published not all package types had been finalized. Contact Winbond

to confirm availability of these packages before designing to this specification. W25X16 and W25X32

are offered in an 8-pin plastic 208-mil width SOIC (package code SS). The W25X16 in 6x5-mm

WSON (package code ZP) and 25X32 and 25X64 in 8x6-mm WSON. (package code ZE). The 25X16,

W25X32 and W25X64 are offered in 16-pin plastic 300-mil width SOIC (package code SF) and 300-

mil DIP (package code DA). See figures 1a-d. Package diagrams and dimensions are illustrated at the

end of this datasheet.

8.2 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is

deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices

power consumption will be at standby levels unless an internal erase, program or status register cycle

is in progress. When /CS is brought low the device will be selected, power consumption will increase

to active levels and instructions can be written to and data read from the device. After power-up, /CS

must transition from high to low before a new instruction will be accepted. The /CS input must track

the VCC supply level at power-up (see “Write Protection” and figure 20). If needed a pull-up resister

on /CS can be used to accomplish this.

8.3 Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from

(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

8.4 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register

Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is

active low.

8.5 HOLD (/HOLD)

The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought

low, while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will

be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD

function can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)

8.6 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Operations")

8.7 Serial Data Input / Output (DIO)

The SPI Serial Data Input/Output (DIO) pin provides a means for instructions, addresses and data to

be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock

(CLK) input pin. The DIO pin is also used as an output when the Fast Read Dual Output instruction is

executed.

W25X16, W25X32, W25X64

Publication Release Date:

- 9 - March 21, 2007, Revision F

9. BLOCK DIAGRAM

/HOLD

/WP

CLK

/CS

DIO

000000h

00FF00h

0000FFh

00FFFFh

1F0000h 1F00FFh

1FFF00h 1FFFFFh

200000h

20FF00h

2000FFh

20FFFFh

3F0000h

3FFF00h 3FFFFFh

3F00FFh

400000h

40FF00h

4000FFh

40FFFFh

7F0000h

7FFF00h 7FFFFFh

7F00FFh

Figure 2. W25X16, W25X32 and W25X64 Block Diagram

W25X16, W25X32, W25X64

- 10 -

10. FUNCTIONAL DESCRIPTION

10.1 SPI OPERATIONS

10.1.1 SPI Modes

The W25X16/32/64 is accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI bus

operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode

3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not

being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK

signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of the

CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.

10.1.2 Dual Output SPI

The W25X16/32/64 supports Dual output operation when using the "Fast Read with Dual Output" (3B

hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice the

rate possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash

to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM for

execution. The Dual output feature simply allows the SPI input pin to also serve as an output during

this instruction. All other operations use the standard SPI interface with single output signal.

10.1.3 Hold Function

The /HOLD signal allows the W25X16/32/64 operation to be paused while it is actively selected (when

/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are

shared with other devices. For example, consider if the page buffer was only partially written when a

priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the

instruction and the data in the buffer so programming can resume where it left off once the bus is

available again.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will

activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition

will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will terminate after the next falling edge of CLK.

During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data

Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept

active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the

device.

W25X16, W25X32, W25X64

Publication Release Date:

- 11 - March 21, 2007, Revision F

10.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and

other adverse system conditions that may compromise data integrity. To address this concern the

W25X16/32/64 provides several means to protect data from inadvertent writes.

10.2.1 Write Protect Features

• Device resets when VCC is below threshold.

• Time delay write disable after Power-up.

• Write enable/disable instructions.

• Automatic write disable after program and erase.

• Software write protection using Status Register.

• Hardware write protection using Status Register and /WP pin.

• Write Protection using Power-down instruction.

Upon power-up or at power-down the W25X16/32/64 will maintain a reset condition while VCC is

below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 20). While

reset, all operations are disabled and no instructions are recognized. During power-up and after the

VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time

delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase

and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC

supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up

resister on /CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register

Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page

Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically

cleared to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status

with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under

hardware control. See Status Register for further information.

Additionally, the Power-down instruction offers an extra level of write protection as all instructions are

ignored except for the Release Power-down instruction.

W25X16, W25X32, W25X64

- 12 -

11. CONTROL AND STATUS REGISTERS

The Read Status Register instruction can be used to provide status on the availability of the Flash

memory array, if the device is write enabled or disabled, and the state of write protection. The Write

Status Register instruction can be used to configure the devices write protection features. See Figure 3.

11.1 STATUS REGISTER

11.1.1 BUSY

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing

a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During

this time the device will ignore further instructions except for the Read Status Register instruction (see

tW, tPP, tSE, TBE, and tCE in AC Characteristics). When the program, erase or write status register

instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for

further instructions.

11.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing

a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A

write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

11.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4,

S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the

Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory

array can be protected from Program and Erase instructions (see Status Register Memory Protection

table). The factory default setting for the Block Protection Bits is 0, none of the array protected. The

Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write

Protect (/WP) pin is low.

11.1.4 Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0)

or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB

bit is non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write Status

written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.

11.1.5 Reserved Bits

Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit location.

It is recommended to mask out the reserved bit when testing the Status Register. Doing this will

ensure compatibility with future devices.

W25X16, W25X32, W25X64

Publication Release Date:

- 13 - March 21, 2007, Revision F

11.1.6 Status Register Protect (SRP)

The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be

used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the SRP

bit is set to a 0 state (factory default) the /WP pin has no control over status register. When the SRP

pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low. When the

/WP pin is high the Write Status Register instruction is allowed.

Figure 3. Status Register Bit Locations

W25X16, W25X32, W25X64

- 14 -

1.1.7 Status Register Memory Protection

STATUS REGISTER(1) W25X64 (64M-BIT) MEMORY PROTECTION

TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY

(KB) PORTION

x 0 0 0 NONE NONE NONE NONE

0 0 0 1 126 and 127 7E0000h - 7FFFFFh 1M -bit Upper 1/64

0 0 1 0 124 and 127 7C0000h - 7FFFFFh 2M-bit Upper 1/32

0 0 1 1 120 thru 127 780000h - 7FFFFFh 4M-bit Upper 1/16

0 1 0 0 112 thru 127 700000h - 7FFFFFh 8M-bit Upper 1/8

0 1 0 1 96 thru 127 600000h - 7FFFFFh 16M-bit Upper 1/4

0 1 1 0 64 thru 127 400000h - 7FFFFFh 32M-bit Upper 1/2

1 0 0 1 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/64

1 0 1 0 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/32

1 0 1 1 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/16

1 1 0 0 0 thru 15 000000h – 0FFFFFh 8M-bit Lower 1/8

1 1 0 1 0 thru 31 000000h – 1FFFFFh 16M-bit Lower 1/4

1 1 1 0 0 thru 63 000000h – 3FFFFFh 16M-bit Lower 1/2

x 1 1 1 0 thru 127 000000h - 7FFFFFh 64M-bit ALL

STATUS REGISTER(1) W25X32 (32M-BIT) MEMORY PROTECTION

TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY

(KB) PORTION

x 0 0 0 NONE NONE NONE NONE

0 0 0 1 63 3F0000h - 3FFFFFh 512K-bit Upper 1/64

0 0 1 0 62 and 63 3E0000h - 3FFFFFh 1M-bit Upper 1/32

0 0 1 1 60 thru 63 3C0000h - 3FFFFFh 2M-bit Upper 1/16

0 1 0 0 56 thru 63 380000h - 3FFFFFh 4M-bit Upper 1/8

0 1 0 1 48 thru 63 300000h - 3FFFFFh 8M-bit Upper 1/4

0 1 1 0 32 thru 63 200000h - 3FFFFFh 16M-bit Upper 1/2

1 0 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/64

1 0 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/32

1 0 1 1 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/16

1 1 0 0 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/8

1 1 0 1 0 thru 15 000000h – 0FFFFFh 8M-bit Lower 1/4

1 1 1 0 0 thru 31 000000h – 1FFFFFh 16M-bit Lower 1/2

x 1 1 1 0 thru 63 000000h - 3FFFFFh 32M-bit ALL

W25X16, W25X32, W25X64

Publication Release Date:

- 15 - March 21, 2007, Revision F

STATUS REGISTER(1) W25X16 (16M-BIT) MEMORY PROTECTION

TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY (KB) PORTION

x 0 0 0 NONE NONE NONE NONE

0 0 0 1 31 1F0000h - 1FFFFFh 512K-bit Upper 1/32

0 0 1 0 30 and 31 1E0000h - 1FFFFFh 1M-bit Upper 1/16

0 0 1 1 28 thru 31 1C0000h - 1FFFFFh 2M-bit Upper 1/8

0 1 0 0 24 thru 31 180000h - 1FFFFFh 4M-bit Upper 1/4

0 1 0 1 16 thru 31 100000h - 1FFFFFh 8M-bit Upper 1/2

1 0 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/32

1 0 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/16

1 0 1 1 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/8

1 1 0 0 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/4

1 1 0 1 0 thru 15 000000h - 0FFFFFh 8M-bit Lower 1/2

x 1 1 x 0 thru 31 000000h - 1FFFFFh 16M-bit ALL

Note:

1. x = don’t care

W25X16, W25X32, W25X64

- 16 -

11.2 INSTRUCTIONS

The instruction set of the W25X16/32/64 consists of fifteen basic instructions that are fully controlled

through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip

Select (/CS). The first byte of data clocked into the DIO input provides the instruction code. Data on

the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first.

Instructions vary in length from a single byte to several bytes and may be followed by address bytes,

data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed

with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in

figures 4 through 19. All read instructions can be completed after any clocked bit. However, all

instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a

full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects

the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or

when the Status Register is being written, all instructions except for Read Status Register will be

ignored until the program or erase cycle has completed.

11.2.1 Manufacturer and Device Identification

MANUFACTURER ID (M7-M0)

Winbond Serial Flash EFH

Device ID (ID7-ID0) (ID15-ID0)

Instruction ABh, 90h 9Fh

W25X16 14h

3015h

W25X32 15h

3016h

W25X64 16h

3017h

W25X16, W25X32, W25X64

Publication Release Date:

- 17 - March 21, 2007, Revision F

11.2.2 Instruction Set

(1)

INSTRUCTION

NA ME BYTE 1

CODE BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 N-BYTES

Write Enable 06h

Write Disable 04h

Read Status

Write Status

Read Data 03h A23–A16 A15–A8 A7–A0 (D7–D0) (Next byte) continuous

Fast Read 0Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0) (Next Byte)

continuous

Fast Read Dual

Output 3Bh A23–A16 A15–A8 A7–A0 dummy

I/O =

(D6,D4,D2,D0)

O =

(D7,D5,D3,D1)

(one byte

per 4 clocks,

continuous)

Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0) (Next byte) Up to 256

bytes

Block Erase

(64KB) D8h A23–A16 A15–A8 A7–A0

Sector Erase

(4KB) 20h A23–A16 A15–A8 A7–A0

Chip Erase C7h

Power-down B9h

Release Power-

down / Device ID ABh dummy dummy dummy (ID7-ID0)(4)

Manufacturer/

Device ID (3) 90h dummy dummy 00h (M7-M0) (ID7-ID0)

JEDEC ID 9Fh (M7-M0)

Manufacturer

(ID15-ID8)

Memory

Type

(ID7-ID0)

Capacity

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being

read from the device on the DO pin.

2. The Status Register contents will repeat continuously until /CS terminates the instruction.

3. See Manufacturer and Device Identification table for Device ID information.

4. The Device ID will repeat continuously until /CS terminates the instruction.

W25X16, W25X32, W25X64

- 18 -

11.2.3 Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to

a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase

and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low,

shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then

driving /CS high.

Figure 4. Write Enable Instruction Sequence Diagram

11.2.4 Write Disable (04h)

The Write Dissable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status

code “04h” into the DIO pin and then driving /CS high. Note that the WEL bit is automatically reset

after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block

Erase and Chip Erase instructions.

Figure 5. Write Disable Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 19 - March 21, 2007, Revision F

11.2.5 Read Status Register (05h)

The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is

entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge of

CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and

include the BUSY, WEL, BP2-BP0, TB and SRP bits (see description of the Status Register earlier in

this datasheet).

The Status Register instruction may be used at any time, even while a Program, Erase or Write Status

cycle is complete and if the device can accept another instruction. The Status Register can be read

continuously, as shown in Figure 6. The instruction is completed by driving /CS high.

Figure 6. Read Status Register Instruction Sequence Diagram

W25X16, W25X32, W25X64

- 20 -

11.2.6 Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. A Write Enable

instruction must previously have been executed for the device to accept the Write Status Register

Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by

driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as

illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this

datasheet.

Only non-volatile Status Register bits SRP, TB, BP2, BP1 and BP0 (bits 7, 5, 4, 3 and 2) can be

written to. All other Status Register bit locations are read-only and will not be affected by the Write

Status Register instruction.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed

Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While

the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed

to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a

0 when the cycle is finished and ready to accept other instructions again. After the Write Register

cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.

The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0) to be set

for protecting all, a portion, or none of the memory from erase and program instructions. Protected

areas become read-only (see Status Register Memory Protection table). The Write Status Register

instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction

with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0

state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a

1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is

high the Write Status Register instruction is allowed.

Figure 7. Write Status Register Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 21 - March 21, 2007, Revision F

11.2.7 Read Data (03h)

The Read Data instruction allows one more data bytes to be sequentially read from the memory. The

instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed

by a 24-bit address (A23-A0) into the DIO pin. The code and address bits are latched on the rising

edge of the CLK pin. After the address is received, the data byte of the addressed memory location

will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The

address is automatically incremented to the next higher address after each byte of data is shifted out

allowing for a continuous stream of data. This means that the entire memory can be accessed with a

single instruction as long as the clock continues. The instruction is completed by driving /CS high. The

Read Data instruction sequence is shown in figure 8. If a Read Data instruction is issued while an

Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any

effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of

fR (see AC Electrical Characteristics).

Figure 8. Read Data Instruction Sequence Diagram

W25X16, W25X32, W25X64

- 22 -

11.2.8 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the

highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding

eight “dummy” clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the

devices internal circuits additional time for setting up the initial address. During the dummy clocks the

data value on the DIO pin is a “don’t care”.

Figure 9. Fast Read Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 23 - March 21, 2007, Revision F

11.2.9 Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction

except that data is output on two pins, DO and DIO, instead of just DO. This allows data to be

transferred from the W25X16/32/64 at twice the rate of standard SPI devices. The Fast Read Dual

Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for

applications that cache code-segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest

possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight

“dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device's

internal circuits additional time for setting up the initial address. The input data during the dummy

clocks is “don’t care”. However, the DIO pin should be high-impedance prior to the falling edge of the

first data out clock.

Figure 10. Fast Read Dual Output Instruction Sequence Diagram

W25X16, W25X32, W25X64

- 24 -

11.2.10 Page Program (02h)

The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased

to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will

accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is

initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address

(A23-A0) and at least one data byte, into the DIO pin. The /CS pin must be held low for the entire

length of the instruction while data is being sent to the device. The Page Program instruction

sequence is shown in figure 11.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address

bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the

remaining page length, the addressing will wrap to the beginning of the page. In some cases, less

than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the

same page. One condition to perform a partial page program is that the number of clocks can not

exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will

wrap to the beginning of the page and overwrite previously sent data.

As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last

byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS

is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See

AC Characteristics). While the Page Program cycle is in progress, the Read Status Register

instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during

the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept

other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit

in the Status Register is cleared to 0. The Page Program instruction will not be executed if the

addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register

Memory Protection table).

Figure 11. Page Program Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 25 - March 21, 2007, Revision F

11.2.11 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state

of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS

pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure

2). The Sector Erase instruction sequence is shown in figure 12.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector

Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector

Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the Sector Erase

cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector

Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB,

BP2, BP1, and BP0) bits (see Status Register Memory Protection table).

Figure 12. Sector Erase Instruction Sequence Diagram

W25X16, W25X32, W25X64

- 26 -

11.2.12 Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of

all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS

pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2).

The Block Erase instruction sequence is shown in figure 13.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block

Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block

Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle

has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase

instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,

and BP0) bits (see Status Register Memory Protection table).

Figure 13. Block Erase Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 27 - March 21, 2007, Revision F

11.2.13 Chip Erase (C7h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and

shifting the instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 14.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip

Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction

will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in

progress, the Read Status Register instruction may still be accessed to check the status of the BUSY

bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is

ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed

if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory

Protection table).

Figure 14. Chip Erase Instruction Sequence Diagram

W25X16, W25X32, W25X64

- 28 -

11.2.14 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be further

reduced with the Power-down instruction. The lower power consumption makes the Power-down

instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC

Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code

“B9h” as shown in figure 15.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-

down instruction will not be executed. After /CS is driven high, the power-down state will entered

within the time duration of tDP (See AC Characteristics). While in the power-down state only the

Release from Power-down / Device ID instruction, which restores the device to normal operation, will

be recognized. All other instructions are ignored. This includes the Read Status Register instruction,

which is always available during normal operation. Ignoring all but one instruction makes the Power

Down state a useful condition for securing maximum write protection. The device always powers-up in

the normal operation with the standby current of ICC1.

Figure 15. Deep Power-down Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 29 - March 21, 2007, Revision F

11.2.15 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to

release the device from the power-down state, obtain the devices electronic identification (ID) number

or do both.

When used only to release the device from the power-down state, the instruction is issued by driving

the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 16. After

the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other

instructions will be accepted. The /CS pin must remain high during the tRES1 time duration.

When used only to obtain the Device ID while not in the power-down state, the instruction is initiated

by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The

Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as

shown in figure 17. The Device ID values for the W25X16, W25X32, and W25X64 are listed in

Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction

is completed by driving /CS high.

When used to release the device from the power-dow n state and obtain the Device ID, the instruction

is the same as previously described, and shown in figure 17, except that after /CS is driven high it

must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the

device will resume normal operation and other instructions will be accepted.

If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write

cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on

the current cycle

Figure 16. Release Power-down Instruction Sequence

W25X16, W25X32, W25X64

- 30 -

Figure 17. Release Power-down / Device ID Instruction Sequence Diagram

W25X16, W25X32, W25X64

Publication Release Date:

- 31 - March 21, 2007, Revision F

11.2.16 Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /

Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device

ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device

ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code

“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond

(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first

as shown in figure 18. The Device ID values for the W25X16, W25X32, AND W25X64 are listed in

Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device

ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can

be read continuously, alternating from one to the other. The instruction is completed by driving /CS

high.

Figure 18. Read Manufacturer / Device ID Diagram

W25X16, W25X32, W25X64

- 32 -

11.2.17 JEDEC ID (9Fh)

For compatibility reasons, the W25X16/32/64 provides several instructions to electronically determine

the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for

SPI compatible serial memories that was adopted in 2003.

The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The

JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type

(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant

bit (MSB) first as shown in figure 19. For memory type and capacity values refer to Manufacturer and

Device Identification table.

Figure 19. Read JEDEC ID

W25X16, W25X32, W25X64

Publication Release Date:

- 33 - March 21, 2007, Revision F

12. ELECTRICAL CHARACTERISTICS (1)

12.1 Absolute Maximum Ratings (2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT

Supply Voltage VCC –0.6 to +4.0 V

Voltage applied to any Pin VIO Relative to Ground –0.6 to VCC +0.4 V

Transient Voltage on any Pin VIOT <20nS Transient

Relative to Ground –2.0V to VCC+2.0V V

Storage Temperature TSTG –65 to +150 °C

Lead Temperature TLEAD See Note

(3) °C

Electrostatic Discharge Voltage VESD Human Body Model(4) –2000 to +2000 V

Notes:

1. Specifications for W25X32 and W25X64 are preliminary. See preliminary designation at the end of

this datasheet.

2. This device has been designed and tested for the specified operation ranges. Proper operation

outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device

reliability. Exposure beyond absolute maximum ratings may cause permanent damage.

3. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly

and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.

4. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).

12.2 Operating Ranges

SPEC

PARAMETER SYMBOL CONDITIONS MIN MAX

UNIT

Supply Voltage(1) VCC

FR = 50MHz, fR = 33MHz

FR0 = 70MHz, fR = 33MHz

FR1 = 75MHz, fR = 33MHz

2.7

3.0

3.6

3.6 V

Ambient Temperature,

Operating TA Commercial (2)

Industrial 0

–40 +70

+85 °C

Note:

1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the

programming (erase/write) voltage.

2. Commercial temperature only applies to Fast Read (FR0 & FR1) and 100K cycles endurance for 4K byte sectors .

Industrial temperature applies to all other parameters.

W25X16, W25X32, W25X64

- 34 -

12.3 Endurance and Data Retention

PARAMETER CONDITIONS MIN MAX UNIT

Erase/Program Cycles 4KB sector, 64KB block or full chip. 100,000 cycles

Data Retention 55°C 20 years

12.4 Power-up Timing and Write Inhibit Threshold

SPEC

PARAMETER SYMBOL

MIN MAX

UNIT

VCC (min) to /CS Low tVSL(1) 10 µs

Time Delay Before Write Instruction tPUW(1) 1 10 ms

Write Inhibit Threshold Voltage VWI(1) 1 2 V

Note:

1. These parameters are characterized only.

Figure 20. Power-up Timing and Voltage Levels

W25X16, W25X32, W25X64

Publication Release Date:

- 35 - March 21, 2007, Revision F

12.5 DC Electrical Characteristics

SPEC

PARAMETER SYMBOL CONDITIONS MIN TYP MAX

UNIT

Input Capacitance CIN(1) VIN = 0V(2) 6 pf

Output Capacitance Cout(1) VOUT = 0V(2) 8 pf

Input Leakage ILI ±2 µA

I/O Leakage ILO ±2 µA

Standby Current ICC1 /CS = VCC,

VIN = GND or VCC 25 50 µA

Power-down Current ICC2 /CS = VCC,

VIN = GND or VCC <1 10 µA

Current Read Data /

Dual Output Read

1MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC

DO = Open 5/6 7/8 mA

Current Read Data /

Dual Output Read

33MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC

DO = Open 7/8 11/12 mA

Current Read Data /

Dual Output Read

50MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC

DO = Open 9/10 13/15 mA

Current Read Data /

Dual Output Read

75MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC

DO = Open 11/12 16/18 mA

Current Page

Program ICC4 /CS = VCC 20 25 mA

Current Write Status

Current Sector/Block

Erase ICC6 /CS = VCC 20 25 mA

Current Chip Erase ICC7 /CS = VCC 20 25 mA

Input Low Voltage VIL –0.5 VCC x 0.3 V

Input High Voltage VIH VCC x0.7 VCC +0.4 V

Output Low Voltage VOL IOL = 1.6 mA 0.4 V

Output High Voltage VOH IOH = –100 µA VCC –0.2 V

Notes:

1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V.

2. Checker Board Pattern.

W25X16, W25X32, W25X64

- 36 -

12.6 AC Measurement Conditions

SPEC

PARAMETER SYMBOL

MIN MAX

UNIT

Load Capacitance

Load Capacitance for FR1 only CL 30

15 pF

Input Rise and Fall Times TR, TF 5 ns

Input Pulse Voltages VIN 0.2 VCC to 0.8 VCC V

Input Timing Reference Voltages IN 0.3 VCC to 0.7 VCC V

Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V

Note:

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC Measurement I/O Waveform

W25X16, W25X32, W25X64

Publication Release Date:

- 37 - March 21, 2007, Revision F

12.7 AC Electrical Characteristics

SPEC

DESCRIPTION SYMBOL ALT MIN TYP MAX UNIT

Clock frequency

for all instructions, except Read Data (03h)

2.7V-3.6V VCC & Industrial Temperature FRfCD.C. 50 MHz

Clock frequency

for all instructions, except Read Data (03h)

3.0V-3.6V VCC & Commercial Temperature FR0 (4) f

C0 D.C. 70 MHz

Clock frequency, for Fast Read (0Bh, 3Bh) only

3.0V-3.6V VCC & Commercial Temperature FR1 (4) f

C1 D.C. 75 MHz

Clock freq. Read Data instruction 03h fR D.C. 33 MHz

Clock High, Low Time, for Fast Read (0Bh, 3Bh) /

other instructions except Read Data (03h) tCLH,

tCLL(1) 6/7 ns

Clock High, Low Time for Read Data (03h)

instruction tCRLH,

tCRLL(1) 8 ns

Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns

Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns

/CS Active Setup Time relative to CLK tSLCH tCSS 5 ns

/CS Not Active Hold Time relative to CLK tCHSL 5 ns

Data In Setup Time tDVCH tDSU 2 ns

Data In Hold Time tCHDX tDH 5 ns

/CS Active Hold Time relative to CLK tCHSH 5 ns

/CS Not Active Setup Time relative to CLK tSHCH 5 ns

/CS Deselect Time tSHSL tCSH 100 ns

Output Disable Time tSHQZ(2) tDIS 7 ns

Clock Low to Output Valid

2.7V-3.6V / 3.0V-3.6V tCLQV tV 7 / 6 ns

Output Hold Time tCLQX tHO 0 ns

Continued – next page

W25X16, W25X32, W25X64

- 38 -

12.8 AC Electrical Characteristics (cont’d)

SPEC

DESCRIPTION SYMBOL ALT MIN TYP MAX UNIT

/HOLD Active Setup Time relative to CLK tHLCH 5 ns

/HOLD Active Hold Time relative to CLK tCHHH 5 ns

/HOLD Not Active Setup Time relative to CLK tHHCH 5 ns

/HOLD Not Active Hold Time relative to CLK tCHHL 5 ns

/HOLD to Output Low-Z tHHQX(2) tLZ 7 ns

/HOLD to Output High-Z tHLQZ(2) tHZ 12 ns

Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns

Write Protect Hold Time After /CS High tSHWL(3) 100 ns

/CS High to Power-down Mode tDP(2) 3 µs

/CS High to Standby Mode without Electronic

Signature Read tRES1(2) 3 µs

/CS High to Standby Mode with Electronic

Signature Read tRES2(2) 1.8 µs

Write Status Register Time tW 10 15 ms

Byte Program Time (First Byte) (5) t

BP1 100 150 µs

Additional Byte Program Time (After First Byte) (5) t

BP2 6 12 µs

Page Program Time tPP 1.6 3 ms

Sector Erase Time (4KB) tSE 150 300 ms

Block Erase Time (64KB) tBE 0.8 2 s

Chip Erase Time W25X16

Chip Erase Time W25X32

Chip Erase Time W25X64

tCE 25

100

Notes:

1. Clock high + Clock low must be less than or equal to 1/fC.

2. Value guaranteed by design and/or characterization, not 100% tested in production.

3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.

4. Commercial temperature only applies to Fast Read (FR0 & FR1). Industrial temperature applies to all other parameters.

5. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N

= number of bytes programmed.

W25X16, W25X32, W25X64

Publication Release Date:

- 39 - March 21, 2007, Revision F

12.9 Serial Output Timing

12.10 Input Timing

12.11 Hold Timing

W25X16, W25X32, W25X64

- 40 -

13. PACKAGE SPECIFICATION

13.1 8-Pin SOIC 208-mil (Package Code SS)

MILLIMETERS INCHES

SYMBOL MIN MAX MIN MAX

A 1.75 2.16 0.069 0.085

A1 0.05 0.25 0.002 0.010

A2 1.70 1.91 0.067 0.075

b 0.35 0.48 0.014 0.019

C 0.19 0.25 0.007 0.010

D 5.18 5.38 0.204 0.212

E 7.70 8.10 0.303 0.319

E1 5.18 5.38 0.204 0.212

e 1.27 BSC 0.050 BSC

L 0.50 0.80 0.020 0.031

θ 0o 8

o 0

o 8

y --- 0.10 --- 0.004

Notes:

1. Controlling dimensions: inches, unless otherwise specified.

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.

4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.

W25X16, W25X32, W25X64

Publication Release Date:

- 41 - March 21, 2007, Revision F

13.2 8-Pin PDIP 300-mil (Package Code DA)

1.631.47

0.0640.058

Symbol Min Nom Max Max

Nom

Min

Dimension in inch Dimension in mm

0.060 1.52

0.175 4.45

0.010

0.125

0.016

0.130

0.018

0.135

0.022

3.18

0.41

0.25

3.30

0.46

3.43

0.56

0.008

0.120

0.375

0.010

0.130

0.014

0.140

0.20

3.05

0.25

3.30

0.36

3.56

0.255

0.250

0.245 6.486.35

6.22

9.53

7.62

7.37 7.87

0.3000.290 0.310

2.29 2.54 2.790.090 0.100 0.110

0.360 0.380 9.14 9.65

015

0.045 1.14

0.355

0.335 8.51 9.02

150

Seating Plane

Base Plane

W25X16, W25X32, W25X64

- 42 -

13.3 8-contact 6x5 WSON

W25X16, W25X32, W25X64

Publication Release Date:

- 43 - March 21, 2007, Revision F

13.4 8-contact 6x5 WSON Cont’d.

W25X16, W25X32, W25X64

- 44 -

13.5 16-Pin SOIC 300-mil (Winbond Package Code SF)

MILLIMETERS INCHES

SYMBOL MIN MAX MIN MAX

A 2.36 2.64 0.093 0.104

A1 0.10 0.30 0.004 0.012

b 0.33 0.51 0.013 0.020

C 0.18 0.28 0.007 0.011

D(3) 10.08 10.49 0.397 0.413

E 10.01 10.64 0.394 0.419

E1(3) 7.39 7.59 0.291 0.299

e(2) 1.27 BSC 0.050 BSC

L 0.39 1.27 0.015 0.050

θ 0o 8

o 0

o 8

y --- 0.076 --- 0.003

Notes:

1. Controlling dimensions: inches, unless otherwise specified.

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.

W25X16, W25X32, W25X64

Publication Release Date:

- 45 - March 21, 2007, Revision F

14. ORDERING INFORMATION

(1)

Notes:

1a. Only the 2nd letter is used for the part marking.

1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel

(shape T), when placing orders.

1c. The “W” prefix is not included on the part marking.

W25X16, W25X32, W25X64

- 46 -

Valid Part Numbers and Top Side Marking:

The following table provides the valid part numbers for the 25X16/32/64 SpiFlash Memories. Please

contact Winbond for specific availability by density and package type. Winbond SpiFlash memories

use an 11-digit Product Number for ordering. However, due to limited space, the Top Side Marking on

all packages use an abbreviated 9-digit number.

PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING

16M-bit W25X16VSSIG 25X16VSIG

SOIC-8 208mil 32M-bit W25X32VSSIG 25X32VSIG

16M-bit W25X16VSFIG 25X16VFIG

32M-bit W25X32VSFIG 25X32VFIG

SOIC-16 300mil 64M-bit W25X64VSFIG 25X64VFIG

WSON-8 6x5mm 16M-bit W25X16VZPIG 25X16VPIG

32M-bit W25X32VZEIG 25X32VEIG

WSON-8 8x6mm 64M-bit W25X64VZEIG 25X64VEIG

16M-bit W25X16VDAIZ 25X16VAIZ

32M-bit W25X32VDAIZ 25X32VAIZ

PDIP-8 300mil

64M-bit W25X64VDAIZ 25X64VAIZ

W25X16, W25X32, W25X64

Publication Release Date:

- 47 - March 21, 2007, Revision F

15. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A 02/13/06 New Create

B 06/28/06

1-4, 6, 32-36,

41 & 42

Added W25X64 in the product family. Added

300mil PDIP package. Added 6x5 mm

WSON package. Updated Endurance and

Data Retention table (11.3), ICC’s in DC

Parameter table (11.5 & 11.6). Reduced tPP

(max) from 5mS to 3mS. Changed tSHCH

from 5nS to 0nS. Added byte programming

parameters (tBP1 & tBPn. Added additional

byte programming parameter, tBP2 and

moved multiple byte programming tBPn with

formula to foot note.

C 10/19/06 18, 35, 37 & 45

Changed tCHSH and tSHCH respectively

from 10nS and 0nS to 5nS and 5nS. Modified

the ordering information table to eliminate the

hyphen in the part number. Corrected Write

Enable/Disable text. Change ICC2 from 5uA

to 10uA.. Added footnotes in the ordering

information table. Updated ICC3 specs.

D 2/1/07 4 - 8 & 45 Updated package and ordering information.

E 2/26/07

6-9, 29, 33, 35,

38 & 45

Updated Figure 2.

Updated ICC3 specs.

Added Valid Combinations for ordering info.

Added transient voltage specification.

Removed preliminary designation for 25X16.

Updated typical ratings on erase operations.

F 3/21/07 34, 35, 41 & 46

Updated table 12.3.

Updated ICC3 and ICC5 specs.

Added 300mil DIP package.

added valid part number and marking table.

W25X16, W25X32, W25X64

- 48 -

Preliminary Designation

The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully

characterized. The specifications are subject to change and are not guaranteed. Winbond or an

authorized sales representative should be consulted for current information before using this product.

Trademarks

Winbond and spiFlash are trademarks of Winbond Electronics Corporation.

All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments, airplane

or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, or for other applications intended to support or sustain life. Further more, Winbond

products are not intended for applications wherein failure of Winbond products could result or lead to

a situation wherein personal injury, death or severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Information in this document is provided solely in connection with Winbond products. Winbond

reserves the right to make changes, corrections, modifications or improvements to this document and

the products and services decribed herein at any time, without notice.