‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
8Mb: 512K x 16 Async/Page PSRAM
Features
Advance‡
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Async/Page PSRAM Memory
MT45W512KW16PGA
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/psram/
Features
• Asynchronous and page mode interface
• Random access time: 70ns
•V
CC, VCCQ voltages:
–1.7V–1.95V VCC
–1.7V–3.6V VCCQ
• Page mode read access:
–16-word page size
–Interpage read access: 70ns
–Intrapage read access: 20ns
• Low power consumption:
–Asynchronous READ: <20mA
–Intrapage READ: <15mA
–Standby: 80µA
–Deep power-down: <10µA (TYP @ 25°C)
•Low power features:
–Temperature compensated refresh (TCR)
–On-chip temperature sensor
–Par tial array refresh (PAR)
–Deep power-down (DPD) mode
Notes: 1. Contact factory for availability.
Options Designator
•Configuration
–512K x 16 MT45W512KW16P
•Package
–48-ball VFBGA (green) GA
•Access time
–70ns –70
• Operating temperature range
–Wireless (–30°C to +85°C) WT
–Industrial (–40°C to +85°C)1IT
Figure 1: Ball Assignment – 48-Ball VFBGA
Part Nu mber Example:
MT45W512KW16PGA-70WT
A
B
C
D
E
F
G
H
1 2 3 4 5 6
Top View
(Ball Down)
LB#
DQ8
DQ9
VSSQ
VCCQ
DQ14
DQ15
A18
OE#
UB#
DQ10
DQ11
DQ12
DQ13
NC
A8
A0
A3
A5
A17
NC
A14
A12
A9
A2
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
ZZ#
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
A1
A4
A6
A7
A16
A15
A13
A10
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8Mb: 512K x 16 Async/Page PSRAM
General Description
Advance
General Description
Micron® PSRAM products are high-s peed, CMOS PSRAM memory devices developed for
low-power, portable applications. The MT45W512KW16P is an 8Mb DRAM core device
organized as 512K x 16 bits. These devices include the industry-standard, asynchronous
memory inter fa ce found on other low-power SRAM or PSRAM offerings.
A user-accessible configuration register (CR) defines how the PSRAM device performs
on-chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power up and can be updated at any
time during normal operation.
To ensure seamless operation on an asynchronous memory bus, PSRAM products incor-
porate a transparent self refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
S p ecial attention has been focused on current consumption during self refresh. These
PSRAM products include three system-accessible mechanisms to minimize refresh
current. Temperature-compensated refr esh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The refresh rate decreases at lower
temperatures to minimize curr ent co nsumpt io n during standby. TCR can also be set by
the system for maximum device temperatures of +85°C, +45°C, and +15°C. Setting sleep
enable (ZZ#) to LO W enable s one of two lo w-po wer modes: partial-arr ay re fres h (P A R) or
deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that
contains essential data. DPD halts r efresh operation altoge ther and is used w hen no vital
information is stored in the device. These three refresh mechanisms are accessed
through the CR.
Functional Block Diagram
Figure 2: Functional Block Diagram 512K x 16
Notes: 1. Functional block diagrams illustrate simplified device operation. See truth table, ball
descript ions, and timing diagrams for detai le d information.
A[18:0]
Input/
Output
MUX
and
Buffers
Control
Logic
512K x 16
DRAM
Memory
Array
DQ[7:0]
DQ[15:8]
Address Decode
Logic
LB#
UB#
CE#
WE#
OE#
ZZ#
Configuration
Register (CR)
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8Mb: 512K x 16 Async/Page PSRAM
Ball Descriptions
Advance
Ball Descriptions
Table 1: VFBGA Ball Descriptions
VFBGA Ball
Assignment Symbol Type Description
H1, D3, E4, F4,
F3, G4, G3, H5,
H4, H3, H2, D4,
C4, C3, B4, B3,
A5, A4, A3
A[18:0] Input Address inputs: Inputs for the address accessed during READ or WRITE
operations. The address lines are also used to define the value to be loaded into
the CR.
A6 ZZ# Input Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can enter
one of two low-power modes (DPD or PAR).
B5 CE# Input Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
A2 OE# Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
G5WE#Input
Write enable: Enables WRITE operations when LOW.
A1 LB# Input Lower byte enable: DQ[7:0]
B2 UB# Input Uppe r by te enable: DQ[15:8]
G1, F1, F2, E2,
D2, C2, C1, B1,
G6, F6, F5, E5,
D5, C6, C5, B6
DQ[15:0] Input/
Output Data inputs/outputs.
H6, E3, G2NCNot internally connected.
D6 VCC Supply Device power supply: (1.7V–1.95V) Power supply for device core operation.
E1 VCCQ Supply I/O power supply: (1.7V–3.6V) Power supply for input/output buffers.
E6 VSS Supply VSS must be connected to ground.
D1 VSSQ Supply VSSQ must be connected to ground.
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8Mb: 512K x 16 Async/Page PSRAM
Bus Operations
Advance
Bus Operations
Notes: 1. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated fr om any external influence.
2. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum
standby current.
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in
select mode, only DQ[7:0] are affected. When UB# alone is in the select mode, only DQ[15:8]
are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
Table 2: Bus Operations
Mode Power CE# WE# OE# LB#/UB# ZZ# DQ[15:0]1Notes
Standby Standby H X X X H High-Z 1, 2
Read Active L H L L H Data-out 3, 4
Write Active L L X L H Data-in 3, 5, 4
No operation Idle L X X X H X 4, 2
PAR Partial-array refresh H X X X L High-Z 6
DPD Deep power-down H X X X L High-Z 6
Load
configuration
register
Active L L X X L High-Z
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8Mb: 512K x 16 Async/Page PSRAM
Part Numbering Information
Advance
Part Numbering Information
Micron PSRAM devices are available in several different configurations and densities
(see Figure 3).
Figure 3: Part Number Chart
Valid Part Number Combinations
After building the part number from the part numbering chart, go to the Micron Part
Mark ing Decoder Web site at www.micron.com/products/parametric to verify that the
part number is offered and valid. If the devic e required is not on this list, please contact
the factory.
Device Marking
Due to the size of the package, the Micron standard part number is not printed on the
device. Instead, an abbreviated de vice mark comprised of a five-digit alphanumeric
code is used. The abbreviated device marks are cr oss-re fere nced to the Micron part
numbers at www.micron.com/products/parametric. To view the loc ation of the abbrevi-
ated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,”
available on Micron’s Web site.
MT 45 W 512K W 16 P GA -70 WT ES
Micron Technology
Product Family
45 = PSRAM/CellularRAM® Memory
Operating Core Voltage
W = 1.7V–1.95V
Address Locations
K = Kilobits
Operating Voltage
W = 1.7V–3.6V
Bus Configuration
16 = x16
Read/Write Mode Operation
P = Asynchronous/Page
Package Codes
GA = VFBGA “Green” (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball
Production Status
Blank = Production
ES = Engineering Sample
MS = Mechanical Sample
Operating Temperature
WT = −30°C to +85°C
IT = −40°C to +85°C (contact factory)
Standby Power Options
Blank = Standard
Access/Cycle Time
-70 = 70ns
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8Mb: 512K x 16 Async/Page PSRAM
Functional Description
Advance
Functional Description
In general, the MT45W512KW16P device is a high-density alternative to SRAM and
PSRAM products, popular in low-power, portable applications. The MT45W512KW16P
contains an 8,388,608-bit DRAM core organized as 524,288 addr esses by 16 bits. These
devices include the ind u s try-standard, asynchronous memory interface found on othe r
low-power SRAM or PSRAM offerings. Page mode accesses are also included as a band-
width-enhancing extension to the asynchronous read pr otocol.
Power-Up Initialization
Micron PSRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. In i tial izat ion will loa d the CR with its default setting.
VCC and VCCQ must be applied simultaneously, and when they re ach a stable level abo v e
1.7V, the device will require 150µs to complete its self-initialization process (see
Figur e4). During the initialization period, CE # should r emain HIGH. When initialization
is complete, the device is ready for normal operation.
Figure 4: Power-Up Initialization Timing
Bus Operating Modes
The MT45W512KW16P PSRAM product incorporates the industry-standard, asynchro-
nous interface found on other low-power SRAM or PSRAM offerings. This bus interface
supports asynchronous READ and WRITE operations as well as the bandwidth-
enhancing page mode READ operation. The specific interface that is supported is
defined by the value loaded into the CR.
Asynchronous Mode
Micron PSRAM products power up in the asynchronous operating mode. This mode
uses the industr y-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ
operations (Figure 5 on page 7) are initiated by bringing CE#, OE#, and LB#/UB# LOW
while keeping WE# HIGH. Valid data will be driv en out of the I/Os after the specified
access time has elapsed. WRITE operations (Figure 6 on page 7) occur when CE#, WE#,
and LB#/UB# are driven LO W. During WRITE operatio ns, the level of OE# is a “D on't
Care”; WE# will override OE#. The data to be written will be latched on the rising edge of
CE#, WE#, or LB#/UB# (whichever occurs first). WE# LO W time must be limited to tCEM.
Device ready for
normal operation
Vcc, VccQ = 1.7V tPU
Vcc (MIN)
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8Mb: 512K x 16 Async/Page PSRAM
Bus Operating Modes
Advance
Figure 5: READ Operation
Figure 6: WRITE Operation
ADDRESS VALID
DATA
CE#
DON’T CARE
DATA VALID
OE#
WE#
LB#/UB#
tRC = READ Cycle Time
ADDRESS
ADDRESS VALID
DATA
CE#
DON’T CARE
DATA VALID
OE#
WE#
LB#/UB#
tWC = WRITE Cycle Time
< tCEM
ADDRESS
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8Mb: 512K x 16 Async/Page PSRAM
Bus Operating Modes
Advance
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
performed. Adjacent addresses can then be quickly read by simply changing the low-
order address . Addresses A[3:0] are used to determine the members of the 16-address
PSRAM page. Any change in addresses A[4] or higher will initiate a new tAA access.
Figure 7 shows the timing diagram for a page mode access.
Page mo de takes advantage of the fact that adjacent addresses can be read in a shorter
period of time than random addresses. WRITE operations do not include comparable
page mode functionality.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than tCEM.
Figure 7: Page READ Operation
LB#/UB# Operation
The lower byte (LB#) enable and upper byte (UB#) enable signals allow for byte-wide
data transfers. During READ operations, enabled bytes are driven onto the DQs. The
DQs associated with a disabled byte ar e put into a High-Z state during a READ opera-
tion. During WRITE operations, any disabled b ytes will not be transferr ed to the memory
array and the internal value will remain unchanged. During a WRITE cycle, the data to
be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will appear
to be deselect e d, it remains in an active mode as long as CE# is LOW.
DATA
C
E#CE#
OE#
WE#
LB#/UB#
ADDRESS
ADDRESS[0]
D[1] D[2] D[3]
tAA tAPA tAPA tAPA
D[0]
< tCEM
ADDRESS
[1] ADDRESS
[2] ADDRESS
[3]
DON'T CARE
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8Mb: 512K x 16 Async/Page PSRAM
Low-Power Operation
Advance
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation on the full array. Standby operation occurs when
CE# and ZZ# are HIGH.
The device will enter a reduced power state during READ and WRITE operations where
the address and control inputs remain static for an extended period of time. This mode
will continue until a change occurs to the address or control inputs.
Temperature-Compensated Refresh (TCR)
TCR allows for adequate refresh at different temperatures. This PSRAM device includes
an on-chip temperature sensor. When the sensor is enabl ed , it continually adjusts the
refresh rate accordin g to the operating temperature. The on-chip sensor is enabled by
default.
Three fixed refresh rates are also available, corresponding to temperature thre sholds of
+15°C, +45°C, and +85°C. The setting selected must be for a temperature higher than the
case temperatur e of the PSRAM device . If the case temperature is +35°C, the system can
minimize self refresh current consumption by selecting the +45°C setting. Using the
+15°C setting in the same environment would result in an inadequate refr esh rate and
cause data corruption.
Partial-Array Refresh (PAR)
PAR restricts refresh operation to a portion of the total memory array. This feature
enables the system to reduce refresh current by only refreshing that part of the memory
array that is absolutely necessary. The refresh options are full array, one-half array, one-
quarter array, one-eighth array, or none of the array. Data stored in addresses not
receiving refresh will become corrupted. The mapping of these partitions can start at
either the beginning or the end of the addr ess map (Table 3 on page 13). READ and
WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH
(CR[4] = 1). P AR can be initiated by bringing the ZZ# ball to the LOW state for longer than
10µs. Returning ZZ# to HIGH will cause an exit from PAR and the entire array wi ll be
immediately available for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software acce ss sequence (see “Software
Access to the Configuration Register” on page 11). PAR is enabled immediately upon
setting CR[4] to “1” using this method. However , using softwar e access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ#
continues to enable WRITEs to the CR. This functional change persists until the next
time the device is powered up (see Figure 8 on page 10).
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8Mb: 512K x 16 Async/Page PSRAM
Low-Power Operation
Advance
Figure 8: Software Access PAR Functionality
Deep Power-Down (DPD) Operation
DPD operation disables all refresh-related activity. This mode is used when the system
does not re quire the storage pro vid ed b y the PSRAM device . Any stored data will become
corrupted when DPD is enter ed. When refresh activity has been re-enabled, the PSRAM
device will require 150µs to perform an initialization procedure before normal opera-
tions can resume. READ and WRITE operations are ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150µs initialization process. During
this 150µs period, the current consumption will be higher than the specified standby
levels but consi derably lower than the active current specification.
Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has
been set HIGH (CR[4] = 1).
The device should not be put into DPD using CR software access.
NO
YES
Power-Up
To enable PAR,
bring ZZ# LOW
for 10µs.
Change to ZZ#
functionality.
PAR permanently
enabled,
independent of
ZZ# level.
Software
LOAD
executed?
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8Mb: 512K x 16 Async/Page PSRAM
Configuration Register (CR) Operation
Advance
Configuration Register (CR) Operation
The CR defines how the PSRAM device performs its transparent self refresh. Altering the
refr esh parameters can dramatically reduce current consumption during standby mode .
Page mode control is also embedded into the CR. This r egister can be updated any time
the device is oper ating in a standby state. F i gure 12 on page 13 describes the control bits
used in the CR. At power-up, the CR is set to 0010h.
Access Using ZZ#
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-
to-LOW transition (see Fi gur e 9). The values placed on ad dr esses A[18:0] are latched into
the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t
Care.” Access using ZZ# is WRITE only.
Figure 9: Load Configuration Register Operation
Software Access to the Configuration Register
The contents of the CR can either be read or modified using a software sequence. The
nature of this access mechanism may eliminate the need for the ZZ# ball.
If the software mechanism is used, ZZ# can simply be tied to VCCQ. The port line typi-
cally used for ZZ# control purposes will no longer be required. However, ZZ# should not
be tied to VCCQ if the s ystem will use DPD; DPD cannot be enabled or disabled usi ng the
software access sequen ce.
The CR is loaded using a four -step sequence consisting of two READ operations foll o wed
b y two WRITE operations (see Figur e10 on page 12). The read s equence i s virtually iden-
tical except that an asynchronous READ is performed during the fourth operation (see
Figure 11 on page 12). Note that a third READ cycle of the highes t address will cancel the
access sequence until a different address is read.
The address used during all READ and WRITE operations is the highest address of the
PSRAM device being accessed (7FFFFh for 8Mb); the content of this address is not
changed by using this sequence. The data bus is used to transfer data into or out of bits
15–0 of the CR.
Writing to the CR using the software sequence modifies the function of the ZZ# ball.
Once the softwar e sequence loads the CR, the level of the ZZ# ball no longer enables PAR
operation. PAR operation will be updated whenever the software sequence loads a new
value into the CR. This ZZ# functionality will continue until the next time the device is
po wer ed up. The operation of the ZZ# ball is no t affected if the softwar e sequ ence is only
used to re ad the contents of the CR. The use of the software sequence does not affect the
ability to perform the standard (ZZ#-controlled) method of loading the CR.
ADDRESS VALID
CE#
ZZ#
WE# t < 500ns
ADDRESS
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8Mb: 512K x 16 Async/Page PSRAM
Configuration Register (CR) Operation
Advance
Figure 10: Software Access Load Configuration Register
Figure 11: Software Access Read Configuration Register
ADDRESS
(MAX) ADDRESS
(MAX) ADDRESS
(MAX)
XXXXh XXXXh CR VALUE
IN
ADDRESS
CE#
OE#
WE#
LB#/UB#
DATA
DON'T CARE
READ READ WRITE WRITE
ADDRESS
(MAX)
0000h
ADDRESS
(MAX) ADDRESS
(MAX) ADDRESS
(MAX)
XXXXh XXXXh CR VALUE
OUT
ADDRESS
CE#
OE#
WE#
LB#/UB#
DATA
DON'T CARE
READ READ WRITE READ
ADDRESS
(MAX)
0000h
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8Mb: 512K x 16 Async/Page PSRAM
Configuration Register (CR) Operation
Advance
Figure 12: Configuration Register Bit Mapping
Partial Array Refresh (CR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the system to reduce current by only refreshing that part of the memory
array required by the host system. The refr esh options ar e: full array, one-half array, one-
quarter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either th e be g inni ng or th e end of the address map (see Table 3).
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
The sleep mode bit determines which low-power mode is to be entered when ZZ# is
driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is
enabled. PAR can also be enabled d irectly by wri t ing to the CR using the software access
sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or
disabled using the software access sequence; this should only be done using ZZ# to
access the CR.
Table 3: 8Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density
0 0 0 Full die 000000h–07FFFFh 512K x 16 8Mb
0 0 1 One-half of die 000000h–03FFFFh 256K x 16 4Mb
0 1 0 One-quarter of die 000000h–01FFFFh 128K x 16 2Mb
0 1 1 One-eighth of die 000000h–00FFFFh 64K x 16 1Mb
1 0 0 None of die 0 0 Meg x 16 0Mb
1 0 1 One-half of die 40000h–07FFFFh 256K x 16 4Mb
1 1 0 One-quarter of die 60000h–07FFFFh 128K x 16 2Mb
1 1 1 One-eighth of die 70000h–07FFFFh 64K x 16 1Mb
PAR
A4 A3 A2
A1
A0 Address Bus
41
2
30
RESERVED
6 5
A5
0
1
Sleep Mode
DPD Enabled
PAR Enabled (default)
CR[4]
TCR
CR[6] CR[5]
11
1
1
00
0
0
Maximum Case Temp.
+85˚C
Internal sensor (default)
+45˚C
+15˚C
A6
18–8
RESERVED
A[18:8]
CR[1] CR[0] PAR Coverage
CR[2]
SLEEP
Must be set to “0”All must be set to “0”
A7
7
PAGE
0
1
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enabled
CR[7] Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 14 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Configuration Register (CR) Operation
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DPD operation disables all refresh-related activity. This mode will be used when the
system does not require the storage provided by the PSRAM device. Any stored data will
become corrupted when DPD is en abled. When r efresh activity has been r e-enabled, the
PSRAM device will require 150µs to perform an initializatio n procedure before normal
operation can resume. DPD should not be enabled using CR software access.
TCR (CR[6:5]) Default = On-Chip Temperature Sensor
This PSRAM device includes an on-chip temperature sensor that automatically adjusts
the refresh rate according to the operating temperature. The on-chip TCR is enabled by
clearing both of the TCR bits in the r efresh configuration register (CR[6:5] = 00b). Any
other TCR setting enables a fixed refresh rate. When the on-chip temperature sensor is
enabled, the device continually adjusts the refresh rate according to the operating
temperature.
The TCR bits also allow for adequate fixed rate refresh at three different temperature
thresholds (+ 15 °C, +4 5°C, and +85°C) . The setting selected must be for a temperature
higher than the case temperature of the PSRAM device. If the case temperature is
+35°C, the system can minimize self-refresh current consumption by selecting the
+45°C setting. Using the +15°C setting in the same environment would result in an
inadequate refresh rate and cause data corruption.
Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations are
enabled. In the power-up default state, page mode is disabled.
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 15 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Electrical Characteristics
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Electrical Characteristics
S tresses greater than those listed in Table 4 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this spec ifi cat ion is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reli ability.
Notes: 1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
2. Input signals ma y undershoot to VSS - 1.0V for periods less than 2ns during transitions
3. This parameter is specified with the outputs disabled to avoid external loading effects. The
user must add the current required to drive output capacitance expected in the actual sys-
tem.
4. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. In order to
achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly
higher for up to 500ms after power-up or when entering standby mode.
Table 4: Absolute Maximum Ratings
Parameter Rating
Voltage to any ball except VCC, VCCQ relative to VSS –0.50V to (4.0V or VCCQ + 0.3V, whichever is less)
Voltage on VCC supply relative to VSS –0.2V to 2.45V
Voltage on VCCQ supply relative to VSS –0.2V to 4.0V
Storage temperature –55°C to 150°C
Operating temperature (case)
Wireless
Industrial –30°C to 85°C
–40°C to 85°C
Soldering temperature and time
10 seconds (solder ball only) 260°C
Table 5: Electrical Characteristics and Operating Conditions
Wireless Temperature (–30ºC ≤ TC ≤ +85 ºC), Industrial Temperature (–40ºC < TC < +85ºC)
Description Conditions Symbol Min Max Units Notes
Supply voltage VCC 1.7 1.95 V
I/O supply voltage VCCQ1.73.6V
Input high volt ag e VIH 1.4 VCCQ + 0.2 V 1
Input low voltage VIL –0.2 0.4 V 2
Output high voltage IOH = –0.2mA VOH 0.8 VCCQV
Output low voltage IOL = 0.2mA VOL 0.2 VCCQV
Input leakage current VIN = 0 to VCCQILI 1μA
Output leakage current OE# = VIH or
Chip Disabled ILO 1μA
Operating Current
Asynchronous random
READ/WRITE VIN = VCCQ or 0V
Chip Enabled, IOUT = 0 ICC1 –70 20 mA 3
Asynchronous page READ ICC1P –70 15 mA 3
Standby current VIN = VCCQ or 0V
CE# = VCCQISB 80 μA4
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 16 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Electrical Characteristics
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Typical Standby Currents
Figure 13 refers to the typical standby current s for the MT45W 512KW16P device. The
values shown in Figure13 are measured with the on-chip temperature sensor control
enabled (default setting).
Figure 13: Typical Refresh Current vs. Temperature (ITCR)
Notes: 1. Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature
sensor enabled.
Temperature (°C)
PAR FULL
PAR 1/2,
PAR 1/4,
PAR 1/8
PAR 0
0
5
10
15
20
25
30
35
40
45
-45C
-35C
-25C
-15C
-5C
5C
15C
25C
35C
45C
55C
65C
75C
85C
I
SB
(µA)
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 17 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Electrical Characteristics
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Notes: 1. These parameters are verified in device characterization and are not 100 percent tested.
Figure 14: AC Input/Output Reference Waveform
Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall
times (10% to 90%) < 1.6ns.
2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ,
the input test point may not be shown to scale.
3. Output timing ends at VCCQ/2.
Figure 15: Output Load Circuit
Table 6: DPD Specifications and Conditions
Description Conditions Symbol TYP Units
Deep power-down VIN = VCCQ or 0V; +25°C
ZZ# = 0V
CR[4] = 0
IZZ 10 µA
Table 7: Capaci tance Specifications and C onditions
Description Conditions Symbol Min Max Units Notes
Input capacitance TC = +25ºC; f = 1 MHz;
VIN = 0V CIN 2.0 6.5 pF 1
Input/output capacitance (DQ) CIO 3.0 6.5 pF 1
Output
Test Points
Input
1
V
CC
Q
V
SS
Q
V
CC
Q/2
3
V
CC
/2
2
DUT VccQ/2
30pF
Test Point
50
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 18 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Electrical Characteristics
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Notes: 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 17. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 17. The Low-
Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either
VOH or VOL.
3. Page mode enabled only.
Table 8: READ Cycle Timing Requirements
Parameter Symbol
70ns
Units NotesMin Max
Address access time tAA 70 ns
Page access time tAPA 20 ns
LB#/UB# access time tBA 70 ns
LB#/UB# disable to High-Z output tBHZ 8 ns 1
LB#/UB# enable to Low-Z output tBLZ 10 ns 2
Maximum CE# pulse width tCEM 8 µs 3
Chip select access time tCO70ns
Chip disable to High-Z output tHZ 8 ns 1
Chip enable to Low-Z output tLZ 10 ns 1
Output enable to valid output tOE 20 ns
Output hold from address change tOH 5 ns
Output disable to High-Z output tOHZ 8 ns 1
Output enable to Low-Z output tOLZ 5 ns 1
Page cycle time tPC20 ns
READ cycle time tRC70 ns
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 19 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Electrical Characteristics
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Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 17. The Low-
Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either
VOH or VOL.
2. Low-Z to High-Z timings are teste d with the circuit shown in Figure 15 on page 17. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
3. WE# LOW time must be limited to tCEM (8µs).
Table 9: WRITE Cycle Timing Requirements
Parameter Symbol
70ns
Units NotesMin Max
Address setup time tAS 0 ns
Address valid to end of write tAW 70 ns
Byte select to end of write tBW 70 ns
CE# HIGH time during write tCPH 5 ns
Chip enable to end of write tCW70 ns
Data hold from write time tDH 0 ns
Data write setup time tDW 23 ns
Chip enable to Low-Z output tLZ 10 ns 1
End write to Low-Z output tOW 5 ns 1
WRITE cycle time tWC 70 ns
WRITE to High-Z output tWHZ 8 ns 2
WRITE pulse width tWP 46 ns 3
WRITE pulse width HIGHtWPH 10 ns
WRITE recovery time tWR 0 ns
Table 10: Load Configuration Register Timing Requirements
Description Symbol
70ns
Units Min Max
Address setup time tAS 0 ns
Address valid to end of write tAW 70 ns
Chip deselect to ZZ# LOW tCDZZ 5 ns
Chip enable to end of write tCW70 ns
WRITE cycle time tWC70 ns
WRITE pulse width tWP 40 ns
WRITE recovery time tWR 0 ns
ZZ# LOW to WE# LOW tZZWE 10 500 ns
Table 11: DPD Timing Requirements
Description Symbol
70ns
Units Min Max
Chip deselect to ZZ# LOW tCDZZ 5 ns
DPD recovery tR 150 µs
Minimum ZZ# pulse width tZZ (MIN) 10 µs
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 20 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Timing Diagrams
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Timing Diagrams
Figure 16: Power-Up Initialization Period
Figure 17: Load Configuration Register
Figure 18: Deep Power-Down – Entry/Exit
Table 12: Initia lization Timing Parameters
Parameter Symbol
70ns
UnitsMin Max
Initialization period (required before normal operations) tPU 150 µs
Device ready for
normal operation
Vcc, VccQ = 1.7V tPU
Vcc (MIN)
ADDRESS
ZZ#
tWC
tAW tWR
tAS
CE#
LB#/UB#
tZZWE
DON’T CARE
WE#
tWP
tCDZZ
OPCODE
tCW
OE#
ZZ#
CE#
tZZ (MIN)
DON’T CARE
tCDZZ
tR
Device ready for
normal operation
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8Mb: 512K x 16 Async/Page PSRAM
Timing Diagrams
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Figure 19: Single READ Operation (WE# = VIH)
Figure 20: Page Mode READ Operation (WE# = VIH)
ADDRESS
OE#
tRC
tAA
DATA-OUT
CE#
LB#/UB#
tOLZ
tLZ
DON’T CARE UNDEFINED
High-Z High-Z
DATA VALID
tOHZ
tBA tBHZ
tHZ
tBLZ
tCO
tOE
ADDRESS VALID
ADDRESS
A[18:4]
OE#
tAA
DATA-OUT
CE#
LB#/UB#
tOLZ
tLZ
DON’T CARE UNDEFINED
High-Z High-Z
DATA
VALID DATA
VALID DATA
VALID DATA
VALID
tOHZ
tBA tBHZ
tHZ
tCEM
tBLZ
tCO
ADDRESS
A[3:0]
tRC
tOH
tPC
ADDRESS VALID
tAPA
tOE
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 22 ©2006 Micron Technology, Inc. All rights reserved.
8Mb: 512K x 16 Async/Page PSRAM
Timing Diagrams
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Figure 21: WRITE Cycle (WE# Control)
Figure 22: WRITE Cycle (CE# Control)
ADDRESS
WE#
tWC
tAW tWR
DATA-IN
CE#
LB#/UB#
tBW
tWHZ tOW
tDH
tDW
tAStWP tWPH
DON’T CARE
High-Z
DATA-OUT
DATA VALID
tCW
OE#
ADDRESS VALID
ADDRESS
CE#
LB#/UB#
OE#
WE#
DATA-IN
Valid Address
tWC
Valid Input
tAW
Don’t Care
tWR
tCWtCPH
DATA-OUT
tWHZ
tBW
tDW
tLZ
tDH
tAS
tWP
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
High-Z
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8Mb: 512K x 16 Async/Page PSRAM
Timing Diagrams
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Figure 23: WRITE Cycle (LB#/UB# Control)
ADDRESS
WE#
tWC
tAW tWR
DATA-IN
CE#
LB#/UB#
tBW
tWHZ
tDH
tAS
tDW
DON’T CARE
DATA-OUT
DATA VALID
ADDRESS VALID
tCW
OE#
High-Z
tOW
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-49 92
Micron, the M logo, and the Micron logo are trademarks of Micron Technology , Inc. All other trademarks ar e the property of
their respective owners.
Advance: This data sheet contains initial descriptions of products still under development.
8Mb: 512K x 16 Async/Page PSRAM
Package Dimensions
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8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 24 ©2006 Micron Technology, Inc. All rights reserved.
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Package Dimensions
Figure 24: 48-Ball VFBGA
Notes: 1. All dimensions in millimeters, MAX/MIN or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusio n is
0.25mm per side.
3. The MT45W512KW16P uses “green” packa ging.
BALL A1 ID
1.00 MAX
4.00 ±0.05
3.00 ±0.051.875
6.00 ±0.10
C
L
C
L
SOLDER BALL MATERIAL:
96.5% Sn, 3% Ag, 0.5% Cu
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE MATERIAL: PLASTIC LAMINATE
0.75
TYP
0.75 TYP
8.00 ±0.10
5.25
2.625
BALL A1
BALL A1 ID
3.75
0.70 ±0.05
SEATING
PLANE
0.10 A
A
BALL A6
DIMENSIONS APPLY
TO SOLDER BALLS
POST REFLOW.
PRE-REFLOW BALL
DIAMETER IS 0.35
ON A 0.30 SMD
BALL PAD.
48X Ø0.37
