Advance 8Mb: 512K x 16 Async/Page PSRAM Features Async/Page PSRAM Memory MT45W512KW16PGA For the latest data sheet, refer to Micron's Web site: www.micron.com/products/psram/ Features Figure 1: * Asynchronous and page mode interface * Random access time: 70ns * VCC, VCCQ voltages: - 1.7V-1.95V VCC - 1.7V-3.6V VCCQ * Page mode read access: - 16-word page size - Interpage read access: 70ns - Intrapage read access: 20ns * Low power consumption: - Asynchronous READ: <20mA - Intrapage READ: <15mA - Standby: 80A - Deep power-down: <10A (TYP @ 25C) * Low power features: - Temperature compensated refresh (TCR) - On-chip temperature sensor - Partial array refresh (PAR) - Deep power-down (DPD) mode Options Designator 1 2 3 4 5 6 A LB# OE# A0 A1 A2 ZZ# B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 NC Top View (Ball Down) * Configuration MT45W512KW16P - 512K x 16 * Package GA - 48-ball VFBGA (green) * Access time -70 - 70ns * Operating temperature range WT - Wireless (-30C to +85C) IT - Industrial (-40C to +85C)1 Notes: 1. Contact factory for availability. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN Ball Assignment - 48-Ball VFBGA Part Number Example: MT45W512KW16PGA-70WT 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. Advance 8Mb: 512K x 16 Async/Page PSRAM General Description General Description Micron(R) PSRAM products are high-speed, CMOS PSRAM memory devices developed for low-power, portable applications. The MT45W512KW16P is an 8Mb DRAM core device organized as 512K x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings. A user-accessible configuration register (CR) defines how the PSRAM device performs on-chip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power up and can be updated at any time during normal operation. To ensure seamless operation on an asynchronous memory bus, PSRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Special attention has been focused on current consumption during self refresh. These PSRAM products include three system-accessible mechanisms to minimize refresh current. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature. The refresh rate decreases at lower temperatures to minimize current consumption during standby. TCR can also be set by the system for maximum device temperatures of +85C, +45C, and +15C. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are accessed through the CR. Functional Block Diagram Figure 2: Functional Block Diagram 512K x 16 A[18:0] Address Decode Logic 512K x 16 DRAM Memory Array Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] Configuration Register (CR) CE# WE# OE# UB# Control Logic LB# ZZ# Notes: PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 1. Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Ball Descriptions Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol Type H1, D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4, A3 A6 A[18:0] Input Address inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. ZZ# Input B5 CE# Input A2 OE# Input G5 A1 B2 G1, F1, F2, E2, D2, C2, C1, B1, G6, F6, F5, E5, D5, C6, C5, B6 H6, E3, G2 D6 E1 E6 D1 WE# LB# UB# DQ[15:0] Input Input Input Input/ Output Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can enter one of two low-power modes (DPD or PAR). Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Enables WRITE operations when LOW. Lower byte enable: DQ[7:0] Upper byte enable: DQ[15:8] Data inputs/outputs. NC VCC VCCQ VSS VSSQ PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN Supply Supply Supply Supply Description Not internally connected. Device power supply: (1.7V-1.95V) Power supply for device core operation. I/O power supply: (1.7V-3.6V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Bus Operations Bus Operations Table 2: Bus Operations Mode Standby Read Write No operation PAR DPD Load configuration register Power CE# WE# OE# LB#/UB# ZZ# DQ[15:0]1 Notes Standby Active Active Idle Partial-array refresh Deep power-down Active H L L L H H L X H L X X X L X L X X X X X X L L X X X X H H H H L L L High-Z Data-out Data-in X High-Z High-Z High-Z 1, 2 3, 4 3, 5, 4 4, 2 6 6 Notes: PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 1. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are internally isolated from any external influence. 2. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current. 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in select mode, only DQ[7:0] are affected. When UB# alone is in the select mode, only DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os. 6. DPD is enabled when configuration register bit CR[4] is "0"; otherwise, PAR is enabled. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Part Numbering Information Part Numbering Information Micron PSRAM devices are available in several different configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 W 512K W 16 P GA -70 Micron Technology WT ES Production Status Blank = Production Product Family ES = Engineering Sample 45 = PSRAM/CellularRAM(R) Memory MS = Mechanical Sample Operating Core Voltage Operating Temperature W = 1.7V-1.95V WT = -30C to +85C IT = -40C to +85C (contact factory) Address Locations Standby Power Options K = Kilobits Blank = Standard Operating Voltage W = 1.7V-3.6V Access/Cycle Time Bus Configuration -70 = 70ns 16 = x16 Read/Write Mode Operation P = Asynchronous/Page Package Codes GA = VFBGA "Green" (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball Valid Part Number Combinations After building the part number from the part numbering chart, go to the Micron Part Marking Decoder Web site at www.micron.com/products/parametric to verify that the part number is offered and valid. If the device required is not on this list, please contact the factory. Device Marking Due to the size of the package, the Micron standard part number is not printed on the device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at www.micron.com/products/parametric. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, "Product Mark/Label," available on Micron's Web site. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Functional Description Functional Description In general, the MT45W512KW16P device is a high-density alternative to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W512KW16P contains an 8,388,608-bit DRAM core organized as 524,288 addresses by 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization Micron PSRAM products include an on-chip voltage sensor that is used to launch the power-up initialization process. Initialization will load the CR with its default setting. VCC and VCCQ must be applied simultaneously, and when they reach a stable level above 1.7V, the device will require 150s to complete its self-initialization process (see Figure 4). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 4: Power-Up Initialization Timing Vcc (MIN) Vcc, VccQ = 1.7V tPU Device ready for normal operation Bus Operating Modes The MT45W512KW16P PSRAM product incorporates the industry-standard, asynchronous interface found on other low-power SRAM or PSRAM offerings. This bus interface supports asynchronous READ and WRITE operations as well as the bandwidthenhancing page mode READ operation. The specific interface that is supported is defined by the value loaded into the CR. Asynchronous Mode Micron PSRAM products power up in the asynchronous operating mode. This mode uses the industry-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ operations (Figure 5 on page 7) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 6 on page 7) occur when CE#, WE#, and LB#/UB# are driven LOW. During WRITE operations, the level of OE# is a "Don't Care"; WE# will override OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited to tCEM. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Bus Operating Modes Figure 5: READ Operation CE# OE# WE# ADDRESS ADDRESS VALID DATA DATA VALID LB#/UB# tRC = READ Cycle Time DON'T CARE Figure 6: WRITE Operation CE# OE# < tCEM WE# ADDRESS ADDRESS VALID DATA DATA VALID LB#/UB# tWC = WRITE Cycle Time DON'T CARE PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Bus Operating Modes Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed. Adjacent addresses can then be quickly read by simply changing the loworder address. Addresses A[3:0] are used to determine the members of the 16-address PSRAM page. Any change in addresses A[4] or higher will initiate a new tAA access. Figure 7 shows the timing diagram for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. Figure 7: Page READ Operation < tCEM CE# OE# WE# ADDRESS ADDRESS[0] tAA DATA ADDRESS ADDRESS ADDRESS [1] [2] [3] tAPA tAPA tAPA D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE LB#/UB# Operation The lower byte (LB#) enable and upper byte (UB#) enable signals allow for byte-wide data transfers. During READ operations, enabled bytes are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will appear to be deselected, it remains in an active mode as long as CE# is LOW. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Low-Power Operation Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH. The device will enter a reduced power state during READ and WRITE operations where the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Temperature-Compensated Refresh (TCR) TCR allows for adequate refresh at different temperatures. This PSRAM device includes an on-chip temperature sensor. When the sensor is enabled, it continually adjusts the refresh rate according to the operating temperature. The on-chip sensor is enabled by default. Three fixed refresh rates are also available, corresponding to temperature thresholds of +15C, +45C, and +85C. The setting selected must be for a temperature higher than the case temperature of the PSRAM device. If the case temperature is +35C, the system can minimize self refresh current consumption by selecting the +45C setting. Using the +15C setting in the same environment would result in an inadequate refresh rate and cause data corruption. Partial-Array Refresh (PAR) PAR restricts refresh operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are full array, one-half array, onequarter array, one-eighth array, or none of the array. Data stored in addresses not receiving refresh will become corrupted. The mapping of these partitions can start at either the beginning or the end of the address map (Table 3 on page 13). READ and WRITE operations are ignored during PAR operation. The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated by bringing the ZZ# ball to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause an exit from PAR and the entire array will be immediately available for READ and WRITE operations. Alternatively, PAR can be initiated using the CR software access sequence (see "Software Access to the Configuration Register" on page 11). PAR is enabled immediately upon setting CR[4] to "1" using this method. However, using software access to write to the CR alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ# continues to enable WRITEs to the CR. This functional change persists until the next time the device is powered up (see Figure 8 on page 10). PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Low-Power Operation Figure 8: Software Access PAR Functionality Power-Up To enable PAR, bring ZZ# LOW for 10s. NO Software LOAD executed? YES Change to ZZ# functionality. PAR permanently enabled, independent of ZZ# level. Deep Power-Down (DPD) Operation DPD operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the PSRAM device. Any stored data will become corrupted when DPD is entered. When refresh activity has been re-enabled, the PSRAM device will require 150s to perform an initialization procedure before normal operations can resume. READ and WRITE operations are ignored during DPD operation. The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is initiated by bringing ZZ# to the LOW state for longer than 10s. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150s initialization process. During this 150s period, the current consumption will be higher than the specified standby levels but considerably lower than the active current specification. Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using CR software access. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Configuration Register (CR) Operation Configuration Register (CR) Operation The CR defines how the PSRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the CR. This register can be updated any time the device is operating in a standby state. Figure 12 on page 13 describes the control bits used in the CR. At power-up, the CR is set to 0010h. Access Using ZZ# The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGHto-LOW transition (see Figure 9). The values placed on addresses A[18:0] are latched into the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are "Don't Care." Access using ZZ# is WRITE only. Figure 9: Load Configuration Register Operation ADDRESS ADDRESS VALID CE# WE# t < 500ns ZZ# Software Access to the Configuration Register The contents of the CR can either be read or modified using a software sequence. The nature of this access mechanism may eliminate the need for the ZZ# ball. If the software mechanism is used, ZZ# can simply be tied to VCCQ. The port line typically used for ZZ# control purposes will no longer be required. However, ZZ# should not be tied to VCCQ if the system will use DPD; DPD cannot be enabled or disabled using the software access sequence. The CR is loaded using a four-step sequence consisting of two READ operations followed by two WRITE operations (see Figure 10 on page 12). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 11 on page 12). Note that a third READ cycle of the highest address will cancel the access sequence until a different address is read. The address used during all READ and WRITE operations is the highest address of the PSRAM device being accessed (7FFFFh for 8Mb); the content of this address is not changed by using this sequence. The data bus is used to transfer data into or out of bits 15-0 of the CR. Writing to the CR using the software sequence modifies the function of the ZZ# ball. Once the software sequence loads the CR, the level of the ZZ# ball no longer enables PAR operation. PAR operation will be updated whenever the software sequence loads a new value into the CR. This ZZ# functionality will continue until the next time the device is powered up. The operation of the ZZ# ball is not affected if the software sequence is only used to read the contents of the CR. The use of the software sequence does not affect the ability to perform the standard (ZZ#-controlled) method of loading the CR. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Configuration Register (CR) Operation Figure 10: Software Access Load Configuration Register ADDRESS READ READ WRITE WRITE ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) XXXXh XXXXh 0000h CR VALUE IN CE# OE# WE# LB#/UB# DATA DON'T CARE Figure 11: Software Access Read Configuration Register ADDRESS READ READ WRITE READ ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) XXXXh XXXXh 0000h CE# OE# WE# LB#/UB# DATA CR VALUE OUT DON'T CARE PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Configuration Register (CR) Operation Figure 12: Configuration Register Bit Mapping A7 A[18:8] 18-8 RESERVED 7 PAGE A6 6 A4 A5 5 TCR 4 3 SLEEP RESERVED All must be set to "0" CR[7] A3 Must be set to "0" 1 2 A0 Address Bus 0 PAR CR[2] CR[1] CR[0] PAR Coverage 0 0 0 Full array (default) 0 0 1 Bottom 1/2 array 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array Maximum Case Temp. 1 0 1 Top 1/2 array Page Mode Enable/Disable 0 Page Mode Disabled (default) 1 Page Mode Enabled CR[6] CR[5] A1 A2 1 1 +85C 1 1 0 Top 1/4 array 0 0 Internal sensor (default) 1 1 1 Top 1/8 array 0 1 +45C 1 0 +15C CR[4] Sleep Mode 0 DPD Enabled 1 PAR Enabled (default) Partial Array Refresh (CR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the system to reduce current by only refreshing that part of the memory array required by the host system. The refresh options are: full array, one-half array, onequarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 3). Table 3: 8Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-07FFFFh 000000h-03FFFFh 000000h-01FFFFh 000000h-00FFFFh 0 40000h-07FFFFh 60000h-07FFFFh 70000h-07FFFFh 512K x 16 256K x 16 128K x 16 64K x 16 0 Meg x 16 256K x 16 128K x 16 64K x 16 8Mb 4Mb 2Mb 1Mb 0Mb 4Mb 2Mb 1Mb Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled The sleep mode bit determines which low-power mode is to be entered when ZZ# is driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can also be enabled directly by writing to the CR using the software access sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or disabled using the software access sequence; this should only be done using ZZ# to access the CR. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Configuration Register (CR) Operation DPD operation disables all refresh-related activity. This mode will be used when the system does not require the storage provided by the PSRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the PSRAM device will require 150s to perform an initialization procedure before normal operation can resume. DPD should not be enabled using CR software access. TCR (CR[6:5]) Default = On-Chip Temperature Sensor This PSRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The on-chip TCR is enabled by clearing both of the TCR bits in the refresh configuration register (CR[6:5] = 00b). Any other TCR setting enables a fixed refresh rate. When the on-chip temperature sensor is enabled, the device continually adjusts the refresh rate according to the operating temperature. The TCR bits also allow for adequate fixed rate refresh at three different temperature thresholds (+15C, +45C, and +85C). The setting selected must be for a temperature higher than the case temperature of the PSRAM device. If the case temperature is +35C, the system can minimize self-refresh current consumption by selecting the +45C setting. Using the +15C setting in the same environment would result in an inadequate refresh rate and cause data corruption. Page Mode READ Operation (CR[7]) Default = Disabled The page mode operation bit determines whether page mode READ operations are enabled. In the power-up default state, page mode is disabled. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Electrical Characteristics Electrical Characteristics Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 4: Absolute Maximum Ratings Parameter Rating -0.50V to (4.0V or VCCQ + 0.3V, whichever is less) -0.2V to 2.45V -0.2V to 4.0V -55C to 150C Voltage to any ball except VCC, VCCQ relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage temperature Operating temperature (case) Wireless Industrial -30C to 85C -40C to 85C Soldering temperature and time 10 seconds (solder ball only) Table 5: 260C Electrical Characteristics and Operating Conditions Wireless Temperature (-30C TC +85 C), Industrial Temperature (-40C < TC < +85C) Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Operating Current Asynchronous random READ/WRITE Asynchronous page READ Standby current Notes: PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN IOH = -0.2mA IOL = 0.2mA VIN = 0 to VCCQ OE# = VIH or Chip Disabled VIN = VCCQ or 0V Chip Enabled, IOUT = 0 VIN = VCCQ or 0V CE# = VCCQ Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO Min Max Units 1.7 1.7 1.4 -0.2 0.8 VCCQ 1.95 3.6 VCCQ + 0.2 0.4 0.2 VCCQ 1 1 V V V V V V A A Notes 1 2 ICC1 -70 20 mA 3 ICC1P ISB -70 15 80 mA A 3 4 1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. 2. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions 3. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 4. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. In order to achieve low standby current, all inputs must be driven to VCCQ or VSS. ISB may be slightly higher for up to 500ms after power-up or when entering standby mode. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Electrical Characteristics Typical Standby Currents Figure 13 refers to the typical standby currents for the MT45W512KW16P device. The values shown in Figure 13 are measured with the on-chip temperature sensor control enabled (default setting). Figure 13: Typical Refresh Current vs. Temperature (ITCR) 45 40 35 ISB (A) 30 PAR FULL PAR 1/2, PAR 1/4, PAR 1/8 PAR 0 25 20 15 10 5 C 85 C 75 C C C C 65 55 45 35 C 25 C 15 5C -5 C -1 5C -2 5C -3 5C -4 5C 0 Temperature (C) Notes: PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 1. Typical ISB currents for each PAR setting with the appropriate TCR selected, or temperature sensor enabled. 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Electrical Characteristics Table 6: DPD Specifications and Conditions Description Deep power-down Table 7: Symbol TYP Units VIN = VCCQ or 0V; +25C ZZ# = 0V CR[4] = 0 IZZ 10 A Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: Figure 14: Conditions Conditions Symbol Min Max Units Notes TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.0 6.5 6.5 pF pF 1 1 1. These parameters are verified in device characterization and are not 100 percent tested. AC Input/Output Reference Waveform VCCQ 1 Input 2 VCC/2 Test Points 3 VCCQ/2 Output VSSQ Notes: Figure 15: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not be shown to scale. 3. Output timing ends at VCCQ/2. Output Load Circuit Test Point DUT 50 VccQ/2 30pF PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Electrical Characteristics Table 8: READ Cycle Timing Requirements 70ns Parameter Symbol AA APA t BA t BHZ tBLZ t CEM t CO tHZ tLZ t OE tOH tOHZ tOLZ tPC tRC Address access time Page access time LB#/UB# access time LB#/UB# disable to High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time Chip disable to High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to High-Z output Output enable to Low-Z output Page cycle time READ cycle time Notes: PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN Min t t Max Units 70 20 70 8 ns ns ns ns ns s ns ns ns ns ns ns ns ns ns 10 8 70 8 10 20 5 8 5 20 70 Notes 1 2 3 1 1 1 1 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 17. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 17. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 3. Page mode enabled only. 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Electrical Characteristics Table 9: WRITE Cycle Timing Requirements 70ns Parameter Symbol AS AW t BW t CPH tCW t DH t DW tLZ tOW t WC tWHZ tWP tWPH tWR Address setup time Address valid to end of write Byte select to end of write CE# HIGH time during write Chip enable to end of write Data hold from write time Data write setup time Chip enable to Low-Z output End write to Low-Z output WRITE cycle time WRITE to High-Z output WRITE pulse width WRITE pulse width HIGH WRITE recovery time Notes: Table 10: Min t Max Units 0 70 70 5 70 0 23 10 5 70 t ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 46 10 0 Notes 1 1 2 3 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 17. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 17. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. WE# LOW time must be limited to tCEM (8s). Load Configuration Register Timing Requirements 70ns Description Address setup time Address valid to end of write Chip deselect to ZZ# LOW Chip enable to end of write WRITE cycle time WRITE pulse width WRITE recovery time ZZ# LOW to WE# LOW Table 11: Symbol Min tAS 0 70 5 70 70 40 0 10 tAW tCDZZ tCW t WC WP tWR tZZWE t Max Units 500 ns ns ns ns ns ns ns ns Max Units DPD Timing Requirements 70ns Description Symbol t CDZZ tR tZZ (MIN) Chip deselect to ZZ# LOW DPD recovery Minimum ZZ# pulse width PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 19 Min 5 150 10 ns s s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Timing Diagrams Timing Diagrams Figure 16: Power-Up Initialization Period Vcc (MIN) Vcc, VccQ = 1.7V Table 12: tPU Device ready for normal operation Initialization Timing Parameters 70ns Parameter Symbol t PU Initialization period (required before normal operations) Figure 17: Min 150 Max Units s Load Configuration Register tWC ADDRESS OPCODE tAW tWR tCW CE# LB#/UB# tAS tWP WE# OE# tCDZZ tZZWE ZZ# DON'T CARE Figure 18: Deep Power-Down - Entry/Exit tCDZZ tZZ (MIN) ZZ# tR CE# Device ready for normal operation DON'T CARE PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Timing Diagrams Figure 19: Single READ Operation (WE# = VIH) tRC ADDRESS ADDRESS VALID tAA tHZ CE# tCO tBHZ tBA LB#/UB# tLZ tBLZ tOHZ tOE OE# tOLZ DATA-OUT High-Z DON'T CARE Figure 20: High-Z DATA VALID UNDEFINED Page Mode READ Operation (WE# = VIH) tRC ADDRESS A[18:4] ADDRESS VALID ADDRESS A[3:0] tPC tAA tCEM tHZ CE# tCO tBHZ tBA LB#/UB# tBLZ tLZ tOHZ tOE OE# tAPA tOLZ DATA-OUT tOH DATA VALID High-Z DATA VALID DATA VALID DON'T CARE PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 21 DATA VALID High-Z UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Timing Diagrams Figure 21: WRITE Cycle (WE# Control) tWC ADDRESS VALID ADDRESS tWR tAW tCW CE# tBW LB#/UB# tWP tAS tWPH WE# OE# tDW DATA-IN tDH DATA VALID tWHZ tOW DATA-OUT High-Z DON'T CARE Figure 22: WRITE Cycle (CE# Control) tWC ADDRESS VIH Valid Address VIL tAW tAS CE# tWR tCW tCPH VIH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWP VIH WE# VIL tDW tDH VIH DATA-IN High-Z VIL tLZ Valid Input tWHZ VOH DATA-OUT VOL Don't Care PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Timing Diagrams Figure 23: WRITE Cycle (LB#/UB# Control) tWC ADDRESS ADDRESS VALID tAW tWR tCW CE# tAS tBW LB#/UB# WE# OE# tDW DATA-IN tDH DATA VALID tWHZ DATA-OUT tOW High-Z DON'T CARE PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Advance 8Mb: 512K x 16 Async/Page PSRAM Package Dimensions Package Dimensions Figure 24: 48-Ball VFBGA 0.70 0.05 SEATING PLANE A 0.10 A 48X O0.37 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE-REFLOW BALL DIAMETER IS 0.35 ON A 0.30 SMD BALL PAD. SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% Cu SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 3.75 0.75 TYP BALL A1 ID BALL A1 BALL A1 ID 4.00 0.05 BALL A6 CL 5.25 8.00 0.10 2.625 0.75 TYP CL 1.875 1.00 MAX 3.00 0.05 6.00 0.10 Notes: 1. All dimensions in millimeters, MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W512KW16P uses "green" packaging. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Advance: This data sheet contains initial descriptions of products still under development. PDF: 09005aef8220472e/Source: 09005aef8220461e 8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.