UDA1342TSN1 - NXP SEMICONDUCTORS

DATA SH EET

Product specification

Supersedes data of 2000 Mar 29 2000 Jul 31

INTEGRATED CIRCUITS

UDA1342TS

Audio CODEC

2000 Jul 31 2

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.2 ADC analog front-end

8.2.1 Application with 2 V (RMS) input

8.2.2 Double differential mode

8.3 Decimation filter (ADC)

8.4 Digital mixer (ADC)

8.5 Interpolation filter (DAC)

8.6 Mute

8.7 Digital mixer (DAC)

8.8 Noise shap er

8.9 Filter stream DAC

8.10 Digital interface

8.11 Sampling speed

8.12 Power-on reset

8.13 Control modes

8.14 Static pin mode

8.14.1 System clock setting select

8.14.2 Digital interface format select

8.14.3 ADC input chann el se lect

8.15 L3-bus interface

8.15.1 Introduction

8.15.2 Device addressin g

8.15.3 Register addressing

8.15.4 Data write mode

8.15.5 Data read mode

8.16 I2C-bus interfa ce

8.16.1 Addressing

8.16.2 Slave address

8.16.3 Register address

8.16.4 Write cycle

8.16.5 Read cycle

9 REGISTER MAPPING

9.1 Reset

9.2 Quick mode switc h

9.3 Bypass mixer DC filter

9.4 DC filter

9.5 ADC mode

9.6 ADC polarity

9.7 System clock freque ncy

9.8 Data format

9.9 DAC power contr ol

9.10 Input oversampling rate

9.11 DAC polarity

9.12 DAC mixing position switch

9.13 DAC mixer

9.14 Silence detection period

9.15 Multi purpose ou tput

9.16 Mode

9.17 Bass boost

9.18 Treble

9.19 Silence detecto r switch

9.20 Mute

9.21 Quick mute mode

9.22 De-emphasis

9.23 ADC input amplifier gain

9.24 DAC volume control

9.25 DAC mixer volume control

9.26 ADC mixer gain control

10 LIMITING VALUES

11 HANDLING

12 QUALITY SPECIFICATION

13 THERMAL CHARACTERISTI CS

14 DC CHARACTERISTICS

15 AC CHARACTERISTICS

16 TIMING

17 APPLICATION INFORMATION

18 PACKAGE OUTLINE

19 SOLDERING

19.1 Introduction to soldering surface mount

packages

19.2 Reflow soldering

19.3 Wave soldering

19.4 Manual soldering

19.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

20 DATA SHEET STATUS

21 DISCLAIMERS

22 TRADEMARKS

2000 Jul 31 3

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

1 FEATURES

General

•2.7 to 3.6 V power supp ly

•5 V tolerant digital inputs

•High pin compatibility with UDA1341TS

•24 bits data path

•Selectable control via L3-bus interface, I2C-bus

interface or static pin control; choice of 2 device

addresses in L3-bus and I2C-bus mode

•Supports sample frequencies from 16 to 110 kHz

•Separate power control for ADC and DAC

•ADC and Programmable Gain Amplifiers (PGA) plus

integrated high-pass filter to cancel DC offset

•Integrated digital filter plus DAC

•Digital silence detection

•No analog post filtering required for DAC

•Slave mode only applications

•Easy application .

Multiple format data interface

•I2S-bus, MSB-justified an d LSB-justified format

compatible

•1fsto 4fs input and 1fsoutput format data rate.

DAC digital sound processing

•Separate digital logarithmic volume control for left and

right channels in L3 -bus mode or I2C-bus mode

•Digital tone control, bass boost and treble in L3-bus

mode or I2C-bus mode

•Digital de-emphasis for sample frequencies o f

32, 44.1, 48 and 96 kHz in L3-bus mode or I2C-bus

mode

•Soft or quick mute in L3-bus mode or I2C-bus mode

•Output sign al polarity contro l in L3-bus mode o r I2C-bus

mode

•Digital mixer for ADC output signal and digital serial

input signal.

Advanced audio configuration

•4 channel (2 ×stereo) single-ended inputs with

programmable gain amplifiers and 2 channel

(1 ×stereo) single-ended outputs configuration

•Output signal polarity control in L3-bus mode or I2C-bus

mode

•High linearity, wide dynamic range, low distortion

•Double differential input configuration for enhanced

ADC sound qualit y.

2 APPLICATIONS

•Eminently suitable for MiniDisc (MD) home and portable

applications.

3 GENERAL DESCRIPTION

The UDA1342TS is a single-chip 4 channel

analog-to- digital converter and 2 channel digital-to -analog

converter with si gn al pr ocessing features employing

bitstream conv ersion technique s. The low power

consumption and low voltage requir ements make the

device eminently suitable for use i n low-voltage low-power

portable digital audio equipment which incorporates

recording and playback functions.

The UDA1342TS supports the I2S-bus data format with

word lengths of up to 24 bits, the MSB-justified data format

with word lengths of up to 24 bits and the LSB-justified

serial data format with word lengths of 16, 20 and 24 bits.

The device also supports a combination of the

MSB-justified output format and the LSB-justified input

format.

The UDA1342TS has special sound processing features in

the playback mode such as de-emphasis, volume, mute,

bass boost and treble, which can be contro lled by the

microcontroller via the L3-b us or I2C-bus interface.

2000 Jul 31 4

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V

VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V

VDDD digital supply voltage 2.7 3.0 3.6 V

IDDA(ADC) ADC analog su pply current 1 ADC + 1 PGA enabled −10.0 −mA

2ADCs+2PGAs enabled −20.0 −mA

all ADCs + all PGAs

power-down −200 −μA

IDDA(DAC) DAC analog supply current operating −6.0 −mA

DAC power-down −250 −μA

IDDD digit al supply current operating −9.0 −mA

ADC power-dow n −4.5 −mA

DAC power-down −5.5 −mA

Tamb ambient temperature −40 −+85 °C

Analog-to-digit al convertor

Vi(rms) input voltage (RMS value) at 0 dB (FS) digital output −0.9 −V

(THD+N)/S48 total har m on ic d i sto rt i on - plu s- noise

to signal ratio at fs=48kHz normal mode

at −1dB −−90 −dB

at −60 dB; A-weighted −−40 −dB

double differential

at −1dB −−93 −dB

at −60 dB; A-weighted −−41 −dB

(THD+N)/S96 total har m on ic d i sto rt i on - plu s- no ise

to signal ratio at fs=96kHz normal mode

at −1dB −−84 −dB

at −60 dB; A-weighted −−39 −dB

S/N48 signal-to-noise ratio at fs= 48 kHz normal mode;

Vi= 0 V; A-weighted −100 −dB

double differential mode;

Vi= 0 V; A-weighted −101 −dB

S/N96 signal-to-noise ratio at fs= 96 kHz normal mode;

Vi= 0 V; A-weighted −99 −dB

αcs channel separation −100 −dB

2000 Jul 31 5

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Note

1. The output voltage of the DAC is proportionally to the DAC pow er s upply voltage.

5 ORDERING INFORMATION

Digital-to-analog convertor

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input;

note 1 −0.9 −V

(THD+N)/S48 total har m on ic d i sto rt i on - plu s- noise

to signal ratio at fs=48kHz at 0 dB −−90 −dB

at −60 dB; A-weighted −−40 −dB

(THD+N)/S96 total har m on ic d i sto rt i on - plu s- noise

to signal ratio at fs=96kHz at 0 dB −−83 −dB

at −60 dB; A-weighted −−39 −dB

S/N48 signal-to-noise ratio at fs= 48 kHz code = 0; A-weighted −100 −dB

S/N96 signal-to-noise ratio at fs= 96 kHz code = 0; A-weighted −99 −dB

αcs channel separation −100 −dB

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1342TS SSOP28 plastic shrink sm all ou tlin e package; 28 leads; body width 5.3 mm SOT341-1

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 6

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

6 BLOCK DIAGRAM

handbook, full pagewidth

MGT016

ADC

PGA

6 8

VINL2

VSSD

VDDD

DATAO

BCK

DATAI

VOUTL

26 VOUTR

SYSCLK

21 STATIC

L3DATA

L3CLOCK

L3MODE

VINR2

10 11

DC-CANCELLATION FILTER

DECIMATION FILTER

DIGITAL MIXER (ADC)

DIGITAL

INTERFACE

L3-BUS/

I2C-BUS

INTERFACE

ADC

DAC

VSSA(DAC)

VDDA(DAC) Vref

DAC

INTERPOLATION FILTER

NOISE SHAPER

DIGITAL MIXER (DAC)

DSP FEATURES

20 TEST1

VDDA(ADC) VSSA(ADC)

VADCP VADCN

UDA1342TS

PGA

23 QMUTE

22 STATUS

9IPSEL

ADC

2 4

VINL1 VINR1

ADC

Fig.1 Block diagram.

2000 Jul 31 7

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

7 PINNING

SYMBOL PIN TYPE DESCRIPTION

VSSA(ADC) 1 analog ground pad ADC analog ground

VINL1 2 analog input pad ADC input left 1

VDDA(ADC) 3 analog supply pad ADC analog supply voltage

VINR1 4 analog input pad ADC input right 1

VADCN 5 analog pad ADC reference voltage N

VINL2 6 analog input pad ADC input left 2

VADCP 7 analog pad ADC reference voltage P

VINR2 8 analog input pad ADC input right 2

IPSEL 9 5 V tolerant digital input pad channel select inpu t: input left 1 and right 1 or

input left 2 and right 2

VDDD 10 digital supply pad digital supply voltage

VSSD 11 digital ground pad digital ground

SYSCLK 12 5 V tolerant digital input pad system clock input: 256fs,384f

s,512f

s or 768fs

L3MODE 13 5 V tolerant digital input pad L3-bus mode input or mode selection input

L3CLOCK 14 5 V tolerant digital input pad L3-bus /I2C-bus clock input or clock selection

input

L3DATA 15 5 V tolerant open drain input/output L3-bus/I2C-bus data input/ ou tput or format

selection input

BCK 16 5 V tolerant digital input pad bit clock input

WS 17 5 V tolerant digital input pad word select input

DATAO 18 5 V tolerant 2 mA slew rate controlled digital

output data output

DATAI 19 5 V tolerant digital input pad data input

TEST1 20 5 V tolerant digital input pad test control input; to be connected to ground

STATIC 21 5 V tolerant digital input pad mode selection input: static pin control or

L3-bus/I2C-bus control

STATUS 22 5 V tolerant 2 mA slew rate controlled digital

output general purpose output

QMUTE 23 5 V tolerant digital input pad quick mute input

VOUTR 24 analog output pa d DAC output right

VDDA(DAC) 25 analog supply pad DAC analog supply voltage

VOUTL 26 analog output pad DAC output left

VSSA(DAC) 27 analog ground pad DAC analog grou nd

Vref 28 analog pad reference voltage for ADC and DAC

2000 Jul 31 8

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1342TS operates in slave mode only, this means

that in all applications the system must provide the system

clock. The system c l ock frequency is selectable and

depends on the mode of op eration:

•L3-bus/I2C-bus mode: 256fs, 384fs, 512fs or 768fs

•Static pin mode: 256fs or 384fs.

The system clock must be locked in frequency to the digital

interface signals.

Remarks:

•The bit clock frequen cy fBCK can be up to 128fs, or in

other words the bit clock fr equency is 128 times the

word select frequency fWS or less: fBCK ≤128fWS

•The WS edge MUST fall on the negative edge of the

BCK signal at all times for proper operation of the digital

interface

•The UDA1342TS operates with sample frequencies

from 16 to 110 kHz, however for a system clock of 768fs

the sampling frequency must be limited to 55 kHz.

8.2 ADC analog front-end

The analog front-end of the UDA1342T S co nsists of two

stereo ADCs with a programmable gain stage (gai n from

0 to 24 dB with 3 dB steps) which can be controlled via the

L3-bus/I2C-bus interface.

8.2.1 APPLICATION WITH 2V(RMS) INPUT

In applications in which a 2 V (RMS) input signal is used,

a 15 kΩ resistor must be used in series with the input of the

ADC (see Fig.3). This forms a voltage divider together with

the internal A DC resistor and ensure s that only 1 V (RMS)

maximum is input to the IC. Using this application for a

2 V (R MS) input signal, the gain switch must be set to

0 dB. When a 1 V (RMS) input signal is input to the ADC in

the same application, the gain switch must be set to 6 dB.

An overview of the maximum input voltages allowed

against the presence of an external resistor and the setting

of the gain switch is given in Table 1.

Table 1 Application modes using input gain stage

handbook, halfpage

VSSA(ADC)

VINL1

VDDA(ADC)

VINR1

VADCN

VINL2

VADCP

VINR2

IPSEL

VDDD

VSSD

SYSCLK

L3MODE

L3CLOCK

Vref

VSSA(DAC)

VOUTL

VDDA(DAC)

QMUTE

STATUS

VOUTR

STATIC

TEST1

DATAI

DATAO

BCK

L3DATA

1514

UDA1342TS

MGT017

Fig.2 Pin configuration.

RESISTOR

(15 kΩ)PGA GAIN MAXIMUM INPUT

VOLTAGE

Present 0 dB 2 V (RMS)

Present 6 dB 1 V (RMS)

Absent 0 dB 1 V (RMS)

Absent 6 dB 0.5 V (RMS)

handbook, halfpage

MGT018

Vref

VINL1,

VINR1,

VINL2,

VINR2

gain = 0 dB

10 kΩ

15 kΩ

input signal

2 V (RMS)

UDA1342TS

Fig.3 Schematic of ADC front-end.

2000 Jul 31 9

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.2.2 DOUBLE DIFFERENTIAL MODE

Since the UDA1342TS is equipped with two stereo ADCs,

these two pairs of s te reo ADCs can be used to co nvert a

single stereo signal to a signal with a higher performance

by using the ADCs in the double differential mode.

This mode and the input sig nals, being channel 1 or 2 as

input to the double differe ntial co nfiguration, can be

selected via the L3-bus/I2C-bus interface.

8.3 Decimation filter (ADC)

The decimation from 64fs to 1fs is performed in two stages.

The first stage realizes a characteristic with a

decimation factor of 8. The second stage consists of three

half-band filters, each decimating by a factor of 2. The filter

characteristics are shown in Table 2.

Table 2 Decimation filter characteristics

8.4 Digital mixer (ADC)

The two stereo ADC outputs are mixed with gain

coefficients from +24 to −63.5 dB to be set via the

microcontroller interface.

In front of the mixer there is a DC filter. In order to prevent

clipping, i t is needed to filter out the DC component be fore

mixing or amplifying the signals.

The mixing function can be enabled via the microcontroller

interface.

8.5 Interpolation filter (DAC)

The digital interpolation filter interpolates from 1fsto 64fs

by means of a cascade of FIR filters. The filter

characteristics are shown in Table 3.

Table 3 Interpolation filter characteristics

8.6 Mute

Muting the DAC will result in a cosine roll-off soft mute,

using 32 ×32 = 1024 samples in the normal mo de: this

results in 24 ms at fs= 44.1 kHz. The cosine roll-off curve

is illustrated in Fig.4.

This cosine roll-off functions are implemented in the DAC

data path before the digita l mixer and before the master

mute (see Fig.5).

In the L3-bu s and I2C-bus mode, the setting of the master

mute can be overruled always by pin QMUTE. This quick

mute uses the same cos i ne roll-off, but now for only

32 samples: this is 750 μs at fs=44.1kHz.

8.7 Digital mixer (DAC)

The ADC output signal and the digital interface input signal

can be mixed withou t an external DSP (see Fig.5).

This mixer can be controlled via the microcontroller

interface.

In order to prevent clipping when mixing two 0 dB signals,

the signals are attenuated digitally by −6dB before mixing.

After mixing the signal is gained by 6 dB after the master

volume. This way clipping at the digital mi xer is prevented.

After the 6 dB gain, the signals can clip again, but this

clipping can be removed by decreasing the master

volume.

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45fs±0.01

Pass-band dr oop 0 .4 5fs−0.2

Stop band >0.55fs−70

Dynamic range 0 to 0.45f s>135

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45fs±0.025

Stop band >0.55fs−60

Dynamic range 0 to 0.45f s>135

xsin

-----------

⎝⎠

⎛⎞

handbook, halfpage

01051525

0.8

MGU119

0.6

0.4

0.2

t (ms)

mute

factor

Fig.4 Mute as a function of raised cosine roll-off.

2000 Jul 31 10

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

MGT019

BASS BOOST

AND

TREBLE

VOLUME

AND

MUTE

DE-EMPHASIS VOLUME

AND

MUTE

master

VOLUME

AND

MUTE

digital

interface

output

from

digital

interface

input

from

decimation

filter

interpolation

filter

+ +

Fig.5 Digital mixer (DAC).

8.8 Noise shaper

The 5th-order noise sh aper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise sh aping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a Filter

Stream Digital-to-Analog Converter (FSDAC).

8.9 Filte r stream DAC

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output vo ltage. The filter coefficients are

implemented as current sources and are summed at virtual

ground of th e output opera tional amplifier. In t his way very

high signal-to-noise performance and low clock jitter

sensitivity is achieved . A post-filter is not needed due to

the inherent filter function of the DAC. On-board amplifiers

convert the FSDAC output current to an output voltage

signal capable of driving a line output.

The output voltage of the FSDAC is proportionally to the

power supply v oltage.

8.10 Digital interface

The UDA1342TS supports the following data input/output

formats for the vario us modes (see Fig.6).

L3-bus and I2C-bus mode:

•I2S-bus format with data word length of up to 24 bits

•MSB-justified serial format with data word length of up to

24 bits

•LSB-justified serial format with data word lengths of

16, 20 or 24 bits

•MSB-justified da ta ou tp ut and

LSB-justified 16, 20 and 24 bits data input.

Static pin mode:

•I2S-bus format with data word length of up to 24 bits

•MSB-justified da ta ou tp ut and

LSB-justified 16, 20 and 24 bits data input.

2000 Jul 31 11

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

ATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB MSBB2

21> = 812 3

LEFT

I2S-BUS FORMAT

BCK

ATA

RIGHT

3> = 8

MSB B2

MGT02

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

ATA

RIGHT

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

ATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB-JUSTIFIED FORMAT

SLEFT RIGHT

321321

MSB B2 MSBLSB LSB MSB B2B2

> = 8 > = 8

ATA

Fig.6 Serial interface input/output formats.

2000 Jul 31 12

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.11 Sampling speed

The UDA1342TS operates with sample frequencie s fro m

16 to 110 kHz. This range holds for the CODEC as a

whole. The DAC part can be configured in the L3-bus and

I2C-bus mode to ac cept 2 times and even 4 times the data

speed (e.g. fs is 96 or 192 kHz), but in these modes not all

of the features can be us ed.

Some examples of the input oversampling rate settings are

shown in Table 4.

Important: in the double speed mode an input signal of

0 dB is allowed, but in the quad speed mode the input

signal must be limited to −6 dB to prevent the system from

clipping.

Table 4 Examples of the input over sampling rate settings

SYSTEM CLOCK

SYSTEM

CLOCK

FREQUENCY

SETTING

SAMPLING

FREQUENCY

(kHz)

INPUT OVER-

SAMPLING

RATE FEATURES SUPPORTED

12.288 MHz (256 ×48 kHz) 256fs48 sing le speed all

96 double speed only master volume and mute

192 quad speed no features

22.5792 MHz (5 12 ×44.1 kHz) 512fs44.1 single speed all

256fs88.2 single speed all

176.4 double speed only master volume and mute

33.8688 MHz (7 68 ×44.1 kHz) 768fs44.1 single speed all

384fs88.2 single speed all

176.4 double speed only master volume and mute

8.12 Power-on reset

The UDA1342TS has an internal Power-on reset circuit

(see Fig.7) which resets the test control block. All the

digital sound pr ocessing features and the system

controlling features a re set to their default setting in the

L3-bus and I2C-bus mode.

The reset time (see Fig.8) is determined by an external

capacitor which is connected between pin Vref and ground.

The reset time should be at least 1 μs for Vref < 1.25 V.

When VDDA(DAC) is switched off, the device will be reset

again for Vref <0.75V.

During the reset time the system clock should be running.

handbook, halfpage VDDA(DAC)

Vref

3.0 V 25

MGU001

UDA1342TS

C1 >

10 μF

RESET

CIRCUIT

8 kΩ

Fig.7 Power-on reset circuit.

2000 Jul 31 13

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, halfpage

3.0

VDDD

(V)

1.5

3.0

DDA(DAC)

(V)

1.5

3.0

Vref

(V)

1.5

1.25

0.75

MGU002

>1 μs

Fig.8 Power-on reset timing.

8.13 Control modes

The control mode can be set with pin STATIC and

pin L3MODE:

•Static pin mode

•I2C-bus mode

•L3-bus mode.

Table 5 Mode selection

The pin functions in the va rious modes are summarized in

Table 6.

Table 6 Pin function in the selected mode

All features in the L3 -bus and I2C-bus mode are explained

in Sections 8.15 and 8.16.

PIN STATIC PIN L3MODE SELECTION

LOW −L3-bus mode

HIGH LOW I2C-bus mode

HIGH HIGH static pin mode

PIN NAME FUNCTION

L3-BUS

MODE I2C-BUS

MODE STATIC PIN

MODE

L3CLOCK L3CLOCK SCL clock select

L3MODE L3MODE LOW level HIGH level

L3DATA L3DATA SDA format select

QMUTE QMUTE QMUTE format select

IPSEL A0 A0 channel select

2000 Jul 31 14

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.14 St atic pin mode

The controllab le fe atu r es in the static pin mode are:

•System clock frequency

•Data input and output fo rmat select

•ADC input channel select .

8.14.1 SYSTEM CLOCK SETTING SELECT

In the static pin mode pin L3CLOCK is used to select the

system clock setting.

Table 7 System clock setting

8.14.2 DIGITAL INTERFACE FORMAT SELECT

In the static pin mode the digital interface audio formats

can be selected via pin s L3DATA an d QMUTE. The

following interface form ats can be selected (see Tabl e 8):

•I2S-bus format with data word length of up to 24 bits

•MSB-justified output format and LSB-justified input

format with data word length of 16, 20 or 24 bits.

Table 8 Data format select in static pin mode

8.14.3 ADC INPUT CHANNEL SELECT

In the static pin mode pin IPSEL selects the ADC input

channel.

Table 9 ADC input channel s elec t

8.15 L3-bus interface

All digital processing features and system controlling

features of the UD1342TS can be controlled by a

microcontroller via the L3-bus interface.

The controllable fe atures are:

•Reset

•System clock frequency

•Data input and output format

•Multi purpose output

•ADC features

– Operation mode co ntrol

– Polarity control

– Input amplifier ga in control

–Mixer control

– DC filtering.

•DAC features

– Power control

– Polarity control

– Input data oversamp ling rate

– Mixer position selection

–Mixer control

– Silence detector

– De-emphasis

–Volume

– Flat/min./max. switch

– Bass boost

–Treble

–Mute

– Quick mute mode.

8.15.1 INTRODUCTION

The exchange of data and control information between the

microcontroller an d the UDA1342TS is accomplish ed

through a serial hardware interface comprisin g the

following pins:

•L3DATA: microcontroller interface data lin e

•L3MODE: microcontroller interface mode line

•L3CLOCK: microcontroller interface clock line.

The UDA1342TS acts as a slave receiver or a slave

transmitter. Therefore L3CLOCK and L3MODE lines

transfer only input data and the L3DATA line transfers

bidirectional data.

L3CLOCK SYSTEM CLOCK SETTING

0 256fs

1 384fs

L3DATA PIN

QMUTE INPUT/OUTPUT FORMAT

00I

0 1 LSB-justified 16 bits input and

MSB-justified output

1 0 LSB-justified 20 bits input and

MSB-justified output

1 1 LSB-justified 24 bits input and

MSB-justified output

IPSEL CHANNEL SELECT

0 input channel 1 (pins VINL1 and VINR1)

1 input channel 2 (pins VINL2 and VINR2)

2000 Jul 31 15

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Information transfer via th e microcontroller bus is

organized LSB first and in accordance with the so called

‘L3’ format, in which two different modes of operation can

be distinguished: ad dress mode and data transfer mode.

Important:

•When the de vice is powered -up, at least on e L3CLOCK

pulse must be sent to the L3-bus interface to wake-up

the interface pr io r to sen d i ng info rmation to the device.

This is only needed once after the device is powered-up.

•Inside the microcontroller there is a hand-shake

mechanism which handles proper data transfer from the

microcontroller clock to destination clock domains. This

means that when data is sent to the microcontroller

interface, the s ys t em clock must be running.

•The L3-bus interface is designed in such a way that data

is clocked into the device (write mode) on the pos itive

clock edge, w hile the device start s the output data (re ad

mode) on the negative clock edge. The microcontroller

must read the data from the device on the positive clock

edge to ensure the data is always stable.

8.15.2 DEVICE ADDRESSING

The device address mode is used to select a device for

subsequent data trans f er. The address mode is

characterized by L3MODE being LOW and a burst of

8 pulses on L3CLOCK, accompanied by 8 bits. The

fundamental timing in the address mode is s hown in

Fig.13.

The device address consists of one byte, which is split up

in two parts (see Table 10):

•Bits 0 and 1 are called Data Operation Mode (DOM) bits

and represent the type of data transfer

•Bits 2 to 7 represent a 6-bit device address.

Table 10 L3-bus interface slave address

The UDA1342TS c an be set to different addresses

(00 1000 or 10 1000) by setting pin IPSEL to HIGH or

LOW level. In the event that the device receives a different

address, it will deselect its microcontroller interface logic.

Basically, 2 types of data transfer can be defined: data

transfer to the de vice and data transfer from the device

(see Table 11).

Table 11 Selection of data transfer

8.15.3 REGISTER ADDRESSING

After sending the device address, including the flags (DOM

bits) whether the information is read or written, the data

transfer mode is ente red and one byte is sent with the

destination register address (see Table 12) usin g 7 bits,

and one bit which signals whether information will be read

or written.

The fundamental timing for the data transfer mode is given

in Fig.14.

Table 12 L3-bus register address

Basically there ar e 3 cases for regis te r addressing:

1. Register addressing for L3-bus write: the first bit is at

logic 0 indicating a write action to the des tin ation

address.

2. Prepare read addressing: the first bit of the byte is at

logic 1, signalling data will be read from the register

indicated.

3. Read action itself: in this case the device returns a

the register address was invalid.

Important:

1. Each time a new destination address n eeds to be

written, the device ad dress must be sent again.

2. When addressing the device for the first time after

power-up of the dev ice, at lea st one L3CLOCK cycle

must be given to enable the L3-bus interface.

DOM DEVICE ADDRESS

LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB

R/W 1 IPSEL 0 1 0 0 0

DOM TRANSFER

BIT 0 BIT 1

0 0 not used

1 0 not used

0 1 data write or prepare read

11data read

LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB

R/W A6 A5 A4 A3 A2 A1 A0

2000 Jul 31 16

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.15.4 DATA WRITE MODE

The data write format is given in Table 13 and illustrated

in Fig.9.

When writing data to a device four bytes must be sent:

1. One byte with the de vic e address, being ‘01X0 1000’

where ‘X’ stands for the IPSEL value, including ‘01’ for

signalling write to the device.

2. One byte starting with a logic 0 for signalling write

followed by 7 bits indicating the register address.

3. One byte which is the Most Significant Data (MSD)

byte 1.

4. One byte which is the Least Significant Data (LSD)

byte 2.

8.15.5 DATA READ MODE

The data write format is given in Table 14 and illustrated

in Fig.10.

When reading from the device, a prepare read must first be

done. After the prepare read, the device address is sent

again. The device then retu rns with the register address,

indicating whe ther the address was valid or not, and the

data of the register.

The data read mode is exp l ained below:

1. One byte with the device address, being ‘01X0 1000’

where ‘X’ stands for the IPSEL value, including ‘01’ for

signalling write to the device.

2. One byte is sent with the register address which needs

to be read. This byte starts with a logic 1, which

indicates that there will be a read action from the

3. One byte with the device address including ‘11’ is sent

to the device. The ‘11’ indicates that the device must

write data to the microcontroller.

4. The device now writes the requested register address

on the L3-bus, indicating whether the requested

5. The device writes data from the requested register to

the L3-bus with the MSD byte 1 first, followed by the

LSD byte 2.

Table 13 L3-bus format for data write

Table 14 L3-bus format for prepare read a nd read data

L3MODE DATA TYPE FIRST IN TIME LAST IN TIME

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

Address device address 01IPSEL01000

Data transfer 1 register address 0 A6 A5 A4 A3 A2 A1 A0

Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8

Data transfer3LSD byte2 D7D6D5D4D3D2D1D0

L3MODE DATA TYPE FIRST IN TIME LAST IN TIME

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

Prepare read

Address device address 01IPSEL01000

Data transfer 1 register address 1 A6 A5 A4 A3 A2 A1 A0

Read data

Address device address 11IPSEL01000

Data transfer 1 register address 0/1 A6 A5 A4 A3 A2 A1 A0

Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8

Data transfer3LSD byte2 D7D6D5D4D3D2D1D0

2000 Jul 31 17

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

MGS75

3CLOCK

L3MODE

L3DATA 0

write

L3 wake-up pulse after power-up

device address

DOM bits

Fig.9 Data write mode for L3-bus version 2.

MGS75

3CLOCK

3MODE

3DATA 0

read valid/non-valid

device address

prepare read send by the device

DOM bits

111

0/1

Fig.10 Data read mode for L3-bus version 2.

2000 Jul 31 18

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.16 I2C-bus interface

Besides the L3-bus mode the UDA1342TS supports the

I2C-bus mode; all the fe atu r es can be controlled by the

microcontroller with the same register addresses as used

in the L3-bus mode.

The exchange of data and control information between the

microcontroller and the UDA1342TS in the I2C-bus mode

is accomplished through a serial hardware inter face

comprising the follow i ng pins and signals:

•L3CLOCK: Serial Clock Line (SCL)

•L3DATA: Serial Data line (SDA).

The clock and data timing of the I2C-bus transfer is shown

in Fig.15.

8.16.1 ADDRESSING

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. The addressing is

always done with the first byte transmitted after the START

procedure (S).

8.16.2 SLAVE ADDRESS

The UDA1342TS ac ts as a slave receiver or a slave

transmitter. Therefore, the clock signal SCL is only an

input signal. The data signal SDA is an input or output

signal (bidire ctional line).

The UDA1342TS s lave address format is sh own in

Table 15.

Table 15 I2C-bus slave address format

The slave address bit IPSEL corresponds to the hardware

address pin IPSEL which allows selecting the slave

address.

8.16.3 REGISTER ADDRESS

The UDA1342TS register address format is given in

Table 16.

Table 16 I2C-bus register address format

The register mapping of the I2C-bus and L3-bus interfaces

is the same (see Section 9).

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

001101IPSEL R/W

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

0A6A5A4A3A2A1A0

2000 Jul 31 19

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.16.4 WRITE CYCLE

The write cycle is used to write data from the microcontroller to the internal regist ers. The I2C-bus format for a write cycle is shown in Table 17.

The device and re gis ter addresses ar e one byte each, data is alwa ys two bytes (2-byt es data).

The format of the write cycle is as follows:

1. The microcontroller starts with a START condition S.

2. The first byte (8 bits) contains the de vice address 0011 01X and a write command (bit R/W =0).

3. This is followed by an a cknowledge (A) from the UDA1342TS.

4. The microcontroller then writes the register addr ess (8 bits) where writing of the register content of the UDA1342TS must start.

5. The UDA1342T S acknowledges this register ad dress.

6. The microcontroller sends 2-bytes data with the Most Significant Data (MSD) byte first and then the Leas t Significant Data (L SD) by te, where each

byte is acknowledged by the UDA1342TS.

7. After the last acknowled ge the UDA1342TS frees the I2C-bus and the microcontroller can generate a STOP condition (P).

Table 17 Master transmitter writes to UDA1 342TS registers

Note

1. Auto increment of the reg i ster address is carried out if re peated groups of 2 bytes are transmitted.

ACKNOWLEDGE FROM UDA1342TS

DEVICE

ADDRESS R/W REGISTER

ADDRESS DATA(1)

S 0 011 01X 0 A 0XXX XXXX A MSD1 A LSD1 A MSD2 A LSD2 A MSDn A LSDn A P

8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits

2000 Jul 31 20

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

8.16.5 READ CYCLE

The read cycle is used to read data from the internal registers of the UDA1342TS to the microcontroller. The I2C-bus format for a read cycle is shown

in Table 18.

The format of the read cycle is as follows:

1. The microcontroller starts with a START condition S.

2. The first byte (8 bits) contains the de vice address 0011 01X and a write command (bit R/W =0).

3. This is followed by an a cknowledge (A) from the UDA1342TS.

4. The microcon troller then writes the register address where reading of the regi ster content of the UDA1342TS mus t s t art.

5. The UDA1342T S acknowledges this register ad dress.

6. Then the microcontroller generates a repe ated START (Sr).

7. Again the device address 0011 01X is given, but this time follow ed by a r ead command (bit R/W =1).

8. The UDA1342TS sen ds the two-byte data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where

each byte is acknowledge d by the microcontroller (master).

9. The microcontroller stops this cycle by generating a neg ative acknowledge (NA).

10. The UDA1342TS then frees the I2C-bus and the microcontroller can generate a STOP condition (P).

Table 18 Master transmitter re ads from UDA1342TS regis te rs

Note

1. Auto increment of the reg i ster address is carried out if re peated groups of 2 bytes are transmitted.

ACKNOWLEDGE FROM UDA1342TS ACKNOW L EDGE FROM MASTER

DEVICE

ADDRESS R/W REGISTER

ADDRESS DEVICE

ADDRESS R/W DATA(1)

S 0011 01X 0 A 0XXX XXXX A Sr 0011 01X 1 A MSD1 A LSD1 A MSD2 A LSD2 A MSDn A LSDn NA P

8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits

2000 Jul 31 21

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

9 REGISTER MAPPING

The addresses of the control registers with default values at Power-on reset are shown in Table 19. Functions of the registers are shown in

Tables 20 to 45.

Table 19 Register map

ADDRESS FUNCTION D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

00H system RST QS MDC DC AM2 AM1 AM0 PAD 0 SC1 SC0 IF2 IF1 IF0 DP PDA

−001101000000010

01H sub sys tem −−−−−−−−OS1 OS0 MPS MIX SD1 SD0 MP1 MP0

−−−−−−−−00000000

02H to 0FH reserved −−−−−−−−−−−−−−−−

10H DAC features M1 M0 BB3 BB2 BB1 BB0 TR1 TR0 SDS MTB MTA MT QM DE2 DE1 DE0

0000000000000000

11H DAC master volume VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0

0000000000000000

12H DAC mixer volume VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0

0000000000000000

13H to 1FH reserved −−−−−−−−−−−−−−−−

20H ADC input and mixer

gain channel 1 0 0 0 0 IA3 IA2 IA1 IA0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

0000000000000000

21H ADC input and mixer

gain channel 2 0 0 0 0 IB3 IB2 IB1 IB0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0

0000000000000000

22H to 2FH reserved −−−−−−−−−−−−−−−−

30H evaluation 0000000000000000

31H to FFH reserved −−−−−−−−−−−−−−−−

2000 Jul 31 22

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

9.1 Reset

A 1-bit value to initializ e the L3-bus and I2C-bus registers

except the system registe r (0 0H) with default settings by

setting bit RST = 1.

Table 20 Reset bit

9.2 Quick mode switch

A 1-bit value to enable the quick mode change of the ADC.

The soft mode change works only between modes if

bit AM2 = 1.

Table 21 Quick mode switch

9.3 Byp as s mixer DC filter

A 1-bit value to disable the DC filter of the ADC mixer. This

DC filter is in front of the mixer to prevent clipping insi de

the mixer due to DC signals.

Table 22 Mixer DC filtering

9.4 DC filter

A 1-bit value to enable the DC filter of the ADC output. This

DC filter is inside the decimation filter.

Table 23 DC-filtering

9.5 ADC mode

A 3-bit value to select the mode of the ADC.

Table 24 ADC mode

9.6 ADC polarity

A 1-bit value to control th e ADC polarity.

Table 25 Polarity control of the ADC

9.7 System clock frequency

A 2-bit value to select the ex ternal clock frequency.

Table 26 System clock freq uency settings

RST FUNCTION

0no reset

1 reset registers to default

QS FUNCTION

0 soft mode c hange

1 quick mode change

MDC FUNCTION

0 enable mixer DC filtering

1 disable mixer DC filtering

DC FUNCTION

0 disable output DC filtering

1 enable output DC filtering

AM2 AM1 AM0 FUNCTION

000ADC power-off

0 0 1 input 1 select (input 2 off)

0 1 0 input 2 select (input 1 off)

0 1 1 not used

1 0 0 channel swap and signal inversion

1 0 1 input 1 select (double differential

mode)

1 1 0 input 2 select (double differential

mode)

1 1 1 mixing mode

PAD FUNCTION

0 non-inverting

1 inverting

SC1 SC0 FUNCTION

0 0 256fs

0 1 384fs

1 0 512fs

1 1 768fs

2000 Jul 31 23

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

9.8 Data format

A 3-bit value to select the data format.

Table 27 Data format selection

9.9 DAC power control

A 1-bit value to disab le the DAC to reduce power

consumption. The DAC power-off is not recommended

when the DAC outputs are DC loaded.

Table 28 DAC power control

9.10 Input oversampling rate

A 2-bit value to select the oversampling rate of the input

signal (see Table 32). In the quad speed input rate, care

must be taken that the input signal is sm aller than

−5.67 dB (FS).

9.11 DAC polarity

A 1-bit value to control th e DAC polarity.

Table 29 Polarity control of DAC

9.12 DAC mixing position sw it ch

A 1-bit value to select the mixing position of the ADC signal

in the DAC.

Table 30 DAC mixing position switch

9.13 DAC mixer

A 1-bit value to enable the digital mixer of the DAC.

IF2 IF1 IF0 FUNCTION

000I

2S-bus

0 0 1 LSB-justified16 bits

0 1 0 LSB-justified 20 bits

0 1 1 LSB-justified 24 bits

1 0 0 MSB-justified

1 0 1 LSB-justified 16 bits input and

MSB-justified output

1 1 0 LSB-justified 20 bits input and

MSB-justified output

1 1 1 LSB-justified 24 bits input and

MSB-justified output

DP FUNCTION

0 D AC power-off

1 D AC power-on

PDA FUNCTION

0 non-inverting

1 inverting

MPS FUNCTION

0 before sound features

1 a fter sound features

Table 31 DAC mixer

MIX FUNCTION

0 disable mixer

1 enable mixer

2000 Jul 31 24

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Table 32 Input oversampling rate

9.14 Silence detection period

A 2-bit value to define the silence period for the silence

detector.

Table 33 Silence detection period

9.15 Multi purpose output

A 2-bit value to select the output signal on pin STATUS.

Table 34 Multi purpose output selection

9.16 Mode

A 2-bit value to program the mode of the sound processing

filters of bass boost and treble.

Table 35 Flat/min./max. switch position

9.17 Bass boost

A 4-bit value to program the bass boost settings. The used

set depends on the setting of bits M1 and M0.

At fs= 44.1 kHz the −3 dB point for minimum setting is

250 Hz and the −3 dB point for maximum setting is 300 Hz.

The default value is 0000.

OS1 OS0 MODE SAMPLING

FREQUENCY ADC DAC FEATURES

0 0 single speed 16 to 110 kHz supporte d all digit al filters and all feat ures, including mixi ng

are availabl e

0 1 double speed 32 to 220 kHz not supported first digital filter is bypassed, only master volume

and master mute features are available

1 0 quad sp eed 64 to 440 kHz not supported no mixing nor any sou nd feature is supp orted

1 1 reserved −− −

SD1 SD0 FUNCTION

003200 samples

014800 samples

109600 samples

1 1 19200 samples

MP1 MP0 FUNCTION

0 0 no output

0 1 overflow (ADC) detection

1 0 reserved

1 1 digital sile nc e de te ctio n

M1 M0 FUNCTION

00flat

01min.

10min.

11max.

2000 Jul 31 25

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Table 36 Bass boost settings

9.18 Treble

A 2-bit value to program the treble setting. The used set

depends on the setting of bits M1 and M0. At fs=44.1kHz

the −3 dB point for minimum setting is 3.0 kHz and the

−3 dB point for maximum setting is 1.5 kHz. The default

value is 00.

Table 37 Treble settings

9.19 Silence detec tor switch

A 1-bit value to enable the silence detector.

Table 38 Silence detector switch

9.20 Mute

Three 1-bit values to enable the digital mute. Bit MT is the

master mute, using bit MTA the signa l from the digital

interface can be s oft muted when the DAC mixer is

enabled and using b it MTB the s ig na l from ADC can be

soft muted.

Table 39 Mute

9.21 Quick mute mode

A 1-bit value to enable th e quick mute function of the

master mute.

Table 40 Quick mute mode settings

9.22 De-emphasis

A 3-bit value to enable the digital de-empha sis filter.

BB3 BB2 BB1 BB0 BASS BOOST (dB)

FLAT MIN. MAX.

0000000

0001022

0010044

0011066

0100088

010101010

011001212

011101414

100001616

100101818

101001820

101101822

110001824

110101824

111001824

111101824

TR1 TR0 TREBLE (dB)

FLAT MIN. MAX.

00 0 0 0

01 0 2 2

10 0 4 4

11 0 6 6

SDS FUNCTION

0 disable silence detector

1 enable silence detector

MTA

MTB FUNCTION

0 no muting

1muting

QM FUNCTION

0 soft mute mode

1 quick mute mode

2000 Jul 31 26

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Table 41 De-emphasis settings

9.23 ADC input amplifier gain

Two 4-bit values to pro gra m the gain of the input amplifiers. Bits IA ap plies for input amplifier A and bits IB to input

amplifier B.

Table 42 ADC input amplifier gain settings

DE2 DE1 DE0 FUNCTION

0 0 0 no de-emp ha sis

0 0 1 de-emphasis at fs=32kHz

0 1 0 de-emphasis at fs=44.1kHz

0 1 1 de-emphasis at fs=48kHz

1 0 0 de-emphasis at fs=96kHz

IA3

IB3 IA2

IB2 IA1

IB1 IA0

IB0 AMPLIFIER GAIN (dB)

0000 0

0001 3

0010 6

0011 9

0100 12

0101 15

0110 18

0111 21

1000 24

2000 Jul 31 27

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

9.24 DAC volume control

Four 8-bit values to program the volume attenuations. The range is from 0 to −6 6 dB and −∞ dB in steps of 0.25 dB.

Bits VL and VR are master volumes for th e left and right channels.

Table 43 DAC volume settings

9.25 DAC mixer volume control

Four 8-bit values to program the volume attenuations. The range is from 0 to −6 0 dB and −∞ dB in steps of 0.25 dB.

When the DAC mixer is enabled, the signal from the digital interface can be controlled by bits VA and the signal from the

ADC can be controlled by bits VB.

VL7

VR7 VL6

VR6 VL5

VR5 VL4

VR4 VL3

VR3 VL2

VR2 VL1

VR1 VL0

VR0 VOLUME (dB)

00000000 0

00000001 −0.25

00000010 −0.50

00000011 −0.75

00000100 −1.00

:::::::: :

11000100 −49.0

11000101 −49.25

11000110 −49.5

11000111 −49.75

11001000 −50.0

11001100 −52.0

11010000 −54.0

11010100 −57.0

11011000 −60.0

11011100 −66.0

11100000 −∞

:::::::: :

11111111 −∞

2000 Jul 31 28

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Table 44 DAC volume settings

9.26 ADC mixer gain control

Two 8-bit value s to program the cha nnel 1 and 2 mixing, when the mixer mode is selected. Bits MA applies to channel 1

and bits MB to channel 2. The range is from +24 to −63.5 dB and −∞ dB in steps of 0.5 dB.

Table 45 ADC mixer gain settings

VA7

VB7 VA6

VB6 VA5

VB5 VA4

VB4 VA3

VB3 VA2

VB2 VA1

VB1 VA0

VB0 VOLUME (dB)

00000000 0

00000001 −0.25

00000010 −0.50

00000011 −0.75

00000100 −1.00

:::::::: :

10101100 −43.0

10101101 −43.25

10101110 −43.5

10101111 −43.75

10110000 −44.0

10110100 −46.0

10111000 −48.0

10111100 −51.0

11000000 −54.0

11000100 −60.0

11001000 −∞

:::::::: :

11111111 −∞

MA7

MB7 MA6

MB6 MA5

MB5 MA4

MB4 MA3

MB3 MA2

MB2 MA1

MB1 MA0

MB0 MIXER GAIN (dB)

00110000 +24.0

00101111 +23.5

00101110 +23.0

:::::::: :

00000010 +1.0

00000001 +0.5

00000000 0

11111111 −0.5

:::::::: :

10000100 −62.0

10000011 −62.5

2000 Jul 31 29

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

10000010 −63.0

10000001 −63.5

10000000 −∞

MA7

MB7 MA6

MB6 MA5

MB5 MA4

MB4 MA3

MB3 MA2

MB2 MA1

MB1 MA0

MB0 MIXER GAIN (dB)

2000 Jul 31 30

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

10 LIMITING VALUES

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Notes

1. All supply conn ections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capac itor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 20 0 pF capac itor via a 0.75 μH series inductor.

4. DAC operation afte r short-circui ting cannot be warranted.

11 HANDLING

Inputs and outputs are protected against electrostatic discharg e in normal handling. However, to be totally safe, it is

desirabl e to tak e no rmal precautions appropriate to hand lin g MOS de vice s.

12 QUALITY SPECIFICATION

In accordance with “SNW-FQ-611-E”.

13 THERMAL CHARACTERISTICS

14 DC CHARACTERISTICS

VDDD =V

DDA(ADC) =V

DDA(DAC) = 3.0 V; Tamb =25°C; RL=5kΩ; all voltages measured with respect to grou nd; unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage note 1 −4V

Txtal(max) maximum cryst al temperature −150 °C

Tstg storage temperature −65 +125 °C

Tamb ambient temperature −40 +85 °C

Ves electrostatic handling voltage note 2 −1100 +1100 V

note 3 −250 +250 V

Ilu(prot) latch-up protection current Tamb =125°C; VDD = 3.6 V - 200 mA

Isc(DAC) short-circuit current of DAC Tamb =0°C; VDD = 3 V; note 4

output short-circuited to VSSA(DAC) −450 mA

output short-circuited to VDDA(DAC) −325 mA

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 90 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies; note 1

VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V

VDDA(DAC) DAC analog supply v oltage 2.7 3.0 3.6 V

VDDD digital supply voltage 2.7 3.0 3.6 V

2000 Jul 31 31

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Notes

1. All supply connections must be made to the same power supply unit.

2. VDDA =V

DDA(DAC) =V

DDA(ADC).

3. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in

order to prevent os cillations in the output operational amplifier.

IDDA(ADC) ADC analog su pply current 1 ADC + 1 PGA enabled −10 −mA

2 ADCs + 2 PGAs enabled −20 −mA

all ADCs + all PGAs

power-down −200 −μA

IDDA(DAC) DAC analog supply current operating −6.0 −mA

DAC power-down −250 −μA

IDDD digital supply current operating −9.0 −mA

ADC power-down −4.5 −mA

DAC power-down −5.5 −mA

Digital input pins (5 V tolerant TTL compatible)

VIH HIGH-level input voltage 2.0 −5.5 V

VIL LOW-level input voltage −0.5 −+0.8 V

⎪ILI⎪input leakage current −−1μA

Ciinput capacitance −−10 pF

Digital output pins

VOH HIGH-level output voltage IOH =−2mA 0.85V

DDD −−V

VOL LOW-level output voltage IOL =2mA −−0.4 V

Reference voltage

Vref reference voltage with respect to V SSA(ADC);

note 2 0.45VDDA 0.5VDDA 0.55VDDA V

Ro(Vref) output resistance on pin Vref −5−kΩ

Analog-to-digit al converter

VADCP positive reference volt age of

the ADC −VDDA(ADC) −V

VADCN negative reference voltage

of the ADC −0.0 −V

Riinput resistance −10 −kΩ

Ciinput capacitance −24 −pF

Digital-to-analog converter

Io(max) maximum output current (THD + N)/S < 0.1% −1.6 −mA

RLload resistance 3 −−kΩ

CLload capacitance note 3 −−50 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 32

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

15 AC CHARACTERISTICS

VDDD =V

DDA(ADC) =V

DDA(DAC) =3.0V; f

i= 1 kHz at −1dB; T

amb =25°C; RL=5kΩ; all voltages measured with respect

to ground; unles s oth erwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digit al converter

Vi(rms) input voltage

(RMS value) 0 dB setting −900 −mV

3 dB setting −640 −mV

6 dB setting −450 −mV

9 dB setting −320 −mV

12 dB setting −225 −mV

15 dB setting −160 −mV

18 dB setting −122.5 −mV

21 dB setting −80 −mV

24 dB setting −61.25 −mV

ΔViunbalance be tw een

channels −<0.1 −dB

(THD + N)/S48 total harmonic

distortion-plus-n ois e to

signal ratio at fs=48kHz

normal mode; at −1dB

0dB setting −−90 −dB

3dB setting −−90 −dB

6dB setting −−90 −dB

9dB setting −−90 −dB

12 dB setting −−89 −dB

15 dB setting −−89 −dB

18 dB setting −−88 −dB

21 dB setting −−87 −dB

24 dB setting −−85 −dB

normal mode; at −60 dB; A-weighted

0dB setting −−40 −dB

3dB setting −−37 −dB

6dB setting −−36 −dB

9dB setting −−35 −dB

12 dB setting −−33 −dB

15 dB setting −−31 −dB

18 dB setting −−30 −dB

21 dB setting −−28 −dB

24 dB setting −−26 −dB

double differential mode

at 0 dB gain −−93 −dB

at 0 dB gain; −60 dB input;

A-weighted −−41 −dB

2000 Jul 31 33

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

(THD + N)/S96 total harmonic

distortion-plus-n ois e to

signal ratio at fs=96kHz

normal mode

at 0 dB gain −−84 −dB

at −60 dB; A-weighted −−39 −dB

S/N48 signal-to-noise ratio at

fs=48kHz Vi= 0 V; A-weighted

normal mode −100 −dB

double differential mode −101 −dB

S/N96 signal-to-noise ratio at

fs=96kHz Vi= 0 V; A-weighted; normal mode −99 −dB

αcs channel separation −100 −dB

PSRR power supply reject ion

ratio fripple = 1 kHz; Vripple =30mV(p-p) −30 −dB

Digital-to-analog converter

Vo(rms) output voltage

(RMS value) a t 0 dB (FS) digital input −0.9 −V

ΔVounbalance be tw een

channels −<0.1 −dB

(THD+N)/S48 total harmonic

distortion-plus-n ois e to

signal ratio at fs=48kHz

at 0 dB −−90 −dB

at −60 dB; A-weighted −−40 −dB

(THD+N)/S96 total harmonic

distortion-plus-n ois e to

signal ratio at fs=96kHz

at 0 dB −−83 −dB

at −60 dB; A-weighted −−39 −dB

S/N48 signal-to-noise ratio at

fs=48kHz code = 0; A-weighted −100 −dB

S/N96 signal-to-noise at

fs=96kHz code = 0; A-weighted −99 −dB

αcs channel separation −100 −dB

PSRR power supply reject ion

ratio fripple = 1 kHz; Vripple =30mV(p-p) −60 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 34

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

16 TIMING

VDDD =V

DDA(ADC) =V

DDA(DAC) = 2.7 to 3.6 V; Tamb =−20 to +85 °C; all voltages referenced to ground; unless otherwise

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing; note 1 (see Fig.11)

Tsys system clock cycle time fsys = 256fs35 81 250 ns

fsys = 384fs23 54 170 ns

fsys = 512fs17 41 130 ns

fsys = 768fs17 27 90 ns

tCWL system clock LOW time fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

tCWH system clock HIGH time fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

Serial interface input/output data timing (see Fig.12)

fBCK bit clock frequency −−128fsHz

Tcy(BCK) bit clock cycle time Tcy(s) = sample

frequency cycle time −−

1⁄128Tcy(s) s

tBCKH bit clock HIGH time 30 −− ns

tBCKL bit clock LOW time 30 −− ns

trrise time −−20 ns

tffall time −−20 ns

tsu(WS) word select set-up time 10 −− ns

th(WS) word select hold time 10 −− ns

tsu(DATAI) data input set-up time 10 −− ns

th(DATAI) data input hold time 10 −− ns

th(DATAO) data output hold time 0 −− ns

td(DATAO-BCK) data output to bit clock delay −−30 ns

td(DATAO-WS) data output to word select delay −−30 ns

L3-bus interface timing (see Figs 13 and 14)

trrise time note 2 −−10 ns/V

tffall time note 2 −−10 ns/V

Tcy(CLK)L3 L3CLOCK cycle time note 3 500 −− ns

tCLK(L3)H L3CLOCK HIGH time 250 −− ns

tCLK(L3)L L3CLOCK LOW time 250 −− ns

tsu(L3)A L3MODE set-up time in address

mode 190 −− ns

th(L3)A L3MODE hold time in address

mode 190 −− ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 35

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

tsu(L3)D L3MODE set-up time in data

transfer mode 190 −− ns

th(L3)D L3MODE hold time in data

transfer mode 190 −− ns

tstp(L3) L3MODE stop time in data

transfer mode 190 −− ns

tsu(L3)DA L3DATA set-up time in address

and data transfer mode 190 −− ns

th(L3)DA L3DATA hold time in address and

data transfer mode 30 −− ns

tsu(L3)R L3DATA set-up time for read data 50 −− ns

th(L3)R L3DATA hold time for rea d data 360 −− ns

ten(L3)R L3DATA enable time for read data 380 −− ns

tdis(L3)R L3DATA disable time for read

data 50 −− ns

I2C-bus interface timing (see Fig.15)

fSCL SCL clock frequency 0 −400 kHz

tLOW SCL LOW time 1.3 −− μs

tHIGH SCL HIGH time 0.6 −− μs

trrise time SDA and SCL note 4 20 + 0.1C b−300 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Notes

1. The typical value of the timing is specified at 48 kHz sampling frequency.

2. In order to prevent dig ital noise inter fering with the L3-bus communicat ion, it is best t o have the rise and fall times a s

small as possible.

3. When the samplin g frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1⁄64fs cycle.

4. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.

5. After this period, the first clock pulse is generated.

6. To be suppressed by the input filter.

tffall time SDA and SCL note 4 20 + 0.1Cb−300 ns

tHD;STA hold time START condition note 5 0.6 −− μs

tSU;STA set-up time repeated START 0.6 −− μs

tSU;STO set-up time STOP condition 0.6 −− μs

tBUF bus free time between a STOP

and START condition 1.3 −− μs

tSU;DAT data set-up time 100 −− ns

tHD;DAT data hold time 0 −− μs

tSP pulse width of spikes note 6 0 −50 ns

Cbcapacitive load for each bus line −−400 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 36

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

MGR984

Tsys

tCWH

tCWL

Fig.11 Timing of system clock.

handbook, full pagewidth

MGS756

BCK

DATAO

DATAI

trth(WS) tsu(WS)

tBCKH

tBCKL

Tcy(BCK) th(DATAO)

tsu(DATAI) th(DATAI)

td(DATAO-BCK)

td(DATAO-WS)

Fig.12 Serial interface input data timing.

2000 Jul 31 37

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

handbook, full pagewidth

th(L3)A

th(L3)DA

tsu(L3)DA

Tcy(CLK)(L3)

BIT 0

L3MODE

L3CLOCK

L3DATA BIT 7

MGL723

tCLK(L3)H

tCLK(L3)L

tsu(L3)A

th(L3)A

Fig.13 Timing of address mode.

handbook, full pagewidth

tstp(L3)

tsu(L3)D

th(L3)DA

tsu(L3)DA

th(L3)D

Tcy(CLK)L3

BIT 0

L3MODE

L3CLOCK

L3DATA

read

L3DATA

write BIT 7

MGU015

tCLK(L3)H

tCLK(L3)L

td(L3)R tdis(L3)R

Fig.14 Timing of data transfer mode fo r w rite and read.

2000 Jul 31 38

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

MBC611

PSSr P

tSU;STO

tSP

tHD;STA

tSU;STA

tSU;DAT

tHIGH

tHD;DAT

tLOW

tHD;STA

tBUF

Fig.15 Timing of the I2C-bus transfer.

2000 Jul 31 39

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

17 APPLICATION INFORMATION

handbook, full pagewidth

MGT021

47 Ω

R13

C13

100 μF

(16 V)

C12

100 μF

(16 V)

VDDD

VDDA

BLM32A07

+3 V

ground

VSSA(ADC)

UDA1342TS

SYSCLK

Vref

5727

VDDA(ADC) VADCN VADCP

system

clock

DATAO

BCK

C1 R1

0 Ω

47 μF

(16 V)

VINL1 26 VOUTL R5

100 Ω

R11

10 kΩ

24 VOUTR R6

100 Ω

R12

10 kΩ

47 μF

(16 V)

VINR1

DATAI

L3MODE

L3CLOCK

L3DATA

VDDA

VSSA(DAC) VDDA(DAC)

47 μF

(16 V)

47 μF

(16 V)

47 μF

(16 V)

C20

100 nF

(63 V)

23 QMUTE

9IPSEL

22 STATUS

21 STATIC

20 TEST1

100 nF

(63 V)

100 μF

(16 V)

C22

R15

1 Ω

100 nF

(63 V)

C11

100 μF

(16 V)

C24

R17

220 Ω

100 nF

(63 V)

C10

100 μF

(16 V)

C23

R16

1 Ω

VDDD

VSSD

R14

1 Ω

100 μF

(16 V)

C21

100 nF

(63 V)

VDDD

left

output

right

output

left

input 1

right

47 μF

(16 V)

VINL2

47 μF

(16 V)

VINR2

left

input 2

right

I2S-bus

I2C-bus

L3-bus

Fig.16 Application diagram.

2000 Jul 31 40

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

18 PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 10.4

10.0 5.4

5.2 0.65 1.25

7.9

7.6 0.9

0.7 1.1

0.7 8

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT341-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

114

28 15

0.25

pin 1 index

0 2.5 5 mm

scale

SOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341

-1

max.

2000 Jul 31 41

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

19 SOLDERING

19.1 Introduction to soldering surface mount

packages

This text gives a very brief insight to a complex technology.

A more in-depth acco un t of sold er ing ICs can be found in

our “Data Handbook IC26; Integra te d Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method tha t is idea l for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population dens ities. In these situations reflow

soldering is often used.

19.2 Re flow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-s yringe dispensing before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 sec onds depending on heating

method.

Typical reflow peak temperatur es range from

215to250°C. The top-surface temperature of the

packages sh ould preferable be kept below 230 °C.

19.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wa ve soldering method comprising a

turbulent wave with high up ward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axi s is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint lon gitudinal axis

must be parallel to the transport direction of the

printed-circuit board .

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be plac ed at a 45° angle to the transp ort direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adh esive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

19.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads ca n be

soldered in one ope ration within 2 to 5 seconds between

270 and 320 °C.

2000 Jul 31 42

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

19.5 Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with res pect to time) and body size of the package, there is a risk th at internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integ rated Circuit Packages; Section: Pac kin g Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be place d at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side cor ners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2000 Jul 31 43

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

20 DATA SHEET STATUS

Notes

1. Please consult the most rec en tly issued document before initiating or co mpleting a design.

2. The product s tatus of device(s ) described in this do cument may have changed since this docu ment was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective s pecification for product

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Produc tio n This document contains the product specification.

21 DISCLAIMERS

Limited warranty and liability ⎯ Information in this

document is believed to be accurate and reliable.

However, NXP Semiconduc tors does not give any

representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and

shall have no liability for the consequences of use of such

information.

In no event shall NXP Semiconductors be liable for any

indirect, incidental, punitive, special or consequential

damages (including - without limitation - lost profits, lost

savings, busin es s interru ption, costs related to the

removal or replacement of any products or rework

charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any

other legal theory.

Notwithstanding any damages that customer might incur

for any reason whatsoever, NXP Semiconductors’

aggregate and cu mulative liability towards customer for

the products described herein shall be limited in

accordance with the Terms and conditio ns of commercial

sale of NXP Semiconductors.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to informa tion

published in this doc ument, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereo f.

Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are

not designed, au thorized or warran ted to be suitable for

use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reasonably be

expected to result in pe rs onal injury, death or severe

property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP

Semiconductor s pr oducts in such equipment or

application s and therefore suc h inclusion and/or us e i s at

the customer’s own risk.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors pro du ct is su itable and fit for the

customer’s applications and products planned, as well as

for the planned a pplication and use of custom er’s third

party customer(s). Customers should provide appropriate

design and opera t ing saf eg ua rd s to minimize the risks

associated with their applications and products.

NXP Semiconduc tors does n ot a ccept any liabil ity rela ted

to any default, damage, costs or problem which is based

on any weakne ss or default in t he customer’s applic ations

or products, or the application or use by customer’s third

party customer( s) . C us to m er is responsible for doin g all

necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applic ations and the products or of

the application or use by customer’s third party

customer(s). NXP does not accept any liability in this

respect.

2000 Jul 31 44

NXP Semiconductors Product specification

Audio CODEC UDA1342TS

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratin gs only and

(proper) operation of the device at these or any other

conditions abo ve those given in th e Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the quality and

reliability of the device.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold subject to the general

terms and conditio ns of commercial sale, as published at

http://www.nxp.com/profile/terms, unless other wise

agreed in a valid written ind i vidual agreement. In case an

individual agreeme nt is co nc luded only the terms and

conditions of the resp ective agreement shall apply. NXP

Semiconductors hereby expressly objects to applying the

customer’s general terms and conditions with regard to the

purchase of NXP Semicon ductors products by customer.

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyan ce or

implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control ⎯ This document as well as the item(s)

described he re in may be subject to export con trol

regulations. Export might require a prior authorization from

national auth or itie s.

Quick refer ence data ⎯ The Quick reference data is an

extract of th e product data given in the Limiting values and

Characteristics sections of this document, and as such is

not complete, exhaus tive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is au tomotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor te sted in accordanc e with automot ive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified prod ucts in automotive equipm en t or

applications.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such au t omo tive applications, us e an d

specifications, and (b) whenever customer uses the

product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at

customer’s own ris k, and (c) customer fully inde mnifies

NXP Semiconductors for any liability, damages or failed

product clai ms r esult ing fr om custo mer desi gn an d us e o f

the product for automotive ap plic ations beyond NXP

Semiconductors ’ st andard warranty and NXP

Semiconductors’ product specifications.

22 TRADEMARKS

I2C-bus ⎯ logo is a trademark of NXP B.V.

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Contact information

For additional information p lease visit: http://www.nxp.com

For sales offices addresses send e-mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information pr e sent ed in this document d oes not form part of any quotation or contract, is b elieve d to be accurate and re li a ble and may be change d

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other ind ustrial or intellectual property right s.

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimer s. No changes were made to the tech nical content, except for package outline

drawings which were updated to the latest version.

Printed in The Netherlands 753503/25/02/pp45 Date of release: 2000 Jul 31 Document order number: 9397 750 07241