© Semiconductor Components Industries, LLC, 2017
April, 2019 − Rev. 4
1Publication Order Number:
NVMFD5C466NL/D
NVMFD5C466NL
Power MOSFET
40 V, 7.4 mW, 52 A, Dual N−Channel
Features
•Small Footprint (5x6 mm) for Compact Design
•Low RDS(on) to Minimize Conduction Losses
•Low QG and Capacitance to Minimize Driver Losses
•NVMFD5C466NLWF − Wettable Flank Option for Enhanced Optical
Inspection
•AEC−Q101 Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 40 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain
Current RJC
(Notes 1, 2, 3) Steady
State
TC = 25°CID52 A
TC = 100°C 37
Power Dissipation
RJC (Notes 1, 2)
TC = 25°CPD38 W
TC = 100°C 19
Continuous Drain
Current RJA
(Notes 1, 2, 3) Steady
State
TA = 25°CID15 A
TA = 100°C11
Power Dissipation
RJA (Notes 1, 2)
TA = 25°CPD3.0 W
TA = 100°C 1.5
Pulsed Drain Current TA = 25°C, tp = 10 sIDM 198 A
Operating Junction and Storage Temperature
Range
TJ, Tstg −55 to
+175
°C
Source Current (Body Diode) IS31.3 A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, IL(pk) = 3 A)
EAS 72 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State RJC 4°C/W
Junction−to−Ambient − Steady State (Note 2) RJA 47.3
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
MARKING
DIAGRAM
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A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
V(BR)DSS RDS(ON) MAX ID MAX
40 V 7.4 m @ 10 V
52 A
12.6 m @ 4.5 V
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
D1
D1
D2
D2
S1
G1
S2
G2
Dual N−Channel
D1
S1
G1
XXXXXX
AYWZZ
D2
D1
D2
S2
G2
D2
D1
DFN8 5x6
(SO8FL)
CASE 506BT
1
NVMFD5C466NL
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 A40 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
29 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 40 V
TJ = 25 °C 10
A
TJ = 125°C 250
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = 20 V 100 nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 30 A1.2 2.2 V
Negative Threshold Temperature Coefficient VGS(TH)/TJ−4.7 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = 10 V ID = 10 A 6.2 7.4
m
VGS = 4.5 V ID = 10 A 10 12.6
Forward Transconductance gFS VDS = 15 V, ID = 25 A 33 S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = 25 V
997
pF
Output Capacitance COSS 354
Reverse Transfer Capacitance CRSS 13
Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 32 V; ID = 25 A 7.0
nC
Total Gate Charge QG(TOT) VGS = 10 V, VDS = 32 V; ID = 25 A 16
Threshold Gate Charge QG(TH)
VGS = 4.5 V, VDS = 32 V; ID = 25 A
1.5
Gate−to−Source Charge QGS 2.3
Gate−to−Drain Charge QGD 2.2
Plateau Voltage VGP 3.3 V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time td(ON)
VGS = 4.5 V, VDS = 32 V,
ID = 25 A, RG = 1.0
10
ns
Rise Time tr67
Turn−Off Delay Time td(OFF) 26
Fall Time tf60
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 10 A
TJ = 25°C 0.9 1.2
V
TJ = 125°C 0.7
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 100 A/s,
IS = 25 A
20
ns
Charge Time ta10
Discharge Time tb10
Reverse Recovery Charge QRR 8 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 s, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
NVMFD5C466NL
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3
TYPICAL CHARACTERISTICS
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
1.51.00.50
0
10
30
40
20
60
70
64320
0
20
50
60
70
100
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
1098765
0
5
20
30252015 505
5
7
14
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1251007550250−25−50
0.5
1.1
1.3
1.5
1.7
2.1
40302520105
1
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
IDSS, LEAKAGE (nA)
VGS = 10 to 5 V
4.5 V
3.8 V
3.6 V
3.4 V
3.2 V
VDS = 10 V
TJ = 125°CTJ = −55°C
TJ = 25°C
10
15
25 ID = 10 A
TJ = 25°C
4535
4
9
10
TJ = 25°C
VGS = 4.5 V
VGS = 10 V
ID = 10 A
VGS = 10 V
TJ = 125°C
TJ = 150°C
TJ = 25°C
15 35
10
100
1K
10K
100K
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
90
43
175
1.9
3.02.52.0 51
0.9
0.7
150
50
80
40
30
10
40
6
8
11
TJ = 85°C
0.6
1.2
1.4
1.6
1.8
2.0
1.0
0.8
10
12
13
NVMFD5C466NL
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)
3025520 40100
1
10
100
10K
543210
0
4
9
10
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
RG, GATE RESISTANCE ()VSD, SOURCE−TO−DRAIN VOLTAGE (V)
100101
1
10
100
1000
0.90.70.60.50.40.3
0.1
1
10
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10001010.1
0.1
1
10
1000
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
IS, SOURCE CURRENT (A)
ID, DRAIN CURRENT (A)
TJ = 25°C
VGS = 0 V
f = 1 MHz
Ciss
Coss
Crss
2
5
6
TJ = 25°C
VDS = 32 V
ID = 25 A
QT
VGS = 4.5 V
VDS = 32 V
ID = 25 A
tr
tf
td(off)
td(on)
0.8 1.0
VGS = 0 V
TC = 25°C
VGS ≤ 10 V
Single Pulse
RDS(on) Limit
Thermal Limit
Package Limit
10 s
10 ms
1076
Qgd
100
1K
89
0.5 ms
1 ms
Figure 12. Maximum Drain Current vs. Time in
Avalanche
TIME IN AVALANCHE (s)
1.0E−05
0.1
1
10
100
IPEAK (A)
TJ(initial) = 25°C
TJ(initial) = 100°C
1.0E−04 1.0E−03 1.0E−02
100
15 35
1
3
7
8
Qgs
TJ = 25°C
TJ = 125°C
TJ = −55°C
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5
TYPICAL CHARACTERISTICS
Figure 13. Thermal Response
PULSE TIME (sec)
0.010.001 100.0001 0.10.00001 10.000001
0.1
1
10
100
R(t) (°C/W)
100 1000
50% Duty Cycle
Single Pulse
20%
10%
5%
2%
1%
0.01
DEVICE ORDERING INFORMATION
Device Marking Package Shipping†
NVMFD5C466NLT1G 5C466L DFN8
(Pb−Free)
1500 / Tape & Reel
NVMFD5C466NLWFT1G 466LWF DFN8
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NVMFD5C466NL
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6
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.27
0.75
1.40
3.70
4.56
8X
PITCH
6.59
4.84
1.00
DIMENSION: MILLIMETERS
2.30
4X
0.70
5.55
4X
0.56
2X
2.08
2X
M3.25
h−−−
3.50
−−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1
h
D
E
B
A
0.20 C
0.20 C
2X
2X
DIM MIN
MILLIMETERS
A0.90
A1 −−−
b0.33
c0.20
D5.15 BSC
D1 4.70
D2 3.90
E6.15 BSC
E1 5.70
E2 3.90
e1.27 BSC
G0.45
K0.51
L0.48
A
0.10 C
0.10 C
14
8
e
8X
D2
b1 E2
b
A0.10 B
C
0.05 C
L
DETAIL A
A1
c
4X
5
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
0.61
M
N1.80 2.00
78
N
PIN ONE
IDENTIFIER
NOTE 7
NOTE 4 CSEATING
PLANE
DETAIL A NOTE 6
4X
K
NOTE 3
D3 1.50 1.70
b1 0.33 0.42
ÉÉ
ÉÉ
4X
D3
G
4X
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
K1 0.56 −−−
K1
3.75
12
_
MAX
1.10
0.05
0.51
0.33
5.10
4.30
6.10
4.40
0.65
−−−
0.71
2.20
1.90
0.51
−−−
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NVMFD5C466NL/D
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