SBOS230A − MARCH 2002 − REVISED JUNE 2002
1
FEATURES
DDIGITALLY-CONTROLLED ANALOG VOLUME
CONTROL:
Four Independent Audio Channels
Serial Control Interface
Zero Crossing Detection
Mute Function
DWIDE GAIN AND ATTENUATION RANGE:
+31.5dB to −95.5dB with 0.5dB Steps
DLOW NOISE AND DISTORTION:
120dB Dynamic Range
0.0004% THD+N at 1kHz (U−Grade)
0.0002% THD+N at 1kHz (A−Grade)
DNOISE-FREE LEVEL TRANSITIONS
DLOW INTERCHANNEL CROSSTALK:
−130dBFS
DPOWER SUPPLIES: ±5V Analog, +5V Digital
DAVAILABLE IN AN SOP-28 PACKAGE
APPLICATIONS
DAUDIO AMPLIFIERS
DMIXING CONSOLES
DMULTI−TRACK RECORDERS
DBROADCAST STUDIO EQUIPMENT
DMUSICAL INSTRUMENTS
DEFFECTS PROCESSORS
DA/V RECEIVERS
DCAR AUDIO SYSTEMS
DESCRIPTION
The PGA4311 is a high−performance, 4-channel audio
volume control designed for professional and high-end
consumer audio systems. Using high performance
operational amplifier stages internal to the PGA4311
yields low noise and distortion, while providing the
capability to drive 600Ω loads directly without bu ffering.
The 3-wire serial control interface allows for connection
to a wide variety of host controllers, in addition to
support for daisy-chaining of multiple PGA4311
devices.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
!" #
! ! $ %&#
!' & ' !#
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
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2
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage, VA+ +5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
VA− −5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VD+ +5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VA+ to VD+< ± 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input Voltage 0V to VA+, VA−. . . . . . . . . . . . . . . . . . . . . .
Digital Input Voltage −0.3V to VD+. . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range −40°C to +85°C. . . . . . . . . . . . . . . .
Storage Temperature Range −65°C to +150°C. . . . . . . . . . . . . . . .
Junction Temperature +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (soldering, 10s) +300°C. . . . . . . . . . . . . . . . . . .
Package Temperature (IR reflow, 10s) +235°C. . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to ob-
serve proper handling and installation procedures can
cause damage.
ESD damage can range from subtle performance
degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because very small parametric changes could cause
the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE−LEAD PACKAGE
DESIGNATOR(1) OPERATING
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING
NUMBER TRANSPORT
MEDIA, QUANTITY
PGA4311 (U−Grade)
SOP−28
DW
−40°C to +85°C
PGA4311U PGA4311U Rails
PGA4311 (U−Grade
)
SOP−28 DW −40°C to +85°CPGA4311U PGA4311U/1K Tape and Reel, 1000
PGA4311 (A−Grade)
SOP−28
DW
−40°C to +85°C
PGA4311UA PGA4311UA Rails
PGA4311 (A−Grade) SOP−28 DW −40°C to +85°CPGA4311UA PGA4311UA/1K Tape and Reel, 1000
(1) For the most current specifications and package information, refer to our web site at www. ti.com.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VA+ = +5V, VA− = −5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
PARAMETER
CONDITIONS
PGA4311U (U−Grade) PGA4311UA (A−Grade)
UNITS
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DC CHARACTERISTICS
Step Size 0.5 0.5 dB
Gain Error Gain Setting = 31.5dB ±0.05 ±0.05 dB
Gain Matching ±0.05 ±0.05 dB
Input Resistance 10 10 kΩ
Input Capacitance 3 3 pF
AC CHARACTERISTICS
THD+N VIN = 2Vrms, f = 1kHz 0.0004 0.001 0.0002 0.0004 %
Dynamic Range VIN = AGND, Gain = 0dB 116 120 116 120 dB
Voltage Range, Output (VA−) +
1.25 (VA+) −
1.25 (VA−) +
1.25 (VA+) −
1.25 V
Voltage Range, Input (without clipping) 2.5 2.5 Vrms
Output Noise VIN = AGND, Gain = 0dB 2.5 4 2.5 4 µVrms
Interchannel Crosstalk f = 1kHz −130 −130 dBFS
OUTPUT BUFFER
Offset Voltage VIN = AGND, Gain = 0dB 0.25 0.5 0.25 0.5 mV
Load Capacitance Stability 100 100 pF
Short−Circuit Current 50 50 mA
Unity−Gain Bandwidth, Small Signal 10 10 MHz
SBOS230A − MARCH 2002 − REVISED JUNE 2002
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3
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VA+ = +5V, VA− = −5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
PARAMETER
CONDITIONS
PGA4311U (U−Grade) PGA4311UA (A−Grade)
UNITS
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DIGITAL CHARACTERISTICS
High−Level Input Voltage, VIH +2.0 VD+ +2.0 VD+ V
Low−Level Input Voltage, VIL −0.3 0.8 −0.3 0.8 V
High−Level Output Voltage, VOH IO = 200µA(VA+) −
1.0 (VD+) −
1.0 V
Low−Level Output Voltage, VOL IO = −3.2mA 0.4 0.4 V
Input Leakage Current 1 10 1 10 µA
SWITCHING CHARACTERISTICS
Serial Clock (SCLK) Frequency fSCLK 0 6.25 0 6.25 MHz
Serial Clock (SCLK) Pulse Width LOW tPH 80 80 ns
Serial Clock (SCLK) Pulse Width HIGH tPL 80 80 ns
MUTE Pulse Width LOW tMI 2.0 2.0 ms
Input Timing
SDI Setup Time tSDS 20 20 ns
SDI Hold Time tSDH 20 20 ns
CS Falling to SCLK Rising tCSCR 90 90 ns
SCLK Falling to CS Rising tCFCS 35 35 ns
Output Timing
CS LOW to SDO Active tCSO 35 35 ns
SCLK Falling to SDO Data Valid tCFDO 60 60 ns
CS HIGH to SDO High Impedance tCSZ 100 100 ns
POWER SUPPLY
Operating Voltage
VA+ +4.75 +5 +5.25 +4.75 +5 +5.25 V
VA− −4.75 −5 −5.25 −4.75 −5 −5.25 V
VD+ +4.75 +5 +5.25 +4.75 +5 +5.25 V
Quiescent Current
IA+ VA+ = +5V 17 22 17 22 mA
IA− VA− = −5V 19 24 19 24 mA
ID+ VD+ = +5V 0.5 1.0 0.5 1.0 mA
Power−Supply Rejection Ratio PSRR (250Hz) 100 100 dB
TEMPERATURE RANGE
Operating Range −40 +85 −40 +85 °C
Storage Range −65 +150 −65 +150 °C
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
4
PIN CONFIGURATION
Top View SO
PIN ASSIGNMENTS
PIN NAME FUNCTION
1 MUTE Mute Control Input (Active LOW)
2 AGND_1 Analog Ground, Channel 1
3 AIN_1 Analog Input, Channel 1
4 AGND_1 Analog Ground, Channel 1
5 AOUT_1 Analog Output, Channel 1
6 VA−Analog Power Supply, −5V
7 VA+Analog Power Supply, +5V
8 AOUT_3 Analog Output, Channel 3
9 AGND_3 Analog Ground, Channel 3
10 AIN_3 Analog Input, Channel 3
11 AGND_3 Analog Ground, Channel 3
12 VD+Digital Power Supply, +5V
13 SDI Serial Data Input
14 CS Chip Select Input
15 SCLK Serial Clock Input
16 SDO Serial Data Output
17 DGND Digital Ground
18 AGND_4 Analog Ground, Channel 4
19 AIN_4 Analog Input, Channel 4
20 AGND_4 Analog Ground, Channel 4
21 AOUT_4 Analog Output, Channel 4
22 VA+Analog Power Supply, +5V
23 VA−Analog Power Supply, −5V
24 AOUT_2 Analog Output, Channel 2
25 AGND_2 Analog Ground, Channel 2
26 AIN_2 Analog Input, Channel 2
27 AGND_2 Analog Ground, Channel 2
28 ZCEN Zero Crossing Enable (Active HIGH)
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
5
TYPICAL CHARACTERISTICS
At TA = +25°C, VA+ = +5V, VA− = −5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
(NOTE: All plots taken with PGA4311 A−Grade.)
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
6
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VA+ = +5V, VA− = −5V, VD+ = +5V, RL = 100kΩ, CL = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
(NOTE: All plots taken with PGA4311 A−Grade.)
GENERAL DESCRIPTION
The PGA4311 is a four-channel audio volume control.
It may be used in a wide array of professional and
consumer audio equipment. The PGA4311 is fabricated
in a sub-micron CMOS process.
The h eart o f t he P GA4311 i s a r esistor n etwork, an a nalog
switch array, and a high-performance op a mp stage. The
switches are used to select taps in the resistor network
that, in turn, determine the gain of the amplifier stage.
Switch selections are programmed using a serial control
port. The s erial p ort a llows c onnection t o a w ide v ariety o f
host controllers. See Figure 1 for a functional block
diagram of the PGA4311.
POWER−UP STATE
On power up, “power-up reset” is activated for about
100ms during which the circuit is in hardware MUTE state
and all internal flip-flops are reset. At the end of this period,
the o f fset calibration i s i nitiated without a ny external s ignals.
Once this has been completed, the gain byte value for all
channels are set to 00HEX, or the software MUTE condi-
tion. The gain will remain at this setting until the host con-
troller programs new settings for for each channel via the
serial control port.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
7
Figure 1. PGA4311 Block Diagram.
If during normal operation the power supply voltage
drops below ±3.2V, the circuit enters a hardware MUTE
state. A power-up sequence will be initiated if the
power-supply voltage returns to greater than ±3.2V.
ANALOG INPUTS AND OUTPUTS
The PGA4311 includes four independent channels.
Each channel h as a c orresponding i nput a nd o utput pin.
The input and output pins are unbalanced, and refer-
enced to analog ground.
The input a nd o utput p ins m ay s wing w ithin 1 .25V of t he
analog power supplies, VA+ and VA−. Given VA+ = +5V
and VA− = −5V, the maximum input or output voltage
range is 7.5Vp-p.
For o ptimal p erformance, i t i s b est t o d rive t he P GA4311
with a low source impedance. A source impedance of
600Ω or less is recommended. Source impedances up
to 2 kΩ w ill cause m inimal degradation o f THD+N. P lease
refer to the “THD+N vs Source Impedance” plot in the
Typical Characteristics section of the datasheet.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
8
SERIAL CONTROL PORT
The s erial c ontrol p ort i s u tilized t o p rogram t he g ain s et-
tings for the PGA4311. The serial control port includes
three input pins and one output pin. The inputs include
CS (pin 14), SDI (pin 13), and SCLK (pin 15). The sole
output pin is SDO (pin 16).
The C S pin f unctions a s t he chip s elect input. D ata m ay
be written to the PGA4311 o nly when CS is LOW. SDI
is t he serial d ata input pin. Control d ata is provided a s
a 32-bit word at the SDI pin, 8 bits each for each chan-
nel gain setting.
Data is formatted as MSB first, straight binary code.
SCLK is the s erial clock input. Data i s clocked into SDI
on the rising edge of SCLK.
SDO is the serial data output pin, and is used when
daisy-chaining multiple PGA4311 devices. Daisy-chain
operation is described i n detail l ater in t his section. S DO
is a t ri-state o utput, a nd a ssumes a h igh i mpedance s tate
when CS is HIGH. Data appears at SDO on the falling
edge of SCLK.
The protocol for the serial control port is shown in
Figure 2. See Figure 3 for detailed timing specifi-
cations for the serial control port.
Gain Byte Format is MSB First, Straight Binary
0 is the Least Significant Bit of the Channel Gain Byte
7 is the Most Significant Bit of the Channel Gain Byte
SDI is latched on the rising edge of SCLK.
SDO transitions on the falling edge of SCLK.
Figure 2. Serial Interface Protocol.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
9
Figure 3. Serial Interface Timing Requirements.
GAIN SETTINGS
The gain for each channel is set by its corresponding
8-bit code, [7:0] (see Figure 2). The gain code data is
straight binary format. If we let N equal the decimal
equivalent of [ 7:0], then t he following r elationships e x -
ist for the gain settings:
For N = 0:
Mute Condition. The input multiplexer i s connected to
analog ground.
For N = 1 to 255:
Gain (dB) = 31.5 − [0.5 w (255 − N)]
This results in a gain range of +31.5dB (with N = 255)
to −95.5dB (with N = 1).
Changes in gain setting may be made with or without
zero crossing detection. The operation of the zero
crossing d etector a nd timeout circuitry i s discussed lat -
er in this data sheet.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
10
DAISY-CHAINING MULTIPLE PGA4311 DEVICES
In order to reduce the number of control signals re-
quired to support multiple PGA4311 devices on a
printed circuit board, the serial control port supports
daisy-chaining o f multiple P GA4311 d evices. Figure 4
shows the connection requirements for daisy-chain
operation. This arrangement allows a 3-wire serial in-
terface to control many PGA4311 devices.
As s hown i n F igure 4 , t he S DO p in f rom d evice # 1 i s c on-
nected to t he SDI i nput o f d evice # 2, a nd i s r epeated f or
additional devices. This in turn forms a large shift regis-
ter, in which gain data may be written for all PGA4311s
connected t o t he s erial b us. T he l ength o f t he s hift r egis-
ter is 32 • N bits, where N is equal to the number of
PGA4311 devices included in the chain. The CS input
must remain LOW for 32 • N SCLK periods, where N is
the number of devices connected in the chain, in order
to allow enough SCLK cycles to load all devices.
ZERO CROSSING DETECTION
The PGA431 1 i ncludes a z ero c rossing d etection f unc-
tion that can provide for noise-free level transitions.
The c oncept i s t o c hange g ain s ettings on a z ero cross-
ing o f t he input signal, t hus minimizing audible g litches.
This f unction i s enabled o r d isabled u sing t he Z CEN i n-
put. When ZCEN is LOW, zero crossing detection is
disabled. When ZCEN is HIGH, zero crossing detec-
tion will be enabled.
The zero c rossing d etection t akes e ffect w ith a c hange
in gain setting for a corresponding channel. The new
gain s etting w ill not be implemented until either positive
slope z ero crossing i s detected o r a time-out period o f
16ms has elapsed. In the case of a time-out, the new
gain setting takes effect with no attempt to minimize
audible artifacts.
Figure 4. Daisy-Chaining Multiple PGA4311 Devices.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
11
MUTE FUNCTION
Muting c an b e achieved by e ither hardware o r s oftware
control. Hardware muting is accomplished via the
MUTE i nput, a nd s oftware m uting b y l oading all z eroes
into the volume control register.
MUTE disconnects the internal buffer amplifiers from
the output pins and terminates the outputs with 10kΩ
resistors to ground. The mute is activated with a zero
crossing detection (independent of the zero cross en-
able status) o r a n 16ms t ime-out t o eliminate a ny a udi -
ble “clicks” or “pops”. MUTE also initiates an internal
offset calibration.
A software mute is implemented by loading all z eroes
into the volume control register. The internal amplifier
is set t o unity g ain w ith t he a mplifier i nput connected t o
AGND.
APPLICATIONS INFORMATION
This s ection i ncludes a dditional i nformation t hat i s p er-
tinent to designing the PGA4311 into an end applica-
tion.
RECOMMENDED CONNECTION DIAGRAM
Figure 5 depicts the recommended connections for the
PGA4311. Power-supply bypass capacitors should be
placed as close to the PGA4311 package as physically
possible.
PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDE-
LINES
It i s r ecommended that t he ground p lanes for t he d igital
and a nalog sections of the P CB be s eparate from one
another. The planes should be connected at a single
point. See Figure 6 for the recommended PCB floor
plan for the PGA4311.
Figure 5. Recommended Connection Diagram.
SBOS230A − MARCH 2002 − REVISED JUNE 2002
www.ti.com
12
Figure 6. Typical PCB Layout Floor Plan.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PGA4311U ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
PGA4311U/1K ACTIVE SOIC DW 28 1000 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
PGA4311U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
PGA4311U2 PREVIEW SOIC DW 28 1 TBD Call TI Call TI
PGA4311UA ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
PGA4311UA1 PREVIEW SOIC DW 28 1 TBD Call TI Call TI
PGA4311UAG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
PGA4311UG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 20-Oct-2011
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PGA4311U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PGA4311U/1K SOIC DW 28 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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