A4931METTR-T - Allegro Microsystems

Description

The A4931 is a complete 3-phase brushless DC motor pre-driver.

The device is capable of driving a wide range of N-channel

power MOSFETs and can support motor supply voltages up to

30 V. Commutation logic is determined by three Hall-element

inputs spaced at 120°.

Other features include fixed off-time pulse width modulation

(PWM) current control for limiting inrush current, locked-rotor

protection with adjustable delay, thermal shutdown, overvoltage

monitor, and synchronous rectification. Internal synchronous

rectification reduces power dissipation by turning on the

appropriate MOSFETs during current decay, thus shorting

the body diode with the low RDS(on) MOSFET. Overvoltage

protection disables synchronous rectification when the motor

pumps the supply voltage beyond the overvoltage threshold

during current recirculation.

The A4931 offers enable, direction, and brake inputs that can

control current using either phase or enable chopping. Logic

outputs FG1 and FG2 can be used to accurately measure motor

rotation. Output signals toggle state during Hall transitions,

providing an accurate speed output to a microcontroller or

speed control circuit.

Operating temperature range is –20°C to 105°C. The A4931

is supplied in a 5 mm × 5 mm, 28-terminal QFN package with

exposed thermal pad. This small footprint package is lead (Pb)

free with 100% matte tin leadframe plating.

4931-DS, Rev. 4

Features and Benefits

▪ Drives 6 N-channel MOSFETs

▪ Synchronous rectification for low power dissipation

▪ Internal UVLO and thermal shutdown circuitry

▪ Hall element inputs

▪ PWM current limiting

▪ Dead time protection

▪ FG outputs

▪ Standby mode

▪ Lock detect protection

▪ Overvoltage protection

3-Phase Brushless DC Motor Pre-Driver

Package: 28-contact QFN (ET package)

Typical Application

A4931

Approximate Scale 1:1

VBB

0.1 μF

0.1 μF0.1 μF

2 kΩ

VIN

FG1

System

Control

Logic

FG2

A4931

HBIAS

DIR

GND

BRAKEZ

ENABLE

CP1CLD CP2 VCP

GLA

GHA

GLB

GHB

GLC

GHC

SENSE

HA+ HA– HB+ HB– HC+ HC–

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB 38 V

Motor Phase Output SXtw < 500 ns –3 V

Hall Input VHx DC –0.3 to 7 V

Logic Input Voltage Range VIN –0.3 to 7 V

Operating Ambient Temperature TARange M –20 to 105 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –40 to 150 ºC

Selection Guide

Part Number Packing Package

A4931METTR-T 1500 pieces per reel 5 mm x 5 mm, 0.90 mm nominal height QFN

Thermal Characteristics

Characteristic Symbol Test Conditions* Rating Units

Package Thermal Resistance, Junction

to Ambient RθJA 4-layer PCB based on JEDEC standard 32 ºC/W

Package Thermal Resistance, Junction

to Exposed Pad RθJP 2 ºC/W

*For additional information, refer to the Allegro website.

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

RSENSE

CHARGE PUMP

GATE

DRIVE

VCP

HALL

Commun-

ication

Logic

DIR

HB+

HB-

HALL

HC+

HC-

HA+

HA-

HALL

BRAKEZ

ENABLE

SENSE

GLA

GHA

VBB

VCP

CP1

CP2

Control

Logic

HBIAS

GND

VIN

System

Logic

VIN

GHB

GLB

GHC

GLC

FG1

FG2

200 mV

CLD Lock

Detect

OVP

VREG

FG1

VREG

0.1 μF

2 kΩ

Enable

Functional Block Diagram

Number Name Description

1 HA+ Hall input A

2 HA - Hall input A

3 HB+ Hall input B

4 HB - Hall input B

5 HC+ Hall input C

6 HC- Hall input C

7 GND Ground

8 HBIAS Hall bias power supply output

9 CP1 Charge pump capacitor terminal

10 CP2 Charge pump capacitor terminal

11 VBB Supply voltage

12 VCP Reservoir capacitor terminal

13 SENSE Sense resistor connection

14 GLC Low side gate drive C

Number Name Description

15 GLB Low side gate drive B

16 GLA Low side gate drive A

17 GHC High side gate drive C

18 SC High side source connection C

19 GHB High side gate drive B

20 SB High side source connection B

21 GHA High side gate drive A

22 SA High side source connection A

23 FG1 FG 1 speed control output (3 Φ inputs)

24 FG2 FG 2 speed control output (ΦA input)

25 CLD Locked rotor detect timing capacitor

26 DIR Logic input – motor direction

27 ENABLE Logic input – external PWM control

28 BRAKEZ Logic input – motor brake (active low)

Terminal List

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS* Valid at TA= 25°C, VBB = 24 V, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Supply Voltage Range VBB Operating 8 – VBBOV V

Motor Supply Current IBB

fPWM < 30 kHz, CLOAD = 1000 pF – 5 6 mA

Charge pump on, outputs disabled, Standby mode – 3 3.5 mA

HBIAS VHBIAS 0 mA ≤ IHBIAS ≤ 24 mA 7.2 7.5 7.8 V

HBIAS Current Limit IHBIASlim 30 – – mA

Control Logic

Logic Input Voltage VIN(1) 2–– V

VIN(0) – – 0.8 V

Logic Input Current IIN(1) VIN = 2 V –1 <1.0 1 μA

IIN(0) VIN = 0.8 V –1 <–1.0 1 μA

Input Pin Glitch Reject tGLITCH

ENB pin 350 500 650 ns

DIR, BRAKEZ pins 700 1000 1300 ns

ENB Standby Pulse Propagation Delay tdENB To outputs off 2.1 3 3.9 ms

HBIAS Wake-up Delay, Standby Mode tdHBIAS CHBIAS = 0.1 μF – 15 25 μs

Gate Drive

High-Side Gate Drive Output VGS(H) Relative to VBB, IGATE = 2 mA 7 – – V

Low-Side Gate Drive Output VGS(L) IGATE = 2 mA 7 – – V

Gate Drive Current (Sourcing) IGate GH = GL = 4 V 20 30 – mA

Gate Drive Pull Down Resistance RGate 10 28 40 Ω

Dead Time tdead 700 1000 1300 ns

Current Limit Input Threshold VREF 180 200 220 mV

Fixed Off-Time tOFF 18 25 37 μs

Protection

Thermal Shutdown Temperature TJTSD 155 170 185 °C

Thermal Shutdown Hysteresis TJTSDhys 14 15 26 °C

VBB UVLO Enable Threshold VBBUV Rising VBB 6.2 7 7.85 V

VBB UVLO Hysteresis VBBUVhys 0.4 0.75 1 V

VCP UVLO VCPUV Relative to VBB 4.6 – 6 V

Lock Detect Duration tlock C = 0.1 μF 1.5 2 2.5 s

VBB Overvoltage Threshold VBBOV Rising VBB 30 33 37.5 V

Hall Logic

Hall Input Current IHALL VIN = 0.2 to 3.5 V –1 0 1 μA

Common Mode Input Range VCMR 0.2 – 3.5 V

AC Input Voltage Range VHALL 60 – – mVp-p

Hall Thresholds Vth Difference between Hall inputs at transitions – +10,–10 – mV

Hall Threshold Hysteresis VHYS

TJ = 25°C 10 20 30 mV

TJ = –20°C to 125°C 5 20 40 mV

Pulse Reject Filter tpulse –2–μs

FG Output Saturation Voltage VFG(sat) IFG = 2 mA – – 0.5 V

FG Leakage Current IFGlkg VFG = 5 V – – 1 μA

*Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for

individual units, within the specified maximum and minimum limits.

For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.

Specifications throughout the allowed operating temperature range are guaranteed by design and characterization.

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Logic States Table (See timing charts, below) X = Don’t Care, Z = high impedance

Condition Inputs Resulting Pre-Driver Outputs Motor Output

HA HB HC BRAKEZ ENB GHA GLA GHB GLB GHC GLC A B C

DIR = 1

(Forward)

A+– + HI LO HI LO LO HI LO LO HI LO Z

B+– – HI LO HI LO LO LO LO HI HI Z LO

C++ – HI LO LO LO HI LO LO HI Z HI LO

D–+ – HI LO LO HI HI LO LO LO LO HI Z

E–+ + HI LO LO HI LO LO HI LO LO Z HI

F–– + HI LO LO LO LO HI HI LO Z LO HI

DIR = 0

(Reverse)

A+– + HI LO LO HI HI LO LO LO LO HI Z

F–– + HI LO LO LO HI LO LO HI Z HI LO

E–+ + HI LO HI LO LO LO LO HI HI Z LO

D–+ – HI LO HI LO LO HI LO LO HI LO Z

C++ – HI LO LO LO LO HI HI LO Z LO HI

B+– – HI LO LO HI LO LO HI LO LO Z HI

Fault* ++ + HI X LOLOLOLOLOLO Z Z Z

Fault* –– – HI X LOLOLOLOLOLO Z Z Z

Brake* X X X LO X LO HI LO HI LO HI LO LO LO

* DIR = Don’t Care

ABCDEF

FG1

DIR = 1 = FOR

AFEDCB

FG1

DIR = 0 = REV

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VBB

Charge

Pump

ENB

HBIAS

Voltage

VBBUV

3 ms

Standby Mode

Turn off Hall

Bias Supply

Outputs DisabledOutputs Enabled Outputs Enabled

dENB

VBB

Charge

Pump

VBB+7.5 V

7.5V

ENB

HBIAS

Voltage

VHBIAS

VBBUV

PWM

VCPUV

Outputs DisabledOutputs Enabled

Power-up and Standby Modes Timing Diagram

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Current Regulation Load current is regulated by an internal

fixed off-time PWM control circuit. When the outputs of the full

bridge are turned on, current increases in the motor winding until

it reaches a value, ITRIP , given by:

ITRIP = 200 mV / RSENSE .

When ITRIP is reached, the sense comparator resets the source

enable latch, turning off the source driver. At this point, load

inductance causes the current to recirculate for the fixed off-time

period.

Enable Logic The Enable input terminal (ENB pin) allows

external PWM. ENB low turns on the selected sink-source pair.

ENB high switches off the appropriate drivers and the load

current decays. If ENB is held low, the current will rise until it

reaches the level set by the internal current control circuit. Typi-

cally PWM frequency is in 20 kHz to 30 kHz range. If the ENB

high pulse width exceeds 3 ms, the gate outputs are disabled. The

Enable logic is summarized in the following table:

ENB Pin Setting Outputs Outputs State

0 On Drive

1 Source Chopped

Slow Decay with

Synchronous

Rectification

1 for > 3 ms typical Off Disable

Fixed Off-Time The A4931 fixed off-time is set to 25 μs

nominal.

PWM Blank Timer When a source driver turns on, a current

spike occurs due to the reverse recovery currents of the clamp

diodes as well as switching transients related to distributed

capacitance in the load. To prevent this current spike from errone-

ously resetting the source Enable latch, the sense comparator is

blanked. The blanking timer runs after the off-time counter com-

pletes, in order to provide the blanking function. The blanking

timer is reset when ENB is chopped or DIR is changed. With

external PWM control, a DIR change or an ENB on triggers the

blanking function. The duration is fixed at 1.5 μs.

Synchronous Rectification When a PWM-off cycle is

triggered, either by a chop command on ENB or by an internal

fixed off-time cycle, load current recirculates. The A4931 syn-

chronous rectification feature turns on the appropriate MOSFETs

during the current decay, and effectively shorts out the body

diodes with the low RDS(on) driver. This lowers power dissipation

significantly and can eliminate the need for external Schottky

diodes.

Brake Mode A logic low on the BRAKEZ pin activates Brake

mode. A logic high allows normal operation. Braking turns on all

three sink drivers, effectively shorting out the motor-generated

BEMF. The BRAKEZ input overrides the ENB input and also the

Lock Detect function.

It is important to note that the internal PWM current control cir-

cuit does not limit the current when braking, because the current

does not flow through the sense resistor. The maximum current

can be approximated by VBEMF / RLOAD. Care should be taken to

insure that the maximum ratings of the A4391 are not exceeded

in the worse case braking situation, high speed and high inertial

load.

HBIAS Function This function provides a power supply of

7.5 V, current-limited to 30 mA. This reference voltage is used to

power the logic sections of the IC and also to power the external

Hall elements.

Standby Mode To prevent excessive power dissipation due

to the current draw of the external Hall elements, Standby mode

turns off the HBIAS output voltage. Standby mode is triggered

Functional Description

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

by holding ENB high for longer than 3 ms. Note that Brake mode

overrides Standby mode, so hold the BRAKEZ pin high in order

to enter Standby mode.

Charge Pump The internal charge pump is used to generate a

supply above VBB to drive the high-side MOSFETs. The volt-

age on the VCP pin is internally monitored, and in case of a fault

condition, the outputs of the device are disabled.

Fault Shutdown In the event of a fault due to excessive

junction temperature or due to low voltage on VCP or VBB,

the outputs of the device are disabled until the fault condition is

removed. At power-up the UVLO circuit disables the drivers.

Overvoltage Protection VBB is monitored to determine if

a hazardous voltage is present due to the motor generator pump-

ing up the supply bus. When the voltage exceeds VBBOV , the

synchronous rectification feature is disabled.

Overtemperature Protection If die temperature exceeds

approximately 170°C, the Thermal Shutdown function will dis-

able the outputs until the internal temperature falls below the

15°C hysteresis.

Hall State Reporting The FG1 pin is an open drain output

that changes state at each transition of an external Hall element.

The FG2 pin is an open drain output that changes state at each

HAx transition.

Lock Detect Function The IC will evaluate a locked rotor

condition under either of these two different conditions:

• The FG1 signal is not consistently changing.

• The proper commutation sequence is not being followed. The

motor can be locked in a condition in which it toggles between

two specific Hall device states.

Both of these fault conditions are allowed to persist for period

of time, tlock. tlock is set by capacitor connected to CLD pin. CLD

produces a triangle waveform (1.67 V peak-to-peak) with fre-

quency linearly related to the capacitor value. tlock is defined as

127 cycles of this triangle waveform, or:

tlock = CLD × 20 s/μF

After the wait time, tlock , has expired, the outputs are disabled,

and the fault is latched. These fault conditions can only be cleared

by any one of the following actions:

• Rising or falling edge on the DIR pin

• VBB UVLO threshold exceeded (during power-up cycle)

• ENB pin held high for > tlock / 2

The Lock Detect function can be disabled by connecting CLD to

GND.

When the A4931 is in Brake mode, the Lock Detect counter is

disabled.

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ET Package, 28-Contact QFN

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

0.25 +0.05

–0.07

0.55 +0.20

–0.10

0.50

0.90 ±0.10

C0.08

29X SEATING

PLANE

ATerminal #1 mark area

BExposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

For Reference Only

(reference JEDEC MO-220VHHD-1)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

CReference land pattern layout (reference IPC7351

QFN50P500X500X100-29V1M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as

necessary to meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal vias at the

exposed thermal pad land can improve thermal dissipation (reference

EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

3.15

0.30

28 0.50

1.15

4.80

5.00 ±0.15

DCoplanarity includes exposed thermal pad and terminals