March 2010 Rev 12 1/55
1
M25P64
64 Mbit, low voltage, Serial Flash memory
with 75 MHz SPI bus interface
Features
64 Mbit of Flas h me m or y
2.7 V to 3.6 V single supply voltage
SPI bus compatible serial interface
75 MHz clock rate (maximum)
Page Program (up to 256 Bytes)
– in 1.4 ms (typical)
– in 0.35 ms (typical with VPP = 9 V)
Sector Erase (512 Kbit)
Bulk Erase (64 Mbit)
Electronic Signatures
– JEDEC standard two-Byte signature
(2017h)
– RES instruction, one-Byte, signature (16h),
for backward compatibility
– Unique ID code (UID) with 16 bytes
readonly: available upon customer request
Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
More than 100 000 Erase/Program cycles per
sector
More than 20-year data retention
Packages
– RoHS compliant
Automotive certified parts available
VDFPN8 (ME)
8 × 6 mm (MLP8)
SO16 (MF)
300 mils width
www.numonyx.com
Contents M25P64
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . 10
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
4.4 Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M25P64 Contents
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6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 31
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11 Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12 Ordering Information, Standard Parts . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13 Ordering Information, Automotive Parts . . . . . . . . . . . . . . . . . . . . . . . . 52
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
List of tables M25P64
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Read identifica tion (RDI D) da ta-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15. DC characteristics process technology T9HX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. AC characteristics, T9HX parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
M25P64 List of figures
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List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 26
Figure 11. Read Status Register (RDSR) instruction sequen ce and data-out sequence . . . . . . . . . . 27
Figure 12. Write Status Register (WRSR) instructio n sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 30
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out sequence . . . 31
Figure 15. Page Program (PP) instruction sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Read Electronic Signature (RES) instruction sequence and data-out sequence . . . . . . . . 36
Figure 19. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. Write Protect setup an d ho ld timing du r in g WR SR when SRWD = 1. . . . . . . . . . . . . . . . . 46
Figure 23. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 25. VPPH timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 49
Description M25P64
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1 Description
The M25P64 is a 64 Mbit (8M x 8) Serial Flash Memory, with advanced write protec tion
mechanisms, accessed by a high speed SPI-compatible bus instructions allowing clock
frequency up to 75 MHz.(1)
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
An enhanced Fast Program/Erase mode is available to speed up operations in factory
environment. The device e nters this mode whenever the VPPH voltage is applied to the Write
Protect/Enhanced Program Supply Voltage pin (W/VPP).(2)
The memory is organized as 128 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 32768 pages, or
8388608 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environment al requireme nts, Num onyx offers the M25 P64 in Lead-fr ee and
RoHS compliant packages.
Note: Important: This datasheet details the functionality of the M25P64 devices, based on the
previous process or based on the current T9HX process (available since March 2008). The
new device in T9HX is backward compatible with the old on e and it includes these additional
features:
- improved max frequency (Fast Read) to 75 MHz
- UID/CFD protection feature
1. 75 MHz operation is available only for process technology T9HX devices, identified by process identification
digit "4" in the device marking.
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices, identified by
process identification digit "4" in the device marking.
M25P64 Description
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Figure 1. Logic diagram
Figure 2. VDFPN connections
1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally, to VSS,
and must not be allowed to be connected to any other voltage or signal line o n the PCB.
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data Input Input
Q Serial Data Output Output
S Chip Select Input
W/VPP Write Protect/Enhanced Program Supply Voltage Input
HOLD Hold Input
VCC Supply Voltage
VSS Ground
AI07485B
S
VCC
M25P64
HOLD
VSS
W/VPP
Q
C
D
1
AI08595B
2
3
4
8
7
6
5DVSS
C
HOLDQ
SV
CC
W/VPP
M25P64
M25P64 Signal description
9/55
2 Signal description
2.1 Serial Data Output (Q)
This output signal is u sed to transfer dat a serially out of the device . Data is shif ted out on the
falling edge of Serial Clock (C).
2.2 Serial Data Input (D)
This input signal is used to transfer data serially into th e device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an intern al Program, Erase or Write Status Registe r cycle is in progress,
the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the
device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to p ause any serial commun ications with the de vice without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To st art the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Signal description M25P64
10/55
2.6 Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pi n. The two func tions are selected by the
voltage range applied to the pin .
If the W/VPP input is kept in a low voltage range (0V to VCC) the pin is seen as a control
input. This input signal is used to freeze the size of the area of memory that is protected
against program or erase instru ctions (as specified by the values in the BP2, BP1 and BP0
bits of the Status Register).
If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must
be stable until the Program/Erase algorithm is completed.(1)
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices, identified by
process identification digit "4" in the device marking.
M25P64 SPI modes
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3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in eith er of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The dif ference b etween the two modes, as shown in Figure 5, is the clock polarity when th e
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus master and memory devices on the SPI bus
1. The Write Protect (W/VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one de vice drives the Serial Data Output (Q) line at
a time, the other devices are high impedance. Re sistors R (represented in Figure 4) ensure
that the M25P64 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Ma ster may enter a state wher e all inputs/output s are in high impedance at
the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacit a nce of the bu s line) is sho rter than th e tim e during which th e Bus Master leaves the
SPI bus in high impedance.
AI13792
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W/VPP HOLD HOLD HOLD
RR R
VCC
VCC VCC VCC
VSS
VSS VSS VSS
R
W/VPP W/VPP
SPI modes M25P64
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Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 5. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M25P64 Operating features
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4 Operating features
4.1 Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus usin g several Page
Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)
and Table 16: AC characteristics).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instru ction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a tim e, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Eras e (BE) instruc tio n. T his starts an internal Erase cycle (of
duration tSE or tBE).
The Erase inst ru ctio n mus t be preceded by a Write Enable (WRE N) ins tru ct ion .
4.3 Polling during a Write, Program or Erase cycle
A further improvemen t in the time to Write Status Registe r (WRSR) , Pr og ram (PP) or Era se
(SE or BE) can be achieved by not waiting for the worst case d elay (tW, tPP, tSE, or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so th at the application program
can monitor its value, polling it to est ablish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4 Fast Program/Erase mode
The Fast Program/Erase mode is used to speed up programming/erasing. The device
enters the Fast Program/Erase mode during the Page Program, Sector Erase, or Bulk
Erase(1) instruction whenever a volt age equal to VPPH is applied to the W/VPP pin.
The use of the Fast Program/Erase mode req uires specific operating conditions in addition
to the normal ones (VCC must be within the normal operating range):
the voltage ap plied to the W/VPP pin must be equal to VPPH (see Table 10)
ambient temperature, TA must be 25°C ±10°C,
the cumulated time during which W/VPP is at VPPH should be less than 80 hours
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices, identified by
process identification digit "4" in the device marking.
Operating features M25P64
14/55
4.5 Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to ICC1.
4.6 Status Register
The Status Register contains a num ber of status and contr ol bi ts that can be re ad or set (a s
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4: Read Status Register (RDSR).
M25P64 Operating features
15/55
4.7 Protection modes
The environme nts where non -vo la tile memo ry de vice s ar e us ed can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P64 features the following data protection mechanisms:
Power On Reset and an internal timer (tPUW) can provide protection against
inadvertant changes while the power supply is outside the operating specification.
Program, Erase and Write S t atus Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This b it is retur ned to its reset state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Progra m (PP) instr uc tio n co mple tion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be protected. This is the Har dwa re
Protected Mode (HPM).
Table 2. Protected area sizes
Status Register
content Memory content
BP2
Bit BP1
Bit BP0
Bit Protected area Unprotected area
0 0 0 none All sectors(1) (128 sectors: 0 to 127)
1. The device is ready to accept a Bulk Erase instruction, if and only if, all Block Protect (BP2, BP1, BP0) are
0.
0 0 1 Upper 64th (2 sectors: 126 and 127) Lower 63/64ths (126 sectors: 0 to 125)
0 1 0 Upper 32nd (4 sectors: 124 to 127) Lower 31/32nds (124 sectors: 0 to 123)
0 1 1
Upper sixteenth (8 sectors: 120 to
127) Lower 15/16ths (120 sectors: 0 to 119)
1 0 0 Upper eighth (16 sectors: 112 to 127) Lower seven-eighths (112 sectors: 0 to
111)
1 0 1 Upper quarter (32 sectors: 96 to 127) Lower three-quarters (96 sectors: 0 to
95)
1 1 0 Upper half (64 sectors: 64 to 127) Lower half (64 sectors: 0 to 63)
1 1 1 All sectors (128 sectors: 0 to 127) none
Operating features M25P64
16/55
4.8 Hold Condition
The Hold (HOLD) signal is used to p ause any serial communica tions with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 6).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (Th i s is show n in Figure 6).
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duratio n
of the Hold condition. This is to ensure that the st ate of the internal logic remains unch anged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold con dition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Figure 6. Hold condition activation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
M25P64 Memory organization
17/55
5 Memory organization
The memory is organized as:
8388608 bytes (8 bits each)
128 sectors (512 Kbits, 65536 bytes each)
32768 pa ges (256 bytes each).
Each pag e can be individually programme d (bits are progra mmed from 1 to 0). The device is
Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Figure 7. Block diagram
AI08520B
HOLD
S
W/VPP Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
Size of the
read-only
memory are
a
C
D
Q
Status
Register
00000h
7FFFFFh
000FFh
Memory organization M25P64
18/55
Table 3. Memory organization
Sector Address range
127 7F0000h 7FFFFFh
126 7E0000h 7EFFFFh
125 7D0000h 7DFFFFh
124 7C0000h 7CFFFFh
123 7B0000h 7BFFFFh
122 7A0000h 7AFFFFh
121 790000h 79FFFFh
120 780000h 78FFFFh
119 770000h 77FFFFh
118 760000h 76FFFFh
117 750000h 75FFFFh
116 740000h 74FFFFh
115 730000h 73FFFFh
114 720000h 72FFFFh
113 710000h 71FFFFh
112 700000h 70FFFFh
111 6F0000h 6FFFFFh
110 6E0000h 6EFFFFh
109 6D0000h 6DFFFFh
108 6C0000h 6CFFFFh
107 6B0000h 6BFFFFh
106 6A0000h 6AFFFFh
105 690000h 69FFFFh
104 680000h 68FFFFh
103 670000h 67FFFFh
102 660000h 66FFFFh
101 650000h 65FFFFh
100 640000h 64FFFFh
99 630000h 63FFFFh
98 620000h 62FFFFh
97 610000h 61FFFFh
96 600000h 60FFFFh
95 5F0000h 5FFFFFh
94 5E0000h 5EFFFFh
93 5D0000h 5DFFFFh
M25P64 Memory organization
19/55
92 5C0000h 5CFFFFh
91 5B0000h 5BFFFFh
90 5A0000h 5AFFFFh
89 590000h 59FFFFh
88 580000h 58FFFFh
87 570000h 57FFFFh
86 560000h 56FFFFh
85 550000h 55FFFFh
84 540000h 54FFFFh
83 530000h 53FFFFh
82 520000h 52FFFFh
81 510000h 51FFFFh
80 500000h 50FFFFh
79 4F0000h 4FFFFFh
78 4E0000h 4EFFFFh
77 4D0000h 4DFFFFh
76 4C0000h 4CFFFFh
75 4B0000h 4BFFFFh
74 4A0000h 4AFFFFh
73 490000h 49FFFFh
72 480000h 48FFFFh
71 470000h 47FFFFh
70 460000h 46FFFFh
69 450000h 45FFFFh
68 440000h 44FFFFh
67 430000h 43FFFFh
66 420000h 42FFFFh
65 410000h 41FFFFh
64 400000h 40FFFFh
63 3F0000h 3FFFFFh
62 3E0000h 3EFFFFh
61 3D0000h 3DFFFFh
60 3C0000h 3CFFFFh
59 3B0000h 3BFFFFh
58 3A0000h 3AFFFFh
Table 3. Memory organization (continued)
Sector Address range
Memory organization M25P64
20/55
57 390000h 39FFFFh
56 380000h 38FFFFh
55 370000h 37FFFFh
54 360000h 36FFFFh
53 350000h 35FFFFh
52 340000h 34FFFFh
51 330000h 33FFFFh
50 320000h 32FFFFh
49 310000h 31FFFFh
48 300000h 30FFFFh
47 2F0000h 2FFFFFh
46 2E0000h 2EFFFFh
45 2D0000h 2DFFFFh
44 2C0000h 2CFFFFh
43 2B0000h 2BFFFFh
42 2A0000h 2AFFFFh
41 290000h 29FFFFh
40 280000h 28FFFFh
39 270000h 27FFFFh
38 260000h 26FFFFh
37 250000h 25FFFFh
36 240000h 24FFFFh
35 230000h 23FFFFh
34 220000h 22FFFFh
33 210000h 21FFFFh
32 200000h 20FFFFh
31 1F0000h 1FFFFFh
30 1E0000h 1EFFFFh
29 1D0000h 1DFFFFh
28 1C0000h 1CFFFFh
27 1B0000h 1BFFFFh
26 1A0000h 1AFFFFh
25 190000h 19FFFFh
24 180000h 18FFFFh
23 170000h 17FFFFh
Table 3. Memory organization (continued)
Sector Address range
M25P64 Memory organization
21/55
22 160000h 16FFFFh
21 150000h 15FFFFh
20 140000h 14FFFFh
19 130000h 13FFFFh
18 120000h 12FFFFh
17 110000h 11FFFFh
16 100000h 10FFFFh
15 0F0000h 0FFFFFh
14 0E0000h 0EFFFFh
13 0D0000h 0DFFFFh
12 0C0000h 0CFFFFh
11 0B0000h 0BFFFFh
10 0A0000h 0AFFFFh
9 090000h 09FFFFh
8 080000h 08FFFFh
7 070000h 07FFFFh
6 060000h 06FFFFh
5 050000h 05FFFFh
4 040000h 04FFFFh
3 030000h 03FFFFh
2 020000h 02FFFFh
1 010000h 01FFFFh
0 000000h 00FFFFh
Table 3. Memory organization (continued)
Sector Address range
Instructions M25P64
22/55
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data In put (D) is sampled on the fir st rising ed ge of Seria l Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte in structi on code must be sh if ted in to the device, m ost
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR), Read Identification (RDID) or Read Electronic Signature
(RES) instruction, the shifted-in instruction sequence is followed by a data- out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequen ce is being shifted
out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select (S) must driven High when the number of clock pulses after
Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 4. Instruction set
Instruction Description One-byte instruction
code Address
bytes Dummy
bytes Data
bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at
Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to
256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
RES Read Electronic Signature 1010 1011 ABh 0 3 1 to ∞
M25P64 Instructions
23/55
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction i s entered by driving Chip Select (S) Low , sending the
instruction code, and then driving Chip Select (S) High.
Figure 8. Write Enable (WREN) instruction sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M25P64
24/55
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 9. Write Disable (WRDI) instruction sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25P64 Instructions
25/55
6.3 Read Identification (RDID)
The read identification (RDID) instruction allows to read the device identif ica tion da ta:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A unique ID code (UID) (17 bytes, of which 16 available upon customer request).(1)
The manufacturer identification is assigned b y JEDEC, and has the value 20h fo r Numonyx.
The device identification is assigned by the device man ufacturer, and indicates the memory
type in the first byte (20h), and the memory capacity of the device in the second byte (17h).
The UID contain s the length of the following dat a in the first byte (set to 10h) and 16 bytes of
the optional customized factory data (CFD) content. The CFD bytes are read-only and can
be programmed with customers data up on their demand. If the customers do not make
requests , the devices are shipped with all the CFD bytes programmed to zero (00h).
Any read identification (RDID) instruction while an erase or program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The read identification (RDID) instruction should not be issued while the device is in deep
power-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
serial data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The read identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output. When Chip Select (S) is driven High, the device is put in the
standby power mode. Once in the standby power mode, the device waits to be selected so
that it can receive, decode, and execute instructions.
1. The UID feature is available only for process technology T9HX devices, identified by process identification digit
"4" in the device marking.
Table 5. Read identification (RDID) data-out sequence
Manufacturer identification Device identification UID
Memory type Memory capacity CFD length CFD content
20h 20h 17h 10h 16 bytes
Instructions M25P64
26/55
Figure 10. Read Identification (RDID) instru ction sequence and data-out sequence
6.4 Read Status Register (RDSR)
The Read St atus Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read th e Status Register contin uo us ly, as show n in Figure 11.
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They defin e the size of the ar ea to
be software protected against Program and Erase instructions. These bits are written with
C
DQ0
S
213456789101112131415
Instruction
0
AI06809d
DQ1
Manufacturer identification
High Impedance
MSB
Device identification
MSB
15 14 13 3 2 1 0
16 17 18 28 29 30 31
MSB
UID
Table 6. Status Register format
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
M25P64 Instructions
27/55
the Write Status Register (WRSR) instruction. When one or more of the Block Protect ( BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W/VPP) signal allo w the d evice to be put in the Hard ware Pro tected mode (w hen the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M25P64
28/55
6.5 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bi t of the dat a byte has been latched in.
If not, the Write S tatus Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows
the user to set or reset the S t atus Register Write Disable (SRWD) bit in accordance with the
Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write
Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM).
The Wr ite Status Register (W RSR) instruction is not executed once the Hardware Protected
Mode (HPM) is entered.
The protection features of the de vice are summarized in Table 7.
Table 7. Protection modes
W/VPP
signal SRWD
bit Mode Write Protection of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
Unprotected are a (1)
10
Software
Protected
(SPM)
S tat us Register is W ritab le
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardwar
e
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
M25P64 Instructions
29/55
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previo usly been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect ( W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Pro tect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a W rite Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution) . As a conse quence, all the data bytes in the memor y area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect/ (W/VPP) High.
If Write Protect/ (W/VPP) is permane ntly tied High, the Hardware Protected Mode (HPM) can
never be activat ed , an d on ly the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write Status Register (WRSR) instruction sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
Instructions M25P64
30/55
6.6 Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low . The instruction code for the Read
Data Bytes (READ) instruction is followed b y a 3- byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory ca n,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during dat a outp ut. Any Read Dat a Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejecte d without havi ng
any effects on the cycle that is in progress.
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bit A23 is Don’t Care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
M25P64 Instructions
31/55
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low . The instruction code for the Read
Data Bytes at Higher S peed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory ca n,
therefore, be read wi th a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time d uring dat a output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out
sequence
1. Address bit A23 is Don’t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25P64
32/55
6.8 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Befo re it can be acce p ted , a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, th ree address bytes and at least one data byte on Serial Data Input (D) .
If the 8 least significant ad dr ess bits (A7-A0) are not all zero, all tran sm itt ed data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the ad dress whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 25 6 bytes are sent to the device, previo usly latched dat a are d iscarded and the
last 256 dat a bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus usin g several Page
Program (PP) sequences with each containing only a few Bytes (see Table 16: AC
characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Progr am cycle is in progress, the S tatus Register
may be read to check the value of the Write In Progress (WIP) bit. T h e Write In Progress
(WIP) bit is 1 during the self -t im e d Pa ge Prog ra m cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
M25P64 Instructions
33/55
Figure 15. P age Program (PP) instruction sequence
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
Instructions M25P64
34/55
6.9 Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instru ction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progr ess (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspecified
time before the cycle is completed, the W rite Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Figure 16. Sector Erase (SE) instruction sequence
1. Address bit A23 is Don’t Care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25P64 Instructions
35/55
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instructio n is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (W EL) bit is res et .
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 17. Bulk Erase (BE) instruction sequence
C
D
AI03752D
S
21 345670
Instruction
Instructions M25P64
36/55
6.11 Read Electronic Signature (RES)
The instruction is used to read, on Serial Data Output (Q), the old-style 8-bit Electronic
Signature, whose value for the M25P64 is 16h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic
Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic
Signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic
Signature, and the Read Identifier ( RDID) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge
of Serial Clock (C). Then, the old-style 8-bit Electronic Signature, stored in the memory, is
shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 18.
The Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S)
High after the Electronic Signature has been read at least once. Sending additional clock
cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic
Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the S tan dby Power mode, the device waits to be selected, so that it can receive , decode and
execute instructions.
Driving Chip Select (S) High af ter the 8-bit instruction byte h as been received by the de vice,
but before the whole of the 8-bit Electr onic Signatu re has been transmitted for the first time,
still ensures that the device is put into Standby Power mode. Once in the Standby Power
mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Figure 18. Read Electronic Signat ure (RES) instruction sequence and data-out
sequence
1. The value of the 8-bit Electronic Signature, for the M25P64, is 16h.
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
MSB
M25P64 Power-up and Power-down
37/55
7 Power-up and Power-down
At Power-up and Power-do wn, the device must not be selecte d (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
VCC(min) at Power-up, and then for a further delay of tVSL
VSS at Power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during Power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and W rite Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises abov e th e VWI threshold. However, the
correct operation of the de vice is not guaran teed if, by this time , VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the late r of:
tPUW after VCC passed the VWI threshold
tVSL after VCC passed the VCC(min) level
These values are sp ec ified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
The device is in the Standby Power mode
The Write Enab le Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacito r close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does no t respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.).
Power up se quencing for Fa st program/er ase mode: V CC should attain VCCMIN before VPPH
is applied.
Power-up and Power-down M25P64
38/55
Figure 19. Power-up timing
1. These parameters are characterized only.
Table 8. Power-Up timing and VWI threshold
Symbol Parameter Min. Max. Unit
tVSL(1) VCC(min) to S low 30 µs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI(1) Write Inhibit Voltage 1.5 2.5 V
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
tim
e
Read Access allowed Device fully
accessible
VCC(max)
M25P64 Initial delivery state
39/55
8 Initial delivery state
The device is delivered with the memory array erased: all bits are se t to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9 Maximum rating
Stressing the device outside the ratings listed in Table 9 may cause permanent da mage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the Numonyx SURE Program and other relevant quality
documents.
Table 9. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly) and the European
directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
°C
VIO Input and Output Voltage (with respect to Ground) –0.5 VCC +
0.6 V
VCC Supply Voltage –0.2 4.0 V
VPP Fast Program/Erase Voltage(2)
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices,
identified by process identification digit "4" in the device marking.
–0.2 10.0 V
VESD Electrostatic Discharge Voltage (Human Body model) (3)
3. JEDEC Std JESD22-A114A (C1=100 pF, R1 = 1500 Ω, R2 = 500 Ω).
–2000 2000 V
DC and AC parameters M25P64
40/55
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 10. Operating conditions
Symbol Parameter Min. Typ Max. Unit
VCC Supply Voltage 2.7 3.6 V
VPPH Supply Voltage on W/VPP pin for Fast Program/Erase
mode (1)
1. Avoid applying VPPH to the W/VPP pin during Bulk Erase with process technology T9HX devices,
identified by process identification digit "4" in the device marking.
8.5 9.5 V
TAAmbient Operating Temperature (grade 6)(2)
2. "Autograde 6 and Standard parts (grade 6) are tested to 85 °C, but the Autograde 6 will follow the HRCF.
–40 85 °C
TAAmbient Operating Temperature (grade 3)(3)
3. Autograde 3 is tested to 125 °C.
–40 125 °C
TAVPP Ambient Operating Temperature for Fast
Program/Erase mode 15 25 35 °C
Table 11. Data Retention and Endurance
Parameter Condition Min. Max. Unit
Program / erase cycles Grade 3, Autograde 6, Grade 6 100,000 Cycles per sector
Data retention at 55°C 20 years
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
M25P64 DC and AC parameters
41/55
Figure 20. AC measurement I/O waveform
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 20 MHz.
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
Table 13. Capacitance
Symbol Parameter Test condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0 V 8 pF
CIN Input Capacitance (other pins) VIN = 0 V 6 pF
Table 14. DC characteristics
Symbol Parameter Test condition
(in addition to those in Table 10)Min. Max. Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Grade 6 Standby Current S = VCC, VIN = VSS or VCC 50 µA
ICC1 Grade 3 100
ICC2 Grade 6 Deep Power-down Current S = VCC, VIN = VSS or VCC 10
ICC2 Grade 3 50
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 50 MHz,
Q = open 8mA
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open 4mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 20 mA
ICC6 Operating Current (SE) S = VCC 20 mA
ICC7 Operating Current (BE) S = VCC 20 mA
ICCPP Operating current for Fast
Program/Erase mo de S = VCC, VPP = VPPH 20 mA
VIL Input Low Volt age – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.2 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 µA VCC–0.2 V
DC and AC parameters M25P64
42/55
Table 15. DC characteristics process technology T9HX (1)
1. Technology T9HX devices are identified by process identification digit "4" in the device marking.
Symbol Parameter Test condition (in addition
to those in Table 10)Min Max Unit
ILI Input leakage current ± 2 µA
ILO Output leakage current ± 2 µA
ICC1 Standby current S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 µA
ICC3 Operating current (READ)
C = 0.1VCC / 0.9VCC at
75 MHz, DQ1 = open 12 mA
C = 0.1VCC / 0.9VCC at
33 MHz, DQ1 = open 4mA
ICC4 Operating current (PP) S = VCC 15 mA
ICC5 Operating current (WRSR) S = VCC 15 mA
ICC6 Operating current (SE) S = VCC 15 mA
VIL Input low voltage – 0.5 0.3VCC V
VIH Input high voltage 0.7VCC VCC+0.4 V
VOL Output low voltage IOL = 1.6 mA 0.4 V
VOH Output high voltage I OH = –100 µA VCC–0.2 V
M25P64 DC and AC parameters
43/55
1. tCH + tCL must be greater than or equal to 1/ fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one
sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256).
6. VPPH should be kept at a valid level until the program/erase operation is completed and result (success or failure) is known.
Table 16. AC characteristics
Test conditions specifie d in Table 10 and Table 12
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions: F AST_READ,
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH (1) tCLH Clock High Time 9 ns
tCL (1) tCLL Clock Low Time 9 ns
tCLCH (2) Clock Rise Time(3) (peak to peak) 0.1 V/ns
tCHCL (2) Clock Fall Time(3) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ (2) tDIS Output Disable Time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX (2) tLZ HOLD to Output Low-Z 8 ns
tHLQZ (2) tHZ HOLD to Output High-Z 8 ns
tWHSL (4) Write Protect Setup Time 20 ns
tSHWL (4) Write Protect Hold Time 100 ns
tVPPHSL(6) Enhanced Program Supply Voltage High to Chip Select Low 200 ns
tWWrite Status Register Cycle Time 5 15 ms
tPP (5) Page Program Cycle Time (256 Bytes) 1.4 5ms
Page Program Cycle Time (n Bytes) 0.4+ n*1/256
Page Program Cycle Time (VPP = VPPH) (256 Bytes) 0.35 ms
tSE Sector Erase Cycle Time 1 3 s
Sector Erase Cycle Time (VPP = VPPH)0.5s
tBE Bulk Erase Cycle Time 68 160 s
Bulk Erase Cycle T ime (VPP = VPPH)35160s
DC and AC parameters M25P64
44/55
Table 17. AC characteristics, T9HX part s (p age 1 of 2) (1)
Test conditions specifie d in Table 10 and Table 12
Symbol Alt. Parameter Min Typ(2) Max Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, SE, BE, WREN, WRDI, RDID,
RDSR, WRSR, PP D.C. 75 MHz
fRClock frequency for read instruction s D.C. 33 MHz
tCH(3) tCLH Clock High time 6 ns
tCL(2) tCLL Clock Low time 6 ns
tCLCH(4) Clock rise time(5) (peak to peak) 0.1 V/ns
tCHCL(3) Clock fall time(4) (peak to peak) 0.1 V/ns
tSLCH tCSS S active setup time (relative to C) 5 ns
tCHSL S not active hold time (relative to C) 5 ns
tDVCH tDSU Data in setup time 2 ns
tCHDX tDH Data in hold time 5 ns
tCHSH S active hold time (relative to C) 5 ns
tSHCH S not active setup time (relative to C) 5 ns
tSHSL tCSH S deselect time 80 ns
tSHQZ(3) tDIS Output disable time 8 n s
tCLQV tVClock Low to Output valid under 30 pF 8 ns
Clock Low to Output valid under 10 pF 6 ns
tCLQX tHO Output hold time 0 ns
tHLCH HOLD setup time (relative to C) 5 ns
tCHHH HOLD hold time (relative to C) 5 ns
tHHCH HOLD setup time (relative to C) 5 ns
tCHHL HOLD hold time (relative to C) 5 ns
tHHQX(3) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(3) tHZ HOLD to Output High-Z 8 ns
tWHSL(6) Write protect setup time 20 ns
tSHWL(5) Write protect hold time 100 ns
tVPPHSL(7) Enhanced program supply voltage High
(VPPH) to Chip Select Low 200 ns
tRDP(3) S High to standby mode 30 µs
tWW rite status register cycle time 1.3 15 ms
tPP(8) Page program cycle time (256 bytes) 0.8 5ms
Page program cycle time (n bytes) int(n/8) × 0.025(9)
M25P64 DC and AC parameters
45/55
Figure 21. Serial input timing
tSE Sector erase cycle time 0.7 3 s
tBE Bulk erase cycle time 68 160 s
1. Technology T9HX devices are identified by process identification digit "4" in the device marking.
2. Typical values given for TA = 25° C.
3. tCH + tCL must be greater than or equal to 1/ fC.
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
7. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is
known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
8. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
9. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Table 17. AC characteristics, T9HX part s (p age 2 of 2) (1)
Test conditions specifie d in Table 10 and Table 12
Symbol Alt. Parameter Min Typ(2) Max Unit
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
DC and AC parameters M25P64
46/55
Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1
Figure 23. Hold timing
C
D
S
Q
High Impedance
W/V
PP
tWHSL tSHWL
AI07439
b
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
M25P64 DC and AC parameters
47/55
Figure 24. Output timing
Figure 25. VPPH timing
C
Q
AI01449e
S
LSB OUT
DADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
S
C
D
W/VPP
VPPH
PP, SE, BE
ai12092
tVPPHSL
End of PP, SE or BE
(identified by WPI polling)
Package mechanical M25P64
48/55
11 Package mechanical
Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 18. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 8.00 0.3150
D2 5.16 (1)
1. D2 Max must not exceed (D – K – 2 × L).
0.2031
ddd 0.05 0.0020
E 6.00 0.2362
E2 4.80 0.1890
e1.27– –0.0500– –
K 0.82 0.0323
L 0.50 0.45 0.60 0.0197 0.0177 0.0236
L1 0.15 0.0059
N8 8
D
E
VDFPN-02
A
e
E2
D2
L
b
L1
A1 ddd
K
M25P64 Package mechanical
49/55
Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width
1. Drawing is not to scale.
Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width,
package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e1.27– –0.050– –
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
θ0° 8° 0° 8°
ddd 0.10 0.004
E
16
D
C
H
18
9
SO-H
LA1
A
ddd
A2
θ
Be
h x 45˚
Ordering Information, Standard Parts M25P64
50/55
12 Ordering Information, Standard Parts
Table 20. Ordering information scheme
Example: M25P64 – V MF 6 T P B A
Device Type
M25P = Serial Flash memory for Code Storage
Device Fu nc tion
64 = 64 Mbit (8M x 8)
Security Features (1)
– = no extra security
S– = CFD programmed with UID
Operating Voltage
V = VCC = 2.7 V to 3.6 V
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8 × 6 mm (MLP8)(2)
Device Gr ade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow.
3 = Automotive temperature range, –40 to 125 °C.(1)
Device tested with high reliability certified flow.(3)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = RoHS compliant
Lithography(4)
B = 110nm, Fab.2 Diffusion Plant
Automotive Grade
A = Automoti ve, –40 to 85 °C.
Device tested with high reliability certified flow(5)
blank = standard –40 to 85 °C device.
1. Secure options are available upon customer request.
2. Please contact your nearest Numonyx Sales Office for Automotive Package options availability.
3. Numonyx strongly recommends the use of the Automotive Grade devices (AutoGrade 6 and Grade 3) for use in an
automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask
your nearest Numonyx sales office for a copy.
4. The lithography digit is present only in the automotive parts ordering scheme.
5. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive envirnoment. The High
Reliability Certified Flow (HRCF) is described in the quality note NNEE9801. Please ask your nearest Numonyx sales
office for a copy.
M25P64 Ordering Information, Standard Parts
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For a list of available options (speed, p ackage, etc.) or for fu rther informa tion on any aspect
of this device, please co ntact your nearest Numonyx Sales Office.
The category of second- Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on th e inner box label.
Ordering Information, Automotive Parts M25P64
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13 Ordering Information, Automotive Parts
Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6
and 3) in an automotive envirnoment. The high reliability certified flow (HRCF) is described
in the quality note QNEE9801. Please ask your Numonyx sales office for a copy.
Table 21. Ordering information scheme
Example: M25P64 – V MF 6 T P B A
Device Type
M25P = Serial Flash memory for Code Storage
Device Fu nc tion
64 = 64 Mbit (8 Mbit x 8)
Security Features
– = no extra security
Operating Voltage
V = VCC = 2.7 V to 3.6 V
Package
MF = SO16 (300 mil width)
Device Gr ade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with high reliability certified flow.
3 = Automotive temperature range, –40 to 125 °C.
Device tested with high reliability certified flow.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = RoHS compliant
Lithography
B = 110nm, Fab.2 Diffusion Plant
Automotive Grade
blank = Automotive –40 to 125 °C part
A = Automotive –40 °C to 85 °C part (used ONLY in
conjunction with Device Grade 6 to distinguish the Auto
Tested Parts from the non Auto Tested parts).
M25P64 Revision history
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14 Revision history
Table 22. Docum e n t re vi si on history
Date Revision Changes
28-Apr-2003 0.1 Targe t Specification Document written in brief form
15-May-2003 0.2 Target Specification Document written in full
20-Jun-2003 0.3 8x6 MLP8 and SO16(300 mil) packages added
18-Jul-2003 0.4 tPP, tSE and tBE revised
02-Sep-2003 0.5 Voltage supply range changed
19-Sep-2003 0.6 Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added
17-Dec-2003 0.7 Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. MLP8 package
removed.
15-Nov-2004 1.0 Document status promoted from Target S pecification to Preliminary Data.
8x6 MLP8 package added. Minor wording changes.
24-Feb-2005 2.0
Deep Power-Down mode removed from datasheet (Figure 18: Read
Electronic Signature (RES) instruction sequence and data-out seque nce
modified and tRES1 and tRES2 removed from Table 16: AC
characteristics). SO16 Wide package specifications updated. End timing
line of tSHQZ modified in Figure 24: Output timing. Figures moved below
the corresponding instructions in the Instructions section.
23-Dec-2005 3.0
Updated Page Program (PP) instructions in Page Programming, Page
Program (PP) and Table 16: AC characteristics.
Fast Program/Erase mode added and Power-up specified for Fast
Program/Erase mode in Power-up and Power-down section. W pi n
changed to W/VPP. (see Write Protect/Enhanced Program supply voltage
(W/VPP) description). Note 2 inserted below Figure 26 Blank option
removed under Plating Technology.
tVPPHSL added to Table 16: AC characteristics and Figure 25: VPPH
timing inserted.
All packages are RoHS compliant.
Document status promoted from Preliminary Data to full Datasheet
status.
16-Feb-2006 4.0 VDFPN8 (MLP8) package specifications updated (see Section 11:
Package mechanical).
07-Sep-2006 5 F igure 4: Bus master and memo ry devices on the SPI bus modified.
ICC1 maximum value updated in Table 14: DC characteristics.
19-Jan-2007 6
Hardware Write Protection feature added to Features on page 1.
VCC supply voltage and VSS ground descriptions added.
Figure 4: Bus master and memory devices on the SPI bus updated and
explanatory paragraph added.
At Power-up The Write In Progress (WIP) bit is reset.
VIO max modified and TLEAD added in Table 9: Absolute maximum
ratings. Small text changes.
Note 1 added to Table 18: VDFPN8 (MLP8) 8-lead Very thin Dual Flat
Package No lead, 8 × 6 mm, package mechanical data.
Revision history M25P64
54/55
10-Dec-2007 7 Applied Numonyx branding.
30-Oct-2008 8
To provide support for the Automotive market, added the following:
– Automotive bullet to cover page;
– Grade 3 and grade 6 information to Table 10.: Operating co nditions;
–Table 11.: Data Retention and Endurance
– Automotive information to Table 20.: Ordering information scheme.
22-May-2009 9 Added a lithog raphy note to Table 20.: Orde ring information scheme;
Added information supporting 75 MHz.
2-Oct-2009 10 Introduced CFD programmed secure version.
2-Nov-2009 11 Updated ordering information.
8-March-
2010 12 Created Icc1, Grade 6 and Gra de 3 and Icc2, Grade 6 and Grade 3 in
Table 14.: DC characteristics.
Table 22. Docum e n t re vi si on history
Date Revision Changes
M25P64
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