MMBF5460LT1-D - ON Semiconductor

JFET - General Purpose

Transistor

P–Channel

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain–Gate Voltage VDG 40 Vdc

Reverse Gate–Source Voltage VGSR 40 Vdc

Forward Gate Current IGF 10 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board(1)

TA = 25°C

Derate above 25°C

PD225

1.8

mW/°C

Thermal Resistance, Junction to Ambient RJA 556 °C/W

Junction and Storage Temperature TJ, Tstg –55 to +150 °C

DEVICE MARKING

MMBF5460LT1 = 6E

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Gate–Source Breakdown Voltage (IG = 10 µAdc, VDS = 0) V(BR)GSS 40 — — Vdc

Gate Reverse Current

(VGS = 20 Vdc, VDS = 0)

(VGS = 20 Vdc, VDS = 0, TA = 100°C)

IGSS —

——

—5.0

1.0 nAdc

µAdc

Gate Source Cutoff Voltage (VDS = 15 Vdc, ID = 1.0 µAdc) VGS(off) 0.75 — 6.0 Vdc

Gate Source Voltage (VDS = 15 Vdc, ID = 0.1 mAdc) VGS 0.5 — 4.0 Vdc

ON CHARACTERISTICS

Zero–Gate–Voltage Drain Current (VDS = 15 Vdc, VGS = 0) IDSS –1.0 — –5.0 mAdc

SMALL–SIGNAL CHARACTERISTICS

Forward Transfer Admittance (VDS = 15 Vdc, VGS = 0, f = 1.0 kHz) |Yfs| 1000 — 4000 µmhos

Output Admittance (VDS = 15 Vdc, VGS = 0, f = 1.0 kHz) |yos| — — 75 µmhos

Input Capacitance (VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Ciss — 5.0 7.0 pF

Reverse Transfer Capacitance (VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Crss — 1.0 2.0 pF

1. FR–5 = 1.0  0.75  0.062 in.

ON Semiconductor

 Semiconductor Components Industries, LLC, 2001

March, 2001 – Rev. 1 1Publication Order Number:

MMBF5460LT1/D

MMBF5460LT1

CASE 318–08, STYLE 10

SOT–23 (TO–236AB)

2 SOURCE

GATE

1 DRAIN

MMBF5460LT1

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Yfs FORWARD TRANSFER ADMITTANCE ( mhos)Yfs FORWARD TRANSFER ADMITTANCE ( mhos)

DRAIN CURRENT versus GATE

SOURCE VOLTAGE FORWARD TRANSFER ADMITTANCE

versus DRAIN CURRENT

ID, DRAIN CURRENT (mA)

Yfs FORWARD TRANSFER ADMITTANCE ( mhos)

4.0 4000

0 0.2

VGS, GATE-SOURCE VOLTAGE (VOLTS)

Figure 1. VGS(off) = 2.0 Volts

1.0

ID, DRAIN CURRENT (mA)

3.5

ID, DRAIN CURRENT (mA)

10 10000

0 1.0

VGS, GATE-SOURCE VOLTAGE (VOLTS)

Figure 2. VGS(off) = 4.0 Volts

ID, DRAIN CURRENT (mA)

16 10000

VGS, GATE-SOURCE VOLTAGE (VOLTS)

Figure 3. VGS(off) = 5.0 Volts

ID, DRAIN CURRENT (mA)

Figure 4. VGS(off) = 2.0 Volts

Figure 5. VGS(off) = 4.0 Volts

Figure 6. VGS(off) = 5.0 Volts

3.0

2.5

2.0

1.5

1.0

0.5

00.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDS = 15 V

200

300

500

700

1000

2000

3000

0.2 0.3 0.5 0.7 2.0 3.0 4.0

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

00.5 1.5 2.0 2.5 3.0 3.5 4.0 500

700

1000

2000

3000

5000

7000

0.5 0.7 1.0 2.0 3.0 5.0 7.0

8.0

6.0

4.0

2.0

01.0 2.0 3.0 8.04.0 5.0 6.0 7.0 500

700

1000

2000

3000

5000

7000

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10

TA = -55°C

25°C

125°C

VDS = 15 V

f = 1.0 kHz

VDS = 15 V

TA = -55°C

25°C

125°C

VDS = 15 V

TA = -55°C

25°C

125°C

VDS = 15 V

f = 1.0 kHz

VDS = 15 V

f = 1.0 kHz

MMBF5460LT1

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1000

0.1 0.2

ID, DRAIN CURRENT (mA)

Figure 7. Output Resistance

versus Drain Current

10 0.5 1.0 2.0 5.0 10

ross, OUTPUT RESISTANCE (k ohms)

C, CAPACITANCE (pF)

VDS, DRAIN-SOURCE VOLTAGE (VOLTS)

Figure 8. Capacitance versus

Drain–Source Voltage

NF, NOISE FIGURE (dB)

RS, SOURCE RESISTANCE (k Ohms)

Figure 9. Noise Figure versus

Source Resistance

Figure 10. Equivalent Low Frequency Circuit

100

200

300

500

700

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10 20 30 40

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

1.0 10 100 1000 10,000

NOTE:

1. Graphical data is presented for dc conditions. Tabular

data i s given for pulsed conditions (Pulse Width = 630 ms,

Duty Cycle = 10%).

*Cosp is Coss in parallel with Series Combination of Ciss and Crss.

Crss

Ciss ross Coss | yfs | vi

COMMON SOURCE

y PARAMETERS FOR FREQUENCIES

BELOW 30 MHz

yis = jω Ciss

yos = jω Cosp * + 1/ross

yfs = yfs |

yrs = -jω Crss

VDS = 15 V

f = 1.0 kHz

IDSS = 3.0 mA

6.0 mA

10 mA

f = 1.0 MHz

VGS = 0

Ciss

Coss

Crss

VDS = 15 V

VGS = 0

f = 100 Hz

MMBF5460LT1

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The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature TA of 25°C,

one can calculate the power dissipation of the device which

in this case is 225 milliwatts.

INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to insure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

SOT–23

inches

0.037

0.95

0.037

0.95

0.079

2.0

0.035

0.9

0.031

0.8

SOT–23 POWER DISSIPATION

PD = TJ(max) – TA

RθJA

PD = 150°C – 25°C

556°C/W = 225 milliwatts

The power dissipation of the SOT–23 is a function of the

pad size. This can vary from the minimum pad size for

soldering to a pad size given for maximum power dissipa-

tion. Power dissipation for a surface mount device is deter-

mined b y T J(max), the maximum rated junction temperature

of the die, RθJA, the thermal resistance from the device

junction to ambient, and the operating temperature, TA.

Using the values provided on the data sheet for the SOT–23

package, PD can be calculated as follows:

The 556°C/W for the SOT–23 package assumes the use

of the recommended footprint on a glass epoxy printed

circuit board to achieve a power dissipation of 225 milli-

watts. There are other alternatives to achieving higher

power dissipation from the SOT–23 package. Another

alternative would be to use a ceramic substrate or an

aluminum core board such as Thermal Clad. Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the

rated temperature of the device. When the entire device is

heated to a high temperature, failure to complete soldering

within a short time could result in device failure. There-

fore, the following items should always be observed in

order to minimize the thermal stress to which the devices

are subjected.

•Always preheat the device.

•The delta temperature between the preheat and

soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause exces-

sive thermal shock and stress which can result in damage

to the device.

MMBF5460LT1

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PACKAGE DIMENSIONS

CASE 318–08

ISSUE AF

SOT–23 (TO–236AB)

DIM

MIN MAX MIN MAX

MILLIMETERS

0.1102 0.1197 2.80 3.04

INCHES

B0.0472 0.0551 1.20 1.40

C0.0350 0.0440 0.89 1.11

D0.0150 0.0200 0.37 0.50

G0.0701 0.0807 1.78 2.04

H0.0005 0.0040 0.013 0.100

J0.0034 0.0070 0.085 0.177

K0.0140 0.0285 0.35 0.69

L0.0350 0.0401 0.89 1.02

S0.0830 0.1039 2.10 2.64

V0.0177 0.0236 0.45 0.60

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

STYLE 10:

PIN 1. DRAIN

2. SOURCE

3. GATE

MMBF5460LT1

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Notes

MMBF5460LT1

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Notes

MMBF5460LT1

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MMBF5460LT1/D

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