TSC2302
SLAS394–JULY 2003
PROGRAMMABLE TOUCH SCREEN CONTROLLER
WITH STEREO AUDIO CODEC
FEATURES APPLICATIONS
•SPI™ Serial Interface •Personal Digital Assistants
•Touch Screen Controller •Cellular Phones
– 4-Wire Touch Screen Interface •MP3 Players
– Internal Detection of Screen Touch •Internet Appliances
– Touch Pressure Measurement •Smartphones
– Ratiometric Conversion
– Programmable 8-, 10- or 12-Bit Resolution DESCRIPTION
– Programmable Sampling Rates Up to
125 kHz The TSC2302 is a highly integrated PDA analog
– Direct Battery Measurement (0 to 6 V) interface circuit. It contains a complete 12-bit A/D
– On-Chip Temperature Measurement resistive touch screen converter (ADC) including
– Integrated Touch Screen Processor drivers, touch pressure measurement capability, and
Reduces Host CPU Interrupts and Overhead 8-bit D/A converter (DAC) output for LCD contrast
– Internal Timing Control With Programmable control. The TSC2302 offers programmable resolution
Delays and Averaging of 8, 10, and 12 bits and sampling rates up to 125 kHz
to accommodate different screen sizes. The TSC2302
•Stereo Audio Codec interfaces to the host controller through a standard SPI
– 20-Bit Delta-Sigma ADC/DAC serial interface.
– Dynamic Range: 98 dB
– Sampling Rate Up to 48 kHz The TSC2302 features a high-performance 20-bit,
– I2S Serial Interface 48-ksps stereo audio codec with highly integrated
– Stereo 16-ΩHeadphone Driver analog functionality. The audio portion of the TSC2302
contains microphone input with built-in pre-amp and
•Full Power-Down Control microphone bias circuit, an auxiliary stereo analog
•8-Bit Current Output DAC input, a mono line-level output, and a stereo
•On-Chip Crystal Oscillator headphone amplifier output. The digital audio data is
•Programmable Bass/ Midrange/ Treble EQ transferred through a standard I2S interface. A fully
Effects Processing programmable PLL for generating audio clocks from a
wide variety of system clocks is also included.
•Single 2.7-V to 3.6-V Supply
•48-pin QFN Package The TSC2302 also offers two battery measurement
inputs capable of battery voltages up to 6 V, while
operating at a supply voltage of only 2.7 V. It also has
an on-chip temperature sensor capable of reading
0.3°C resolution. The TSC2302 is available in a
48-lead QFN.
US Patent No. 6246394
SPI is a trademark of Motorola.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
cludetestingofallparameters.
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+20 to −40dB,
0.5dB Steps
Mute, 0db, 6dB, 12dB
Headphone
Driver
Headphone
Driver
Digital
Audio
Processing
Control
Interface
OSC
AVDD
VCM
AGND
RLINEIN
MICIN
LLINEIN
HPGND
HPVDD
HPR
HPL
COI
COO
SPISEL
SPIDIN
SPICLK
SPIDO
DAV
MCLK
LRCLK
I2SDIN
I2SDOUT
BCLK
PENIRQ
+20 to −40dB,
0.5dB Steps
+12dB to −
35dB
0.5dB steps
X−
X+
Y−
Y+
Touch
Panel
Drivers
Temp
Sensor
VBAT2
VBAT1
AUX2
AUX1
Battery
Monitor
Battery
Monitor
ADC
SAR
Control
Logic
and
SPI
Interface
DAC
DACOUT
DACSET
Internal 2.5V/
1.25V Reference
VREFIN
MONO+
Digital Gain
0 to −63.5dB
0.5dB Steps
Digital Gain
0 to −63.5dB
0.5dB Steps
POL
RESET
VREF+
VREF−
GPIO_5/CLKO
DGND
DVDD
AFILTR AFILTL
AVDD−1V
MICBIAS
30 kΩ
20 kΩ
I2S
Interface
Σ−∆
ADC
Σ−∆
ADC
317 Ω
317 Ω
Σ
Σ−∆
DAC
Σ
Σ
Σ
Σ−∆
DAC
and PLL
TSC2302
SLAS394–JULY 2003
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TSC2302
SLAS394–JULY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE OPERATING ORDERING TRANSPORT MEDIA
DESIGNATOR TEMPERATURE NUMBER QUANTITY
RANGE
TSC2302IRGZ Trays, 308
TSC2302I QFN-48 RGZ -40°C to +85°CTSC2302IRGZR Tape and reel, 2000
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TSC2302
Supply voltage: AVDD, HPVDD, DVDD 4 V
Ground voltage differences: AGND, DGND ±0.1 V
Digital input voltage -0.3 V to (DVDD + 0.3 V)
Analog input voltage -0.3 V to (AVDD + 0.3 V)
Ambient temperature under bias, TA-40°C to 125°C
Storage temperature, Tstg -55°C to 150°C
Junction temperature, TJ150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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TSC2302
SLAS394–JULY 2003
ELECTRICAL CHARACTERISTICS
At 25°C, HPVDD = AVDD = DVDD = +3.3 V, VREF = External 2.5 V, unless otherwise noted.
TSC2302
PARAMETER CONDITIONS UNITS
MIN TYP MAX
AUXILARY ANALOG INPUTS
Input voltage range 0 +VREFIN V
Input capacitance 25 ρF
Input leakage current 1 µA
BATTERY MONITOR INPUT
Input voltage range 0 6.0 V
Input capacitance 25 ρF
Input leakage current ±1 µA
TEMPERATURE MEASUREMENT
Temperature range -40 +85 °C
Temperature resolution 0.3 °C
Accuracy ±2°C
TOUCH SCREEN A/D CONVERTER
Resolution Programmable: 8-, 10-,12-Bits 12 Bits
No missing codes 12-bit resolution 10 Bits
Integral linearity ±6 LSB
Offset error ±6 LSB
Gain error ±6 LSB
µV
Noise <300 RMS
AUDIO CODEC
Sampling frequency 48 kHz
AUDIO I/O
0.15*
Audio in Line, Mic inputs 0.65* AVDD V
AVDD
0.15*
Audio out HP outputs 0.65* AVDD V
AVDD
ADC performance measured using Fs
AUDIO ADC = 48 kHz
Signal-to-noise ratio, A-weighted No input 80 88 dB
Total harmonic distortion 1 kHz, -0.5 dB input -70 -60 dB
0.18*
Full-scale input voltage Vrms
AVDD
Transition band 0.45Fs 0.55Fs Hz
Stop band 0.55Fs 127Fs Hz
Stop band rejection 70dB
DAC performance measured at HP
AUDIO DAC Outputs using Fs = 48 kHz
0.18*
Full-scale output voltage Vrms
AVDD
Frequency response 20 0.45Fs Hz
Transition band 0.45Fs 0.55Fs Hz
Stop band 0.55Fs 3.5Fs Hz
Stop band rejection 65 dB
DAC playback through headphone
HEADPHONE DRIVER driver
Output power per channel R = 32 Ω13 mW
R = 16 Ω27 mW
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TSC2302
SLAS394–JULY 2003
ELECTRICAL CHARACTERISTICS (continued)
At 25°C, HPVDD = AVDD = DVDD = +3.3 V, VREF = External 2.5 V, unless otherwise noted.
TSC2302
PARAMETER CONDITIONS UNITS
MIN TYP MAX
R = 16 ΩVDD = 3.6V 31 mW
Signal-to-noise ratio, A-weighted 85 96 dB
Total harmonic distortion R = 32 Ω1-kHz, 0-dB input -83 -70 dB
R = 16 Ω1-kHz, -3-dB input -77 dB
D/A CONVERTER
Output current range Measured with ARNG floating 0.75 1.10 mA
Resolution 8 Bits
VOLTAGE REFERENCE
Voltage range Internal 2.5 V 2.34 2.49 2.64 V
ppm/°
Reference drift 50 C
External reference input 1 VDD V
Current drain 20 µA
DIGITAL INPUT / OUTPUT
Internal clock frequency 8.8 MHz
Logic family CMOS
Logic level: VIH IIH = 5µA 0.7VDD V
VIL IIL = 5µA -0.3 0.3VDD V
0.8*
VOH IOH = 2 TTL loads V
DVDD
VOL IOL = 2 TTL loads 0.2* DVDD V
POWER SUPPLY REQUIREMENTS
Power supply voltage
DVDD, AVDD, HPVDD 2.7 3.6 V
Quiescent current (1)
Touch screen only 1-kHz SAR sample rate, external Vref 14 µA
Touch screen only 20-kHz SAR sample rate, internal Vref 1.7 mA
Stereo playback only 44.1-kHz Playback, VDD = 2.7V 10 mA
Voice record only Mono 8-kHz record, VDD = 2.7V 5.8 mA
Power down Audio fully powered down .05 µA
(1) For more details on power consumption, see the Audio Codec section of the description overview.
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AUX1
HPVDD
Y+
X+
Y−
X−
HPGND
HPR
HPL
AVDD
AGND
MONO+
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
VREF−
VREF+
AFILTL
AFILTR
VCM
MICBIAS
MICIN
LLINEIN
NC
NC
NC
RLINEIN
SCLK
MOSI
MISO
DAV
COI
COO
MCLK
BCLK
LRCLK
I2SDIN
I2SDOUT
RESET
AUX2
VBAT1
VBAT2
VREFIN
ARNG
AOUT
PENIRQ
POL
GPIO_5/CLKO
DGND
SS
NC − No internal connection
DVDD
TSC2302
SLAS394–JULY 2003
PIN ASSIGNMENT
(BOTTOM VIEW)
PIN DESCRIPTION
PIN I/O NAME DESCRIPTION
1 I AUX2 SAR auxillary analog input 2
2 I VBAT1 Battery monitor input 1
3 I VBAT2 Battery monitor input 2
4 I/O VREFIN SAR reference voltage
5 ARNG DAC analog output range set
6 O AOUT Analog output current from DAC
7 O PENIRQ Pen interrupt
8 I POL SPI clock polarity
9 I/O GPIO_5/CLKO General-purpose input/output pin/buffered oscillator clock out
10 I DVDD Digital voltage supply
11 I DGND Digital ground
12 I SS Slave select input (active low). Data is not clocked into MOSI unless SS is
low. When SS is high, MISO is high impedance.
13 I SCLK SPI clock input
14 I MOSI SPI data input. Data is clocked in at SCLK rising edge
15 O MISO SPI data output. Data is clocked out at SCLK falling edge. High impedance
when SS is high.
16 O DAV Data available (active low).
17 I COI Crystal input
18 O COO Crystal output
19 I MCLK Master clock input for audio codec
20 I BCLK I2S bit clock
21 I LRCLK I2S left/right clock
22 I I2SDIN I2S serial data in
23 O I2SDOUT I2S serial data out
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ttd
ta
tsck
tLead tLag
twsck twsck tr
tf
tvtho tdis
thi
tsu
MSB OUT BIT . . . 1 LSB OUT
MSB IN BIT . . . 1 LSB IN
SS
SCLK
MISO
MOSI
TSC2302
SLAS394–JULY 2003
PIN DESCRIPTION (continued)
PIN I/O NAME DESCRIPTION
24 I RESET Device reset (active high)
25 NC NC No connection
26 NC NC No connection
27 NC NC No connection
28 I LLINEIN Left-channel analog input to audio codec
29 I RLINEIN Right-channel analog input to audio codec
30 I MICIN Analog input from microphone
31 O MICBIAS Bias voltage output
32 O VCM Common-mode voltage bypass capacitor
33 O AFILTR Right-channel audio ADC antialiasing filter capacitor
34 O AFILTL Left-channel audio ADC antialiasing filter capacitor
35 I VREF+ Audio codec positive reference voltage
36 I VREF- Audio codec negative reference voltage
37 O MONO+ Mono differential output
38 I AGND Analog ground
39 I AVDD Analog supply
40 O HPL Headphone amplifier left output
41 O HPR Headphone amplifier right output
42 I HPGND Analog ground for headphone amplifier and touch screen circuitry
43 I X- X- position input
44 I Y- Y- position input
45 I X+ X+ position input
46 I Y+ Y+ position input
47 I HPVDD Analog supply for headphone amplifier and touch screen circuitry
48 I AUX1 SAR auxiliary analog input 1
TIMING DIAGRAM
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TSC2302
SLAS394–JULY 2003
TIMING CHARACTERISTICS (1) (2)
All specifications typical at -40°C to +85°C, +VDD = +2.7 V, POL = 1
PARAMETER SYMBOL MIN MAX UNITS
SCLK period tsck 30 ns
Enable lead time tLead 15 ns
Enable lag time tLag 15 ns
Sequential transfer delay ttd 30 ns
Data setup time tsu 10 ns
Data hold time (inputs) thi 10 ns
Data hold time (outputs) tho 0 ns
Slave access time ta15 ns
Slave DOUT disable time tdis 15 ns
Data valid tv10 ns
Rise time tr30 ns
Fall time tf30 ns
(1) All input signals are specified with tR= tF= 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagram, above.
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–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–50 050 100
Change in Error (LSB)
Temperature (C)
Idd (mA)
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
–50 050 100
Temperature (C)
Idd (mA)Idd (mA)
Change in Error (LSB)
–2
–1.5
–1
–0.5
0
0.5
1
–50 050 100
Temperature (C)
On–Resistance (Ohms)
4
4.5
5
5.5
6
6.5
–50 050 100
Temperature (C)
1.193
1.194
1.195
1.196
1.197
1.198
1.199
1.2
1.201
1.202
–50 050 100
Vref (V)
Temperature (C)
8.4
8.5
8.6
8.7
8.8
8.9
9
9.1
–50 050 100
osc
Temperature (C)Temperature (C)
Internal Oscillator Frequency
500
600
700
800
900
–60 –40 –20 0 20 40 60 80 100
Temp2 Voltage (mV)
Temperature (C)
2.46
2.465
2.47
2.475
2.48
2.485
2.49
2.495
2.5
–50 050 1001.225
1.23
1.235
1.24
1.245
1.25
1.255
1.26
1.265
1.27
1.275
Vref (V)
Temperature (C)
Temperature (C)
DAC Output Current (mA)
0.9
0.95
1
1.05
1.1
1.15
1.2
–50 050 100
TSC2302
SLAS394–JULY 2003
TYPICAL CHARACTERISTICS
At TA= +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
CHANGE IN GAIN ERROR CHANGE IN OFFSET ERROR CONVERSION SUPPLY CURRENT
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 1. Figure 2. Figure 3.
TOUCH SCREEN DRIVER INTERNAL OSCILLATOR
ON-RESISTANCE INTERNAL 1.25-V REFERENCE FREQUENCY
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 4. Figure 5. Figure 6.
INTERNAL 2.5-V REFERENCE DAC OUTPUT CURRENT TEMP2 DIODE VOLTAGE
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 7. Figure 8. Figure 9.
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400
450
500
550
600
650
700
750
–50 050 100
Temp1 Voltage (mV)
Temperature (C)
2.085
2.09
2.095
2.1
2.105
2.11
2.115
2.12
2.125
2.13
–50 050 100
Temperature (C)
Vmicbias (V)
–72.000
–71.000
–70.000
–69.000
–68.000
–67.000
–66.000
–65.000
–64.000
–63.000
–62.000
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
83
84
85
86
87
88
89
90
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
93
94
95
96
97
98
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
93
94
95
96
97
98
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
96
97
98
99
100
101
102
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
–103.0
–102.0
–101.0
–100.0
–99.0
–98.0
–60 –40 –20 0 20 40 60 80 100
THD (dB)
Temperature (C)
–102
–101
–100
–99
–98
–97
–96
–95
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
TSC2302
SLAS394–JULY 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
TEMP1 DIODE VOLTAGE MICBIAS THD OF ADC (LINEIN)
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 10. Figure 11. Figure 12.
THD OF DAC (HP DRIVER), 32-Ω
SNR OF ADC (LINEIN) LOAD SNR OF DAC (HP DRIVER)
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 13. Figure 14. Figure 15.
THD OF BYPASS PATH SNR OF BYPASS PATH THD OF MONO PATH
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 16. Figure 17. Figure 18.
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Vref (V)
Vdd (V)
2.483
2.48375
2.4845
2.48525
2.486
2.48675
2.4875
2.5 3 3.5
96
97
98
99
100
–60 –40 –20 0 20 40 60 80 100
SNR (dB)
Temperature (C)
1.1999
1.2
1.2001
1.2002
1.2003
1.2004
1.2005
2.5 3 3.5
Vref (V)
Vdd (V)
609
609.2
609.4
609.6
609.8
610
610.2
610.4
610.6
610.8
611
2.5 3 3.5
Temp1 Voltage (mV)
Vdd (V)
4.9
4.95
5
5.05
5.1
5.15
5.2
5.25
5.3
5.35
2.5 3 3.5
On–Resistance (Ohms)
Vdd (V)
720
722
724
726
728
730
2.5 33.5
Temp2 Voltage (mV)
Vdd (V)
0
0.075
0.15
0.225
0.3
0.375
0.45
2.5 3 3.5
Supply Current (uA)
Vdd (V)
1.0836
1.0857
1.0878
1.0899
2.5 3 3.5
DAC Output Current (mA)
Vdd (V)
8.5
8.6
8.7
8.8
8.9
9
2.5 3 3.5
Internal Oscillator Frequency (MHz)
Vdd (V)
TSC2302
SLAS394–JULY 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
SNR OF MONO PATH 1.25-V REFERENCE 2.5-V INTERNAL REFERENCE
vs vs vs
TEMPERATURE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 19. Figure 20. Figure 21.
SWITCH ON-RESISTANCE TEMP2 DIODE VOLTAGE TEMP1 DIODE VOLTAGE
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 22. Figure 23. Figure 24.
INTERNAL OSCILLATOR
FREQUENCY DAC MAXIMUM CURRENT PD SUPPLY CURRENT
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 25. Figure 26. Figure 27.
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1
1.25
1.5
1.75
2
2.5 33.5
Idd_Total (mA)
Vdd (V)
3
3.25
3.5
3.75
4
4.25
4.5
2.5 3 3.5
INL_Max (LSB)
Vdd (V)
–3
–2.75
–2.5
–2.25
–2
–1.75
–1.5
2.5 3 3.5
INL_Min (LSB)
Vdd (V)
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.5 3 3.5
Vmicbias (V)
Vdd (V)
–77
–76
–75
–74
–73
–72
–71
–70
–69
–68
–67
2.5 3 3.5
THD (dB)
Vdd (V)
83
84
85
86
87
88
89
90
2.5 3 3.5
SNR (dB)
Vdd (V)
92
93
94
95
96
97
98
99
2.5 3 3.5
SNR (dB)
Vdd (V)
–85
–84
–83
–82
–81
–80
–79
–78
2.5 3 3.5
THD (dB)
Vdd (V)
–103
–102
–101
–100
–99
–98
2.5 3 3.5
THD (dB)
Vdd (V)
TSC2302
SLAS394–JULY 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
INL MAXIMUM INL MINIMUM CONVERSION SUPPLY CURRENT
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 28. Figure 29. Figure 30.
MICBIAS THD OF ADC (LINEIN) SNR OF ADC (LINEIN)
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 31. Figure 32. Figure 33.
THD OF DAC (HP DRIVER) SNR OF DAC (HP DRIVER) THD OF BYPASS PATH
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 34. Figure 35. Figure 36.
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96
97
98
99
100
101
102
2.5 33.5
SNR (dB)
Vdd (V)
96
97
98
99
100
101
102
2.5 3 3.5
SNR (dB)
Vdd (V)
–100
–99
–98
–97
–96
–95
2.5 3 3.5
THD (dB)
Vdd (V)
TSC2302
SLAS394–JULY 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
SNR OF BYPASS PATH THD OF MONO PATH SNR OF MONO PATH
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 37. Figure 38. Figure 39.
OVERVIEW
The TSC2302 is an analog interface circuit for human interface devices. A register-based architecture eases
integration with microprocessor-based systems through a standard SPI bus. All peripheral functions are
controlled through the registers and onboard state machines.
The TSC2302 consists of the following blocks (refer to the block diagram on p. 2):
•Touch screen interface
•Battery monitors
•Auxiliary inputs
•Temperature monitor
•Current output digital-to-analog converter
•Audio codec and signal processing
Communication to the TSC2302 is via a standard SPI serial interface. This interface requires that the slave select
signal be driven low to communicate with the TSC2302. Data is then shifted into or out of the TSC2302 under
control of the host microprocessor, which also provides the serial data clock.
Control of the TSC2302 and its functions is accomplished by writing to different registers in the TSC2302. A
simple command protocol is used to address the 16-bit registers. Registers control the operation of the touch
screen A/D converter, and audio codec.
The result of measurements made are placed in the TSC2302 memory map and can be read by the host at any
time. Three signals are available from the TSC2302 to indicate that data is available for the host to read. The
DAV output indicates that an analog-to-digital conversion has completed and that data is available. The PENIRQ
output indicates that a touch has been detected on the touch screen.
For a typical application of the TSC2302, see the TSC2301 data sheet (SLAS371).
DETAILED DESCRIPTION
OPERATION - TOUCH SCREEN
A resistive touch screen works by applying a voltage across a resistor network and measuring the change in
resistance at a given point on the matrix where a screen is touched by an input stylus, pen, or finger. The change
in the resistance ratio marks the location on the touch screen.
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Conductive Bar
Transparent Conductor (ITO)
Bottom Side
X+
X–
Y+
Y–
Transparent Conductor (ITO)
Top Side
Insulating Material (Glass)
ITO= Indium Tin Oxide
Silver Ink
RTOUCH RX–plateX–position
4096 Z2
Z11
(1)
RTOUCH RX–plate X–position
4096 4096
Z11RY–plate1Y–position
4096
(2)
TSC2302
SLAS394–JULY 2003
DETAILED DESCRIPTION (continued)
The TSC2302 supports the resistive 4-wire configuration. The circuit determines the location in two coordinate
pair dimensions, although a third dimension can be added for measuring pressure.
The 4-Wire Touch Screen Coordinate Pair Measurement
A 4-wire touch screen is constructed as shown in Figure 40. It consists of two transparent resistive layers
separated by insulating spacers.
Figure 40. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.
The ADC converts the voltage measured at the point where the panel is touched. A measurement of the Y
position of the pointing device is made by connecting the X+ input to the ADC input, driving Y+ to +VDD and Y-
to GND using switches internal to the TSC2302, and digitizing the voltage seen at the X+ input. The voltage
measured is determined by the voltage divider developed at the point of touch. For this measurement, the
horizontal panel resistance in the X+ lead does not affect the conversion, due to the high input impedance of the
ADC.
Voltage is then applied to the other axis, and the ADC converts the voltage representing the X position on the
screen. This provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2302. To determine pen or finger touch, the
pressure of the touch needs to be determined. Generally, it is not necessary to have very high performance for
this test, therefore, the 8-bit resolution mode is recommended (however, calculations are shown with the 12-bit
resolution mode). There are several different ways of performing this measurement. The TSC2302 supports two
methods. The first method requires knowing the X-plate resistance, measurement of the X-position, and two
additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 41). Using Equation 1
calculates the touch resistance:
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-position and
Y-position, and Z1. Using Equation 2 also calculates the touch resistance:
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Z2–Position
Touch
X+
X–
Y+
Y–
X-Position
Touch
Measure X-Position
Measure Z1-Position X+
X–
Z-Position
Touch
Y+
Y–
X+
X–
Y+
Y– Measure Z2-Position
TSC2302
SLAS394–JULY 2003
Figure 41. Pressure Measurement
When the touch panel is pressed or touched, and the drivers to the panel are turned on, the voltage across the
touch panel often overshoots and then slowly settles (decay) down to a stable dc value. This is due to
mechanical bouncing, which is caused by vibration of the top layer sheet of the touch panel when the panel is
pressed. This settling time must be accounted for, or else the converted value is in error. Therefore, a delay must
be introduced between the time the driver for a particular measurement is turned on, and the time measurement
is made.
In some applications, external capacitors may be required across the touch screen for filtering noise picked up by
the touch screen, i.e. noise generated by the LCD panel or back-light circuitry. The value of these capacitors
provides a low-pass filter to reduce the noise, but causes an additional settling time requirement when the panel
is touched.
Several solutions to this problem are available in the TSC2302. A programmable delay time is available which
sets the delay between turning the drivers on and making a conversion. This is referred to as the panel voltage
stabilization time, and is used in some of the modes available in the TSC2302. In other modes, the TSC2302 can
be commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the
command is issued to perform a conversion.
The TSC2302 touch screen interface can measure position (X,Y) and pressure (Z). Determination of these
coordinates is possible under three different modes of the A/D converter: conversion controlled by the TSC2302,
initiated by detection of a touch; conversion controlled by the TSC2302, initiated by the host responding to the
PENIRQ signal; or conversion completely controlled by the host processor.
A/D CONVERTER
The analog inputs of the TSC2302 are shown in Figure 42. The analog inputs (X, Y, and Z touch panel
coordinates, battery voltage monitors, chip temperature, and auxiliary inputs) are provided via a multiplexer to the
successive approximation register (SAR) analog-to-digital converter (ADC). The A/D architecture is based on
capacitive redistribution architecture, which inherently includes a sample/hold function.
A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power
and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the
converter and a differential reference input architecture, it is possible to negate errors caused by the driver switch
on-resistances.
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PENIRQ +VCC VREF
TEMP1 TEMP0
Ref ON/OFF
1.25/2.5 V
Reference
+IN
–IN
+REF
–REF
Converter
2.5 kΩ
5.0 kΩ
5.0 kΩ
7.5 kΩ
Battery
on Battery
on
GND
IN2
IN1
VBAT2
VBAT1
Y–
Y+
X–
X+
0V
11...111
11...110
11...101
00...010
00...001
00...000
1 LSB
Output Code
Input Voltage - A
FS = Full-Scale Voltage = VREF
1 LSB = VREF /4096
FS - 1 LSB
TSC2302
SLAS394–JULY 2003
The ADC is controlled by an ADC control register. Several modes of operation are possible, depending upon the
bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate may
all be programmed through this register. These modes are outlined in the sections below for each type of analog
input. The results of conversions made are stored in the appropriate result register.
Figure 42. Simplified Diagram of the Touch Screen Analog Input Section
Data Format
The TSC2302 output data is in straight binary format as shown in Figure 43. This figure shows the ideal output
code for the given input voltage and does not include the effects of offset, gain, or noise.
Figure 43. Ideal Input Voltages and Output Codes
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TSC2302
SLAS394–JULY 2003
Reference
The TSC2302 has an internal voltage reference that can be set to 1.2 V or 2.5 V, through the reference control
register. This reference can also be set to automatically power down between conversions to save power, or
remain on to reduce settling time.
The internal reference voltage is only used in the single-ended mode for battery monitoring, temperature
measurement, and for utilizing the auxiliary inputs. Optimal touch screen performance is achieved when using a
ratiometric conversion, thus all touch screen measurements are done automatically in the differential mode.
An external reference can also be applied to the VREFIN pin, and the internal reference can be turned off.
Variable Resolution
The TSC2302 provides three different resolutions for the ADC: 8, 10, or 12 bits. Lower resolutions are often
practical for measurements such as touch pressure. Performing the conversions at lower resolution reduces the
amount of time it takes for the ADC to complete its conversion process, which lowers power consumption.
Conversion Clock and Conversion Time
The TSC2302 contains an internal 8-MHz clock, which is used to drive the state machines inside the device that
perform the many functions of the part. This clock is divided down to generate the actual ADC conversion clock.
The division ratio for this clock is set in the ADC control register. The ability to change the conversion clock rate
allows the user to choose the optimal value for resolution, speed, and power. If the 8-MHz clock is used directly,
the ADC is limited to 8-bit resolution; using higher resolutions at this speed does not result in accurate
conversions. Using a 4-MHz conversion clock is suitable for 10-bit resolution; 12-bit resolution requires that the
conversion clock run at 1 or 2 MHz.
Regardless of the conversion clock speed, the internal clock runs nominally at 8 MHz. The conversion time of the
TSC2302 is dependent upon several functions. While the conversion clock speed plays an important role in the
time it takes for a conversion to complete, a certain number of internal clock cycles is needed for proper
sampling of the signal. Moreover, additional times, such as the panel voltage stabilization time, can add
significantly to the time it takes to perform a conversion. Conversion time can vary depending upon the mode in
which the TSC2302 is used. Throughout this data sheet, internal and conversion clock cycles are used to
describe the times that many functions take. In considering the total system design, these times must be taken
into account by the user.
Touch Detect
The pen interrupt (PENIRQ) output function is detailed in Figure 44. While in the touch screen monitoring mode,
the Y- driver is ON and connected to GND, the X+ input is connected through a pullup resistor to VDD, and the
PENIRQ output reflects the state of the X+ input. When the panel is touched, the X+ input is pulled to ground
through the touch screen and PENIRQ output goes LOW due to the current path through the panel to GND,
initiating an interrupt to the processor. During the measurement cycles for X- and Y-position, the X+ input is
disconnected from PENIRQ to eliminate any leakage current from the pullup resistor that might flow through the
touch screen, thus causing no errors.
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High Except
When TEMP1,
TEMP2 Activated
Internal
50 k
VDD
PENIRQ
VDD
TEMP1 TEMP2
TEMP DIODE
Y+ or X+ Drivers on,
or TEMP1, TEMP2
Measurements Activated
Y+
X+
Y– ON
TSC2302
SLAS394–JULY 2003
Figure 44. PENIRQ Functional Block Diagram
In modes where the TSC2302 needs to detect if the screen is still touched (for example, when doing a
PENIRQ-initiated X, Y, and Z conversion), the TSC2302 must reconnect the drivers so that the 50-kΩresistor is
connected again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs
cause a long delay time, and may prevent the detection from occurring correctly. To prevent this, the TSC2302
has a circuit which allows any screen capacitance to be precharged through a low-resistance connection to VDD,
so that the pullup resistor doesn’t have to be the only source for the charging current. The time allowed for this
precharge, as well as the time needed to sense if the screen is still touched, can be set in the configuration
control register. All other drivers (X-,Y+, Y-) are off during precharging.
This does point out, however, the need to use the minimum capacitor values possible on the touch screen inputs.
These capacitors may be needed to reduce noise, but too large a value increases the needed precharge and
sense times, as well as panel voltage stabilization time.
In self-controlled modes where the TSC2302 automatically performs conversions when it detects a pen touch, it
is generally not necessary for the host processor to monitor PENIRQ. Instead, the host must monitor DAV, which
goes low when data is available in the appropriate data register, and returns high when all new data has been
read back by the host.
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TSC2302
SLAS394–JULY 2003
DIGITAL INTERFACE
The TSC2302 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master
generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start
and synchronize transmissions.
A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the
slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts
out on the MISO pin to the master shift register.
When the POL pin of the TSC2302 is tied high (POL=1), the idle state of the serial clock for the TSC2302 is low,
which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). When the
POL pin of the TSC2302 is tied low (POL=0), the idle state of the serial clock is high, which corresponds to a
clock polarity setting of 1 (typical microprocessor SPI control bit CPOL = 1). The TSC2302 interface is designed
so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins
driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can
remain low between transmissions; however, the TSC2302 only interprets the first 16 bits transmitted after the
falling edge of SS as a command word, and the next 16 bits as a data word only if writing to a register. Reserved
register bits should be written to their default values (see Table 3).
TSC2302 Communication Protocol
The TSC2302 is entirely controlled by registers. Reading and writing these registers is accomplished by the use
of a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown in
the TSC2302 command word bit register.
The command word begins with an R/W bit, which specifies the direction of data flow on the serial bus. The
following 4 bits specify the page of memory this command is directed to, as shown in Table 1. The next six bits
specify the register address on that page of memory to which the data is directed. The last five bits are reserved
for future use.
Table 1. Page Addressing
PG3 PG2 PG1 PG0 PAGE ADDRESSED
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 reserved
0 1 0 0 reserved
0 1 0 1 reserved
0 1 1 0 reserved
0 1 1 1 reserved
1 0 0 0 reserved
1 0 0 1 reserved
1 0 1 0 reserved
1 0 1 1 reserved
1 1 0 0 reserved
1 1 0 1 reserved
1 1 1 0 reserved
1 1 1 1 reserved
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TSC2302
SLAS394–JULY 2003
To read all the first page of memory, for example, the host processor must send the TSC2302 the command
0x8000 - this specifies a read operation beginning at page 0, address 0. The processor can then start clocking
data out of the TSC2302. The TSC2302 automatically increments its address pointer to the end of the page; if
the host processor continues clocking data out past the end of a page, the TSC2302 simply sends back the
value 0xFFFF.
Continuous writing is generally not recommended for the control registers, but for the coefficients of bass-boost
filter coefficient registers, continuous writing works. Writing to these registers consists of the processor writing the
command 0x10E0, which specifies a write operation, with PG1 set to 1, and the ADDR bits set to 07h. This
results in the address pointer pointing at the location of the first bass-boost coefficient in memory see
Table 2(Page 2). See the section on the TSC2302 memory map for details of register locations
TSC2302 COMMAND WORD
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
R/W* PG3 PG2 PG1 PG0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 X X X X X
Figure 45 shows an example of a complete data transaction between the host processor and the TSC2302.
Figure 45. Write and Read Operation of TSC2302 Interface, POL = 1
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TSC2302
SLAS394–JULY 2003
TSC2302 MEMORY MAP
The TSC2302 has several 16-bit registers that allow control of the device as well as providing a location for
results from the TSC2302 to be stored until read by the host microprocessor. These registers are separated into
three pages of memory in the TSC2302: a data page (Page 0), a control page (Page 1), and an audio control
page (Page 2). The memory map is shown in Table 2.
Table 2. TSC2302 Memory Map
PAGE 0: DATA REGISTERS PAGE 1: CONTROL REGISTERS PAGE 2: AUDIO CONTROL REGISTERS
ADDR REGISTER ADDR REGISTER ADDR REGISTER
00 X 00 ADC 00 Audio control
01 Y 01 reserved 01 ADC volume control
02 Z1 02 DACCTL 02 DAC volume control
03 Z2 03 REF 03 Analog audio bypass volume control
04 reserved 04 RESET 04 Audio control 2
05 BAT1 05 CONFIG 05 Audio power/ crystal oscillator control
06 BAT2 06 CONFIG2 06 GPIO control
07 AUX1 07 reserved 07 DAC bass-boost filter coefficients
08 AUX2 08 reserved 08 DAC bass-boost filter coefficients
09 TEMP1 09 reserved 09 DAC bass-boost filter coefficients
0A TEMP2 0A reserved 0A DAC bass-boost filter coefficients
0B DAC 0B reserved 0B DAC bass-boost filter coefficients
0C reserved 0C reserved 0C DAC bass-boost filter coefficients
0D reserved 0D reserved 0D DAC bass-boost filter coefficients
0E reserved 0E reserved 0E DAC bass-boost filter coefficients
0F reserved 0F reserved 0F DAC bass-boost filter coefficients
10 reserved 10 reserved 10 DAC bass-boost filter coefficients
11 reserved 11 reserved 11 DAC bass-boost filter coefficients
12 reserved 12 reserved 12 DAC bass-boost filter coefficients
13 reserved 13 reserved 13 DAC bass-boost filter coefficients
14 reserved 14 reserved 14 DAC bass-boost filter coefficients
15 reserved 15 reserved 15 DAC bass-boost filter coefficients
16 reserved 16 reserved 16 DAC bass-boost filter coefficients
17 reserved 17 reserved 17 DAC bass-boost filter coefficients
18 reserved 18 reserved 18 DAC bass-boost filter coefficients
19 reserved 19 reserved 19 DAC bass-boost filter coefficients
1A reserved 1A reserved 1A DAC bass-boost filter coefficients
1B reserved 1B reserved 1B reserved
1C reserved 1C reserved 1C reserved
1D reserved 1D reserved 1D reserved
1E reserved 1E reserved 1E reserved
1F reserved 1F reserved 1F reserved
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TSC2302
SLAS394–JULY 2003
TSC2302 REGISTER OVERVIEW
Table 3. Register Summary for TSC2302
PAGE ADDR REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET
(HEX) NAME VALUE
(HEX)
0 00 X 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 01 Y 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 02 Z1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 03 Z2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 04 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
0 05 BAT1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 06 BAT2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 07 AUX1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 08 AUX2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 09 TEMP1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 0A TEMP2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
0 0B DAC 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0080
0 0C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 0D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 0E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 0F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 10 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 11 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 12 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 13 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 14 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 15 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 16 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 17 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 18 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 19 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1A reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1B reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
0 1F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 00 ADC PSM STS AD3 AD2 AD1 AD0 RS1 RS0 AV1 AV0 CL1 CL0 PV2 PV1 PV0 0 4000
1 01 reserved 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000
1 02 DACCTL DPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000
1 03 REF 0 0 0 0 0 0 0 0 0 0 0 INT DL1 DL0 PDN RFV 0002
1 04 RESET 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 FFFF
1 05 CONFIG 1 1 1 1 1 1 1 1 1 1 PR2 PR1 PR0 SN2 SN1 SN0 FFC0
1 06 CONFIG2 SDA/ C1 PLL PCT PDC PDC PDC PDC A3 A2 A1 A0 N3 N2 N1 N0 FFFF
V O E 3 2 1 0
1 07 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 08 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 09 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0A reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0B reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 0E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
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TSC2302
SLAS394–JULY 2003
Register Summary for TSC2302 (continued)
PAGE ADDR REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET
(HEX) NAME VALUE
(HEX)
1 0F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 10 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
1 11 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 12 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 13 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 14 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 15 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 16 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 17 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 18 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 19 reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1A reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1B reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1D reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1E reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
1 1F reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
2 00 AUDCNTL HPF HPF INML INML INM INM MIC MIC MCL MCL I2SF I2SF I2SF I2SF I2SF I2SF C003
1 0 1 0 R1 R0 G1 G0 K1 K0 S3 S2 S1 S0 M1 M0
2 01 ADCVOL ADM ADV ADV ADV ADV ADV ADV ADV ADM ADV ADV ADV ADV ADV ADV ADV D7D7
UL L6 L5 L4 L3 L2 L1 L0 UR R6 R5 R4 R3 R2 R1 R0
2 02 DACVOL DAM DAV DAV DAV DAV DAV DAV DAV DAM DAV DAV DAV DAV DAV DAV DAV FFFF
UL L6 L5 L4 L3 L2 L1 L0 UR R6 R5 R4 R3 R2 R1 R0
2 03 BPVOL BPM BPV BPV BPV BPV BPV BPV BPV BPM BPV BPV BPV BPV BPV BPV BPV E7E7
UL L6 L5 L4 L3 L2 L1 L0 UR R6 R5 R4 R3 R2 R1 R0
2 04 AUDCTL2 0 1 0 0 0 1 0 0 0 0 0 1 0 MON SSR SST 4411
S TE EP
2 05 PD/MISC APD AVP ABP HAP MOP DAP ADP ADP PDS MIBP OSC BCK SMP OTS BAS DEE FFC4
D D D D D DL DR TS D C C D YN S MP
2 06 GPIO 0 0 IO5 0 0 0 0 0 0 0 GPI 0 0 0 0 0 0000
O5
2 07 BBCFN0L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 08 BBCFN1L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 09 BBCFN2L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 0A BBCFN3L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 0B BBCFN4L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 0C BBCFN5L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 0D BBCFD1L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 0E BBCFD2L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
2 0F BBCFD4L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 10 BBCFD5L CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
2 11 BBCFN0R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 12 BBCFN1R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 13 BBCFN2R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 14 BBCFN3R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 6BE2
2 15 BBCFN4R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 9667
2 16 BBCFN5R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 675D
2 17 BBCFD1R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 18 BBCFD2R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
2 19 BBCFD4R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 7D82
2 1A BBCFD5R CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 84EF
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TSC2302
SLAS394–JULY 2003
Register Summary for TSC2302 (continued)
PAGE ADDR REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET
(HEX) NAME VALUE
(HEX)
2 1B ADCLKCF 0 0 0 0 0 1 0 0 0 0 0 0 PLP COM 0 0 0400
G N K
2 1C reserved 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF
2 1D reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
2 1E reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
2 1F reserved 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000
TSC2302 TOUCH SCREEN CONTROL REGISTERS
This section describes each of the registers shown in the memory map of Figure 49. The registers are grouped
according to the function they control. In the TSC2302, bits in control registers can refer to slightly different
functions depending upon whether you are reading the register or writing to it. A summary of all registers and bit
locations is shown in Table 3.
TSC2302 ADC Control Register (Page 1, Address 00H)
The ADC in the TSC2302 is shared between all the different functions. A control register determines which input
is selected, as well as other options. The result of the conversion is placed in one of the result registers in Page
0 of memory, depending upon the function selected.
The ADC control register controls several aspects of the ADC. The register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
PSM STS AD3 AD2 AD1 AD0 RS1 RS0 AV1 AV0 CL1 CL0 PV2 PV1 PV0 X
Bit 15 — PSM
Pen Status/Control Mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bit
determines the mode used to read coordinates: host controlled or under control of the TSC2302 responding to a
screen touch. When reading, the PENSTS bit indicates if the pen is down or not. When writing to this register,
this bit determines if the TSC2302 controls the reading of coordinates, or if the coordinate conversions are
host-controlled. The default state is host-controlled conversions (0).
Table 4. PSM Bit Operation
PSM
READ/WRITE VALUE DESCRIPTION
Read 0 No screen touch detected (default)
Read 1 Screen touch detected
Write 0 Conversions controlled by host
Write 1 Conversions controlled by TSC2302
Bit 14 — STS
ADC Status. Reading this bit indicates if the converter is busy. Writing a 0 to this bit causes the touch screen
scans to continue until either the pen is lifted or the process is stopped. Continuous scans or conversions can be
stopped by writing a 1 to this bit. This immediately halts a conversion (even if the pen is still down) and causes
the ADC to power down. The default state is continuous conversions, but if this bit is read after a reset or
power-up, it reads 1.
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TSC2302
SLAS394–JULY 2003
Table 5. STS Bit Operation
STS
READ/WRITE VALUE DESCRIPTION
Read 0 Converter is busy
Read 1 Converter is not busy (default)
Write 0 Normal operation
Write 1 Stop conversion and power down
Bits [13:10] — AD3 - AD0
ADC Function Select bits. These bits control which input is to be converted, and what mode the converter is
placed in. These bits are the same whether reading or writing. See Table 6 for a complete listing of how these
bits are used.
Table 6. ADC Function Select
A/D3 A/D2 A/D1 A/D0 FUNCTION
0 0 0 0 Invalid. No registers are updated. This is the default state after a reset.
0 0 0 1 Touch screen scan function: X and Y coordinates converted and the results returned to X and Y data
registers. Scan continues until either the pen is lifted or a stop bit is sent.
0 0 1 0 Touch screen scan function: X, Y, Z1 and Z2 coordinates converted and the results returned to X, Y, Z1 and
Z2 data registers. Scan continues until either the pen is lifted or a stop bit is sent.
0 0 1 1 Touch screen scan function: X coordinate converted and the results returned to X data register.
0 1 0 0 Touch screen scan function: Y coordinate converted and the results returned to Y data register.
0 1 0 1 Touch screen scan function: Z1 and Z2 coordinates converted and the results returned to Z1 and Z2 data
registers.
0 1 1 0 Battery input 1 converted and the results returned to the BAT1 data register.
0 1 1 1 Battery input 2 converted and the results returned to the BAT2 data register.
1 0 0 0 Auxiliary input 1 converted and the results returned to the AUX1 data register.
1 0 0 1 Auxiliary input 2 converted and the results returned to the AUX2 data register.
1 0 1 0 A temperature measurement is made and the results returned to the temperature measurement 1 data
register.
1 0 1 1 Port scan function: Battery input 1, Battery input 2, Auxiliary input 1, and Auxiliary input 2 measurements are
made and the results returned to the appropriate data registers
1 1 0 0 A differential temperature measurement is made and the results returned to the temperature measurement 2
data register.
1 1 0 1 Turn on X+, X- drivers
1 1 1 0 Turn on Y+, Y- drivers
1 1 1 1 Turn on Y+, X- drivers
Bits[9:8] — RS1, RS0
Resolution Control. The ADC resolution is specified with these bits. SeeTable 7 for a description of these bits.
These bits are the same whether reading or writing.
Table 7. ADC Resolution Control
RS1 RS0 FUNCTION
0 0 12-bit resolution. Power up and reset default.
0 1 8-bit resolution
1 0 10-bit resolution
1 1 12-bit resolution
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TSC2302
SLAS394–JULY 2003
Bits[7:6] — AV1, AV0
Converter Averaging Control. These two bits (see Table 8) allow you to specify the number of averages the
converter performs. Note that when averaging is used, the STS/STP bit and the DAV output indicates that the
converter is busy until all conversions necessary for the averaging are complete. The default state for these bits
is 00, selecting no averaging. These bits are the same whether reading or writing.
Table 8. ADC Conversion Averaging Control
AV1 AV0 FUNCTION
0 0 None (one conversion) (default)
0 1 4 data averages
1 0 8 data averages
1 1 16 data averages
Bits[5:4] — CL1, CL0
Conversion Clock Control. These two bits specify the internal clock rate which the ADC uses when performing a
conversion. See Table 9. These bits are the same whether reading or writing.
Table 9. ADC Conversion Clock Control
CL1 CL0 FUNCTION
0 0 8-MHz internal clock rate - 8-bit resolution only (default)
0 1 4-MHz internal clock rate - 8- or 10-bit resolution only
1 0 2-MHz internal clock rate
1 1 1-MHz internal clock rate
Bits [3:1] — PV2 - PV0
Panel Voltage Stabilization Time Control. These bits allow the user to specify a delay time from when a driver is
turned on to the time sampling begins and a conversion is started. In self-controlled mode, when a pen touch is
detected, the part first turns on a driver, waits a programmed delay time set by PV2-PV0, and then begins
sampling and A/D conversion. See Table 10 for settings of these bits. The default state is 000, indicating a 0µs
stabilization time. These bits are the same whether reading or writing.
Table 10. Panel Voltage Stabilization Time Control
PV2 PV1 PV0 STABILIZATION TIME
0 0 0 0 µs (default)
0 0 1 100 µs
0 1 0 500 µs
0 1 1 1 ms
1 0 0 5 ms
1 0 1 10 ms
1 1 0 50 ms
1 1 1 100 ms
Bit 0
This bit is reserved. When read, it always reads as a zero.
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TSC2302
SLAS394–JULY 2003
DAC Control Register (Page 1, Address 02H)
The single bit in this register controls the power down control of the onboard digital-to-analog converter (DAC).
This register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
DPDXXXXXXXXXXXXXXX
Bit 15 — DPD
DAC Power Down. This bit controls whether the DAC is powered up and operational, or powered down. If the
DAC is powered down, the AOUT pin neither sinks nor sources current.
Table 11. DPD Bit Operation
DPD
VALUE DESCRIPTION
0 DAC is powered and operational
1 DAC is powered down. (default)
Reference Register (Page 1, Address 03H)
This register controls whether the TSC2302 uses an internal or external reference, and if the internal reference is
used, the value of the reference voltage, whether it powers down between conversions and the programmable
settling time after reference power-up. This register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB
MSB 11
X X X X X X X X X X X INT DL1 DL0 PDN RFV
Bit 4 —INT
Internal Reference Mode. If this bit is written to a 1, the TSC2302 uses its internal reference; if this bit is a 0, the
part assumes an external reference is being supplied. The default state for this bit is to select an external
reference (0). This bit is the same whether reading or writing.
Table 12. INT Bit Operation
INT
VALUE DESCRIPTION
0 External reference selected (default)
1 Internal reference selected
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TSC2302
SLAS394–JULY 2003
Bits [3:2] — DL1, DL0
Reference Power-Up Delay. When the internal reference is powered up, a finite amount of time is required for
the reference to settle. If measurements are made before the reference has settled, these measurements are in
error. These bits allow for a delay time for measurements to be made after the reference powers up, thereby
assuring that the reference has settled. Longer delays are necessary depending upon the capacitance present at
the VREFIN pin (see Typical Curves). The delays are shown in Table 13. The default state for these bits is 00,
selecting a 0 microsecond delay. These bits are the same whether reading or writing.
Table 13. Reference Power-Up Delay Settings.
DL1 DL0 DELAY TIME
0 0 0 µs (default)
0 1 100 µs
1 0 500 µs
1 1 1000 µs
Bit 1 —PDN
Reference Power Down. If a 1 is written to this bit, the internal reference are powered down between
conversions. If this bit is a zero, the internal reference is powered at all times. The default state is to power down
the internal reference, so this bit will be a 1. This bit is the same whether reading or writing.
Table 14. PDN Bit Operation
PDN
VALUE DESCRIPTION
0 Internal reference is powered at all times
1 Internal reference is powered down between conversions. (default)
Note that the PDN bit, in concert with the INT bit, creates a few possibilities for reference behavior. These are
detailed in Table 15.
Table 15. Reference Behavior Possibilities
INT PDN REFERENCE BEHAVIOR
0 0 External reference used, internal reference powered down.
0 1 External reference used, internal reference powered down.
1 0 Internal reference used, always powered up
1 1 Internal reference used, powers up during conversions and then powers down.
Bit 0 — RFV
Reference Voltage Control. This bit selects the internal reference voltage, either 1.2 V or 2.5 V. The default value
is 1.2 V. This bit is the same whether reading or writing.
Table 16. RFV Bit Operation
RFV
VALUE DESCRIPTION
0 1.2-V reference voltage (default)
1 2.5-V reference voltage
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TSC2302
SLAS394–JULY 2003
TSC2302 Configuration Control Register (Page 1, Address 05H)
This control register controls the configuration of the precharge and sense times for the touch detect circuit. The
register is formatted as follows:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB LSB
RES RES RES RES RES RES RES RES RES RES PRE2 PRE1 PRE0 SNS2 SNS1 SNS0
Bits [5:3] — PRE[2:0]
Precharge time selection bits. These bits set the amount of time allowed for precharging any pin capacitance on
the touch screen prior to sensing if the screen is being touched.
Table 17. Precharge Times
PRE[2:0]
PRE2 PRE1 PRE0 TIME
0 0 0 20 µs (default)
0 0 1 84 µs
0 1 0 276 µs
0 1 1 340 µs
1 0 0 1.044 ms
1 0 1 1.108 ms
1 1 0 1.300 ms
1 1 1 1.364 ms
Bits [2:0] — SNS[2:0]
Sense time selection bits. These bits set the amount of time the TSC2302 waits to sense a screen touch
between coordinate axis conversions in self-controlled mode.
Table 18. Sense Times
SNS[2:0]
SNS2 SNS1 SNS0 TIME
0 0 0 32 µs (default)
0 0 1 96 µs
0 1 0 544 µs
0 1 1 608 µs
1 0 0 2.080 ms
1 0 1 2.144 ms
1 1 0 2.592 ms
1 1 1 2.656 ms
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TSC2302
SLAS394–JULY 2003
Secondary Configuration Register (Page 1, Address 06H):
This register allows the user to read the status of the DAV pin through the SPI interface. It also controls the audio
codec PLL.
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
SDAV RESV PLLO PCTE PDC3 PDC2 PDC1 PDC0 A3 A2 A1 A0 N3 N2 N1 N0
Bit 15 — SDAV (read only)
SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the host
processor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the host
processor to the TSC2302 DAV pin. This bit is normally high, goes low when touch screen or keypad data is
available, and is reset high when all the new data has been read. When written to, this bit becomes KBC1,
operation detailed below.
Table 19. SPI Data Available (Read Only)
SDAV DESCRIPTION
0 Touchscreen data is available.
1 No new data available (default)
Bit 13 — PLLO
PLL Output on GPIO_0. This bit allows the user to receive the output of the audio codec internal PLL. This bit is
provided so the host processor can use the output of the PLL, to generate its I2S signals in sync with an external
MCLK or crystal oscillator. Writing a 0 to this bit connects the output of the PLL to the GPIO_0 pin. Otherwise,
the GPIO_0 pin operates as normal.
Table 20. PLL Output
PLLO DESCRIPTION
0 Output PLL on GPIO_0.
1 GPIO_0 operates as normal (default).
Bit 12 — PCTE
PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows the
user to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manual
control of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] in
the audio control register (bits 7-2 in register 00h, page 2).
Table 21. PLL Control Enable
PLLO DESCRIPTION
0 Allows modification of bits [11:0].
1 PLL operates as normal, no manual override (default).
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FOUT MCLK
P(4N A)
3,(N A),MCLK
P1MHz
(3)
TSC2302
SLAS394–JULY 2003
Bit [11:8] — PDC3 - PDC0
PLL Predivider Control. This bit controls the predivider to the internal PLL. These bits represent a 4-bit straight
binary number corresponding to the variable P in the PLL control equation discussed later in this section. The
legal range of these bits is 1h to Fh. The default of these bits is Fh.
Bit [7:4] — A3 - A0
AControl. This bit represent a 4-bit straight binary number corresponding to the variable A in the PLL control
equation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.
Bit [3:0] — N3 - N0
NControl. This bit represents a 4-bit straight binary number corresponding to the variable N in the PLL control
equation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.
When using a nonaudio standard MCLK frequency or crystal that is not covered by any of the automatic PLL
settings in MCLK[1:0], the user must manually configure the TSC2302 PLL to generate the proper clock for the
audio data converters. The proper clock for any sampling rates that are submultiples of 44.1 kHz is 512 x 44.1
kHz = 22.5792 MHz. This frequency is valid for 44.1 kHz, 22.05 kHz, and 11.025 kHz. The proper clock for any
sampling rates that are submultiples of 48 kHz is 512 x 48 kHz = 24.576 MHz. This frequency is valid for 48 kHz,
32 kHz, 24 kHz, 16 kHz, 12 kHz, and 8 kHz. Equation 3 is used to obtain the proper frequency. Since variables
P, N, and Aare integers, the exact proper clock frequencies can not always be obtained. However, examples are
provided for common MCLK/crystal frequencies that minimize the error of the PLL output. One constraint is the N
must always be greater than or equal to A. Another constraint is that the output of the MCLK predivider (the
MCLK/P term) should be greater than 1 MHz. Pcan be any integer from 1 to 15, inclusive. Nand Acan be any
integer from 0 to 15, inclusive. In some situations, settings outside of these constraints may work, but should be
verified by the user beforehand. Table 22 shows some settings that have been tested and confirmed to work by
TI.
Table 22. PLL Settings
MCLK (MHZ) DESIRED P A N ACTUAL FOUT % ERROR
FOUT(MHZ) (MHZ)
12 24.576 7 7 9 24.57143 -0.019
13 24.576 9 7 11 24.55556 -0.083
16 24.576 13 12 12 24.61538 0.160
19.2 24.576 13 10 10 24.61538 0.160
19.68 24.576 12 9 9 24.60000 0.097
3.6869 22.5792 3 7 12 22.53106 -0.213
12 22.5792 11 10 13 22.54545 -0.149
13 22.5792 14 13 15 22.59524 0.071
16 22.5792 13 11 11 22.56410 -0.067
19.2 22.5792 15 9 11 22.61333 0.151
19.68 22.5792 9 3 7 22.59556 0.072
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TSC2302
SLAS394–JULY 2003
TSC2302 DATA REGISTERS
The data registers of the TSC2302 hold data results from conversions or keypad scans, or the value of the DAC
output current. All of these registers default to 0000H upon reset, except the DAC register, which is set to 0080H,
representing the midscale output of the DAC.
X, Y, Z1, Z2, BAT1, BAT2, AUX1, AUX2, TEMP1, and TEMP2 REGISTERS
The results of all A/D conversions are placed in the appropriate data register, as described in Table 4 and
Table 2. The data format of the result word, R, of these registers is right-justified, as follows (assuming a 12-bit
conversion):
BIT 15 BIT 14 BIT BIT BIT BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB 13 12 11 LSB
0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
MSB LSB
DAC Data Register (Page 0, Address 0BH)
The data to be written to the DAC is written into the DAC data register, which is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
RES RES RES RES RES RES RES RES D7 D6 D5 D4 D3 D2 D1 D0
There are three different touch screen conversion modes available in the TSC2302: self-controlled or
PENIRQ-Initiated, host-initiated, and host-controlled. These three modes are described below.
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tcoordinate 2.5 s2tPVS tPRE tSNS2NAVGNBITS 1
fconv 4.4 s
(4)
tcoordinate 4.75 s3tPVS tPRE tSNS4NAVGNBITS 1
fconv 4.4 s
(5)
TSC2302
SLAS394–JULY 2003
OPERATION - TOUCH SCREEN MEASUREMENTS
Conversion Controlled by TSC2302 Initiated at Touch Detect
In this mode, the TSC2302 detects when the touch panel is touched and causes the PENIRQ line to go low. At
the same time, the TSC2302 powers up its internal clock. It then turns on the Y-drivers, and after a programmed
panel voltage stabilization time, powers up the ADC and convert the Y coordinate. If averaging is selected,
several conversions may take place; when data averaging is complete, the Y coordinate result is stored in the Y
register.
This mode is recommended to fully utilize the integrated touch screen processing of the TSC2302 and reduce
the processing overhead and number of interrupts to the host processor. In this mode, the host processor does
not need to monitor PENIRQ, instead the host needs only to configure the TSC2302 once at power-up, and then
monitor DAV and read back data after a falling edge on DAV.
If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measures
instead the X coordinate, storing the result in the X register.
If only X and Y coordinates are to be measured, then the conversion process is complete. Figure 46 shows a
flowchart for this process. The time it takes to go through this process depends upon the selected resolution,
internal conversion clock rate, averaging selected, panel voltage stabilization time, and precharge and sense
times.
The time needed to get a complete X/Y coordinate reading can be calculated by:
where:
•tcoordinate = time to complete X/Y coordinate reading;
•tPVS = panel voltage stabilization time, as given in Table 10;
•tPRE = precharge time, as given in Table 17;
•tSNS = sense time, as given in Table 18;
•NAVG = number of averages, as given in Table 8; for no averaging, NAVG = 1;
•NBITS = number of bits of resolution, as given in Table 7;
•fconv = A/D converter clock frequency, as given in Table 9.
If the pressure of the touch is also to be measured, the process continues after the X-conversion is complete,
measuring the Z1 and Z2 values, and placing them in the Z1 and Z2 registers. This process is illustrated in
Figure 47. As before, this process time depends upon the settings described above. The time for a complete
X/Y/Z1/Z2 coordinate reading is given by:
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Turn On Drivers: Y+, Y-
Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert Y coordinates
Store Y Coordinates in Y
Register
Is Screen Touched
Turn On Drivers: X+, X-
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Set /DAV = 0
Is Screen Touched
Turn off clock
Reset PENIRQ and Scan
Trigger
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Turn off clock
Reset PENIRQ and Scan
Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Is Data
Averaging
N
Y
Y
N
Y
N
Y
Y
N
N
Y
Y
N
Done
Done
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN X AND Y PENIRQ INITIATED
Figure 46. X & Y Coordinate Touch Screen Scan, Initiated by Touch
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Issue Interrupt
PENIRQ
Turn On Drivers: Y+, Y-
Is PENSTS =1
Start Clock
Is
Panel Voltage
Stabilization
Done
Convert Y
coordinates
Store Y Coordinates
in Y Register
Is Screen
Touched
Turn On Drivers: X+, X-
Is
Panel Voltage
Stabilization
Done
Convert X
coordinates
Store X Coordinates
in X Register
Is Screen
Touched
Turn off clock
Reset PENIRQ and
Scan Trigger
Screen
Touch
Done
Go To Host
Controlled
Conversion
N
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Done
Is Data
Averaging
Done
N
Y
N
Y
N
Y
Y
N
N
Y
Y
N
Turn On Drivers: Y+, X-
Is
Panel Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0
Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
Y
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Is Screen
Touched
Y
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN X, Y AND Z PENIRQ INITIATED
Figure 47. X,Y and Z Coordinate Touch Screen Scan, Initiated by Touch
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TSC2302
SLAS394–JULY 2003
Conversion Controlled by TSC2302 Initiated By Host Responding to PENIRQ
This mode is provided for users who want more control over the A/D conversion process. This mode requires
more overhead from the host processor, so it is generally not recommended.
In this mode, the TSC2302 detects when the touch panel is touched and causes the PENIRQ line to go low. The
host recognizes the interrupt request, and then writes to the ADC control register to select one of the touch
screen scan functions (single X-, Y-, or Z-conversions, continuous X/Y or X/Y/Z1/Z2 Conversions). The
conversion process then proceeds as described above, and as outlined in Figure 48 through Figure 52.
The main difference between this mode and the previous mode is that the host, not the TSC2302, decides when
the touch screen scan begins after responding to a PENIRQ. In this mode, the host must either monitor both
PENIRQ and DAV, or wait a minimum time after writing to the A/D converter control register. This wait time can
be calculated from equation Equation 6 in the case of single conversions, or from equations Equation 4 or
Equation 5 in the case of multiple conversions. The nominal conversion times calculated by these equations
should be extended by approximately 12% to account for variation in the internal oscillator frequency.
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Issue Interrupt
PENIRQ
Turn On Drivers: Y+, Y-
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert Y coordinates
Store Y Coordinates in Y
Register
Is Screen Touched
Turn On Drivers: X+, X-
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Set /DAV = 0
Is Screen Touched
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Turn off clock
Reset PENIRQ and Scan
Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Done
Is Data
Averaging
Done
N
Y
N
Y
N
Y
N
N
Y
Y
N
Done
Host Writes A/D
Converter
Control Register
Reset PENIRQ
Y
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN X AND Y HOST INITIATED
Figure 48. X and Y Coordinate Touch Screen Scan, Initiated by Host
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Turn On Drivers: Y+, Y-
Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization
Done
Convert Y
coordinates
Store Y Coordinates
in Y Register
Is Screen
Touched
Turn On Drivers: X+, X-
Is
Stabilization
Done
Convert X
coordinates
Store X Coordinates
in X Register
Is Screen
Touched
Turn off clock
Screen
Touch
Done
Go To Host
Controlled
Conversion
N
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Power up ADC
Power Down ADC
Power up ADC
Power Down ADC
Is Data
Averaging
Done
Is Data
Averaging
Done
N
Y
N
Y
N
Y
Y
N
N
Y
Y
N
Turn On Drivers: Y+, X-
Is
Panel Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0
Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
Y
Turn off clock
Reset PENIRQ and
Scan Trigger
Done
Is Screen
Touched
Done
Host Writes A/D
Converter
Control Register
Reset PENIRQ
Panel Voltage
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN X, Y AND Z HOST INITIATED
Figure 49. X,Y and Z Coordinate Touch Screen Scan, Initiated by Host
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Turn On Drivers: X+, X-
Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Set /DAV = 0
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Power up ADC
Power Down ADC
Is Data
Averaging
N
N
Y
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Start Clock
Are Drivers On
Y
N
Y
Done
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN X COORDINATE HOST INITIATED
Figure 50. X Coordinate Reading Initiated by Host
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Turn On Drivers: Y+, Y-
IssueInterrupt
PENIRQ
Is PENSTS =1
Start Clock
Is Panel Voltage
Stabilization Done
Convert Y coordinates
Store Y Coordinates in Y
Register
Set /DAV = 0
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
N
Power up ADC
Power Down ADC
Is Data
Averaging Done
N
N
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Start Clock
Are Drivers On
Y
N
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN Y COORDINATE HOST INITIATED
Figure 51. Y Coordinate Reading Initiated by Host
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Issue Interrupt
PENIRQ
Is PENSTS =1
Start Clock
Turn off clock
Screen
Touch
Go To Host
Controlled
Conversion
N
Turn On Drivers: Y+, X-
Is Panel
Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0
Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
DONE
Y
DONE
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Are Drivers On
Start Clock
N
TSC2302
SLAS394–JULY 2003
TOUCH SCREEN SCAN Z COORDINATE HOST INITIATED
Figure 52. Z Coordinate Reading Initiated by Host
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tcoordinate 2.125 stPVS NAVGNBITS 1
ƒconv 4.4 s
(6)
TSC2302
SLAS394–JULY 2003
Conversion Controlled by the Host
In this mode, the TSC2302 detects when the touch panel is touched and causes the PENIRQ line to go low. The
host recognizes the interrupt request. Instead of starting a sequence in the TSC2302, which then reads each
coordinate in turn, the host now must control all aspects of the conversion. An example sequence would be: (a)
PENIRQ goes low when screen is touched. (b) Host writes to TSC2302 to turn on X-drivers. (c) Host waits a
desired delay for panel voltage stabilization. (d) Host writes to TSC2302 to begin X-conversion. After waiting for
the settling time, the host then addresses the TSC2302 again, this time requesting an X coordinate conversion.
The process is then repeated for Y and Z coordinates. The processes are outlined in Figure 53 through Figure
55.
The time needed to convert any single coordinate under host control (not including the time needed to send the
command over the SPI bus) is given by:
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Turn On Drivers: X+, X-
Issue Interrupt
PENIRQ
Is PENSTS =1
Is Panel Voltage
Stabilization Done
Convert X coordinates
Store X Coordinates in X
Register
Issue Data Available
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
Power up ADC
Power Down ADC
Is Data
Averaging
N
N
Y
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Done
Host Writes A/D
Converter Control
Register
Start Clock
Are Drivers On
Turn On Drivers: X+, X-
Y
N
Y
N
Start Clock
Done
TSC2302
SLAS394–JULY 2003
HOST CONTROLLED X COORDINATE
Figure 53. X Coordinate Reading Controlled by Host
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Turn On Drivers: Y+, Y-
Issue Interrupt
PENIRQ
Is PENSTS =1
Is Panel Voltage
Stabilization Done
Conver Y coordinates
Store Y Coordinates in Y
Register
Set /DAV = 0
Turn off clock
Screen
Touch
Done
Go To Host Controlled
Conversion
Power up ADC
Power Down ADC
Is Data
Averaging
N
N
Y
Done
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Done
Host Writes A/D
Converter Control
Register
Start Clock
Are Drivers On
Y
N
Y
N
Start Clock
Turn On Drivers: Y+, Y-
Done
TSC2302
SLAS394–JULY 2003
HOST CONTROLLED Y COORDINATE
Figure 54. Y Coordinate Reading Controlled by Host
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Start Clock
Turn off clock
N
Turn On Drivers: Y+, X-
Is Panel Voltage
Stabilization
Done
Convert Z1
coordinates
Store Z1 Coordinates
in Z1 Register
Set /DAV = 0Power up ADC
Power Down ADC
Is Data
Averaging
Done
N
Y
Y
N
Convert Z2
coordinates
Store Z2 Coordinates
in Z2 Register
Is Data
Averaging
Done
N
DONE
Y
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Are Drivers On
Start Clock
N
Y
Issue Interrupt
PENIRQ
Is PENSTS =1
Screen
Touch
Go To Host
Controlled Conversion
N
DONE
Turn On Drivers: X+, X-
Host Writes A/D
Converter Control
Register
Reset PENIRQ
Done
TSC2302
SLAS394–JULY 2003
HOST CONTROLLED Z COORDINATE
Figure 55. Z Coordinate Reading Controlled by Host
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X+
MUX A/D
Converter
Temperature Select
TEMP1 TEMP2
°KqV
kn(N)
(7)
VVI82–VI1
(8)
°KqV
kn(N)
(9)
TSC2302
SLAS394–JULY 2003
OPERATION - TEMPERATURE MEASUREMENT
In some applications, such as estimating remaining battery life or setting RAM refresh rate, a measurement of
ambient temperature is required. The temperature measurement technique used in the TSC2302 relies on the
characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has
a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by
knowing the 25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature
changes.
The TSC2302 offers two modes of temperature measurement. The first mode requires calibration at a known
temperature, but only requires a single reading to predict the ambient temperature. A diode, as shown in Figure
56, is used during this measurement cycle. The voltage across this diode is typically 600 mV at 25°C while
conducting a 20-µA current. The absolute value of this diode voltage can vary several millivolts, but the
temperature coefficient (TC) of this voltage is very consistent at -2.1 mV/°C. During the final test of the end
product, the diode voltage would be measured by the TSC2302 ADC at a known room temperature, and the
corresponding digital code stored in system memory, for calibration purposes by the user. The result is an
equivalent temperature measurement resolution of 0.3°C/LSB. This measurement of what is referred to as
Temperature 1 is illustrated in Figure 57.
Figure 56. Functional Block Diagram of Temperature Measurement Mode
The second mode does not require a test temperature calibration, but uses a two-measurement (differential)
method to eliminate the need for absolute temperature calibration, and achieves a 2°C/LSB accuracy. This mode
requires a second conversion with a current 82 times larger than the first 20uA current. The voltage difference
between the first (TEMP1) and second (Temp2) conversion, using 82 times the bias current, is represented by
kT/q ln (N), where N is the current ratio = 82, k = Boltzmann’s constant (1.38054 x 10-23 electron volts/degree
Kelvin), q = the electron charge (1.602189 x 10-19 C), and T = the temperature in degrees Kelvin. This method
can provide much improved absolute temperature measurement without calibration, with resolution of 2°C/LSB.
The resultant equation for solving for °K is:
where:
(in mV)
Temperature 2 measurement is illustrated in Figure 58.
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Start Clock
Turn off clock
Convert Temperature
Input 1
Store Temperature
Input 1 in TEMP1
Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Programmed
Delay)
Y
TSC2302
SLAS394–JULY 2003
TEMPERATURE INPUT 1
Figure 57. Single Temperature Measurement Mode
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Start Clock
Turn off clock
Convert Temperature
Input 2
Store Temperature
Input 2 in TEMP2
Register
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
Set /DAV = 0
TSC2302
SLAS394–JULY 2003
TEMPERATURE INPUT 2
Figure 58. Additional Temperature Measurement for Differential Temperature Reading
OPERATION - BATTERY MEASUREMENT
An added feature of the TSC2302 is the ability to monitor the battery voltage which may be much larger than the
supply voltage of the TSC2302. An example of this is shown in Figure 59, where a battery voltage ranging up to
6 V may be regulated by a dc/dc converter or low-dropout regulator to provide a lower supply voltage to the
TSC2302. The battery voltage can vary from 0.5 V to 6 V while maintaining the voltage to the TSC2302 at a level
of 2.7 V-3.6 V. The input voltage on VBAT1 is divided down by 4 so that a 6-V battery voltage is represented as
1.5 V to the A/D, while the input voltage on VBAT2 is divided by 2 so that 3.0-V battery voltage is represented as
1.5 V to the A/D. If the battery voltage is low enough, the 1.2 V internal reference can be used to decrease LSB
size, potentially improving accuracy. The battery voltage on VBAT1 must be below 4* VREF, and the voltage on
VBAT2 must be below 2* VREF. Due to constraints of the internal switches, the input to the A/D after the voltage
divider cannot be above 1.5 V or VREF, whichever is lower. In order to minimize the power consumption, the
divider is only ON during the sampling of the battery input.
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+
DC/DC
Converter 2.7 V
0.125 V to 1.5 V
VCC
7.5 k
2.5 k
Battery
0.5 V+
to 6.0 V
VBAT1 ADC
+
DC/DC
Converter 2.7 V
0.125 V to 1.5 V
VCC
5.0 k
5.0 k
Battery
0.25 V+
to 3.0 V
VBAT2 ADC
tcoordinate 2.625 stREF NAVGNBITS 1
ƒconv 4.4 s
(10)
TSC2302
SLAS394–JULY 2003
Figure 59. VBAT Example Battery Measurement Functional Block Diagrams, VDD = 2.7 V, VREF = 2.5 V
Flowcharts which detail the process of making a battery input reading are shown in Figure 60 and Figure 61.
The time needed to make temperature, auxiliary, or battery measurements is given by:
where tREF is the reference delay time as given in Table 13.
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Start Clock
Turn off clock
Convert Battery Input
1
Store Battery Input 1
in BAT1 Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averagin
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
TSC2302
SLAS394–JULY 2003
BATTERY INPUT 1
Figure 60. VBAT1 Measurement Process
This assumes the reference control register is configured to power up the internal reference when needed.
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Start Clock
Turn off clock
Convert Battery Input
2
Store Battery Input 2
in BAT2 Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
TSC2302
SLAS394–JULY 2003
BATTERY INPUT 2
Figure 61. VBAT2 Measurement Process
OPERATION - AUXILIARY MEASUREMENT
The two auxiliary voltage inputs can be measured in similar fashion to the battery inputs, with no voltage dividers.
The input range of the auxiliary inputs is 0 V to VREF. Figure 62 and Figure 63 illustrate the process. Applications
for this feature may include external temperature sensing, ambient light monitoring for controlling an LCD
back-light, or sensing the current drawn from the battery.
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Start Clock
Turn off clock
Convert Auxiliary
Input 1
Store Auxiliary Input
Set /DAV = 0
Power up ADC Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
1 in AUX1 Register
TSC2302
SLAS394–JULY 2003
AUXILIARY INPUT 1
Figure 62. AUX1 Measurement Process
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Start Clock
Turn off clock
Convert Auxiliary
Input 2
Store Auxiliary Input
Set /DAV = 0
Power up ADC Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
2 in AUX2 Register
TSC2302
SLAS394–JULY 2003
AUXILIARY INPUT 2
Figure 63. AUX2 Measurement Process
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tcoordinate 7.5 stREF 4NAVGNBITS 1
ƒconv 4.4 s
(11)
Start Clock
Turn off clock
Convert Battery Input
1
Store Battery Input 1
in BAT1 Register
Set /DAV = 0
Power up ADC
Power Down
Reference
Is Data
Averaging
Done
N
Y
Power Down ADC
DONE
Host Writes A/D
Converter Control
Register
Power Up Reference
(Including Delay)
Convert Battery Input
2
Store Battery Input 2
in BAT2 Register
Is Data
Averaging
Done
N
Y
Convert Auxiliary
Input 1
Store Auxiliary Input
in AUX1 Register
Is Data
Averaging
Done
N
Y
Convert Auxiliary
Input 2
Store Auxiliary Input
2 in AUX2 Register
Is Data
Averaging
Done
N
Y
TSC2302
SLAS394–JULY 2003
OPERATION - PORT SCAN
If measurements of all the battery and auxiliary inputs are required, the port scan mode can be used. This mode
causes the TSC2302 to sample and convert both battery inputs and both auxiliary inputs. At the end of this cycle,
the battery and auxiliary data registers contain the updated values, and the DAV pin is asserted low, signaling
the host to read the data. Thus, with one write to the TSC2302, the host can cause four different measurements
to be made. Because the battery and auxiliary data registers are consecutive in memory, all four registers can be
read in one SPI transaction, as described in Figure 45.
The flowchart for this process is shown in Figure 64. The time needed to make a complete port scan is given by:
PORT SCAN
Figure 64. Port Scan Mode
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RRNG
VBIAS
DAC
8-Bits
V+
ARNG
AOUT
R1
R2
TSC2301
TSC2302
SLAS394–JULY 2003
OPERATION - D/A CONVERTER
The TSC2302 has an onboard 8-bit DAC, configured as shown in Figure 65. This configuration yields a current
sink (AOUT) controlled by the value of a resistor connected between the ARNG pin and ground. The D/A
converter has a control register, which controls whether or not the converter is powered up. The eight-bit data is
written to the DAC through the DAC data register.
Figure 65. D/A Converter Configuration
This circuit is designed for flexibility in the output voltage at the VBIAS point shown in Figure 65 to accommodate
the widely varying requirements for LCD contrast control bias. V+ can be a higher voltage than the supply
voltage for the TSC2302. The only restriction is that the voltage on the AOUT pin can never go above the
absolute maximum ratings for the device, and should stay above 1.5 V for linear operation.
The DAC has an output sink range which is limited to approximately 1 mA. This range can be adjusted by
changing the value of RRNG shown in Figure 65. As this DAC is not designed to be a precision device, the
actual value of the output current range can vary as much as ±20%. Furthermore, the current output changes
due to variations in temperature; the DAC has a temperature coefficient of approximately 0.9 uA/°C.
To set the full-scale current, RRNG can be determined from the graph shown in Figure 66.
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1
300
200
100
0
10 k 100 k 1 M 10 M 100 M
DAC Fullscale Output Current – A
400
500
RRNG Resistor Value
DAC FULLSCALE OUTPUT CURRENT
vs
RRNG RESISTOR VALUE
600
µ
1000
900
800
700
1100
TSC2302
SLAS394–JULY 2003
Figure 66. DAC Output Current Range vs RRNG Resistor Value
For example, consider an LCD that has a contrast control voltage VBIAS that can range from 2 V to 4 V, that
draws 400 µA when used, and has an available 5-V supply. This is higher than the TSC2302 supply voltage, but
it is within the absolute maximum ratings.
The maximum VBIAS voltage is 4 V, and this occurs when the D/A converter current is 0, so only the 400-µA
load current ILOAD is flowing from 5 V to VBIAS. This means 1 V is dropped across R1, so R1 = 1 V/400 µA =
2.5 kΩ.
The minimum VBIAS is 2 V, which occurs when the D/A converter current is at its full scale value, IMAX. In this
case, 5 V - 2 V = 3 V is dropped across R1, so the current through R1 is 3 V/2.5 kΩ= 1.2 mA. This current is
IMAX + ILOAD = IMAX + 400 uA, so IMAX must be set to 800 µA. This means that RRNG should be around 1
MΩ.
Since the voltage at the AOUT pin must not go below 1.5 V, this limits the voltage at the bottom of R2 to be
1.5-V minimum; this occurs when the D/A converter is providing its maximum current, IMAX. In this case, IMAX
+ILOAD flows through R1, and IMAX flows through R2. Thus,
R2 x IMAX + R1(IMAX + ILOAD) = 5 V - 1.5 V = 3.5 V
(12)
W R1 = 2.5 kΩIMAX = 800µA, ILOAD = 400µA, thus allowing R2 to be solved as 625 Ω.
In the previous example, when the DAC current is zero, the voltage on the AOUT pin rises above the TSC2302
supply voltage. This is not a problem, however, since V+ was within the absolute maximum ratings of the
TSC2302, so no special precautions are necessary. Many LCD displays require voltages much higher than the
absolute maximum ratings of the TSC2302. In this case, the addition of an NPN transistor, as shown in Figure
67, protects the AOUT pin from damage.
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R2
R1
V+
DAC
RRNG
2N3904
AOUT
ARNG
VDD
TSC2301
VBIAS
8–Bits
TSC2302
SLAS394–JULY 2003
Figure 67. DAC Circuit When Using V+ Higher Than Vsupply.
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TSC2302
SLAS394–JULY 2003
AUDIO CODEC
Audio Analog I/O
The TSC2302 has one pair of stereo inputs, LLINEIN and RLINEIN, and one mono audio input, MICIN. The part
also has a stereo headphone output amplifier capable of driving a 16-Ωload at up to 30 mW/channel, HPL and
HPR. Finally, the part includes a mono output capable of driving a 10-kΩload, MONO.
The common-mode voltage, VCM, used by the audio section can be powered up independently by the AVPD bit
(Bit 14, Reg 05h, Pg 2). Because the audio outputs are biased to this voltage, this voltage is slowly ramped up
when powered on, and there is an internally programmed delay of approximately 500 ms between powering up
this voltage and unmuting the analog audio signals of the TSC2302, in order to avoid pops and clicks on the
outputs. It is recommended to keep VCM powered up if the 500-ms delay is not tolerable.
Audio Digital I/O
Digital audio data samples can be transmitted between the TSC2302 and the CPU via the I2S bus (BCLK,
LRCLK, I2SDIN, I2SDOUT). However, all registers, including those pertaining to audio functionality, are only
accessible via the SPI bus. The I2S bus operates only in slave mode, meaning the BCLK and LRCLK must be
provided as inputs to the part. Four programmable modes for this serial bus are supported and can be set
through the I2SFM bits (Bits[1:0], Reg 00h, Pg 2) .
PCM Audio Interface
The 4-wire digital audio interface for TSC2302 is comprised of BCLK (pin 24), LRCLK (pin 25), I2SDIN (pin 26),
and I2SDOUT (pin 27). For the TSC2302, these formats are selected through the I2SFM bits in Reg 00h, Pg 2.
The following figures illustrate audio data input/output formats and timing.
The TSC2302 can accept 32-, 48-, or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats can
be selected when 32-bit clocks/LRCIN are applied.
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MSB
L–ch R–ch
L–ch R–ch
LSB
LRCIN
BCKIN
FORMAT 0
MSB LSB
DAC: 16–Bit, MSB–First, Right–Justified
ADC: 16–Bit, MSB–First, Left–Justified
116 2 3 14 15 16 1 2 3 14 15 16
MSB LSB
LRCIN
BCKIN
MSB LSB
1 2 3 14 15 16 1 2 3 14 15 16 1
MSB
L–ch R–ch
L–ch R–ch
LSB
LRCIN
BCIN
FORMAT 2
MSB LSB
DAC: 20–Bit, MSB–First, Left–Justified
ADC: 20–Bit, MSB–First, Left–Justified
1 2 3 18 19 20 1 2 3 18 19 20
MSB LSB
LRCIN
BCIN
MSB LSB
1 2 3 18 19 20 1 2 3 18 19 20
MSB
L–ch R–ch
L–ch R–ch
LSB
LRCIN
BCKIN
FORMAT 1
MSB LSB
DAC: 20–Bit, MSB–First, Right–Justified
ADC: 20–Bit, MSB–First, Left–Justified
120 2 3 18 19 20 1 2 3 18 19 20
MSB LSB
LRCIN
BCKIN
MSB LSB
1 2 3 18 19 20 1 2 3 18 19 20 1
1
1
I2SDIN
I2SDOUT
I2SDIN
I2SDOUT
I2SDIN
I2SDOUT
TSC2302
SLAS394–JULY 2003
Figure 68. Audio Data Input/Output Format
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M S B
L –c h R –c h
L –c h R –c h
L S B
F O R M A T 3
M S B L S B
D A C : 2 0 –B it, M S B –F ir s t, I2S
A D C : 2 0 –B it , M S B –F ir s t, I2S
1 2 3 1 8 1 9 2 0 1 2 3 1 8 1 9 2 0
M S B L S B M S B L S B
1 2 3 1 8 1 9 2 0 1 2 3 1 8 1 9 2 0
I2SDIN
BCKIN
LRCIN
BCKIN
LRCIN
I2SDOUT
tBCH
tBCY
tBCL
tLB
tDIH
tDIS
tLRP
tBL
tLDO
tBDO
0.5V DD
0.5VDD
0.5VDD
0.5V DD
I2SDIN
I2SDOUT
BCKIN
LRCIN
TSC2302
SLAS394–JULY 2003
Figure 69. Audio Data Input/Output Format
Figure 70. Audio Data Input/Output Timing
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TSC2302
SLAS394–JULY 2003
Table 23. Audio Data Input/Output Timing
Parameter Symbol Min Max
BCKIN pulse cycle time tBCY 300 ns
BCKIN pulse width high tBCH 120 ns
BCKIN pulse width low tBCL 120 ns
BCKIN rising edge to LRCIN edge tBL 40 ns
LRCIN edge to BCKIN rising edge tLB 40 ns
LRCIN pulse width tLRP tBCY ns
I2SDIN setup time tDIS 40 ns
I2SDIN hold time tDIH 40 ns
I2SDOUT delay time to BCKIN falling edge tBDO 40 ns
I2SDOUT delay time to LRCIN edge tLDO 40 ns
Rising time to all signals tRISE 20 ns
Falling time to all signals tFALL 20 ns
Audio Data Converters
The TSC2302 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are both
capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz.
The DAC and ADC must operate at the same sampling rate.
When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to the
I2S bus clock. The MCLK can be 256/384/512 times the I2S LRCLK rate. An internal PLL takes any of these
possible input clocks and generates a digital clock for use by the internal circuitry of either 44.1 kHz x 512 =
22.5792 MHz (when 44.1 kHz submultiple sample-rates are selected) or 48 kHz x 512 = 24.576 MHz (when 48
kHz submultiple sample-rates are selected). The user is required to set the MCLK bits (Bits[7:6], Reg 00h, Pg 2)
to tell the part the ratio between MCLK and the I2S LRCLK rate (there is no specific phase alignment requirement
between MCLK and BCLK). The user is also required to set the I2SFS bits (Bits[5:2], Reg 00h, Pg 2) to tell the
part what sample rate is in use. When the user is using either 44.1 kHz or 48-kHz sampling rates, and providing
a 512 x Fs MCLK, the internal PLL is powered down, as MCLK can be used directly to clock the internal circuitry.
This reduces power consumption.
If the user wishes to change sampling rates, the data converters (both DACs and ADCs) must be muted, then
powered down. The LRCLK and BCLK rates must then be changed. Next the user must write the appropriate
settings to the MCLK, I2SFS, and I2SFM bits, then power up the data converters. Finally, the data converters
can be unmuted.
Due to the wide supply range over which this part must operate, the audio does not operate on an internal
reference voltage. The common-mode voltage that the single-ended audio signals are referenced to is set by a
divider between the analog supplies and is given by 0.4 x AVDD. The reference voltages used by the audio
codec must be provided as inputs to the part at the Vref+/Vref- pins and are intended to be connected to the
same voltage levels as AVDD and AGND, respectively. Because of this arrangement, the voltages applied to
AVDD, AGND, Vref+, and Vref- should be kept as clean and noise-free as possible.
DAC Digital Volume Control
The DAC digital effects processing block implements a digital volume control that can be set through the SPI
registers. The volume level can be varied from 0 dB to -63.5 dB in 0.5-dB steps independently for each channel.
The user can mute each channel independently by setting the mute bits in the DAC volume control register (Reg
02h, Pg 2). There is a soft-stepping algorithm included in this block, which only changes the actual volume every
20 µs, either up or down, until the desired volume is reached. This speed of soft-stepping can be slowed to once
every 40 µs through the SSRTE bit (Bit 1, Reg 04h, Pg 2).
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TSC2302
SLAS394–JULY 2003
Because of this soft-stepping, the host does not know whether the DAC has actually been fully muted or not.
This may be important if the host wishes to mute the DAC before making a significant change, such as changing
sample rates. In order to help with this situation, the part provides a flag back to the host via a read-only SPI
register bit (Bit 0, Reg 04h, Pg 2) that alerts the host when the part has completed the soft-stepping, and the
actual volume has reached the desired volume level.
The part also includes functionality to detect when the user switches on or off the de-emphasis or bass-boost
functions, and to first soft-mute the DAC volume control, then change the operation of the digital effects
processing, then soft-unmute the part. This avoids any possible pop/clicks in the audio output due to
instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC/ADC.
The circuit begins operation at power-up with the volume control muted, then soft-steps it up to the desired
volume level slowly. At power-down, the logic first soft-steps the volume down to a mute level, then powers down
the circuitry.
Stereo DAC Overview
The stereo DAC consists of a digital block to implement digital interpolation filter, volume control, de-emphasis
filter and programmable digital effects/bass-boost filter for each channel. These are followed by a fifth-order
single-bit digital delta-sigma modulator, and switched capacitor analog reconstruction filter. The DAC has been
designed to provide enhanced performance at low sample rates through increased oversampling and image
filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images
strongly suppressed in the full audio band of 20 Hz-20 kHz, even at low sample rates such as 8 kHz. This is
realized by keeping the upsampled rate approximately constant and changing the oversampling ratio as the input
sample rate is reduced. For rates of 8/12/16/24/32/48 kHz, the digital delta-sigma modulator always operates at a
rate of 6.144 MHz, giving oversampling ratios of 768/512/384/256/192/128, respectively. This ensures that
quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz
at all sample rates. Similarly, for rates of 11.025/22.05/44.1 kHz, the digital delta-sigma modulator always
operates at a rate of 5.6448 MHz, yielding oversampling ratios of 512/256/128, respectively.
Conventional audio DAC designs utilize high-order analog filtering to remove quantization noise that falls within
the audio band when operating at low sample rates. Here, however, the increased oversampling at low sample
rates keeps the noise above 20 kHz, yielding a similar noise floor out to 20 kHz whether the sample rate is 8 kHz
or 48 kHz. If the audio bypass path is not in use when the stereo DAC is in use, the user should power down the
bypass path, as this improves DAC SNR and reduces power consumption.
In addition, the digital interpolation filter provides enhanced image filtering to reduce signal images caused by the
upsampling process that land below 20 kHz. For example, upsampling an 8-kHz signal produces signal images
at multiples of 8 kHz, i.e., 8 kHz, 16 kHz, 24 kHz, etc. The images at 8 kHz and 16 kHz are below 20 kHz and
thus are still audible to the listener, therefore they must be filtered heavily to maintain a good quality output. The
interpolation filter is designed to maintain at least 65-dB rejection of signal images landing between 0.55 Fs and
3.5 Fs, for all sample rates, including any images that land within the audio band (20 Hz-20 kHz). Passband
ripple for all sample-rate cases (from 20 Hz to 0.4535 Fs) is +/-0.1-dB maximum.
The analog reconstruction filter design consists of a switched-capacitor filter with one pole and three zeros. The
single-bit data operates at 128 x 48 kHz = 6.144 MHz (for selected sample-rates that are submultiples of 48 kHz)
or at 128 x 44.1 kHz = 5.6448 MHz (for selected sample-rates that are submultiples of 44.1 kHz). The
interpolation filter takes data at the selected sample-rate from the effects processing block, then performs
upsampling and image filtering, yielding a 6.144-MHz or 5.6448-MHz data stream, which is provided to the digital
delta-sigma modulator.
Audio DAC SNR performance is 98-dB-A typical over 20 Hz–20 kHz bandwidth in 44.1/48-kHz mode at the
line-outputs with a 3.3-V supply level.
DAC Digital De-Emphasis
The DAC digital effects processing block can perform several operations on the audio data before it is passed to
the interpolation filter. One such operation is a digital de-emphasis, which can be enabled or disabled by the user
via the DEEMP bit (Bit 0, Reg 05h, Pg 2). This is only available for sample rates of 32 kHz, 44.1 kHz, and 48
kHz. The transfer function consists of a pole with time constant of 50 µs and a zero with time constant of 15 µs.
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N0 2 N1 Z–1 N2 Z–2
32768–2 D1 Z–1–D2 Z–2N3 2 N4 Z–1 N5 Z–2
32768–2 D4 Z–1–D5 Z–2
(13)
Default Bass-Boost Transfer Function 48 kHz Mode
1 10 100 1000 10000 100000
Frequency (Hz)
0
–0.5
–1
–1.5
–2
–2.5
–3
–3.5
Gain (dB)
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DAC Programmable Digital Effects Filter
The DAC digital effects processing block also includes a fourth order digital IIR filter with programmable
coefficients (independently programmable per channel). The filter transfer function is given by:
The N and D coefficients are set via SPI registers, and this filter can be enabled or disabled via the BASS bit (Bit
1, Reg 05h, Pg 2). This functionality can implement a number of different functions, such as bass-boost (default),
treble-boost, mid-boost, or other equalization. This transfer function(s) can be determined by the user and loaded
to the TSC2302 at power-up, and the feature can then be switched on or off by the user during normal operation.
If a filter with gain over 0 dB is designed and used, and large-scale signals are played at high amplitude through
the DAC, overloading and undesirable effects can occur.
The default coefficients at reset are given by:
N0 = N3 = 27618 D1 = D4 = 32130
N1 = N4 = -27033 D2 = D5 = -31505
N2 = N5 = 26461
which implements the bass-boost transfer function shown in Figure 71, having a 3-dB attenuation for signals
above approximately 150 Hz when operating at a 48-kHz sampling rate. All coefficients are represented by 16-bit
twos complement integers with values ranging from -32768 to +32767.
Figure 71. Transfer Function of Default Bass-Boost Filter Coefficients at 48-kHz Sampling Rate
Audio ADC
The audio ADC consists of a 4th order multi-bit analog delta-sigma modulator, followed by a digital decimation
filter. The digital output data is then passed to the bus interface for transmission back to the CPU.
The analog modulator is a fully differential switched-capacitor design with multi-bit quantizer and dynamic
element matching to avoid mismatch errors. The modulator operates at an oversampling ratio of 128 for all
sample rates. The input to the ADC is filtered by a single-pole analog filter with -3-dB point at approximately 500
kHz for antialiasing. This analog filter uses a single off-chip 1 nF cap per ADC (at the AFILT pins) and on-chip
resistor.
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The digital decimation filter block includes a high-pass IIR filter for the purpose of removing any dc or
sub-audio-frequency component from the signal. Since such a low frequency filter can have significant settling
time, the filter has an adjustable cutoff frequency, in order to allow the host to set a faster settling time initially,
then later switch it back to a level that does not affect the audio band. The settings for this high-pass filter are:
HPF -3-dB frequency: 0.000019 Fs (0.912 Hz at Fs = 48 kHz)
0.000078 Fs (3.744 Hz at Fs = 48 kHz)
0.1 Fs (4.8 kHz at Fs = 48 kHz)
The filter block provides an audio passband ripple of +/-0.03 dB over a passband from 0 Hz to 0.454 sampling
frequency (Fs), and 70-dB minimum stopband attenuation from 0.548 Fs to 64 Fs.
The ADC modulator and digital filter operate on a clock that changes directly with Fs. This is in contrast to the
DAC, which keeps the modulator running at a high rate of 128 x 44.1 kHz or 128 x 48 kHz even if the incoming
data rate is much lower, such as 8 kHz. Group delay of the ADC path varies with sampling frequency and is
given by 28.7/Fs.
Audio ADC SNR performance is 88-dB-A typical over 20-Hz - 20-kHz bandwidth in 44.1/48-kHz mode with a
3.3-V supply level.
Each audio ADC is preceded by an analog volume control with gain programmable from 20 dB to -40 dB or mute
in 0.5-dB steps using Reg 01h, Pg 2. The input to these volume controls are selected as LLINEIN, RLINEIN,
MICIN, or a mono mix of LLINEIN and RLINEIN through the INML bits (Bits [13:12], Reg 00h, Pg 2). An
additional preamp gain is selectable on the MICIN input as 0 dB, 6 dB, or 12 dB using the MICG bits (Bits [9:8],
Reg 00h, Pg 2).
Audio Bypass Mode
In audio bypass mode, the L/RLINEIN analog inputs can be routed to mix with the DAC output and play to the
headphone outputs (HPL/R) and mono output (MONO). This path has a stereo analog volume control associated
with it, with range settings from 12.0 dB to -35.5 dB in 0.5-dB steps. If the audio ADCs and DACs are not used
while the bypass path is in use, the ADCs and DAC must be powered down to improve noise performance and
reduce power consumption.
This analog volume control has soft-stepping logic associated with it, so that when a volume change is made via
the SPI bus, the logic changes the actual volume incrementally, single-stepping the actual volume up or down
once every 20 µsec until it reaches the desired volume level.
This volume control also has similar algorithms as the ADC/DAC volume controls, in that the volume starts at
mute upon power-up, then is slowly single-stepped up to the desired level. At a power-down request, the volume
is slowly single-stepped down to mute before the circuit is actually powered down.
Monophonic Output (MONO)
The mono output of the TSC2302 can be used to drive a power amplifier which drives a low-impedance speaker.
This block can output either a mono mix of the stereo outputs, or the analog input to the left-channel ADC. This
is selected through the MONS bit (Bit 2, Reg 04h, Pg 2). The mono mix of the line outputs is represented by the
equation HPL/2 + HPR/2. Similarly, the mono mix of the analog line inputs is represented by LLINEIN/2 +
RLINEIN/2.
Microphone Bias Voltage (MICBIAS)
The TSC2302 provides an output voltage suitable for biasing an electret microphone capsule. This voltage is
always 1 V below the supply voltage of the part. This output can be disabled through the MIBPD bit (Bit 6, Reg
05h, Pg 2) to reduce power consumption if not used.
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Power Consumption
The TSC2302 provides maximum flexibility to the user for control of power consumption. Towards that end, every
section of the TSC2302 audio codec can be independently powered down. The power down status of the
different sections is controlled by Reg 05h in Pg 2. The analog bypass path, headphone amplifier, mono output,
stereo DAC, left channel ADC, right channel ADC, microphone bias, crystal oscillator, and oscillator clock buffer
sections can all be powered down independently. It is recommended that the end-user power down all unused
sections whenever possible in order to minimize power consumption. Below is a table showing power
consumption in different modes of operation.
Table 24. Power Consumption by Mode of Operation
OPERATING MODE DESCRIPTION REGISTER 05H BIT VALUES POWER CONSUMPTION
TYP UNITS
15 14 13 12 11 10 9 8 6 5 4
STEREO RECORD AND PLAYBACK
Mono record, stereo playback, 48 kHz 0 0 1 1 1 0 0 1 1 0 0 45 mW
Mono record, stereo playback, 8 kHz 0 0 1 1 1 0 0 1 1 0 0 38 mW
Stereo record, stereo playback, 48 kHz 0 0 1 1 1 0 0 0 1 0 0 60 mW
Stereo record, stereo playback, 8 kHz 0 0 1 1 1 0 0 0 1 0 0 48 mW
STEREO PLAYBACK ONLY
Headphone playback only, 48 kHz 0 0 1 0 1 0 1 1 1 0 0 34 mW
RECORD ONLY
Stereo line record only, 48 kHz 0 0 1 1 1 1 0 0 1 0 0 34 mW
Stereo line record only, 8 kHz 0 0 1 1 1 1 0 0 1 0 0 26 mW
Mono record, 48 kHz 0 0 1 1 1 1 0 1 1 0 0 19 mW
Mono record only, 8 kHz 0 0 1 1 1 1 0 1 1 0 0 15 mW
ANALOG BYPASS
Line in to headphone out 0 0 0 0 1 1 1 1 1 0 0 13 mW
POWER DOWN
Power down all 1 1 X X X X X X X 0 0 0.5 µW
Power down, VCM enabled 1 0 X X X X X X X 0 0 0.8 µW
TSC2302 AUDIO CONTROL REGISTERS
TSC2302 Audio Control Register (Page 2, Address 00H)
The audio control register of the TSC2302 controls the digital audio interface, the microphone preamp gain, the
record multiplexer settings, and the ADC highpass filter pole. This register determines which ADC high pass filter
response is selected, as well as which audio inputs are connected to the stereo ADCs. The gain of the MIC input
(0 to 12 dB) is also selected. This register is also used to tell the data converters the frequency of MCLK, along
with the frequency of LRCLK (ADC and DAC sample rates). The format of the audio data is also selected.
The audio control register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
HPF1 HPF0 INML1 INML0 INMR1 INMR0 MICG1 MICG0 MCLK1 MCLK0 I2SFS3 I2SFS2 I2SFS1 I2SFS0 I2SFM1 I2SFM0
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Bits [15:14] — HPF1-HPF0
ADC High Pass Filter. These two bits select the pass-band for the high-pass filter or disable the filter. The default
state of the filter is enabled, with -3-dB frequency at 0.000019xFs.
Table 25. High-Pass Filter Operation
HPF[1:0]
HPF1 HPF0 DESCRIPTION
0 0 HPF Disabled, signal passes through unaltered
0 1 HPF -3-dB frequency = 0.1xFs
1 0 HPF -3-dB frequency = 0.000078xFs
1 1 HPF -3-dB frequency = 0.000019xFs (default)
Bits [13:12] — INML1-INML0
Left Audio ADC Input Multiplexer. These two bits select the analog input for the left channel ADC. The input to
the left channel ADC can come from the microphone input, right line input, left line input, or from a mono mix of
the left and right line inputs. The default input to the left channel ADC is the microphone input.
Table 26. Left Audio ADC Input Selection
INML[1:0]
INML1 INML0 DESCRIPTION
0 0 ADCL input = MIC (default)
0 1 ADCL input = LLINEIN
1 0 ADCL input = RLINEIN
1 1 ADCL input = (RLINEIN+LLINEIN)/2
Bits [11:10] — INMR1-INMR0
Right Audio ADC Input Multiplexer. These two bits select the analog input for the right channel ADC. The input to
the right channel ADC can come from the microphone input, right line input, left line input, or from a mono mix of
the left and right line inputs. The default input to the right channel ADC is the microphone input.
Table 27. Right Audio ADC Input Selection
INMR[1:0]
INMR1 INMR0 DESCRIPTION
0 0 ADCR input = MIC (default)
0 1 ADCR input = LLINEIN
1 0 ADCR input = RLINEIN
1 1 ADCR input = (RLINEIN+LLINEIN)/2
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Bits [9:8] — MICG1-MICG0
Microphone Preamp Gain. These two bits select the gain of the microphone input channel. The gain of the
microphone input channel can be 0 dB, +6 dB, or +12 dB. The default gain of the microphone input channel is 0
dB.
Table 28. Microphone Input Gain Selection
MICG[1:0]
MICG1 MICG0 DESCRIPTION
0 0 MIC gain = 0 dB (default)
0 1 MIC gain = 0 dB
1 0 MIC gain = 6 dB
1 1 MIC gain = 12 dB
Bits [7:6] — MCLK1-MCLK0
Master Clock Ratio. These two bits select the ratio of the audio master clock frequency to the audio sampling
frequency. The ratio can be 256 Fs, 384 Fs, or 512 Fs. The default master clock frequency is 256 Fs.
Table 29. Master Clock Ratio Selection
MCLK[1:0]
MCLK1 MCLK0 DESCRIPTION
0 0 Master clock (MCLK) = 256 x Fs (default)
0 1 Master clock (MCLK) = 384 x Fs
1 0 Master clock (MCLK) = 512 x Fs
1 1 Master clock (MCLK) = 256 x Fs
Bits [5:2] — I2SFS3-I2SFS0
I2S Sample Rate. These bits tell the internal PLL what the audio sampling rate is so that it provides the proper
clock rate to the data converters and the digital filters. The default sample rate is 48 kHz. See Table 30 for a
complete listing of available sampling rates. All combinations of I2SFS[3:0] not in Table 30 are not valid.
Table 30. I2S Sample Rate Select
I2SFS3 I2SFS2 I2SFS1 I2SFS0 FUNCTION
0 0 0 0 Fs = 48 kHz (default)
0 0 0 1 Fs = 44.1 kHz
0 0 1 0 Fs = 32 kHz
0 0 1 1 Fs = 24 kHz
0 1 0 0 Fs = 22.05 kHz
0 1 0 1 Fs = 16 kHz
0 1 1 0 Fs = 12 kHz
0 1 1 1 Fs = 11.05 kHz
1 0 0 0 Fs = 8 kHz
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Bits [1:0] — I2SFM1-I2SFM0
I2S Format. These two bits select the I2S interface format. Both 16-bit and 20-bit data formats are supported. The
default format is 20-bit I2S.
Table 31. I2S Format Selection
I2SFM [1:0]
I2SFM1 I2SFM0 DESCRIPTION
0 0 DAC: 16-bit, MSB-first, right justified ADC: 16-bit, MSB-first, left justified
0 1 DAC: 20-bit, MSB-first, right justified ADC: 20-bit, MSB-first, left justified
1 0 DAC: 20-bit, MSB-first, left justified ADC: 20-bit, MSB-first, left justified
1 1 DAC: 20-bit, MSB-first, I2S (default) ADC: 20-bit, MSB-first, I2S (default)
ADC VOLUME CONTROL REGISTER (Page 2, Address 01h)
The ADC volume control register controls the independent programmable gain amplifiers (PGA’s) on the left and
right channel inputs to the audio ADCs of the TSC2302. The gain of these PGAs can be adjusted from
-40 dB to +20 dB in 0.5-dB steps. The ADC inputs can also be hard-muted, or internally shorted to VCM so that
no input signal is seen.
The ADC volume control register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
ADMUL ADVL6 ADVL5 ADVL4 ADVL3 ADVL2 ADVL1 ADVL0 ADMUR ADVR6 ADVR5 ADVR4 ADVR3 ADVR2 ADVR ADVR
1 0
Bit 15 — ADMUL
Left ADC Mute. This bit is used to mute the input to the left channel ADC volume control. The user can set this
bit to mute the ADC while retaining the previous gain setting in ADVL[6:0], so that the PGA returns to the
previous gain setting when ADMUL is cleared. When the ADMUL bit is set, the left ADC PGA soft-steps down to
its lowest level, then mutes. This procedure is used to reduce any audible artifacts (pops or clicks) during the
mute operation. This soft-stepping process is reversed when the ADMUL bit is cleared (unmute).
Table 32. Left ADC Mute
ADMUL DESCRIPTION
0 Left channel ADC is active.
1 Left channel ADC is mute. (default)
Bits [14:8] — ADVL6- ADVL0
Left ADC Volume Control. These 7 bits control the gain setting of the left channel ADC volume control. This
volume control can be programmed from -40 dB to +20 dB in 0.5-dB steps. Full volume (+20 dB) corresponds to
a setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any value
lower than 07h engages the mute function described above. Volume control changes are always soft-stepped, as
described above. The default volume setting is 0 dB.
ADVL[6:0] = 1010111 (087d) = 0 dB (default)
ADVL[6:0] = 1111111 (127d) = +20 dB (Max)
ADVL[6:0] = 0000111 (007d) = -40 dB (Min)
ADVL[6:0] = 0d-6d = mute
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Bit 7 — ADMUR
Right ADC Mute. This bit is used to mute the input to the right channel ADC. The user can set this bit to mute the
ADC while retaining the previous gain setting in ADVR[6:0], so that the PGA returns to the previous gain setting
when ADMUR is cleared. When the ADMUR bit is set, the right ADC PGA soft-steps down to its lowest level,
then mutes. This procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation.
This soft-stepping process is reversed when the ADMUR bit is cleared (unmute).
Table 33. Right ADC Mute
ADMUR DESCRIPTION
0 Right channel ADC is active.
1 Right channel ADC is mute. (default)
Bits [6:0] — ADVR6- ADVR0
Right ADC Volume Control. These 7 bits control the gain setting of the right channel ADC volume control PGA.
This volume control can be programmed from -40 dB to +20 dB in 0.5-dB steps. Full volume (+20 dB)
corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to
07h. Any value lower than 07h engages the mute function described above. Volume control changes are always
soft-stepped, as described above. The default volume setting is 0 dB.
ADVR[6:0] = 1010111 (087d) = 0 dB (default)
ADVR[6:0] = 1111111 (127d) = +20 dB (Max)
ADVR[6:0] = 0000111 (007d) = -40 dB (Min)
ADVR[6:0] = 0d-6d = mute
DAC VOLUME CONTROL REGISTER (Page 02, Address 02h)
The DAC volume control register controls the independent digital gain controls on the left and right channel audio
DAC’s of the TSC2302. The gain of the DACs can be adjusted from -63.5 dB to 0 dB in 0.5-dB steps. The DAC
inputs can also be muted, so that all zeroes are sent to the DAC interpolation filters.
The DAC volume control register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
DAMUL DAVL6 DAVL5 DAVL4 DAVL3 DAVL2 DAVL1 DAVL0 DAMUR DAVR6 DAVR5 DAVR4 DAVR3 DAVR2 DAVR DAVR
1 0
Bit 15 — DAMUL
Left DAC Mute. This bit is used to mute the input to the left channel DAC. The user can set this bit to mute the
DAC while retaining the previous gain setting in DAVL[6:0], so that the gain control returns to the previous gain
setting when DAMUL is cleared. When the DAMUL bit is set, the left DAC digital gain control soft-steps down to
its lowest level, then all zeroes are sent to the interpolation filter of this DAC. This procedure is used to reduce
any audible artifacts (pops or clicks) of the mute procedure. This soft-stepping process is reversed when the
DAMUL bit is cleared (unmute).
Table 34. Left DAC Mute
DAMUL DESCRIPTION
0 Left channel DAC is active.
1 Left channel DAC is mute. (default)
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Bits [14:8] — DAVL6- DAVL0
Left DAC Volume Control. These 7 bits control the gain setting of the left channel DAC volume control PGA. This
volume control can be programmed from -63.5 dB to 0 dB in 0.5-dB steps. Full volume (0 dB) corresponds to a
setting of 7Fh. Full attenuation (-63.5 dB) corresponds to 00h. The default volume setting is 0 dB.
DAVL[6:0] = 1111111 (127d) = 0 dB (default)
DAVL[6:0] = 0000000 (000d) = -63.5 dB (Min)
1LSB = 0.5 dB
Bit 7 — DAMUR
Right DAC Mute. This bit is used to mute the input to the right channel DAC. The user can set this bit to mute the
DAC while retaining the previous gain setting in DAVR[6:0], so that the gain control returns to the previous gain
setting when DAMUR is cleared. When the DAMUR bit is set, the left DAC digital gain control soft-steps down to
its lowest level, then all zeroes are sent to the interpolation filter of this DAC. This procedure is used to reduce
any audible artifacts (pops or clicks) of the mute procedure. This soft-stepping process is reversed when the
DAMUR bit is cleared (unmute).
Table 35. Right DAC Mute
DAMUR DESCRIPTION
0 Right channel DAC is active.
1 Right channel DAC is mute. (default)
Bits [6:0] — DAVR6- DAVR0
Right DAC Volume Control. These 7 bits control the gain setting of the right channel DAC volume control. This
volume control can be programmed from -63.5 dB to 0 dB in 0.5-dB steps. Full volume (0dB) corresponds to a
setting of 7Fh. Full attenuation (-63.5 dB) corresponds to 00h. The default volume setting is 0 dB.
DAVR[6:0] = 1111111 (127d) = 0 dB (default)
DAVR[6:0] = 0000000 (000d) = -63.5 dB (Min)
1LSB = 0.5 dB
ANALOG AUDIO BYPASS PATH VOLUME CONTROL REGISTER (Page 02, Address 03h)
The bypass path volume control register controls the independent programmable gain amplifiers (PGA’s) on the
left and right channel analog audio bypass paths of the TSC2302. These bypass paths direct the line inputs
directly to the headphone outputs entirely in the analog domain, with no A/D or D/A conversion. This feature can
be used for playback of an external analog source, such as an FM stereo tuner through the TSC2302’s
headphone amplifier. The gain of these PGA’s can be adjusted from -35.5 dB to 12 dB in 0.5 dB steps. The
bypass paths can also be muted, so that no signal is transmitted.
The bypass path volume control register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
BPMUL BPVL6 BPVL5 BPVL4 BPVL3 BPVL2 BPVL1 BPVL0 BPMUR BPVR6 BPVR5 BPVR4 BPVR3 BPVR2 BPVR BPVR
1 0
Bit 15 — BPMUL
Left Channel Audio Bypass Mute. This bit is used to mute the bypass path from the left channel line input
(LLINEIN) to the left channel headphone output. The user can set this bit to mute the bypass path while retaining
the previous gain setting in BPVL[6:0], so that the PGA returns to the previous gain setting when BPMUL is
cleared. When the BPMUL bit is set, the PGA soft-steps down to its lowest level, then the bypass path is muted.
This procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation. This
soft-stepping process is reversed when the BPMUL bit is cleared (unmute).
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Table 36. Left Channel Audio Bypass Mute
BPMUL DESCRIPTION
0 Left channel audio bypass path is active.
1 Left channel audio bypass path is mute. (default)
Bits [14:8] — BPVL6- BPVL0
Left Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the left channel bypass
path volume control PGA. This volume control can be programmed from -35.5 dB to 12 dB in 0.5 dB steps. Full
volume (12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation (-35.5 dB)
corresponds to 20h. Any value lower than 20h engages the mute function described above. The default volume
setting is 0 dB.
BPVL[6:0] = 1100111 (103d) = 0 dB (default)
BPVL[6:0] = 1111111 (127d) = 12 dB (Max)
BPVL[6:0] = 0100000 (032d) = -35.5 dB (Min)
BPVL[6:0] = 0d-31d = mute
Bit 7 — BPMUR
Right Channel Audio Bypass Mute. This bit is used to mute the bypass path from the right channel line input
(RLINEIN) to the headphone output. The user can set this bit to mute the bypass path while retaining the
previous gain setting in BPVR[6:0], so that the PGA returns to the previous gain setting when BPMUR is cleared.
When the BPMUR bit is set, the PGA soft-steps down to its lowest level, then the bypass path is muted. This
procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation. This soft-stepping
process is reversed when the BPMUR bit is cleared (unmute).
Table 37. Right Channel Audio Bypass Mute
BPMUR DESCRIPTION
0 Right channel audio bypass path is active.
1 Right channel audio bypass path is mute. (default)
Bits [6:0] — BPVR6- BPVR0
Right Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the right channel
bypass path volume control PGA. This volume control can be programmed from -35.5 dB to 12 dB in 0.5-dB
steps. Full volume (12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation
(-35.5 dB) corresponds to 20h. Any value lower than 20h engages the mute function described above. The
default volume setting is 0 dB.
BPVR[6:0] = 1100111 (103d) = 0 dB (default)
BPVR[6:0] = 1111111 (127d) = 12 dB (Max)
BPVR[6:0] = 0100000 (032d) = -35.5 dB (Min)
BPVR[6:0] = 0d-31d = mute
AUDIO CONTROL REGISTER 2 (Page 2, Address 04H)
The Audio Control Register 2 of the TSC2302 controls the input to the mono output, and the soft-stepping
function of the TSC2302 volume controls.
The keyclick control register is formatted as follows:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB LSB
RESV RESV RESV RESV RESV RESV RESV RESV RESV RESV RESV RESV RESV MONS SSRT SSTE
E P
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Bit [15:3] — RESERVED
These bits are reserved, and should be written to a default value.
Bit 2 — MONS
Mono Select. This bit determines the position of the mono multiplexer. This multiplexer allows either the left
channel ADC Input or the mono mix of the stereo headphone outputs to be played out of the differential mono
output (MONO+/-).
Table 38. Mono Select
MONS DESCRIPTION
0 Mono output comes from left ADC input (default).
1 Mono output comes from mono mix of headphone outputs.
Bit 1 — SSRTE
Volume Soft-stepping Rate Select. This bit selects the speed of the soft-stepping function of the TSC2302
volume controls. At normal speed, the actual volume is updated approximately once every 20 µs. At half speed,
the actual volume is updated approximately once every 40 µs.
Table 39. Volume Soft-Stepping Rate Select
SSRTE DESCRIPTION
0 Normal step rate used (default).
1 Half step rate used.
Bit 0 — SSTEP
Soft-step Flag. This read-only bit indicates that the TSC2302 volume control soft-stepping is completed.
Table 40. Soft-Step Flag
SSTEP DESCRIPTION
0 Soft-stepping is not complete
1 Soft-stepping is complete (default)
AUDIO POWER CONTROL REGISTER (Page 2, Address 05H)
The audio power / miscellaneous control register of the TSC2302 controls the powering down of various audio
blocks of the TSC2302. The default state of the TSC2302 has all audio blocks powered down. Before using any
of the audio blocks, they must be powered up by writing to this register. This register also controls the crystal
oscillator clock and buffer, the bass-boost filter, and the de-emphasis filter.
The audio power / miscellaneous control register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
APD AVPD ABPD HAPD MOPD DAPD ADPD ADPD PDSTS MIBPD OSCC BCKC SMPD OTSYN BASS DEEMP
L R
For bits 15 through 8 of this register, writing a 1 to a selected bit powers down the affected section, writing a 0
powers up the section.
Bit 15 — APD
Audio Power Down. This bit powers down the entire audio section if set, regardless of the settings of the other
bits in this register. When this bit is cleared, the individual sections of the audio codec still need to be powered
up individually. The settings of the other bits in the register are retained when this bit is set and cleared. The
default is 1 (powered down).
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Bit 14 — AVPD
Audio VCM Power Down. If this is set to 1, the VCM powers up whenever it is needed (such as when the audio
ADC, DAC, or bypass path is enabled) and powers down when no longer needed. If this bit is set to 0, after an
audio component is powered up and causes VCM to power up, it no longer powers down, even if all audio
components are powered down. This is intended to avoid the 500 µs delay needed for VCM to power up slowly.
The default is 1 (powered down).
Bit 13 — ABPD
Audio Bypass Path Power Down. This is used to power up (set to 0) or power down (set to 1) the audio bypass
path. The default is 1 (powered down).
Bits 12 — HAPD
Headphone Amplifier Power Down. This is used to power up (set to 0) or power down (set to 1) the headphone
amplifier. The default is 1 (powered down).
Bit 11 — MOPD
Mono Driver Power Down. This is used to power up (set to 0) or power down (set to 1) the mono output driver. If
only playback of the line or Mic inputs through the mono output is needed, the user need only power up the
mono section, and not the DAC or ADCs. The line inputs, Mic preamp, left channel ADC multiplexer and left
channel volume control all power up if the mono output is powered up. The default is 1 (powered down).
Bit 10 — DAPD
DAC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire stereo DAC. The
default is 1 (powered down).
Bit 9 — ADPDL
Left Channel ADC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire left
channel ADC. The line inputs, Mic preamp, left channel ADC multiplexer and left channel volume control all
automatically power up when the left channel ADC is powered up. The default is 1 (powered down).
Bit 8 — ADPDR
Right Channel ADC Power Down. This is used to power up (set to 0) or power down (set to 1) the entire right
channel ADC. The line inputs, Mic preamp, right channel ADC multiplexer and right channel volume control all
automatically power up when the right channel ADC is powered up. The default is 1 (powered down).
Bit 7 — PDSTS
Power Up/Down Done. This read-only bit indicates that all power-up or power-down processes requested are
completed.
Table 41. Power Up/Down Flag
PDSTS DESCRIPTION
0 Power up/down is not complete.
1 Power up/down is complete (default).
Bit 6 — MIBPD
Microphone Bias Power Down. This is used to power up (set to 0) or power down (set to 1) the microphone bias
output.
Table 42. Microphone Bias Power Down
OSCC DESCRIPTION
0 Microphone bias is on.
1 Microphone bias is off (default).
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Bit 5 — OSCC
Crystal Oscillator Control. This bit turns ON/OFF the crystal Oscillator.
Table 43. Crystal Oscillator Control
OSCC DESCRIPTION
0 Crystal oscillator is off (default).
1 Crystal oscillator is on.
Bit 4 — BCKC
Oscillator Clock Buffer Control. This bit turns ON/OFF the output clock buffer.
Table 44. Oscillator Clock Buffer Control
BCKC DESCRIPTION
0 The output clock buffer is off (default).
1 The output clock buffer is on.
Bit 3 — SMPD
Synchronization Monitor Power Down. This bit turns ON/OFF the I2S bus sync monitor.
Table 45. Synchronization Monitor Power Down
SMPD DESCRIPTION
0 The I2S bus sync monitor is on (default).
1 The I2S bus sync monitor is off.
Bit 2 — OTSYN
I2S Out Of Sync. This read-only sticky bit reflects the sync status of the I2S bus. It always resets to zero after
being read.
Table 46. I2S Out of Sync
OTSYN DESCRIPTION
0 The I2S bus is in sync (default).
1 The I2S bus is out of sync.
Bit 1 — BASS
Digital-effects filter control. This bit turns ON/OFF the digital-effects filter. If the digital-effects filter is off, the
signal passes through with no filtering performed.
Table 47. Digital-Effects Filter Control
BASS DESCRIPTION
0 The digital-effects filter is off (default).
1 The digital-effects filter is on.
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Bit 0 — DEEMP
De-emphasis control. This bit turns ON/OFF the de-emphasis function.
Table 48. De-Emphasis Control
DEEMP DESCRIPTION
0 De-emphasis is off (default).
1 De-emphasis is on.
GPIO CONTROL REGISTER (Page 02, Address 06h)
The GPIO control register controls the GPIO pins of the TSC2302. The direction of each GPIO pin can be set
independently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO’s
configured as inputs, the input data can be read from this register. This register also contains a bit, SDAVB which
mirrors the state of the DAVB output line.
The GPIO Control Register is formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
RESV RESV IO5 RESV RESV RESV RESV RESV RESV RESV GPIO5 RESV RESV RESV RESV RESV
Bits 15,14 — RESERVED
These bits are reserved and should be written to 0. If read, they read back as 0.
Bit 13 — IO5
GPIO Directional Control. This bit controls the direction of the TSC2302s GPIO pin. When this bit is set to one,
the corresponding GPIO pin is configured as an output. When this bit is set to zero, the corresponding GPIO pin
is configured as an input. The default setting of this bit is zero (input).
Bits 7,6 — RESERVED
These bits are reserved, and should be written to 0. If read, they read back as 0.
Bits 5 — GPIO5
GPIO Data. This bit controls the data on the GPIO pin. When the GPIO pin is configured as an output, the data
written to this bit is driven on the GPIO pin. When the GPIO pin is configured as an input, the data input on the
GPIO pin is returned to the corresponding register bit, and can be read by the host processor.
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DAC BASS-BOOST FILTER COEFFICIENT REGISTERS (Page 02, Addresses 07h-1Ah)
The DAC bass-boost coefficient registers implement the transfer function described. The coefficients are
represented by 16-bit twos complement integers with values ranging from -32768 to 32767.
The DAC bass-boost coefficient registers are formatted as follows:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 49. DAC Bass-Boost Coefficient Registers
ADDRESS DAC CHANNEL COEFFICIENT DEFAULT
07h Left N0 6BE2
08h Left N1 9667
09h Left N2 675D
0Ah Left N3 6BE2
0Bh Left N4 9667
0Ch Left N5 675D
0Dh Left D1 7D82
0Eh Left D2 84EF
0Fh Left D4 7D82
10h Left D5 84EF
11h Right N0 6BE2
12h Right N1 9667
13h Right N2 675D
14h Right N3 6BE2
15h Right N4 9667
16h Right N5 675D
17h Right D1 7D82
18h Right D2 84EF
19h Right D4 7D82
1Ah Right D5 84EF
AUDIO CLOCK CONFIGURATION REGISTER (Page 02, Address 1Bh)
This register allows the user to use the output of the crystal oscillator as MCLK, and receive the PLL output on
the PENIRQ pin.
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MSB LSB
X X X X X X X X X X X X PLPN COMK X X
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Bits [15:4] — RESERVED
These bits are reserved, and should be written to 040h. If read, they read back as 040h.
Bits 3 — PLPN
Output PLL on the PENIRQ pin. This bit allows the user to receive the output of the audio codec internal PLL.
This bit is provided so the host processor can use the output of the PLL, to generate its I2S signals in sync with
an external MCLK or crystal oscillator. Writing a 1 to this bit connects the output of the PLL to the PENIRQ pin.
Otherwise, the PENIRQ pin operates as normal. The user must take care in using this function, as PENIRQ
signals are overridden.
Table 50. Output PLL on PENIRQ Pin
DEEMP DESCRIPTION
0 PENIRQ operates as normal (default).
1 Output PLL on PENIRQ.
Bits 2 — COMK
Crystal Oscillator as MCLK. This bit allows the user to use the output of the internal crystal oscillator as the
MCLK for the audio codec. In this case, the MLCK pin must be grounded. In this case, the output of the crystal
oscillator replaces MCLK in all functions.
Table 51. Crystal Oscillator as MCLK
DEEMP DESCRIPTION
0 Crystal oscillator and MCLK operates as normal (default).
1 Use crystal oscillator output as MCLK.
Bits [1:0] — RESERVED
These bits are reserved, and must be written to 0. If read, they read back as 0.
LAYOUT
The following layout suggestions provide optimum performance from the TSC2302. However, many portable
applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable
devices have fairly clean power and grounds because most of the internal components are very low power. This
situation means less bypassing for the converter power and less concern regarding grounding. Still, each
situation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care must be taken with the physical layout of the TSC2302 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and
digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single
conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily
affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the
exact timing of the external event. The error can change if the external event changes in time with respect to the
internal conversion clock. The touch screen circuitry, as well as the audio headphone amplifiers, uses the
HPVDD/HPGND supplies for its power, and any noise on this supply may adversely affect performance in these
blocks.
As described earlier, the audio common-mode voltage VCM is derived directly through an internal resistor divider
between AVDD and AGND. Therefore, noise that couples onto AVDD/AGND is translated onto VCM and can
adversely impact audio performance. The reference pins for the audio data converters, VREF+/VREF-, should
also be kept as clean and noise-free as possible, since noise here affects audio DAC/ADC quality. De-coupling
capacitors are recommended between VREF+ and VREF-, in addition to a series resistance between VREF+
and the source of the voltage (such as connecting to the source providing AVDD).
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With this in mind, power to the TSC2302 must be clean and well bypassed. A 0.1-µF ceramic bypass capacitor
should be placed as close to the device as possible on each supply pin to its respective ground pin. A 1-µF to
10-µF capacitor may also be needed if the impedance of the connection between a supply and the power supply
is high.
A bypass capacitor on the SAR VREF pin may not be absolutely necessary because this reference is buffered by
an internal op amp, but a 0.1uF bypass capacitor may reduce noise on this reference. If an external reference
voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without
oscillation.
The TSC2302 SAR converter architecture offers no inherent rejection of noise or voltage variation in regards to
using an external reference input. This is of particular concern when the reference input is tied to the power
supply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noise
can be filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The HPGND pin must be connected to a clean ground point. In many cases, this is the analog ground for the
SAR converter. Avoid connections which are too near the grounding point of a microcontroller or digital signal
processor. If needed, run a ground trace directly from the converter to the power supply entry or battery
connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated
analog circuitry.
In the specific case of use with a resistive touch screen, care must be taken with the connection between the
converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection
should be as short and robust as possible. Loose connections can be a source of error when the contact
resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch screen applications (e.g., applications that
require a back-lit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and
cause flickering of the converted data. Several things can be done to reduce this error, such as utilizing a touch
screen with a bottom-side metal layer connected to ground. This couples the majority of noise to ground.
Additionally, filtering capacitors, from Y+, Y-, X+, and X- to ground, can also help. Note, however, that the use of
these capacitors increases screen settling time and requires longer panel voltage stabilization times, as well as
increased precharge and sense times for the touch screen control circuitry of the TSC2302.
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TSC2302IRGZ ACTIVE VQFN RGZ 48 52 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TSC2302IRGZG4 ACTIVE VQFN RGZ 48 52 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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