MX1DS10P 15 GHz Ultra - Variable Broadband Prescaler Features * Wide Operating Range: 0.05 - 15 GHz * Variable Divide Ratios: 2 to 220 * Single-Ended and/or Differential Drive * High Input Sensitivity * Size: 6mm x 6mm * Single -3.3 V Power Supply * Low SSB Phase Noise: 153 dBc @ 10 kHz Description The MX1DS10P is a broadband 0.05GHz to 15GHz prescaler with a variable divide ratio between 2 and 1048576 (=220). All inputs and outputs are DC coupled using CML logic levels. The IC used in this part is manufactured in an advanced Silicon Germanium (SiGe) process. The part requires a single 3.3V supply and measures only 6mm x 6mm. Application The MX1DS10P is ideal for phase locked loops and other synthesizers requiring large and variable divide ratios. Other applications include trigger generation for high-speed measurement systems. The MX1DS10P can be employed in high frequency phase locked loops that can take advantage of the low 1/f noise of SiGe HBT's. General purpose test instrumentation systems will also benefit from the high input sensitivity and broad frequency range. Pad Metallization The QFN package pad metallization consists of a 300-800 micro-inch (typical thickness 435 micro-inch or 11.04um) 100% matte Sn plate. The plating covers a Cu (C194) leadframe. The packages are manufactured with a >1hr 150C annealing/heat treating process, and the matte (non-glossy) plating, specifically to mitigate tin whisker growth. Key Specifications (T = 25C): Vee = -3.3 V, Iee = 430 mA, Zo=50 Parameter Description Min Typ Max Clkin (GHz) Input Clock Frequency 0.05 - 15 Clkpwr (dBm) Input Clock Power Max - - 10 Clkpwr (dBm) Input Clock Power Min - -10 - Dout (Vppk) Output Voltage Swing 0.05 1 - Junction-Case Thermal Resistance - 13 - jc (C/W) Parameter Description Min Typ Max S11 (dB) Input Match (Typical) -12 -7 -5 S22 (dB) Output Match (Typical) -7 -5 -3 SMD-00028 Rev E Subject to Change Without Notice 1 of 9 MX1DS10P Frequency Divider Application Return Loss of Differential Input Ports Return Loss of Differential Output Ports Input Sensitivity Window Divide-by-2 Output (Input: 10 GHz; Output: 5 GHz) Divide-by-(8/3) Output (Input: 10 GHz; Output: 3.75 GHz) Divide-by-2048 Output (Input: 10 GHz; Output: 4.9 MHz) SMD-00028 Rev E Subject to Change Without Notice 2 of 9 MX1DS10P Functional Block Diagram SEED = A1 + (A2 x 21) + (A3 x 22) + .......+ (A20 x 219) (Maximum valid SEED = 219) Divide Ratio = 220 / SEED (Lowest valid divide ration = 2) Freqout = Freqclk / (Divide Ratio) Table 1: Pin Description Port Name Description Notes CK Clock Input, Positive Terminal CML signal levels CKN Clock Input, Negative Terminal CML signal levels MSB Divided Output, Positive Terminal CML signal levels MSBN Divided Output, Negative Terminal CML signal levels A1,A2...A20 Divide Ratio Selectors Divide ratio = Value of the binary seed A1...A20 VCC RF & DC Ground - VEE -3.3 V @ 400 mA Negative Supply Voltage Paddle Backside of die Must be connected to good heatsink (see text) Simplified Control Logic Schematic SMD-00028 Rev E Subject to Change Without Notice 3 of 9 MX1DS10P Application Notes Divider Outputs: The equivalent circuit of the divider outputs is shown below. The outputs require a DC return path capable of handling ~35 mA per side. If DC coupling is employed, the DC resistance of the receiving circuits should be ~50 (or less) to VCC to prevent excessive common mode voltage from saturating the prescaler outputs. If AC coupling is used, the perfect embodiment is shown in figure 2. The discrete R/L/C elements should be resonance free up to the maximum frequency of operation for broadband applications. The output amplitude can be adjusted over a 1.5:1 range by one of the two methods The Vadj pin voltage can be set to VCC for maximum amplituded or VCC-1.3 V for an amplitude ~2/3 the max swing. Voltages between these two values will produce a linear change in output swing. Alternatively, users can use a 1k potentiometer or fixed resistor tied between Vadj and VCC. Resistor values approaching 0 ohms will lead to the maximum swing, while values approaching 1k will lead to the minimum output swing. Users who only need/want the maximum swing should simply tie Vadj to VCC. Equivalent Circuit of Output Buffer Recommended Circuit for AC Coupled Outputs Low Frequency Operation: Low frequency operation is limited by external bypass capacitors and the slew rate of the input clock. The next paragraph shows the calculations for the bypass capacitors. If DC coupled, the device operates down to DC for square-wave inputs. Sine-wave inputs are limited to ~50 MHz due to the 10 dBm max input power limitation. The values of the coupling capacitors for the high-speed inputs and outputs (I/O's) are determined by the lowest frequency the IC will be operated at. C>> 1 2**50*flowest For example to use the device below 30 kHz, coupling capacitors should be larger than 0.1uF. Package Heatsink: The package backside provides the primary heat conduction path and should be attached to a good heatsink on the PC board to maximize performance. User PC boards should maximize the contact area to the package paddle and contain an array of vias to aid thermal conduction to either a backside heatsink or internal copper planes. MM-PDS-0038 Rev A Subject to Change Without Notice 4 of 9 MX1DS10P IC Assembly: The device is designed to operate with either single-ended or differential inputs. Figures 1, 2 & 3 show the IC assembly diagrams for positive and negative supply voltages. In either case the supply should be capacitively bypassed to the ground to provide a good AC ground over the frequency range of interest. The backside of the chip should be connected to a good thermal heat sink. All RF I/O's are connected to VCC through on-chip termination resistors. This implies that when VCC is not DC grounded (as in the case of positive supply), the RF I/O's should be AC coupled through series capacitors unless the connecting circuit can generate the correct levels through level shifting. ESD Sensitivity: Although SiGe IC's have robust ESD sensitivities, preventive ESD measures should be taken while storing, handling, and assembling. Inputs are more ESD susceptible as they could expose the base of a BJT or the gate of a MOSFET. For this reason, all the inputs are protected with ESD diodes. These inputs have been tested to withstand voltage spikes up to 400V. CML Logic Levels for DC Coupling (T=25C): Assuming 50 Terminations at Inputs and Outputs Parameter Differential Minimum Typical Maximum { Logic Inputhigh Vcc Vcc Vcc Logic Inputlow Vcc - 0.05 V Vcc - 0.3 V Vcc - 1 V { Logic Inputhigh Vcc + 0.05 V Vcc + 0.3 V Vcc + 1 V Logic Inputlow Vcc - 0.05 V Vcc - 0.3 V Vcc - 1 V { Logic Inputhigh Vcc Vcc Vcc Logic Inputlow Vcc - 0.2 V Vcc - 0.3 V Vcc - 0.6 V Input Single Output Differential & Single Differential versus Single-Ended: The MX1DS10P is fully differential to maximize signal-to-noise ratios for high-speed operation. All high speed inputs and outputs are terminated to Vcc with on-chip resistors (refer to functional block diagram for specific resistor values). The maximum DC voltage on any terminal must be limited to V max to prevent damaging the termination resistors with excessive current. Regardless of bias conditions, the following equation should be satisfied when driving the inputs differentially: I Vdm/2 + Vcm I < Vcc Vmax where Vdm is the differential input signal and Vcm is the common-mode voltage. In addition to the maximum input signal levels, single-ended operation imposes additional restrictions: the average DC value of the waveform at IC should be equal to Vcc for single-ended operation. In practice, this is easily achieved with a single capacitor on the input acting as a DC block. The value of the capacitor should be large enough to pass the lowest frequencies of interest. Use the positive terminals for single-ended operation while terminating the negative terminal to Vcc. MM-PDS-0038 Rev A Subject to Change Without Notice 5 of 9 MX1DS10P Differential vs. Single-Ended: The MX1DS10P is fully differential to maximize signal-to-noise ratios for high-speed operation. All high speed inputs and outputs are terminated to Vcc with on-chip resistors (refer to functional block diagram for specific resistor values). The maximum DC voltage on any terminal must be limited to V max to prevent damaging the termination resistors with excessive current. Regardless of bias conditions, the following equation should be satisfied when driving the inputs differentially: I Vdm/2 + Vcm I < Vcc Vmax where Vdm is the differential input signal and Vcm is the common-mode voltage. In addition to the maximum input signal levels, single-ended operation imposes additional restrictions: the average DC value of the waveform at IC should be equal to Vcc for single-ended operation. In practice, this is easily achieved with a single capacitor on the input acting as a DC block. The value of the capacitor should be large enough to pass the lowest frequencies of interest. Use the positive terminals for single-ended operation while terminating the negative terminal to Vcc. Note that a potential oscillation mechanism exists if both inputs are static and have identical DC voltages; a small DC offset on either input is sufficient to prevent possible oscillations. Tying unused inputs directly to Vcc shorts out the internal 50 bias resistor, imposing a DC offset sufficient to prevent oscillations. Driving the differential inputs with DC blocks, or driving the single-ended inputs without terminating unused inputs, is not recommended without taking additional steps to eliminate the potential oscillation issues. Positive Supply (AC Coupling) Biasing recommendations for positive supply with AC coupling applications MM-PDS-0038 Rev A Subject to Change Without Notice 6 of 9 MX1DS10P Negative Supply (DC Coupling) Biasing recommendations for negative supply with DC coupling applications Negative Supply (AC Coupling) Biasing recommendations for negative supply with AC coupling applications MM-PDS-0038 Rev A Subject to Change Without Notice 7 of 9 MX1DS10P MX1DS10P Physical Characteristics Pkg size: 6.00 x 6.00 mm Pkg size tolerance: +/- 0.25 mm Pkg thickness: 0.9 +/- 0.1 mm Pad dimensions: 0.23 x 0.4 mm Center paddle: 4.20 x 4.20 mm JEDEC designator: MO-220 Top View Table 2: MX1DS10P Pin Definition Function Notes 5,14,22,26,37 (Vcc) RF and DC Ground 0V 1,6,9,13,17,27,34 (Vee) Negative Supply Voltage Nominally -3.3 V 31,32,35,36 - No Connection 2 (A4) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 3 (A5) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 4 (A6) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 7 (CKN) Clock Input Negative Terminal of differential input 8 (CK) Clock Input Positive Terminal of differential Input 10 (A7) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 11 (A8) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 12 (A9) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 15 (A10) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 16 (A11) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 18 (A12) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 19 (A13) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 20 (A14) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 21 (A15) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 23 (A16) Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 24 (A17) Divide Ratio Selector Divide Ratio Selector Divider Output Divider Output Divide Ratio Selector Divide Ratio Selector Divide Ratio Selector Divide Ratio Selector Divide Ratio Selector Defaults to logic 0, connect to 0V for logic 1 25 (A18) 28 (MSBN) 29 (MSB) 30 (A19) 33 (A20) 38 (A1) 39 (A2) 40 (A3) MM-PDS-0038 Rev A Subject to Change Without Notice Defaults to logic 0, connect to 0V for logic 1 Negative Terminal of differential output Positive Terminal of differential output Defaults to logic 0, connect to 0V for logic 1 Defaults to logic 0, connect to 0V for logic 1 Defaults to logic 0, connect to 0V for logic 1 Defaults to logic 0, connect to 0V for logic 1 Defaults to logic 0, connect to 0V for logic 1 8 of 9 MX1DS10P Table 3: Absolute Maximum Ratings Parameter Value Unit Supply Voltage (Vcc-Vee) 4 V RF Input Power (CK,CKN) 10 dBm Max DC Voltage Level (MSB, MSBN) Vcc+1 V V Min DC Voltage Level (MSB, MSBN) Vcc-1V V Max DC Voltage Level (A1,A2,...A20) Vcc V Min DC Voltage Level (A1,A2,...A20) Vee V Operating Temperature -40 to 85 C Storage Temperature -85 to 125 C Junction Temperature 125 C MM-PDS-0038 Rev A Subject to Change Without Notice 9 of 9 MX1DS10P Information contained in this document is proprietary to Microsem. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Microsemi Corporate Headquarters Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor One Enterprise, Aliso Viejo CA 92656 USA and system solutions for communications, defense and security, aerospace, and industrial Within the USA: +1 (949) 380-6100 markets. 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