MTA18ASF1G72AZ-2G3B1 - MICRON TECHNOLOGY

DDR4 SDRAM UDIMM

MTA18ASF1G72AZ – 8GB

Features

• DDR4 functionality and operations supported as

defined in the component data sheet

• 288-pin, unbuffered dual in-line memory module

(UDIMM)

• Fast data transfer rates: PCB4-2666, PC4-2400

• 8GB (1 Gig x 72)

• VDD = 1.20V (NOM)

• VPP = 2.5V (NOM)

• VDDSPD = 2.5V (NOM)

• Supports ECC error detection and correction

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Low-power auto self refresh (LPASR)

• Data bus inversion (DBI) for data bus

• On-die VREFDQ generation and calibration

• Dual-rank

• Onboard I2C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

• 4 internal device bank groups with 4 banks per

group produce 16 device banks

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1: 288-Pin UDIMM (MO-309, R/C-E1)

Module height: 31.25mm (1.23in)

Options Marking

• Operating temperature

– Commercial

(0°C ≤ TOPER ≤ 95°C)

None

• Package

– 288-pin DIMM (halogen-free) Z

• Frequency/CAS latency

– 0.75ns @ CL = 19 (DDR4-2666) -2G6

– 0.83ns @ CL = 17 (DDR4-2400) -2G3

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomen-

clature

Data Rate (MT/s)

tRCD

(ns)

tRP

(ns)

tRC

(ns)

CL =

20,

CL =

10 CL = 9

-2G6 PC4-2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 – 14.16 14.16 46.16

-2G4 PC4-2400 – 2400 2400 2400

2133

2133 1866 1866 1600 1600 1333 1333 13.32 13.32 45.32

-2G3 PC4-2400 – 2400 2400 2133 2133 1866 1866 1600 1600 1333 – 14.16 14.16 46.16

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Features

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 1: Key Timing Parameters (Continued)

Speed

Grade

Industry

Nomen-

clature

Data Rate (MT/s)

tRCD

(ns)

tRP

(ns)

tRC

(ns)

CL =

20,

CL =

10 CL = 9

-2G1 PC4-2133 – – – 2133 2133 1866 1866 1600 1600 1333 1333 13.5 13.5 46.5

Table 2: Addressing

Parameter 8GB

Row address 32K A[14:0]

Column address 1K A[9:0]

Device bank group address 4 BG[1:0]

Device bank address per group 4 BA[1:0]

Device configuration 4Gb (512 Meg x 8), 16 banks

Module rank address 2 CS_n[1:0]

Table 3: Part Numbers and Timing Parameters – 8GB Modules

Base device: MT40A512M8,1 4Gb DDR4 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MTA18ASF1G72AZ-2G6__ 8GB 1 Gig x 72 21.3 GB/s 0.75ns/2400 MT/s 19-19-19

MTA18ASF1G72AZ-2G3__ 8GB 1 Gig x 72 19.2 GB/s 0.83ns/2400 MT/s 17-17-17

Notes: 1. The data sheet for the base device can be found at micron.com.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MTA18ASF1G72AZ-2G6B1.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Features

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

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8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Features

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Pin Assignments

The pin assignment table below is a comprehensive list of all possible pin assignments

for DDR4 UDIMM modules. See Functional Block Diagram for pins specific to this

module.

Table 4: Pin Assignments

288-Pin DDR4 UDIMM Front 288-Pin DDR4 UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 NC 37 VSS 73 VDD 109 VSS 145 NC 181 DQ29 217 VDD 253 DQ41

2 VSS 38 DQ24 74 CK0_t 110 DM5_n/

DBI5_n,

146 VREFCA 182 VSS 218 CK1_t 254 VSS

3 DQ4 39 VSS 75 CK0_c 111 NC 147 VSS 183 DQ25 219 CK1_c 255 DQS5_c

4 VSS 40 DM3_n/

DBI3_n,

76 VDD 112 VSS 148 DQ5 184 VSS 220 VDD 256 DQS5_t

5 DQ0 41 NC 77 VTT 113 DQ46 149 VSS 185 DQS3_c 221 VTT 257 VSS

6 VSS 42 VSS 78 EVENT_n,

114 VSS 150 DQ1 186 DQS3_t 222 PARITY 258 DQ47

7 DM0_n/

DBI0_n,

43 DQ30 79 A0 115 DQ42 151 VSS 187 VSS 223 VDD 259 VSS

8 NC 44 VSS 80 VDD 116 VSS 152 DQS0_c 188 DQ31 224 BA1 260 DQ43

9 VSS 45 DQ26 81 BA0 117 DQ52 153 DQS0_t 189 VSS 225 A10_AP 261 VSS

10 DQ6 46 VSS 82 RAS_n/

A16

118 VSS 154 VSS 190 DQ27 226 VDD 262 DQ53

11 VSS 47 CB4/ NC 83 VDD 119 DQ48 155 DQ7 191 VSS 227 NC 263 VSS

12 DQ2 48 VSS 84 CS0_n 120 VSS 156 VSS 192 CB5, NC 228 WE_n/

A14

264 DQ49

13 VSS 49 CB0/ NC 85 VDD 121 DM6_n/

DBI6_n,

157 DQ3 193 VSS 229 VDD 265 VSS

14 DQ12 50 VSS 86 CAS_n/

A15

122 NC 158 VSS 194 CB1, NC 230 NC 266 DQS6_c

15 VSS 51 DM8_n/

DBI8_n,

87 ODT0 123 VSS 159 DQ13 195 VSS 231 VDD 267 DQS6_t

16 DQ8 52 NC 88 VDD 124 DQ54 160 VSS 196 DQS8_c 232 A13 268 VSS

17 VSS 53 VSS 89 CS1_n,

125 VSS 161 DQ9 197 DQS8_t 233 VDD 269 DQ55

18 DMI_n/

DBI1_n,

54 CB6/

DBI8_n,

90 VDD 126 DQ50 162 VSS 198 VSS 234 NC 270 VSS

19 NC 55 VSS 91 ODT1,

127 VSS 163 DQS1_c 199 CB7, NC 235 NC 271 DQ51

20 VSS 56 CB2/ NC 92 VDD 128 DQ60 164 DQS1_t 200 VSS 236 VDD 272 VSS

21 DQ14 57 VSS 93 NC 129 VSS 165 VSS 201 CB3, NC 237 NC 273 DQ61

22 VSS 58 RESET_n 94 VSS 130 DQ56 166 DQ15 202 VSS 238 SA2 274 VSS

23 DQ10 59 VDD 95 DQ36 131 VSS 167 VSS 203 CKE1,

239 VSS 275 DQ57

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Pin Assignments

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: Pin Assignments (Continued)

288-Pin DDR4 UDIMM Front 288-Pin DDR4 UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

24 VSS 60 CKE0 96 VSS 132 DM7_n/

DBI7_n,

168 DQ11 204 VDD 240 DQ37 276 VSS

25 DQ20 61 VDD 97 DQ32 133 NC 169 VSS 205 NC 241 VSS 277 DQS7_c

26 VSS 62 ACT_n 98 VSS 134 VSS 170 DQ21 206 VDD 242 DQ33 278 DQS7_t

27 DQ16 63 BG0 99 DM4_n/

DBI4_n,

135 DQ62 171 VSS 207 BG1 243 VSS 279 VSS

28 VSS 64 VDD 100 NC 136 VSS 172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63

29 DM2_n/

DBI2_n,

65 A12/BC_n 101 VSS 137 DQ58 173 VSS 209 VDD 245 DQS4_t 281 VSS

30 NC 66 A9 102 DQ38 138 VSS 174 DQS2_c 210 A11 246 VSS 282 DQ59

31 VSS 67 VDD 103 VSS 139 SA0 175 DQS2_t 211 A7 247 DQ39 283 VSS

32 DQ22 68 A8 104 DQ34 140 SA1 176 VSS 212 VDD 248 VSS 284 VDDSPD

33 VSS 69 A6 105 VSS 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA

34 DQ18 70 VDD 106 DQ44 142 VPP 178 VSS 214 A4 250 VSS 286 VPP

35 VSS 71 A3 107 VSS 143 VPP 179 DQ19 215 VDD 251 DQ45 287 VPP

36 DQ28 72 A1 108 DQ40 144 NC 180 VSS 216 A2 252 VSS 288 VPP

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Pin Assignments

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4

modules. All pins listed may not be supported on this module. See Functional Block Di-

agram for pins specific to this module.

Table 5: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for

READ/WRITE commands in order to select one location out of the memory array in the respec-

tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;

see individual entries in this table). The address inputs also provide the op-code during the

MODE REGISTER SET command. A17 is only defined for x4 SDRAM.

A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an

auto precharge should be performed on the accessed bank after a READ or WRITE operation

(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-

mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank

addresses.

A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst

chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst chopped). See Com-

mand Truth Table in the DDR4 component data sheet.

ACT_n Input Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The

input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and

A14. See Command Truth Table.

BAx Input Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command.

BGx Input Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-

tions. x16-based SDRAM only has BG0.

C0, C1, C2

(RDIMM/LRDIMM on-

ly)

Input Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for

x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16

configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,

CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,

are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used

as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of

the command code.

CKx_t

CKx_c

Input Clock: Differential clock inputs. All address, command, and control input signals are sampled

on the crossing of the positive edge of CK_t and the negative edge of CK_c.

CKEx Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device

input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and

SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is

asynchronous for self refresh exit. After VREFCA has become stable during the power-on and ini-

tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE

must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,

CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE

and RESET_n) are disabled during self refresh.

CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external

rank selection on systems with multiple ranks. CS_n is considered part of the command code

(CS2_n and CS3_n are not used on UDIMMs).

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Pin Descriptions

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions (Continued)

Symbol Type Description

ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the

DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/

DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is ena-

bled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,

DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode

registers are programmed to disable RTT.

PARITY Input Parity for command and address: This function can be enabled or disabled via the mode

WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the

clock and at the same time as command and address with CS_n LOW.

RAS_n/A16

CAS_n/A15

WE_n/A14

Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-

mand and/or address being entered and have multiple functions. For example, for activation

with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation com-

mand with ACT_n HIGH, these are command pins for READ, WRITE, and other commands de-

fined in Command Truth Table.

RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE-

SET_n is HIGH. RESET_n must be HIGH during normal operation.

SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range

on the I2C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to

and from the temperature sensor/SPD EEPROM on the I2C bus.

DQx, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. DQ represents

DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic re-

dundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of

the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of inter-

nal VREF level during test via mode register setting MR[4] A[4] = HIGH; training times change

when enabled.

DM_n/DBI_n/

TDQS_t (DMU_n,

DBIU_n), (DML_n/

DBIl_n)

I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input

data is masked when DM_n is sampled LOW coincident with that input data during a write ac-

cess. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the

mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS

is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying

whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/

output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only

supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).

SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS

combo device.

DQS_t

DQS_c

DQSU_t

DQSU_c

DQSL_t

DQSL_c

I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, cen-

tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on

DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS

corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differen-

tial data strobe only and does not support a single-ended data strobe.

ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error

flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and

returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW un-

til the on-going DRAM internal recovery transaction is complete. During connectivity test mode,

this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,

ALERT_n pin must be connected to VDD on DIMMs.

EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical tem-

perature thresholds have been exceeded. This pin has no function (NF) on modules without

temperature sensors.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Pin Descriptions

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions (Continued)

Symbol Type Description

TDQS_t

TDQS_c

(x8 DRAM-based

RDIMM only)

Output Termination data strobe: When enabled via the mode register, the DRAM device enables the

same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.

When the TDQS function is disabled via the mode register, the DM/TDQS_t pin provides the da-

ta mask (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in

the mode register for both the x4 and x16 configurations. The DM function is supported only in

x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are enabled/disabled by

mode register settings. For more information about TDQS, see the DDR4 DRAM component da-

ta sheet (TDQS_t and TDQS_c are not valid for UDIMMs).

VDD Supply Module power supply: 1.2V (TYP).

VPP Supply DRAM activating power supply: 2.5V –0.125V / +0.250V.

VREFCA Supply Reference voltage for control, command, and address pins.

VSS Supply Ground.

VTT Supply Power supply for termination of address, command, and control VDD/2.

VDDSPD Supply Power supply used to power the I2C bus for SPD.

RFU – Reserved for future use.

NC – No connect: No internal electrical connection is present.

NF – No function: May have internal connection present, but has no function.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Pin Descriptions

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

DQ Map

Table 6: Component-to-Module DQ Map

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U1 0 3 157 U2 0 10 23

1 0 5 1 9 161

2 2 12 2 11 168

3 1 150 3 8 16

4 7 155 4 14 21

5 4 3 5 13 159

6 6 10 6 15 166

7 5 148 7 12 14

U3 0 18 34 U4 0 26 45

1 17 172 1 24 38

2 19 179 2 27 190

3 16 27 3 25 183

4 22 32 4 31 188

5 21 170 5 28 36

6 23 177 6 30 43

7 20 25 7 29 181

U5 0 CB2 56 U7 0 34 104

1 CB1 194 1 32 97

2 CB3 201 2 35 249

3 CB0 49 3 33 242

4 CB6 54 4 38 102

5 CB5 192 5 37 240

6 CB7 199 6 39 247

7 CB4 47 7 36 95

U8 0 42 115 U9 0 50 126

1 40 108 1 48 119

2 43 260 2 51 271

3 41 253 3 49 264

4 47 258 4 54 124

5 44 106 5 53 262

6 46 113 6 55 269

7 45 251 7 52 117

U10 0 58 137 U11 0 57 257

1 57 275 1 58 137

2 59 282 2 56 130

3 56 130 3 59 282

4 63 280 4 61 273

5 61 273 5 63 280

6 62 135 6 60 128

7 60 128 7 62 135

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

DQ Map

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 6: Component-to-Module DQ Map (Continued)

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U12 0 48 119 U13 0 40 108

1 50 126 1 42 115

2 49 264 2 41 253

3 51 271 3 43 260

4 53 262 4 44 106

5 54 124 5 47 258

6 52 117 6 45 251

7 55 269 7 46 113

U14 0 32 97 U15 0 CB1 194

1 34 104 1 CB2 56

2 33 242 2 CB0 49

3 35 249 3 CB3 201

4 37 240 4 CB5 192

5 38 102 5 CB6 54

6 36 95 6 CB4 47

7 39 247 7 CB7 199

U16 0 24 38 U17 0 17 172

1 26 45 1 18 34

2 25 183 2 16 27

3 27 190 3 19 179

4 28 36 4 21 170

5 31 188 5 22 32

6 29 181 6 20 25

7 30 43 7 23 177

U18 0 9 161 U19 0 0 5

1 10 23 1 3 157

2 8 16 2 1 150

3 11 168 3 2 12

4 13 159 4 4 3

5 14 21 5 7 155

6 12 14 6 5 148

7 15 166 7 6 10

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

DQ Map

PDF: CCMTD-1725822587-9423

asf18c1gx72az.pdf – Rev. G 11/17 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U19

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U14

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U18

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U13

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U17

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U12

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U16

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U10

U11

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

U15

CS1_n

CS0_n

Rank 0: U1–U5, U7–10

Rank 1: U11–U19

Rank 0

CK0

CK0#

CK1

CK1#

Vref CA

Vss

DDR4 SDRAM

Vdd

Vddspd Temperature sensor/

SPD EEPROM

Vtt

DDR4 SDRAM

Vpp

Clock, control, command, and address line terminations:

Rank 1

Vss

Temperature

sensor/

SPD EEPROM

A1 A2

SA0 SA1

SDA

SCL

EVT

EVENT#

SA2

Control, command, and

address termination

DDR4

SDRAM

VTT

CK#

DDR4

SDRAM

VDD

DM_n/ CS_n DQS_t DQS_c

DBI_n

DQS0_t

DQS0_c

DBI0_n/DM0_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DQS1_t

DQS1_c

DBI1_n/DM1_n

DQS2_t

DQS2_c

DBI2_n/DM2_n

DQS3_t

DQS3_c

DBI3_n/DM3_n

DQS8_t

DQS8_c

DBI8_n/DM8_n

DQS4_t

DQS4_c

DBI4_n/DM4_n

DQS5_t

DQS5_c

DBI5_n/DM5_n

DQS6_t

DQS6_c

DBI6_n/DM6_n

DQS7_t

DQS7_c

DBI7_n/DM7_n

BA[1:0]

BG[1:0]

ACT_n

A[13:0]

RAS_n/A16

CAS_n/A15

WE_n/A14

CKE0

CKE1

ODT0

ODT1

RESET

PAR_IN

ALERT_CONN

BA[1:0]: DDR4 SDRAM

BG[1:0]: DDR4 SDRAM

ACT_n: DDR4 SDRAM

A[13:0]: DDR4 SDRAM

RAS_n/A16: DDR4 SDRAM

CAS_n/A15: DDR4 SDRAM

WE_n/A14: DDR4 SDRAM

CKE0: Rank 0

CKE1: Rank 1

ODT0: Rank 0

ODT1: Rank 1

RESET_n: DDR4 SDRAM

PAR: DDR4 SDRAM

ALERT_DRAM: DDR4 SDRAM

CS_n[1:0], BA[1:0], BG[1:0],

ACT_n, A[13:0], RAS_n/A16,

CAS_n/A15, WE_n/A14,

CKE[1:0], ODT[1:0]

Note: 1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor

that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Functional Block Diagram

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General Description

High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal

memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM

devices have four internal bank groups consisting of four memory banks each, provid-

ing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank

groups consisting of four memory banks each, providing a total of eight banks. DDR4

SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with

an interface designed to transfer two data words per clock cycle at the I/O pins. A single

READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-

wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-

wide, one-half-clock-cycle data transfers at the I/O pins.

DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data

and CK_t and CK_c to capture commands, addresses, and control signals. Differential

clocks and data strobes ensure exceptional noise immunity for these signals and pro-

vide precise crossing points to capture input signals.

Fly-By Topology

DDR4 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock, con-

trol, command, and address pin on each DRAM is connected to a single trace and ter-

minated (rather than a tree structure, where the termination is off the module near the

connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-

nals can be easily accounted for by using the write-leveling feature of DDR4.

Module Manufacturing Location

Micron Technology manufactures modules at sites world-wide. Customers may receive

modules from any of the following manufacturing locations:

Table 7: DRAM Module Manufacturing Locations

Manufacturing Site Location Country of Origin Specified on Label

Boise, USA USA

Aguadilla, Puerto Rico Puerto Rico

Xian, China China

Singapore Singapore

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

General Description

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Address Mapping to DRAM

Address Mirroring

To achieve optimum routing of the address bus on DDR4 multi rank modules, the ad-

dress bus will be wired as shown in the table below, or mirrored. For quad rank mod-

ules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted ad-

dress pins have no secondary functions allowing for normal operation when cross-

wired. Data is still read from the same address it was written. However, Load Mode op-

erations require a specific address. This requires the controller to accommodate for a

rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module

has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more de-

tails.

Table 8: Address Mirroring

Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored

A0 A0 A0

A1 A1 A1

A2 A2 A2

A3 A3 A4

A4 A4 A3

A5 A5 A6

A6 A6 A5

A7 A7 A8

A8 A8 A7

A9 A9 A9

A10 A10 A10

A11 A11 A13

A13 A13 A11

A12 A12 A12

A14 A14 A14

A15 A15 A15

A16 A16 A16

A17 A17 A17

BA0 BA0 BA1

BA1 BA1 BA0

BG0 BG0 BG1

BG1 BG1 BG0

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Address Mapping to DRAM

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Temperature Sensor with SPD EEPROM Operation

Thermal Sensor Operations

The integrated thermal sensor continuously monitors the temperature of the module

PCB directly below the device and updates the temperature data register. Temperature

data may be read from the bus host at any time, which provides the host real-time feed-

back of the module's temperature. Multiple programmable and read-only temperature

registers can be used to create a custom temperature-sensing solution based on system

requirements and JEDEC JC-42.2.

EVENT_n Pin

The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pull-

up to VDDSPD. EVENT_n is a temperature sensor output used to flag critical events that

can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial

presence-detect (SPD) EEPROM.

EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In

interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to

the clear event bit in the status register. In comparator mode, the EVENT_n pin clears

itself when the error condition is removed. Comparator mode is always used when the

temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n

pin is only asserted if the measured temperature exceeds the TCRIT limit; it then re-

mains asserted until the temperature drops below the TCRIT limit minus the TCRIT

hysteresis.

SPD EEPROM Operation

DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC

JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable

blocks. The SPD content is aligned with these blocks as shown in the table below.

Block Range Description

0 0–127 000h–07Fh Configuration and DRAM parameters

1 128–255 080h–0FFh Module parameters

2 256–319 100h–13Fh Reserved (all bytes coded as 00h)

320–383 140h–17Fh Manufacturing information

3 384–511 180h–1FFh End-user programmable

The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,

"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining

128 bytes of storage are available for use by the customer.

The EEPROM resides on a two-wire I2C serial interface and is not integrated with the

memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all

operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achieva-

ble at 2.5V (NOM).

Micron implements reversible software write protection on DDR4 SDRAM-based mod-

ules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently pro-

grammed or corrupted. The upper 128 bytes remain available for customer use and are

unprotected.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Temperature Sensor with SPD EEPROM Operation

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device's data sheet is not implied. Exposure to ab-

solute maximum rating conditions for extended periods may adversely affect reliability.

Table 9: Absolute Maximum Ratings

Symbol Parameter Min Max Units Notes

VDD VDD supply voltage relative to VSS –0.4 1.5 V 1

VDDQ VDDQ supply voltage relative to VSS –0.4 1.5 V 1

VPP Voltage on VPP pin relative to VSS –0.4 3.0 V 2

VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V

Table 10: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.14 1.2 1.26 V 1

VPP DRAM activating power supply 2.375 2.5 2.75 V 2

VREFCA(DC) Input reference voltage command/

address bus

0.49 × VDD 0.5 × VDD 0.51 × VDD V 3

IVTT Termination reference current from VTT –750 – 750 mA

VTT Termination reference voltage (DC) –

command/address bus

0.49 × VDD -

20mV

0.5 × VDD 0.51 × VDD +

20mV

V 4

IIN Input leakage current; any input excluding ZQ;

0V < VIN < 1.1V

–2.0 – 2.0 µA 5

II/O DQ leakage; 0V < Vin < VDD –4.0 – 4.0 µA 5

IZQ Input leakage current; ZQ –3.0 – 3.0 µA 5, 6

IOZpd Output leakage current; VOUT = VDD; DQ is disabled – – 5.0 µA

IOZpu Output leakage current; VOUT =VSS; DQ and ODT are

disabled; ODT is disabled with ODT input HIGH

– – 5.0 µA

IVREFCA VREFCA leakage; VREFCA = VDD/2 (after DRAM is ini-

tialized)

–2.0 – 2.0 µA 5

Notes: 1. VDDQ tracks with VDD; VDDQ and VDD are tied together.

2. VPP must be greater than or equal to VDD at all times.

3. VREFCA must not be greater than 0.6 x VDD. When VDD is less than 500mV, VREF may be

less than or equal to 300mV.

4. VTT termination voltages in excess of the specification limit adversely affect the voltage

margins of command and address signals and reduce timing margins.

5. Multiply by the number of DRAM die on the module.

6. Tied to ground. Not connected to edge connector.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Electrical Specifications

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Table 11: Thermal Characteristics

Symbol Parameter/Condition Value Units Notes

TCCommercial operating case temperature 0 to 85 °C 1, 2, 3

TC>85 to 95 °C 1, 2, 3, 4

TOPER Normal operating temperature range 0 to 85 °C 5, 7

TOPER Extended temperature operating range (optional) >85 to 95 °C 5, 7

TSTG Non-operating storage temperature –55 to 100 °C 6

RHSTG Non-operating Storage Relative Humidity (non-condensing) 5 to 95 %

NA Change Rate of Storage Temperature 20 °C/hour

Notes: 1. Maximum operating case temperature; TC is measured in the center of the package.

2. A thermal solution must be designed to ensure the DRAM device does not exceed the

maximum TC during operation.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-

ing operation.

4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs

interval refresh rate.

5. The refresh rate must double when 85°C < TOPER ≤ 95°C.

6. Storage temperature is defined as the temperature of the top/center of the DRAM and

does not reflect the storage temperatures of shipping trays.

7. For additional information, refer to technical note TN-00-08: "Thermal Applications"

available at micron.com.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR4 component data sheets.

Component specifications are available at micron.com. Module speed grades correlate

with component speed grades, as shown below.

Table 12: Module and Component Speed Grades

DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-3G2 -062E

-2G9 -068

-2G6 -075

-2G3 -083

-2G1 -093E

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level. Mi-

cron encourages designers to simulate the signal characteristics of the system's memo-

ry bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the edge connector of the module, not at the DRAM.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

DRAM Operating Conditions

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IDD Specifications

Table 13: DDR4 IDD Specifications and Conditions – 8GB (Die Revision B)

Values are for the MT40A512M8 DDR4 SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8) com-

ponent data sheet

Parameter Symbol 2666 2400 Units

One bank ACTIVATE-PRECHARGE current IDD01729 702 mA

One bank ACTIVATE-PRECHARGE, Word Line Boost, IPP current IPP0163 63 mA

One bank ACTIVATE-READ-PRECHARGE current IDD11882 855 mA

Precharge standby current IDD2N2756 738 mA

Precharge standby ODT current IDD2NT1684 648 mA

Precharge power-down current IDD2P2396 396 mA

Precharge quite standby current IDD2Q2648 648 mA

Active standby current IDD3N21044 1026 mA

Active standby IPP current IPP3N254 54 mA

Active power-down current IDD3P2594 594 mA

Burst read current IDD4R11719 1611 mA

Burst write current IDD4W11458 1368 mA

Burst refresh current (1x REF) IDD5R1792 783 mA

Burst refresh IPP current (1x REF) IPP5R172 72 mA

Self refresh current: Normal temp range (0–85°C) IDD6N2432 432 mA

Self refresh current: Extended temp range (0–95°C) IDD6E2846 846 mA

Self refresh current: Reduced temp range (0–45°C) IDD6R2450 450 mA

Auto self refresh current (25°C) IDD6A2162 162 mA

Auto self refresh current (45°C) IDD6A2216 216 mA

Auto self refresh current (75°C) IDD6A2846 846 mA

Auto self refresh current IPP current IPP6X254 54 mA

Bank interleave read current IDD712223 2097 mA

Bank interleave read IPP current IPP71153 153 mA

Maximum Power Down Current IDD82342 342 mA

Notes: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.

2. All ranks in this IDD/PP condition.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

IDD Specifications

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Temperature Sensor with SPD EEPROM

The temperature sensor continuously monitors the module's temperature and can be

read back at any time over the I2C bus shared with the serial presence-detect (SPD) EE-

PROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete

details.

SPD Data

For the latest SPD data, refer to Micron's SPD page: micron.com/SPD.

Table 14: Temperature Sensor with SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Nom Max Units

Supply voltage VDDSPD – 2.5 – V

Input low voltage: logic 0; all inputs VIL –0.5 – VDDSPD × 0.3 V

Input high voltage: logic 1; all inputs VIH VDDSPD × 0.7 – VDDSPD + 0.5 V

Output low voltage: 3mA sink current VDDSPD > 2V VOL – – 0.4 V

Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD ILI – – ±5 µA

Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z ILO – – ±5 µA

Table 15: Temperature Sensor and EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Clock frequency fSCL 10 1000 kHz

Clock pulse width HIGH time tHIGH 260 – ns

Clock pulse width LOW time tLOW 500 – ns

Detect clock LOW timeout tTIMEOUT 25 35 ms

SDA rise time tR – 120 ns

SDA fall time tF – 120 ns

Data-in setup time tSU:DAT 50 – ns

Data-in hold time tHD:DI 0 – ns

Data out hold time tHD:DAT 0 350 ns

Start condition setup time tSU:STA 260 – ns

Start condition hold time tHD:STA 260 – ns

Stop condition setup time tSU:STO 260 – ns

Time the bus must be free before a new transi-

tion can start

tBUF 500 – ns

Write time tW – 5 ms

Warm power cycle time off tPOFF 1 – ms

Time from power-on to first command tINIT 10 – ms

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Temperature Sensor with SPD EEPROM

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Module Dimensions

Figure 3: 288-Pin DDR4 UDIMM

31.40 (1.236)

31.10 (1.224)

2.50 (0.098) D

(2X)

0.75 (0.03) R

(8X)

Front view

133.48 (5.255)

133.22 (5.244)

Back view

1.5 (0.059)

1.3 (0.051)

3.9 (0.153)

MAX

3.0 (0.118) (4X) TYP

9.5 (0.374)

TYP

Pin 1

4.8 (0.189) TYP

5.95 (0.234) TYP

126.65 (4.99)

TYP

0.85 (0.033)

TYP

0.60 (0.0236)

TYP

0.75 (0.030) R

64.6 (2.54)

TYP

56.10 (2.21)

TYP

Pin 288 Pin 145

2.20 (0.087) TYP

72.25 (2.84)

TYP

0.5 (0.0197) TYP

28.9 (1.14)

TYP

10.2 (0.4)

TYP 25.5 (1.0)

TYP

22.95 (0.9)

TYP

10.2 (0.4)

TYP

22.95 (0.90)

TYP

3.35 (0.132) TYP

(2X)

3.15 (0.124)

TYP

14.6 (0.57)

TYP 8.0 (0.315)

TYP

16.1 (0.63)

TYP

Pin 144

1.25 (0.049) x 45° (2X)

U1 U2 U3 U4

U7 U8 U9 U10

U11 U12 U13 U14 U15 U16 U17 U18

U19

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

8GB (x72, ECC, DR) 288-Pin DDR4 UDIMM

Module Dimensions

PDF: CCMTD-1725822587-9423

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