MMA8210KEG - Freescale Semiconductor

Document Number: MMA81XXEG

Rev 5, 04/2010

Freescale Semiconductor

Technical Data

Digital X-Axis or Z-Axis

Accelerometer

The MMA81XXEG (Z-axis) and MMA82XXEG/MMA82XXTEG (X-axis) are

members of Freescale’s family of DSI 2.0-compatible accelerometers. These

devices incorporate digital signal processing for filtering, trim and data

formatting.

Features

• Available in 20g, 40g, 150g, and 250g (MMA82XXEG, X-axis),

50g and 100g (MMA82XXTEG, X-axis) and 40g, 100g, 150g, and

250g (MMA81XXEG, Z-axis). Additional g-ranges may be available upon

request

• 80 customer-accessible OTP bits

• 10-bit digital data output from 8 to 10 bit DSI output

• 6.3 to 30 V supply voltage

• On-chip voltage regulator

• Internal self-test

• Minimal external component requirements

• RoHS compliant (-40 to +125ºC) 16-pin SOIC package

• Automotive AEC-Q100 qualified

• DSI 2.0 Compliant

• Z-axis transducer is overdamped

Typical Applicatio ns

• Crash detection (Airbag)

• Impact and vibration monitoring

• Shock detection.

MMA81XXEG

MMA82XXEG

MMA82XXTEG

SERIES

SINGLE-AXIS

DSI 2.0

ACCELEROMETER

EG SUFFIX (Pb-free)

16-LEAD SOIC

CASE 475-01

PIN CONNECTIONS

116

215

314

413

512

611

710

N/C V

REG

BUSRTN

/TEST

CAP

FIL

OUT

GND

CLK

BUSIN

BUSOUT

REG

16-PIN SOIC PACKAGE

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SECTION 1 GENERAL DESCRIPTION

MMA81XXEG/MMA82XXEG/MMA82XXTEG family is a satellite accelerometer which is comprised of a single axis, variable ca-

pacitance sensing element with a single channel interface IC. The interface IC converts the analog signal to a digital format which

is transmitted in accordance with the DSI-2.0 specification.

1.1 OVERVIEW

Signal conditioning begins with a Capacitance to Voltage conversion (C to V) followed by a 2-stage switched capacitor amplifier .

This amplifier has adjustable offset and gain trimming and is followed by a low-pass switched capacitor filter with Bessel function.

Offset and gain of the interface IC are trimmed during the manufacturing process. Following the filter the signal passes to the

output stage. The output stage sensitivity incorporates temperature compensation.

The output of the accelerometer signal conditioning is converted to a digital signal by an A/D converter. After this conversion the

resultant digital word is converted to a serial data stream which may be transmitted via the DSI bus. Power for the device is

derived from voltage applied to the BUSIN/BUSOUT and VSS pins. Bus voltage is rectified and applied to an external capacitor

connected to the HCAP pin. During data transmissions, the device operates from stored charge on the external capacitor. An

integrated regulator supplies fixed voltage to internal circuitry.

A self-test voltage may be applied to the electrostatic deflection plate in the sensing element. Self-Test voltage is factory trimmed.

Other support circuits include a bandgap vol tage reference for the bias sources and the self-test voltage.

A total of 128 bits of One-Time Programmable (OTP) memory, are provided for storage of factory trim data, serial number and

device characteristics. Eighty OTP bits are available for customer programming. These eighty OTP bits may be programmed via

the DSI Bus or through the serial test/trim interface. OTP integrity is verified through continuous parity checking. Separate parity

bits are provided for factory and customer programmed data. In the event that a parity fault is detected, the reserved value of

zero is transmitted in response to a Read Acceleration Data command.

A block diagram illustratin g the major elements of the device is shown in Figure 1-1.

ORDERING INFORMATION

Device Name X-axis g-Level Z-axis g-Level Temperature Range SOIC 16 Package Packaging

MMA8225EGR2 250 —-40 to +125°C 475-01 Tape & Reel

MMA8225EG 250 —-40 to +125°C 475-01 Tubes

MMA8215EGR2 150 —-40 to +125°C 475-01 Tape & Reel

MMA8215EG 150 —-40 to +125°C 475-01 Tubes

MMA8210TEGR2 100 —-40 to +125°C 475-01 Tape & Reel

MMA8210TEG 100 —-40 to +125°C 475-01 Tubes

MMA8205TEGR2 50 —-40 to +125°C 475-01 Tape & Reel

MMA8205TEG 50 —-40 to +125°C 475-01 Tubes

MMA8204EGR2 40 —-40 to +125°C 475-01 Tape & Reel

MMA8204EG 40 —-40 to +125°C 475-01 Tubes

MMA8202EGR2 20 —-40 to +125°C 475-01 Tape & Reel

MMA8202EG 20 —-40 to +125°C 475-01 Tubes

MMA8125EGR2 —250 -40 to +125°C 475-01 Tape & Reel

MMA8125EG —250 -40 to +125°C 475-01 Tubes

MMA8115EGR2 —150 -40 to +125°C 475-01 Tape & Reel

MMA8115EG —150 -40 to +125°C 475-01 Tubes

MMA8110EGR2 —100 -40 to +125°C 475-01 Tape & Reel

MMA8110EG —100 -40 to +125°C 475-01 Tubes

MMA8104EGR2 —40 -40 to +125°C 475-01 Tape & Reel

MMA8104EG —40 -40 to +125°C 475-01 Tubes

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Figure 1-1. Overall Block Diagram

BUSOUTBUSIN

BUSRTN

LOGIC

COMMAND DECODE

STATE MACHINE

RESPONSE GENERATION

BANDGAP

REFERENCE

OSCILLATOR

g-CELL C-TO-V

CONVERTER LOW-PASS

FILTER

OFFSET

TRIM

GAIN

TRIM TCS

TRIM

SELFTEST

TRIM OSC

TRIM

SELFTEST

VOLTAGE SELF-TEST ENABLE

VOLTAGE

REGULATOR CREG

HCAP

INTERNAL

SUPPLY

VOLTAGE

OTP

PROGRAMMING

INTERFACE

VPP/TEST

DOUT

CLK

CFIL

VSS

CREG

VSS

N/C

A-TO-D

CONVERTER

REGULATOR

TRIM

VSS 10

N/C 2

VGND/DIN

GROUND

LOSS

DETECTOR 7

SWITCHES SHOWN

IN NORMAL OPERATING

CONFIGURATION

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1.2 PACKAGE PINOUT

The pinout for this 16-pin device is shown in Figure 1-2.

Figure 1-2. Device Pinout

116

215

314

413

512

611

710

N/C V

REG

BUSRTN

/TEST

CAP

FIL

OUT

GND

CLK

BUSIN

BUSOUT

REG

16-PIN SOIC PACKAGE

ACTIVIATION O F X -AXIS SELF-TEST

-X

CAUSES O UTP UT TO

BECOME MORE POSITIVE

-Z

N/C: NO INTERNAL CONNECTION

+1 g

-1 g

0 g0 g

+1 g

-1 g

0 g0 g

Output response to displacement in the direction of arrows.

Response to static orientation within 1 g field.

TO CENTER OF

GRAVITATION A L FIE LD

PROJECTION

ACTIVATION O F Z-AXIS SELF-TE ST

CAUSES OU TPUT TO

BECOME MORE PO SITIVE

CASE: 475-01

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1.3 PIN FUNCTIONS

The following paragraphs provide descriptions of the general function of each pin.

1.3.1 HCAP and VSS

Power is supplied to the ASIC through BUSIN or BUSOUT and BUSRTN. The supply voltage is rectified internally and applied

to the HCAP pin. An external capacitor connected to HCAP forms the positive supply fo r the integrated voltage regulator. VSS is

supply return node. All VSS pins are internally connected to BUSRTN. To obtain specified performance, all VSS nodes should be

connected to the BUSRTN node on the PWB. T o ensure stability of the internal voltage regulator and meet DFMEA requirements,

the connection from HCAP to the external capacitor should be as short as possible and should not be routed elsewhere on the

printed wiring assembly.

The voltage on HCAP is monitored. If the voltage falls below a specified level, the device will return the value zero in response to

a short word Read Acceleration Data command, and report the undervoltage condition by setting the Undervoltage (U) flag.

Should the undervoltage condition persist for more than one millisecond, the internal Power-On Reset (POR) circuit is activated

and the device will not respond until the voltage at HCAP is restored to operating levels and the device has undergone post-reset

initialization.

1.3.2 BUSIN

The BUSIN pin is normally connected to the DSI bus and su pports bidirectional communication with the master.

The MMA81XXEG, MMA82XXEG and MMA82XXTEG supports reverse initialization for improved system fault tolerance. In the

event that the DSI bus cannot support communication between the master and BUSIN pin, communication with the master may

be conducted via the BUSOUT pin and the BUSIN pin can be used to access other DSI devices.

1.3.3 BUSOUT

The BUSOUT pin is normally connected to the DSI bus for daisy-chained bus configurations. In support of fault tolerance at the

system level, the BUSOUT pin can be used as an input for reverse initialization and data communication.

The internal bus switch is always open following reset. The bus switch is closed when data bit D6 is set when an Initialization or

Reverse Initialization command is received.

1.3.4 BUSRTN

This pin provides the common return for power and signalling.

1.3.5 CREG

The internal voltage regulator requires external capacitance to the VSS pin for stability. This should be a high grade capacitor

without excessive internal resistance or inductance. An optional electrolytic capacitor may be required if a longer power down

delay is required.

Figure 1-3 illustrates the relationship between capacitance, series resistance and voltage regulator stability. Two CREG pins are

provided for redundancy. It is recomme nded that both CREG pins are connected to the external capacitor(s) for best system

reliability.

Figure 1-3. Voltage Regulator Capacitance and Series Res istance

CREG

1 μF100 μF

UNSTABLE

ESR STABLE

STABLE, UNACCEPTABLE

700 mΩ

NOISE PERFORMANCE

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1.3.6 CFIL

The output of the sensor interface circuitry can be monitored at the CFIL pin. An internal buffer is provided to provide isolation

between external signals and the input to the A/D converter . If CFIL monitoring is desired, a low-pass filter and a buffer with high

input impedance located as close to this pin as possible are required. The circuit configuration shown in Figure 1-5 is

recommended.

Figure 1-4. CFIL Filter and Buffer Configuratio n

This pin may be configured as an input to the A/D converter when the MMA81XXEG, MMA82XXEG and MMA82XXTEG devices

are in test mode. Refer to Appendix A for further details regarding test mode operation.

1.3.7 Trim/Test Pins (VPP/TEST, CLK, DOUT)

These pins are used for programming the device during manufacturing. These pins have internal pull-up or pull-down devices to

drive the input whe n left unconnected. The following termination is recommended for these pins in the end application:

CLK may be connected to ground, however this is not advised if the GLDE bit in DEVCFG2 is set, as a short between the adjacent

VGND/DIN pin and ground prevents ground loss detection.

1.3.8 GND Detect Pin (VGND/DIN)

VGND/DIN may be used to detect an open condition between the satellite module and chassis. The ground loss detector circuit

supplies a constant current through VGND/DIN and measures resulting voltage. This determines the resistance between VGND/

DIN and the system’s virtual ground. A fault condition is signalled if the resistance exceeds specified limits. This pin has no internal

pull-down device and must be connected as shown in Figure 1-5.

Ground loss detection circuitry is enabled when the GLDE bit is programmed to a logic ‘1’ state in DEVCFG2. Ground loss

detection is not available when the master operates in differential mode. VGND/DIN must be directly connected to BUSRTN if the

DSI bus is configured for differential operation. VGND/DIN connection options are illustrated in Figure 1-5.

When ground loss dete ction is enabled, a constant current is sourced and the voltage at VGND is continuously monitored. An

open connection between VSS and chassis ground will cause the voltage to rise. If the voltage indicates that the connection

between chassis ground and VSS has opened, a 14-bit counter is enabled. This counter will reverse if the voltage falls below the

detection threshold. Should the counter overflow, a ground loss condition is indicated. The counter acts as a digital low-pass filter,

to provide immunity from spurious signals.

This pin functions as the SPI data input when the device is in test mode.

Table 1-1

PIN Termination

VPP/TEST Connect to ground

CLK Leave unconnected

DOUT Leave unconnected

680 pF

50 kΩ

MMA81XXEG/MMA82XXEG//MMA82XXTEG

CFIL

RIN ≥ 1 MΩ

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Figure 1-5. VGND/DIN Connection Options

1.4 MODULE INTERCONNECT

A typical satellite module configuration supporting daisy-chain configu r ation is shown in Figure 1-6. Capacitors C1 and C2

form a filter network for the internal voltage regulator. Two capacitors are shown for redundancy; this configuration improves

reliability in the event of an open capacitor connection. A single 1 μF capacitor may be used in place of C1 and C2, however

connection from the capacitor to both CREG pins is required. CHOLD stores energy during signal transitions on BUSIN and

BUSOUT. The value of this capacitor is typically 1 μF; however, this depends upon data rates and bus utilization.

Figure 1-6. Typical Satellite Module Diagram

1.5 DEVICE IDENTIFICATION

Thirty-two OTP bits are factory-programmed with a unique serial number during the manufacturing and test. Five additional bits

are factory-programmed to indicate the full-scale range and axis of sensitivity . Device identification dat a may be read at any time

while the device is active.

BUSRTN

1 nF CHASSIS

1.00 kΩ, 1%

MMA81XXEG/MMA82XXEG/MMA82XXTEG

N/C VSS

CREG BUSRTN

VPP/TEST BUSIN

CFIL

DOUT

VGND/DIN

CLK

BUSOUT

HCAP

VSS

CREG

BUSRTN

GROUND-LOSS DETECTION DISABLED GROUND-LOSS DETECTION ENABLED

(SINGLE-ENDED SYSTEMS ONLY)

MMA81XXEG/MMA82XXEG/MMA82XXTEG

N/C VSS

CREG BUSRTN

VPP/TEST BUSIN

CFIL

DOUT

VGND/DIN

CLK

BUSOUT

HCAP

VSS

CREG

BUSRTN

CHOLD

BUSOUT

1 μFC2

1 μF

N/C

BUSIN

SEE NOTE

MMA81XXEG/MMA82XXEG/MMA82XXTEG

N/C VSS

CREG BUSRTN

VPP/TEST BUSIN

CFIL

DOUT

VGND/DIN

CLK

BUSOUT

HCAP

VSS

CREG

NOTE: LEAVE OPEN OR CONNECT TO SIGNAL MONITOR.

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SECTION 2 SUPPORT MODULES

2.1 MASTER OSCILLATOR

A temperature-compensated internal oscillator provides a stable timing reference for the device. The oscillator is factory-trimmed

to operate at a nominal frequency of 4 MHz.

2.2 VOLTAGE REGULATION

The internal voltage regulator has minimum voltage level detection, which will hold the device in reset and prevent data

transmission should the regulator output fall during operation. The regulator also has an input voltage clamp to limit the power

dissipated in the regulator during voltage spikes on the HCAP pin which might come from the two or three wire satellite bus.

2.3 BESSEL FILTER

180-Hz, 2-pole and 400 Hz 4-pole Bessel filter options are provided. The low-pass filter is implemented within a two stage

switched capacitor amplifier . The overall gain of the Bessel filter is set to a fixed value. The output of the Bessel filter output acts

as the input to the A/D converter and is also buffered and made available at the CFIL pin .

2.4 STATUS MONITORING

A number of abnormal conditions are detected by MMA81XXEG/MMA82XXEG/MMA82XXTEG and the behavior of the device

altered if a fault is detected. Detected fault conditions and consequent device behavior is summarized in the table below . Certain

conditions, e.g. ground loss, are qualified by device configuration. Figure 2-1 provides a representation of fault conditions, appli-

cable qualifiers and effects.

Table 2-1 Fault Condition Respo nse Summary

Condition Description Device Behavior

Undervoltage, CREG Internally regulated voltage below operating

level Device continuously undergoes reset, bus switch

open, no response to DSI commands

Sustained Undervoltage, HCAP Voltage at HCAP below operating level for more

than 1 ms

Frame Timeout Bus voltage remains below frame threshold

(tTO) longer than specified time.

Transient Undervoltage, HCAP Voltage at HCAP below operating level for less

than 1 ms Undervoltage (U) flag set, short-word Read

Acceleration Data response value equals zero

Fuse Fault OTP fuse threshold failure Accelerometer Status (S) flag set, short-word Read

Acceleration Data response value equals zero

Parity Fault Parity failure detected in factory or customer

programmed OTP data

Ground Fault Ground loss detected for more than 4.096 ms Accelerometer Status (S) and Ground Fault (GF) flags

set, short-word Read Acceleration Data response

value equals zero

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Figure 2-1. Status Logic Representation

The signal STDIS in Figure 2-1 is set when self-test lockout is activated through the execution of two consecutive Disable Self-

Test S timulus commands, as described in Section 4.6.6. If self-test lockout has been activated, a DSI Clear command or power-

on reset is required to clear a fault conditio n which results in reset of the D flip-flop.

DDIS

FUSE ERROR

GLDE

LOCK1

PAR1 FAULT

LOCK2

PAR2 FAULT

TRANSIENT

UNDERVOLTAGE

CONDITION

SHORT WORD

ACCELERATION

DATA = 0

KEY:

DDIS DEVICE DISABLE BIT, DEVCFG2[4]

FUSE FAULT OTP FUSE THRESHOLD FAILURE

GLDE GROUND LOSS DETECTION BIT, DEVCFG2[5]

GF GROUND FAULT DETECTION CONDITION

LOCK1 FACTORY PROGRAMMED OTP LOCK BIT

LOCK2 CUSTOMER PROGRAMMED OTP LOCK BIT

PAR1 FAULT FACTORY PROGRAMMED OTP PARITY FAULT CONDITION

S ACCELEROMETER STATUS FLAG

ST SELF-TEST ACTIVATION CONDITION

PAR2 FAULT CUSTOMER PROGRAMMED OTP PARITY FAULT CONDITION

STDIS SELF-TEST DISABLE

STDIS

U UNDERVOLTAGE FLAG

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SECTION 3 OTP MEMORY

MMA81XXEG/MMA82XXEG/MMA82XXTEG family features One-Time-Programmable (OTP) memory implemented via a fuse

array . OTP is organized as an array of 96 bits which contains the trim data, configuration data, and serial number for each device.

Sixteen bits of the OTP array may be programmed by the customer through the DSI Bus.

3.1 INTERNAL REGISTER ARRAY AND OTP MEMOR Y

Contents of OTP memory are transferred to a set of registers following power-on reset, after which the OTP array is powered-

down. Contents of the register array are static and may be read at any time following the transfer of data from the OTP memory.

Write operations to OTP mirror registers are supported when the device is in test mode, however any data stored in the register

will be lost when the device is powered down. The mirror registers are also restored when an OTP read operation is performed.

In addition to the registers which mirror OTP memory contents, several other registers are provided. Among these are the OTP

Control Registers which controls OTP programming operations and may be used to restore the registers from the OTP memory.

Figure 3-1. OTP Interface Overview

3.2 OTP WORD ASSIGNMENT

Customer-accessible OTP bits are shown in Table 3-1. Unprogrammed OTP bits are read as logic ‘0’ value s. DEVCFG1,

DEVCFG2 and registers REG-8 through REG-F are programmed by the customer . Other bits are programmed and locked during

manufacturing. There is no requi rement to program any bits in DEVCFG1 or DEVCFG2 for the device to be fully operational.

Table 3-1 Customer Accessible Data

Location Bit Function

AddressRegister76543210

$00 SN0 S7S6S5S4S3S2S1S0

$01 SN1 S15 S14 S13 S12 S11 S10 S9 S8

$02 SN2 S23 S22 S21 S20 S19 S18 S17 S16

$03 SN3 S31 S30 S29 S28 S27 S26 S25 S24

$04 TYPE ORDER 0 AXIS 0 0 RNG2 RNG1 RNG0

$05 RESERVED 0 0000000

$06 DEVCFG1 Customer Defined AT1 AT0

$07 DEVCFG2 LOCK2 PAR2 GLDE DDIS AD3 AD2 AD1 AD0

$08 REG-8 Customer Defined

$09 REG-9 Customer Defined

$0A REG-A Customer Defined

$0B REG-B Customer Defined

$0C REG-C Customer Defined

$0D REG-D Customer Defined

$0E REG-E Customer Defined

$0F REG-F Customer Defined

CLK

DOUT

DIN

VPP/TEST

SERIAL

PERIPHERAL

INTERFACE REGISTER

ARRAY

OTP

ARRAY

TO DIGITAL

INTERFACE

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3.2.1 Devic e Seri al Numb er

A unique serial number is programmed into each device during manufacturing. The serial number is composed of the following

information.

Lot numbers begin at 1 for all devices produce d and are sequentially assigned. Serial numbers begin at 1 for each lot, and are

sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Not all allow-

able lot numbers and serial numbers will be assigned.

3.2.2 Type Byte

The Type Byte is programmed at final trim and test to indicate the axis of orientation of the g-cell and the calibrated range of the

device.

3.2.2.1 Filter Characteristic Bit (ORDER)

This bit denotes the low-pass filter characteristic.

0 - 400 Hz, 4-pole

1 - 180 Hz, 2-pole

3.2.2.2 Bit 6

Bit 6 is reserved. It will always be read as a logic ‘0’ value.

3.2.2.3 Axis of Sensitivity Bit (AXIS)

The AXIS bit indicates direction of sensitivity

0 - Z-axis

1 - X-axis

3.2.2.4 Bit 4, Bit 3

Bit 4 and Bit 3 are reserved. They will always be read as a logic ‘0’ value.

3.2.2.5 Full-Scale Range Bits (RNG2 - RNG0)

These three bits define the calibrated range of the device as follows:

Table 3-2 Serial Number Assignme nt

Bit Range Content

S12 - S0 Serial Number

S31 - S13 Lot Number

Table 3-3 Device Type Register

Location Bit Function

AddressRegister76543210

$04 TYPE ORDER 0 AXIS 0 0 RNG2 RNG1 RNG0

Table 3-4

RNG2 RNG1 RNG0 Range

000Unused

00120g

01040g

01150g

100100g

101150g

110250g

111Unused

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3.2.3 Configuration Bytes

Two customer-programmable configuration bytes are assigned.

3.2.4 Device Configuration Byte 1 (DEVCFG1)

Configuration Byte 1 contains three defined bit functions, plus five bits that can be programmed by the customer to designate any

coding desired for packaging axis, model, etc.

3.2.5 Attribute Bits (AT1, AT0)

These bits may be assigned by the customer as desired. They are transm itted by MMA81XXEG/MMA82XXEG/MMA82XXTEG

in response to Request St atus, Disable Self-Test Stimulus or Enable Self-Test Stimulus commands, as described in Section 4.

3.2.6 Device Configuration Byte 2 (DEVCFG2)

Configuration Byte 2 contains six bits that can be programmed by the customer to control device configuration, along with parity

and lock bits for DEVCFG1 and DEVCFG2.

3.2.6.1 Customer Data Lock Bit (LOCK2)

The bits in configuration bytes 1 and 2 are frozen when the LOCK2 bit is programmed. The LOCK2 bit is not included in the parity

check. Locking does not take effect after this bit is programmed until the device has been subsequentl y reset.

0 - Customer-programmed data area unlocked.

1 - Programming operations inhibited.

The DDIS bit is not affected by LOCK2 and may be programmed at any time.

3.2.6.2 Customer Data Parity Bit (PAR2)

The PAR2 parity bit is used for detectin g changes in configuration bytes 1 and 2 along with regi sters REG-8 through REG-F

(addresses $06 through $0F, inclusive). A fault condition is indicated if a change to parity-protected register data is detected. The

PAR2 bit follows an “e ven” parity scheme (number of logical HIGH bits including parity bit is even).

If an internal parity error is detected, the device will respond to Read Acceleration Da ta commands with zero in the data field, as

described in Section 4.5.4. The S tatus (S) bit will be set in either short word or long word responses to indicate the fault condition.

A parity fault may result from a bit failure within the OTP or the registers which store an image of the OTP during operation. In

the latter case, power-on reset will clear the fault when the registers are re-loaded. A parity fault associated with the OTP array

is a non-recoverable failure.

The parity status of customer programmed data is not monitored if the LOCK2 bit is not programmed to a logic ‘1’ state.

3.2.6.3 Ground Loss Detection Ena ble (GLDE)

When this bit is programmed to a logic ‘1’ value, ground loss errors will be reported if a ground fau lt condition is detected.

1 - Ground-loss detection circuitry enabled

0 - Ground-loss detection disabled.

Table 3-5 Device Configuration Byte 1

Location Bit Function

AddressRegister76543210

$06 DEVCFG1 Customer Defined ATT1 ATT0

Table 3-6 Device Configuration Byte 2

Location Bit Function

AddressRegister76543210

$07 DEVCFG2 LOCK2 PAR2 GLDE DDIS AD3 AD2 AD1 AD0

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3.2.6.4 Device Disable Bit (DDIS)

This bit may be programmed at any time, regardless of the state of LOCK2. This bit is intended to be programmed when a module

has been determined by the DSI Bus Master to be defective. Programming this bit after LOCK2 has been set will cause the device

to respond to short word Read Acceleration Data commands with a zero response. Acceleration results are not affected by this

bit when long word Read Acceleration Data commands are executed, however the Status (S) bit will be set in the response.

1 - Device responds to Read Acceleration Data command with zero value

0 - Device responds normally to Read Acceleration Data command

3.2.6.5 Device Address (AD3 - AD0)

These bits define the pre-programmed DSI Bus device address.

3.3 OTP PROGRAMMING

T wo different methods of programming the eighty customer defined bits are supported. In test mode, these may be programmed

in the same manner as factory programmed OTP bits. Additionally, the Read Write NVM DSI bus command may be used. Test

mode programming operations are described in Appendix A.3. Read Write NVM command operation is described in

Section 4.6.3.

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SECTION 4 PHYSICAL LAYER AND PROTOCOL

MMA81XXEG/MMA82XXEG/MMA82XXTEG family is compliant with the DSI Bus Standard, Version 2.0. MMA81XXEG/

MMA82XXEG/MMA82XXTEG is designed to be compatible with either DSI Version 2 or DSI Version 1.1 compliant bus masters.

4.1 DSI NETWORK PHYSICAL LAYER INTERFACE

Refer to Section 3 of the DSI Bus Standard for information regarding the ph ysi cal layer interface.

4.2 DSI NETWORK DATA LINK LAYER

Refer to Section 4 of the DSI Bus Standard for information regarding the DSI network data link layer interface. Both standard

and enhanced command structures are supported for short word and long word commands.

4.3 DSI BUS COMMANDS

DSI Bus Commands which are recognized by MMA81XXEG and the MMA82XXEG/MMA82XXTEG are summarized in

Table 4-1. Detailed descriptions of each supported command are described in subsequent sections of this document. If a CRC

error is detected, or a reserved or unimplemented command is received, the device will not respond.

Following all messages, MMA81XXEG and the MMA82XXEG/MMA82XXTEG disregards the DSI bus voltage level for approxi-

mately 18.5 μs. Within this time, all supported commands except Initialization and Reverse Initialization are guaranteed to be

executed and the device will be ready fo r the next message. When the bus voltage falls below the signal high logic level (see

Section 5) after the 18.5 μs period has elapsed, the device will respond as appropriate to a command sent to it in the previous

message. Exactly one response is attempted; if a noise spike or corrupted transfer occurs, th e response is not retried.

If an Initialization or Reverse Initialization command is executed and the Bus Switch (BS) bit is set, MMA81XXEG, MMA82XXEG

and MMA82XXTEG will disregard the bus voltage level for a nominal period of 180 μs. This interval allows for the bus voltage to

recover following closure of the bus switch, while the hold capacitor of a downstream slave charges.

Legend:

BS: Bus Switch Control (0: open, 1: close)

NV: Nonvolatile memory control (1: program NVM)

PA3 - PA0: Device address assigned during Initializati on or Reverse Initialization

RA3 - RA0: Internal user data register address

FA2 - FA0: Format register address

FD3 - FD0: Format register data content

Table 4-1 DSI Bus Command Summary

Command

Size Data

Binary Hex Description

C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 $0 Initialization LW NV BS B1 B0 PA3 PA2 PA1 PA0

0 0 0 1 $1 Request Status SW ————————

0 0 1 0 $2 Read Acceleration Data SW ————————

0 0 1 1 $3 Not Implemented N/A Not Applicable

0 1 0 0 $4 Request ID Information SW ————————

0 1 0 1 $5 Not Implemented N/A Not Applicable

0 1 1 0 $6 Not Implemented N/A Not Applicable

0 1 1 1 $7 Clear SW ————————

1 0 0 0 $8 Not Implemented N/A Not Applicable

1 0 0 1 $9 Read Write NVM LW RA3 RA2 RA1 RA0 RD3 RD2 RD1 RD0

1 0 1 0 $A Format Control LW R/W FA2 FA1 FA0 FD3 FD2 FD1 FD0

1 0 1 1 $B Read Register Data LW 0000RA3 RA2 RA1 RA0

1 1 0 0 $C Disable Self-Test Stimulus SW ————————

1 1 0 1 $D Activate Self-Test Stimulus SW ————————

1 1 1 0 $E Reserved N/A Not Applicable

1 1 1 1 $F Reverse Initialization LW NV BS B1 B0 PA3 PA2 PA1 PA0

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Freescale Semiconductor 15

4.4 COMMAND RESPONSE SUMMARIES

The device incorporates an analog-to-digital converter which translates the low-pass filtered acceleration signal to a 10-bit binary

value. The 10-bit digital result is referred to as AD9 through AD0 in the response tables which follow.

4.4.1 Short Word Response Summary

Short word responses for all commands are summarized below. Detailed DSI command descriptions may be found in

Section 4.5.

Legend:

AT1 - AT0: Attribute codes (see Section 4.5.1.3)

NV: State of fu se program control bit

BS: State of Bus Switch (0: open, 1: closed)

S: Accelerometer status flag (1: internal error)

ST: Self-Test flag (1: self-test active)

U - Undervoltage condition

V2 - V0: Version ID

Table 4-2 Short-Word Re s po nse Summa r y

Command Response

Hex Description D7 D6 D5 D4 D3 D2 D1 D0

$0 Initialization Not Applicable

$1 Request Status NV U ST BS AT1 AT0 S GF

$2 Read Acceleration Data See Section 4.5.4

$3 Not Implemented No Response

$4 Request ID Information V2 V1 V0 0 0100

$5 Not Implemented No Response

$6 Not Implemented No Response

$7 Clear No Response

$8 Not Implemented No Response

$9 Read/Write NVM Not Valid

$A Format Control Not Valid

$B Read Register Data Not Valid

$C Disable Self-Test Stimulus NV U ST BS AT1 AT0 S GF

$D Activate Self-Test Stimulus NV U ST BS AT1 AT0 S GF

$E Reserved No Response

$F Reverse Initialization Not Valid

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4.4.2 Long Word Response Summary

Long word responses for all commands are summarized below. Detailed DSI command descriptions may be found in Section 4.5.

Legend:

A3 - A0: Device address

AD9 - AD0: 10-bit acceleration data result

AT1 - AT0: Attribute codes (see Section 4.5.1.3)

BF: Bus Fault flag (1: bus faul t)

BS: State of Bus Switch (0: open, 1: closed)

FA2 - FA0: Format register address

FD3 - FD0: Format register data content

GF: Ground fault detected

NV: State of fu se program control bit

PA3 - PA0 : Device address assigned during Initialization/Reverse Initialization

RA3 - RA 0: Internal user data register address

RD7 - RD0: Internal user data register contents

R/W: Read/Write flag for Format Con trol Register access

S: Accelerometer Status Flag (1: internal error)

ST: Self-Test Flag (1: self-test active)

U - Undervoltage condition

V2 - V0: Version ID

Table 4-3 Long-Word Response Summary

Command Response

Hex Description D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

$0 Initialization A3 A2 A1 A0 0 0 0 BF NV BS B1 B0 PA3 PA2 PA1 PA0

$1 Request Status A3 A2 A1 A0 0 0 0 0 NV UST BS AT1 AT0 SGF

$2 Read Acceleration Data A3 A2 A1 A0 GF SAD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

$3 Not Implemented No Response

$4 Request ID Information A3 A2 A1 A0 0 0 0 0 V2 V1 V0 0 0 1 0 0

$5 Not Implemented No Response

$6 Not Implemented No Response

$7 Clear No Response

$8 Not Implemented No Response

$9 Read/Write NVM A3 A2 A1 A0 See Section 4.6.3

$A Format Control A3 A2 A1 A0 0 1 1 0 R/W FA2 FA1 FA0 FD3 FD2 FD1 FD0

$B Read Register Data A3 A2 A1 A0 RA3 RA2 RA1 RA0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

$C Disable Self-Test Stimulus A3 A2 A1 A0 0 0 0 0 NV UST BS AT1 AT0 SGF

$D Activate Self-Test Stimulus A3 A2 A1 A0 0 0 0 0 NV UST BS AT1 AT0 SGF

$E Reserved No Response

$F Reverse Initialization A3 A2 A1 A0 0 0 0 BF NV BS B1 B0 PA3 PA2 PA1 PA0

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Freescale Semiconductor 17

4.5 DSI COMMAND DETAIL

Detailed descriptions of command formats and responses are provided in this section.

4.5.1 DSI COMMAND AND RESPONSE BIT DESCRIPTIONS

The following abbreviations are used in the descriptions of DSI commands and responses.

4.5.1.1 DSI Device Ad dress - (A3 - A0)

DSI device address. This address will be set to the pre-programmed device address following reset, or zero if no pre-programmed

address has been assigned. If zero, the device address may be assign ed during initialization or reverse initialization.

4.5.1.2 Acceleration Data - (AD9 - AD0)

Ten-bit acceleration result produced by the device. This value is returned by the Read Acceleration Data command, described in

Section 4.5.4.

4.5.1.3 Attribute Code Bits (AT1, AT0)

These bits indicate the contents of DEVCFG1 bits 1 and 0 in response to a Request S tatus, Activate Self-Test Stimulus or Disable

Self-Test Stimulus comman d.

4.5.1.4 Ban k Select (B1, B0)

These bits are assigned during initializati on or reverse initialization to select speci fic fields within the customer accessible data

registers. Bank selection affect s Read/Write NVM command operation. Invalid combinations of B1 and B0 result in no response

from the device to the associated initialization or reverse initialization command.

Refer to Section 4.6.3 for further details regarding register progra mming and bank selection.

4.5.1.5 Bus Fault Bit (BF)

This bit indicates the success or failure of the bus test which is performed as part of an Initialization or Reverse Initialization com-

mand.

1 - Bus fault detected

0 - Bus test passed

4.5.1.6 Bus Switch Control/Status Bit (BS)

This bit controls the state of the bus switch during an Initialization or Reverse Initialization command. It also indicates the state

of the bus switch in response to the Initialization, Request Status, Disable Self-Test Stimulus, Activate Self-Test Stimulus and

Reverse Initialization commands.

1 - Close bus switch, or bus switch closed

0 - Leave bus switch open, or bus switch opened

4.5.1.7 Format Control Register Address (FA2 - FA0)

This three-bit field selects one of eight format control registers. Format control registers are described in Section 4.6.4.3.

4.5.1.8 Format Register Dat a (FD3 - FD0)

Contents of a format control register. This is the data to be written to the register by a Format Control command, or the contents

read from the register in response to a Format Control command.

Table 4-4 Attribute Code Bit Assignments

LOCK2 DEVGFG1[1] DEVGFG1[0] AT1 AT0

0 X X 1 0

10000

0 1 0 1

1 0 1 0

1 1 1 1

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4.5.1.9 Ground Fault Flag (GF)

If ground loss detection has been enabled and a ground fault condition is detected, this bit will be set in the response to Request

S tatus, Read Acceleration Data, Disable Self-Test S timulus or Activate Self-Test S timulus commands. If ground loss detection is

not enabled, this bit will always be read as a logic ‘0’ value.

1 - Ground fault condition detected

0 - Ground connection within specified limits, or ground loss detection disabled.

4.5.1.10 Nonvolatile Memory Program Control Bit (NV)

This bit enables programming of customer-programmed OTP locations when set during an Initialization or Reverse Initialization

command. Data to be programmed are transferred to the device during subsequent Read Write NVM commands.

1 - Enable OTP programming

0 - OTP programming circuitry disabled

4.5.1.11 Assigned De vi ce Address (PA3 - PA0)

This field contains the device address to be assigned during an Initializati on or Reverse Initialization command. The address

assigned is reported by the device in response to the Initialization or Reverse Initialization command.

4.5.1.12 Register Address (RA3 - RA0)

This field determines the register associated with a Read Write NVM or Read Register Data command. The two Bank Select bits

(B1, B0) are used to additionally specify a nibble or bit when a Read Write NVM command is executed.

4.5.1.13 Register Data (RD7 - RD0)

RD3 - RD0 contain data to be written to an OTP location when a Read Write NVM command is executed if the NV bit is set. RD3

- RD0 contain the data read from the selected register in response to a Read Write NVM command if the NV bit is cleared. RD7

- RD0 indicate the contents of the selected register in response to a Read Register Data command.

4.5.1.14 Format Control Register Read/Write Bit (R/W)

This bit controls the operation performed by a Format Control command.

1 - Write Format Control register selected by FA2 - FA0

0 - Read Format Control register unless global command

4.5.1.15 Accelerometer Status Flag (S)

This bit provides a cumulative indication of the various error conditions which are monitored by the device.

1 - Either one or more error conditions have been detected and/or the internal Self-Test stimulus circuitry is active

0 - No error condition has been detected

The following conditions will cause the status flag to be set:

*Internal Self-Test stimulus circuitry is active

OTP array parity fault

OTP fuse threshold fault (partially-programmed fuse)

Tran sient undervoltage condition

Ground fault (if GLDE bit in DEVCFG2 is set)

4.5.1.16 Self-Test State (ST)

This bit indicates whether internal self-test stimulus circuitry is active in response to Request Status, Disable Self-Test Stimulus

and Activate Self-Test Stimulus commands.

1 - Self-Test stimulus active

0 - Self-Test stimulus disabled

4.5.1.17 Undervoltage Flag (U)

This flag is set if the voltage at HCAP is below a specified threshold. Refer to Section 1.3.1 and Section 5 for further details.

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Freescale Semiconductor 19

4.5.2 Initialization Command

The initialization command conforms to the description provided in Section 6. 2.1 of the DSI Bus S tandard, V ersion 2.0. At power-

up the device is fully compliant with the DSI 1.1 protocol. The initialization command must be transmitted as a DSI 1.1 compliant

long command structure. Features of the DSI 2.0 protocol can not be acce ssed until a valid DSI 1.1 compliant initialization

sequence is performed and the enhanced mode format registers are properly configured.

Figure 4-1 illustrates the sequence of operations performed following negation of internal Power-On Reset (POR) and execution

of a DSI Initialization command. Initialization commands are recogn ized only at BUSIN. The BUSOUT node is tested for a bus

short to battery high voltage condition, and the Bus Fault (BF) flag set if an error condition is detected. If no bus fault condition is

detected and the BS bit is set in the command structure, the bus switch will be closed. If the BS bit is set, the DSI bus voltage

level is disregarded for approximately 180 μs following initialization to allow the hold capacitor on a downstream slave to charge.

If the device has been pre-programmed, PA3 - P A0 and A3 - A0 must match the pre-programmed address. If no device address

has been previously programmed into the OTP array, PA3 - PA0 contain the device address, while A3 - A0 must be zero. If any

addressing condition is not met, the device address is not assigned, the bus switch will remain open and the device will not

respond to the Initializa tion command.

In the response, bits D15 - D12 and D3 - D0 will contain the device address. If the dev ice was unprogrammed when the

initialization command was issued, the device address is assigned as the command executes. Both fields will contain the value

PA3 - PA0 to indicate successful device address assignment.

Initialization or reverse initialization commands which attempt to assign device address zero are ignored.

Table 4-5 Initialization Command Structure

Data Address Command CRC

D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 C3 C2 C1 C0

NV BS B1 B0 PA3 PA2 PA1 PA0 A3 A2 A1 A0 0000 4 bits

Table 4-6 Initialization Command Respon se

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 000BF NV BS B1 B0 A3 A2 A1 A0 4 bits

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Figure 4-1. Initialization Sequence

POR

INITIALIZATION

COMMAND AT

LOAD REGISTERS

FROM FUSE ARRAY

NEGATED

CLOSE BUS SWITCH

MEASURE

BUSOUT VOLTAGE

ENABLE IRESP CURRENT

DRIVE AT BUSOUT

BUSOUT

< V

THH

BUSIN?

BS == 1?

WAIT FOR NEXT DSI

BUS COMMAND

CLOSE BUS SWITCH

MEASURE

BUSIN VOLTAGE

ENABLE IRESP CURRENT

DRIVE AT BUSIN

BUSIN

< V

THH

BS == 1?

SET BF

FLAG

SET BF

FLAG

REVERSE

INITIALIZATION

COMMAND AT

BUSOUT?

DELAY 10 μs

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Freescale Semiconductor 21

4.5.3 Request Status Command

The Request S tatus command may be transmitted as either a DSI long command structure or a DSI short command structure of

any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is taken if this

command is sent to the DSI Global Device Address.

4.5.4 Read Acceleration Data Command

The Read Acceleration Data command may be transmitted as either a DSI long command structure or a DSI short command

structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is

taken if this command is sent to the DSI Global Device Address.

Table 4-1 Request Status Command Structure

Address Command CRC

A3 A2 A1 A0 C3 C2 C1 C0

A3 A2 A1 A0 0 0 0 1 0 to 8 bits

Table 4-2 Short Response Structure - Request Status Command

Response

Length Response

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NV UST BS AT1 AT0 SGF

13 0

14 0

15 0

Table 4-3 Long Response Structure - Request Status Com mand

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 0 0 0 0 NV UST BS AT1 AT0 SGF 0 to 8 bits

Table 4-4 Read Acceleration Data Command Structure

Address Command CRC

A3 A2 A1 A0 C3 C2 C1 C0

A3 A2 A1 A0 0 0 1 0 0 to 8 bits

Table 4-5 Short Response Structure - Read Acceleration Data Command

Response

Length Response

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

8AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

9AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1

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Data returned in response to a Read Acceleration Data command varies, as illustrated in Table 4-5 and Table 4-6. The result is

also affected by the state of the self-test circuitry and internal parity. If the self-test circuitry is enabled, the ST bit will be set in

data bit D12 of a short word response. If a transient undervoltage condition, parity fault, ground fault or device disable condition

exists, the reserved data value of zero will be reported in response to a short word command structure to indicate that a fault

condition has been detected. The data value is not affected by a fault condition when a long word response is reported, however

the S and GF bits will be set as appropriate.

If the self-test circuitry is active, acceleration data is reported regardless of parity faults. The Status (S) bit will be set in either

short word or long word responses if a parity fault is detected.

4.5.4.1 ACCELERATION DATA REPRESENTATION

Acceleration values may be determined from th e 10-bit digital output (DV) as follows:

a = sensitivity × (DV - 512)

Sensitivity is determined by nominal full-scale range (FSR), linear range of digital values and a scaling factor to compensate for

sensitivity error.

The linear range of digital values for MMA81XXEG/MMA82XXEG/MMA82XXTEG is 1 to 1023. The digital value of 0 is reserved

as an error

indicator.

For the linear ranges of digital values indicated, the nominal value of 1 LSB for each full-scale range is shown in the table below.

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

13 ST

14 DEVCFG1[0]

15 DEVCFG1[1]

Table 4-6 Long Respon s e Struct ure - Read Acc ele r ati on Data Comma nd

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 GF SAD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 to 8 bits

Table 4-7 Nominal Sensitivity (10-bit data)

Full-Scale Range (g) Nominal Sensitivity (g/digit)

250 0.61

150 0.366

100 0.244

50 0.122

40 0.0976

20 0.0488

Table 4-5 Short Response Structure - Read Acceleration Data Command

Response

Length Response

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

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4.6 ACCELERATION MEASUREMENT TIMING

Upon verification of the CRC associated with a Read Acceleration Data c ommand, MMA81XXEG/MMA82XXEG/MMA82XXTEG

initiates an analog-to-digital conversion. The conversion occurs during the inter frame separation (IFS) and involves a delay

during which the BUSIN line is allowed to stabilize, a sample period and finally the translation of the analog signal level to a digital

result.

4.6.1 Request ID Information Command

The Request ID Information command may be transmitted as either a DSI long command structure or a DSI short command

structure of any length. The data field in the command structure is ignored but is included in the CRC calculation. No action is

taken by MMA81XXEG/MMA82XXEG/MMA82XXTEG if this command is sent to the DSI Global Device Address.

4.6.2 Clear Command

The Clear command may be transmitted as either a DSI long command structure or a DSI short command structure of any length.

The data field in the command structure is ignored but is included in the CRC calculation.

When a Clear Command is successfully decoded and the address field matches either the assigned device address or the DSI

Global Device Address, the bus switch is opened and the device undergoe s a full reset operation.

There is no response to the Clear Command.

Table 4-8 Request ID Information Command Structure

Address Command CRC

A3 A2 A1 A0 C3 C2 C1 C0

A3 A2 A1 A0 0 1 0 0 0 to 8 bits

Table 4-9 Short Response Structure - Request ID Information Command

Response

Length Response

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

V2 V1 V0 0 0 1 0 0

13 014 0

15 0

Table 4-10 Long Response Structure - Request ID Information Command

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 0 0 0 0 V2 V1 V0 001000 to 8 bits

Table 4-11 Clear Command Structure

Address Command CRC

A3 A2 A1 A0 C3 C2 C1 C0

A3 A2 A1 A0 0 1 1 1 0 to 8 bits

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4.6.3 Read/Write NVM Command

The Read/Write NVM command must be transmitted as a DSI long command structure. No action is taken by MMA81XXEG/

MMA82XXEG/MMA82XXTEG if this command is sent to the DSI Global Device Address.

There is no response if the Read/Write NVM Command is received within a DSI short command structure.

OTP data are accessed by fields, where a field is a combination of register address (RA3 - RA0) and bank select (B1, B0) bits.

Bank select bits are assigned during an Initialization or Reverse Initialization command. Individual bits with predefined functions

(the upper four bits of DEVCFG2) each have their own field address. The remaining OTP data are grouped into four-bit fields.

Field addresses are shown in Tab le 4-15.

The structure of the OTP arr ay re sul ts in data being prog ra mmed in 16-bit groups. DEVCFG1 and DEVCFG2 are in the same

group. As a result, a non-zero device address assigned during Initialization or Reverse Initialization will be permanently

programmed into the OTP array when any field within the two device configuration bytes is programmed.

To avoid programming a non-zero device address, ensure th at device address 0 is assigned during Initialization or Reve rse

Initialization before programming any other bit(s) in DEVCFG1 or DEVCFG2.

OTP programming operations occur when the Read/Write NVM command is executed after the NV bit has been set during a

preceding Initialization or Reverse Initialization command.

The minimum DSI Bus idle voltage must exceed 14 V when programming the OTP array.

When this command is executed while the NV bit is cleared, the DSI device address will be returned regardless of the state of

the register address and bank select bits. The Read Register Data command (described in Section 4.6.5) may be us ed to access

the full range of customer accessible data.

Table 4-12 Read Write NVM Command Structure

Data Address Command CRC

D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 C3 C2 C1 C0

RA3 RA2 RA1 RA0 RD3 RD2 RD1 RD0 A3 A2 A1 A0 1 0 0 1 0 to 8 bits

Table 4-13 Long Response Structure - Read/Write NVM Command (NV = 1)

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 RA3 RA2 RA1 RA0 1 1 B1 B0 RD3 RD2 RD1 RD0 0 to 8 bits

Table 4-14 Long Response Structure - Read/Write NVM Command (NV = 0)

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 00001111A3 A2 A1 A0 0 to 8 bits

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4.6.4 Format Control Command

The Format Control command must be transmitted as a DSI long command structure. No change to the format registers occurs

if the Format Control Command is received within a DSI short command structure.

If this command is sent to the DSI Global Device Address, the format registers are updated, however there is no response.

The Format Control command conforms to the DSI 2.0 Specification.

4.6.4.1 Format Register Read/Write Control Bit (R/W)

1 - Write Format Control register selected by FA2 - FA0

0 - Read Format Control register unless global command

Table 4-15 OTP Field Assignments

RA3 RA2 RA1 RA0 B1 B0

0 1 1 0 0 1 DEVCFG1[3:0] User Defined

1 0 DEVCFG1[7:4]

0 1 1 1 0 0 DEVCFG2[7] LOCK2

0 1 DEVCFG2[3:0] DSI Bus Device Address

1 0 DEVCFG2[5] GLDE

1 1 DEVCFG2[6] PAR2

1 0 0 0 0 1 REG8[3:0] User Defined

1 0 REG8[7:4]

1 0 0 1 0 1 REG9[3:0] User Defined

1 0 REG9[7:4]

1 0 1 0 0 1 REGA[3:0] User Defined

1 0 REGA[7:4]

1 0 1 1 0 1 REGB[3:0] User Defined

1 0 REGB[7:4]

1 1 0 0 0 1 REGC[3:0] User Defined

1 0 REGC[7:4]

1 1 0 1 0 1 REGD[3:0] User Defined

1 0 REGD[7:4]

1 1 1 0 0 1 REGE[3:0] User Defined

1 0 REGE[7:4]

1 1 1 1 0 1 REGF[3:0] User Defined

1 0 REGF[7:4]

1 1 DEVCFG[4] DDIS

Table 4-16 Format Co ntrol Command Structure

Data Address Command CRC

D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 C3 C2 C1 C0

R/W FA2 FA1 FA0 FD3 FD2 FD1 FD0 A3 A2 A1 A0 1 0 1 0 0 to 8 bits

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4.6.4.2 Format Control Register Selection (F A2 - FA0)

This three-bit field selects one of eight format control registers. Format control registers are describ ed in Section 4.6.4.3.

There is no response if the Format Control Command is received within a DSI short command structure.

4.6.4.3 Format Control Registers

The seven 4-bit format control registers defined in the DSI 2.0 Bus Specification are shown in Table 4-18 below . The default val-

ues assigned to each re gister following reset are indicated.

The following restrictions apply to format control register operations, in accordance with the DSI 2.0 Bus Spec ification:

• Attempting to write a value greater than eight to the CRC Length Register will cause the write to be ignored. The contents

of the register will remain unchanged.

• Attempting to write a value less than eight to the Short Word Data Length register will cause the write to be ignored. The

contents of the register will remain unchanged.

• The contents of the Format Selection register determine whether standard DSI values or the values contained in the

remaining format control registers will be used. The values contained in the remaining format control registers become

effective when this register is successfully written to ‘1 11 1’. If the register is currently cleared, and one of the data bits FD3

- FD0 is not received as a logic ‘1’, the data in the register will remain all zeroes and the device will continue to use

standard DSI format settings. If the register bits FD3 - FD0 are all set and one of the bits is received as a logic ‘0’ value,

the data in the register will remain ‘1111’ and the values contained in the remaining format control registers will continue

to be used.

Table 4-17 Long Response Structure - Format Control Command

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 0 1 1 0 R/W FA2 FA1 FA0 FD3 FD2 FD1 FD0 0 to 8 bits

Table 4-18 Format Control Registers

Format Control Register Default Value

Name Address

Decimal FA2 FA1 FA0 FD3 FD2 FD1 FD0

CRC Polynomial - Low Nibble 0 0 0 0 0 0 0 1

CRC Polynomial - High Nibble 1 0 0 1 0 0 0 1

Seed - Low Nibble 2 0 1 0 1 0 1 0

Seed - High Nibble 3 0 1 1 0 0 0 0

CRC Length (0 to 8) 4 1 0 0 0 1 0 0

Short Word Data Length (8 to 15) 5 1 0 1 1 0 0 0

Reserved 6 1 1 0 0 0 0 0

Format Selection 7 1 1 1 0 0 0 0

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4.6.5 Read Register Data Command

The Read Register Data command must be transmitted as a DSI long command structure.

There is no response if the Read Register Data Command is received within a DSI short command structure or if this command

is sent to the DSI Global Device Address.

The sixteen registers shown in Table 3-1 may be accessed using this command. Register address combinations are listed below .

Table 4-19 Read Register Data Command Structur e

Data Address Command CRC

D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 C3 C2 C1 C0

0 0 0 0 RA3 RA2 RA1 RA0 A3 A2 A1 A0 1 0 1 1 0 to 8 bits

Table 4-20 Long Response Structure - Read Register Data Command

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 RA3 RA2 RA1 RA0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0 to 8 bits

Table 4-21 Read Register Data Comman d Ad dress Assignment

RA3 RA2 RA1 RA0 Register

0000 SN0

0001 SN1

0010 SN2

0011 SN3

0100 TYPE

0101 Reserved

0110 DEVCFG1

0111 DEVCFG2

1000 REG-8

1001 REG-9

1010 REG-A

1011 REG-B

1100 REG-C

1101 REG-D

1110 REG-E

1111 REG-F

MMA81XXEG

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28 Freescale Semiconductor

4.6.6 Disable Self-Test Stimulus Command

The Disable Self-Test Stimulus command may be transmitted as either a DSI long command structure or a DSI short command

structure of any length. The data field in the command structure is ignored but is included in the CRC calculation.

This command will execute if either the device specifi c address or DSI global device address (address $0) is provided. A

secondary function, self-test locko ut, is activated when two consecutive Disable Self-Test Stimulus commands are recei ved.

Following self-test lockout, the internal self-test circuitry is disabled until a Clear command is received or the device undergoes

power-on reset.

4.6.7 Enable Self-Test Stimulus Command

The Enable Self-Test Stimulus command may be transmitted as either a DSI long command structure or a DSI short command

structure of any length. The data field in the command structure is ignored but is included in the CRC calcul ation. No action is

taken by the device if this command is sent to the DSI Global Device Address.

Table 4-22 Disable Self-Test Stimulus Co mmand Structure

Address Command CRC

A3 A2 A1 A0 C3 C2 C1 C0

A3A2A1A011000 to 8 bits

Table 4-23 Short Response Structure - Disabl e Self-Test Stimulus Comma nd

Response

Length Response

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NV UST BS AT1 AT0 SGF

13 014 0

15 0

Table 4-24 Long Response Stru cture - Disable Self-Test Stimulus Command

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 0 0 0 0 NV UST BS AT1 AT0 SGF 0 to 8 bits

Table 4-25 Enable Self-Test Stimulus Command Structure

Address Command CRC

A3 A2 A1 A0 C3 C2 C1 C0

A3 A2 A1 A0 11010 to 8 bits

MMA81XXEG

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Freescale Semiconductor 29

If self-test locking has been activated, the ST bit will be cleared in the response from the device. Self-Test locking is described in

Section 4.6.6.

4.6.8 Reverse Initialization Command

The reverse initialization command conforms to the description provided in Section 6.2.1 of the DSI Bus St andard, Version 2.0.

At power-up the device is fully compliant with the DSI 1.1 protocol. The initialization command must be transmitted as a DSI 1.1

compliant long command structure. Features of the DSI 2.0 protocol can not be accessed until a valid DSI 1.1 compliant in itial-

ization sequence is performed and th e enhanced mode format registers are properly configured.

Figure 4-1 illustrates the sequence of operations performe d following negation of internal power-on reset (POR) and execution

of a DSI Reverse Initialization command. Reverse Initialization commands are recognized only at BUSOUT. The BUSIN node is

tested for a bus short to battery high voltage condition, and the bus fa ult (BF) flag set if an error condition is detected. If no bus

fault condition is detected and the BS bit is set in the command structure, the bus switch will be closed.

If the device has been pre-programmed, PA3 - P A0 and A3 - A0 must match the pre-programmed address. If no device address

has been previously programmed into the OTP array, PA3 - PA0 contain the device address, while A3 - A0 must be zero. If any

addressing condition is not met, the device address is not assigned, the bus switch will remain open and the device will not re-

spond to the Reverse Initializati on command. If the BS bit is set, the DSI bus voltage level is disregarded for approximately

180 μs following reverse initialization to allow hold capacitors on downstream slaves to charge.

In the response, bits D15 - D12 and D3 - D0 will contain the device address. If the device was unprogrammed when the reverse

initialization command was issued, the device address is assigned as the command executes. Both fields will contain the value

PA3 - PA0 to indicate successful device address assignment.

Initialization or reverse initialization commands which attempt to assign device address zero are ignored.

Table 4-26 Short Response Structure - Enable Self-Test Stimulus Command

Response

Length Response

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NV UST BS AT1 AT0 SGF

13 014 0

15 0

Table 4-27 Long Response Struc tu re - Enable Self-Test Stimulus Command

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 0 0 0 0 NV UST BS AT1 AT0 SGF 0 to 8 bits

Table 4-28 Reverse Initialization Comma nd Structure

Data Address Command CRC

D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 C3 C2 C1 C0

NV BS B1 B0 PA3 PA2 PA1 PA0 A3 A2 A1 A0 1 1 1 1 4 bits

Table 4-29 Long Response Structure - Reverse Initialization Command

Data CRC

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 0 0 0 BF NV BS B1 B0 A3 A2 A1 A0 4 bits

MMA81XXEG

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30 Freescale Semiconductor

SECTION 5 PERFORMANCE SPECIFICATIONS

5.1 MAXIMUM RATINGS

Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. Th e device

contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those

shown in the table below.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristic.

Table 5-1

Ref Rating Symbol Value Unit

Supply Voltages

HCAP

BUSIN, BUSOUT VHCAP

VBUS

-0.3 to +40

-0.3 to +40 V

V(3)

(3)

3Voltage at Programming/Test Mode Entry pin VPP/TEST -0.3 to +11 V(3)

4Voltage at CREG, DIN, CLK, CFIL, DOUT VIN -0.3 to +3.0 V(3)

5Voltage at VGND VGND -0.3 to +3.0 V(3)

BUSIN, BUSOUT, BUSRTN and HCAP Current

Maximum duration 1 s

Continuous IIN

IIN

400

200 mA

mA (3)

(3)

8Current Drain per Pin Excluding VSS, BUSIN, BUSOUT, BUSRTN I±10 mA (3)

Acceleration (without hitting internal g-cell stops)

Z-axis g-cell

X-axis g-cell (40g, 70g)

X-axis g-cell (100g - 250g)

gmax

±1400

±950

±2200

(3)

12 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g(3)

13 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g(3)

14 Drop Shock (to concrete surface) hDROP 1.2 m(3)

Electrostatic Discharge

Human Body Model (HBM)

Charge Device Model (CDM)

Machine Model (MM)

VESD

±2000

±500

±200

(3)

Temperature Range

Storage

Junction Tstg

-40 to +125

-40 to +150 °C

°C (3)

(3)

MMA81XXEG

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Freescale Semiconductor 31

5.2 THERMAL CHARACTERISTICS

5.3 OPERATING RANGE

The operating ratings are the limits normally expected in the application and define the range of operation.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristic.

5. Minimum operating voltage may be reduced pending characterization.

6. Device fully characterized at +105 °C and +125 °C. Production units tested +105 °C, with operation at +125 °C guarante ed through

correlation with characterization results.

9. Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24 V at final test.

Ref Characteristic Symbol Min Typ Max Units

20 Thermal Resistance θJA

θJC

—

——

—85

46 °C/W

°C/W (3)

(3)

Ref Characteristic Symbol Min Typ Max Units

Supply Voltage (Note 9)

VHCAP (Note 5)

BUSIN, BUSOUT VHCAP

VBUS

6.3

-0.3 —

—

30 V

V(1)

(1)

VHCAP Undervoltage Detection

(see Figure 5-1)

Undervoltage Detection Threshold

VHCAP Recovery Threshold

Hysteresis (VLVR - VLVD)

VLVD

VLVR

VLVH

—

100

6.2

6.3

—

(1)

(3)

CREG Undervoltage Detection

(see Figure 5-2)

Undervoltage Detection Threshold

CREG Recovery Threshold

Hysteresis (VLVR - VLVD)

VLVD

VLVR

VLVH

—

2.25

2.35

100

—

(3)

29 Test Mode Activation Voltage VTEST 4.5 —10 V(3)

Programming Voltage

via SPI

via DSI VPP/TEST

VBUS

7.5

14 8.0

—8.5

30 V

V(3)

(3)

32 OTP Programming Current IPROG — — 85 mA (3)

33 Operating Temperature Range

Standard Temperature Range TA

-40 —TH

+125 °C(6)

MMA81XXEG

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32 Freescale Semiconductor

5.4 ELECTRICAL CHARACTERISTICS

The unit digit is defined to be 1 least significant bit (LSB) of the 10-bit digital value, or 1 LSB of the equivalent 8-bit value if explicitly

stated.

VL ≤ (VBUS - VSS) ≤ VH, VL ≤ (VHCAP - VSS) ≤ VH,TL ≤ TA ≤ TH, unless otherwise specified.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristic.

7. Tested 100% at 10-bit output. 8-bit value verified via scan.

8. Functionality verified 100% via scan.

Ref Characteristic Symbol Min Typ Max Units

Digital Output Sensitivity

20g Range

40g Range

50g Range

100g Range

150g Range

250g Range

CFIL Output Sensitivity (TA = 25 °C)

20g Range

40g Range

50g Range

100g Range

150g Range

250g Range

Sensitivity Error

TA = 25 °C

TL ≤ TA ≤ TH

SENS

ΔSENS

—

-5

-7

0.0488

0.0976

0.122

0.244

0.366

0.610

20.1

10.0

8.02

4.01

2.67

1.60

—

g/digit

mV/V/g

(7)

(3)

(1)

Offset (measured in 0g orientation)

TA = 25 °C (8-bit)

TL ≤ TA ≤ TH (8-bit)

TA = 25 °C (10-bit)

TL ≤ TA ≤ TH (10-bit)

*OFF8

OFF8

OFF10

122

116

488

464

128

512

134

140

536

560

digit

(7)

(1)

Full-Scale Range, including sensitivity and offset errors

20g Range

40g Range

50g Range

100g Range

150g Range

250g Range

FSR

21.0

42.0

52.5

105

158

263

24.9

49.9

62.3

124.7

187

312

26.6

53.4

66.7

133

200

334

(3)

Range of Output

Normal (10-bit)

Normal (8-bit)

Fault

RANGE

FAULT

—

1023

255

—

digit

(3)

(8)

61 Nonlinearity

Measured at CFIL output, TA = 25 °CNL

OUT -1 0 +1 % (3)

Internal Voltage Regulator

Output Voltage

Line regulation

Load regulation (IREG < 6 mA)

Ripple rejection

(DC ≤ fRIPPLE ≤ 10 kHz, CREG ≥ 0.9 μF)

CREG capacitance

Effective series resistance, CREG capacitor

VCREG

REGLINE

REGLOAD

CREG

ESR

2.37

—

0.45

0.9

—

2.5

—

2.63

—

700

mV/mA

μF

mΩ

(1)

(3)

MMA81XXEG

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Freescale Semiconductor 33

5.5 ELECTRICAL CHARACTERISTICS (continued)

VL ≤ (VBUS - VSS) ≤ VH, VL ≤ (VHCAP - VSS) ≤ VH,TL ≤ TA ≤ TH, unless otherwise specified.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristic.

10. The external circuit configuration shown in Section 1.3.6 is recommended.

Ref Characteristic Symbol Min Typ Max Units

Input Voltage

LOW (CLK,DIN)

HIGH (CLK,DIN)VIL

VIH

—

0.7xVCreg

—

—0.3xVCreg

—V

V(3)

(3)

Output Voltage (IOUT = 200 μA)

LOW (DOUT)

HIGH (DOUT)VOL

VOH

—

VCreg- 0.1 —

—VSS+ 0.1

—V

V(3)

(3)

Output Loading, CFIL pin (Note 10)

Resistance to VCREG, VSS

Capacitance to VCREG, VSS

Output voltage range

RLOAD

CLOAD

VOUT

—

VSS + 50 mV

—

VCREG-50mV

kΩ

(3)

75 Bus Switch Resistance * RSW —4.08.0Ω(1)

76 Rectifier Forward Resistance * RFWD ——2.5Ω(3)

77 Rectifier Leakage Current * IRLKG — — 100 μA(1)

BUSIN or BUSOUT to HCAP Rectifier Voltage Drop

(VBUS = 26 V)

IBUSIN or IBUSOUT = -15 mA

IBUSIN or IBUSOUT = -100 mA

(VBUS = 7 V)

IBUSIN or IBUSOUT = -15 mA

IBUSIN or IBUSOUT = -100 mA

*VRECT

VRECT

—

1.0

1.2

1.0

1.2

(3)

(1)

BUSIN + BUSOUT Bias Current

VBUSIN or VBUSOUT = 8.0 V, VHCAP = 9.0 V

VBUSIN or VBUSOUT = 0.5 V, VHCAP = 24 V

*IBIAS

IBIAS

—

——

—100

20 mA

μA(1)

(1)

BUSIN and BUSOUT Logic Thresholds

Signal Low

Signal High *

*VTHL

VTHH

2.7

5.4 3.0

6.0 3.3

6.6 V

V(1)

(1)

BUSIN and BUSOUT Hysteresis

Signal

Frame *

*VHYSS

VHYSF

100 —

—90

300 mV

mV (3)

(3)

88 BUSIN + BUSOUT Response Current

VBUSIN and/or VBUSOUT = 4.0 V *IRESP 9.9 11 12.1 mA (1)

89 Quiescent Current * IQ— — 7.5 mA (1)

90 Internal pull-down resistance CLK RPD 20 60 100 kΩ(2)

91 Internal pull-down resistance VPP/TEST RPD 437 kΩ(2)

GND Loss Detect (with external 3 kΩ resistor)

Measurement Current

Detection Resistance IGNDETC

RGNDDETC

309

1340

— 371

10 μA

kΩ

(1)

MMA81XXEG

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34 Freescale Semiconductor

5.6 ELECTRICAL CHARACTERISTICS (continued)

VL ≤ (VBUS - VSS) ≤ VH, VL ≤ (VHCAP - VSS) ≤ VH,TL ≤ TA ≤ TH, unless otherwise specified.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristic.

7. Tested 100% at 10-bit output. 8-bit value verified via scan.

Ref Characteristic Symbol Min Typ Max Units

Total Noise (see Figure 5-3)

400 Hz, 4-pole filter, 20g range

RMS, 100 samples

P-P, 100 samples

180 Hz, 2-pole filter, 20g range

RMS, 100 samples

P-P, 100 samples

nRMS

nP-P

nRMS

nP-P

—

digit

(3)

100

101

Cross-Axis Sensitivity

X-axis, X-axis to Y-axis

X-axis, X-axis to Z-axis

Y-axis, Y-axis to X-axis

Y-axis, Y-axis to Z-axis

VXY

VXZ

VYX

VYZ

-5

—

(3)

102

103

104

105

106

107

Analog to digital converter

Relative accuracy

Differential nonlinearity

Gain error

Offset error (VIN = VCREG/2)

Noise (RMS, 100 samples)

Noise (peak)

INL

DNL

GAINERR

OFST

nRMS

nP-P

-2

-1

-3

-1

-3

—

digit

%FSR

digit

(3)

(2)

(3)

108

109

110

111

112

113

114

115

116

117

Deflection

(Self-Test Output - Offset, average of 30 samples,

measured in 0g orientation, TA = 25° C)

X-axis, 20g Range

X-axis, 40g Range

X-axis, 50g Range

X-axis, 100g Range

X-axis, 150g Range

X-axis, 250g Range

Z-axis, 40g Range

Z-axis, 100g Range

Z-axis, 150g Range

Z-axis, 250g Range

ΔDFLCT

DDFLCT

ΔDFLCT

—

246

123

307

299

205

123

—

digit

(7)

118 Self-Test deflection range, TA = 25 °C, measured in 0g

orientation ΔDFLCT -10 — +10 % (1)

119 Self-Test deflection range, TL ≤ TA ≤ TH, measured in

0g orientation ΔDFLCT -20 — +20 % (1)

MMA81XXEG

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Freescale Semiconductor 35

Figure 5-1. VHCAP Undervoltage Detection

Figure 5-2. VCREG Undervoltage Detection

GND

LVR

HCAP

LVD

UNDERVOLTAGE

LVH

RESUMES

OPERATION

NORMAL t

UVR

UV: UNDERVOLT AGE CONDITION

EXISTS

POR ASSERTED

POR NEGATE D

GND

VLVR

VCREG

VLVD

LOW-VOLTAGE

CONDITION

DETECTED

POR NEGATED

VLVH

INTERNAL RESET IS INITIALLY

ASSERTED UNTIL VCREG ≥ VLVR,

AND THEREAFTER WHEN

VCREG ≤ VLVD.

RESUMES

OPERATION

NORMAL

POR ASSERTED

MMA81XXEG

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36 Freescale Semiconductor

Figure 5-3. Total Nois e Measurement Cond itions

A3 A2 A0A1 0 0 1 00 00 00 00 00 0 A3 A2 A0A1 C3 C2 C1 C0D1 D0D3 D2D5 D4D7 D6D9 D8

COMMAND FORMAT

CMD 99 CMD 100CMD 1 CMD 2

RESP 98 RESP 99XXX RESP 1

XXX

RESP 100

CMD 3

RESP 2

MEASUREMENT WINDOW (10910

MEASUREMENT TIMING

UUT

BUSIN

BUSOUT

BUSRTN N/C

DOL

DOH

DSI BUS CONFIGURATION

MASTER

MMA81XXEG

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Freescale Semiconductor 37

5.7 CONTROL TIMING

VL ≤ (VBUS - VSS) ≤ VH, VL ≤ (VHCAP - VSS) ≤ VH,TL ≤ TA ≤ TH, unless otherwise specified.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristics.

8. Functionality verified 100% via scan. Timing is directly determined by internal oscillator frequency.

Ref Characteristic Symbol Min Typ Max Units

120

VHCAP Undervoltage Reset Period

(see Figure 5-1)

VHCAP < VRA to POR assertion tUVR 0.95 1.0 1.05 ms (8)

121

122

123

Analog to digital converter (see Figure 5-4)

Sample time

Conversion time

Delay following bus idle

tSAMPLE

tCONVERT

tDELAY

4.28

7.13

2.85

4.5

7.5

3.0

4.73

7.88

3.15

μs

(8)

124 BUSIN and BUSOUT response current transition

1.0 mA to 9.0 mA, 9.0 to 1.0 mA tITR 4.5 — 7.5 mA/μs(3)

125 Initialization to Bus Switch Closing tBS 89 — 138 μs(3)

126 Signal Bit Transition Time tBIT 5—200μs(3)

127 Loss of Signal Reset Time

Maximum time below frame threshold tTO ——10ms(8)

128

129

BUSIN or BUSOUT Timing to Response Current

BUSIN or BUSOUT ≤ VTHL to IBUS ≥ 7 mA

BUSIN or BUSOUT ≤ VTHH to IBUS ≤ 5 mA tRSPH

tRSPL

—

——

—3.0

3.0 μs

μs(3)

(3)

130

131

132

133

Interframe Separation Time (see Figure 5-5)

Following Read Write NVM Command

Following Initialization or Reverse Initialization

BS = 1

BS = 0

Following other DSI bus commands

tIFS

200

—

μs

(3)

134

135

Low Pass Filter

(4-pole, -3 db Rolloff Frequency)

(2-pole, -3 db Rolloff Frequency) BWOUT

BWOUT

360

162 400

180 440

198 Hz

Hz (1)

(1)

136

137

Ground Loss Detection Filter Time

Cycles of fOSC

Time tGNDETC

tGNDETC

—16384

4.096

—cycles

ms (8)

(8)

138

139

140

Reset Recovery Time

POR negated to Initialization Command

POR negated to 180 Hz Data Valid

POR negated to 400 Hz Data Valid

tRESET

—

5.3

2.4

100

—

μs

(8)

(3)

141 Internal Oscillator Frequency fOSC 3.80 4.0 4.20 MHz (1)

142

143

Logic Duty Cycle

Logic ‘0’

Logic ‘1’ *

*DCL

DCH

60 33

67 40

90 %

%(8)

(8)

144 OTP Programming, SPI program control tPROG —— 2ms(8)

MMA81XXEG

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38 Freescale Semiconductor

5.8 CONTROL TIMING (continued)

VL ≤ (VBUS - VSS) ≤ VH, VL ≤ (VHCAP - VSS) ≤ VH,TL ≤ TA ≤ TH, unless otherwise specified.

1. Parameters tested 100% at final test.

2. Parameters tested 100% at unit probe.

3. Verified by characterization, not tested in production.

4. (*) Indicates a customer critical characteristic or Freescale important characteristics.

8. Functionality verified 100% via scan. Timing is directly determined by internal oscillator frequency.

Ref Characteristic Symbol Min Typ Max Units

145

146

147

148

SPI Timing (see Figure 5-6)

CLK period

DIN to CLK setup

CLK to DIN hold

CLK to DOUT

tCLK

tDC

tCDIN

tCDOUT

500

—

(3)

149

150

151

Sensing Element Resonant Frequency

Z-axis g-cell

X-axis medium-g g-cell (20-50g)

X-axis high-g g-cell (100-250g)

fGCELL

—

11.2

18.0

22.0

12.8

20.6

—

15.3

24.2

kHz

(3)

152

153

154

Sensing Element Rolloff Frequency (-3 db)

Z-axis g-cell

X-axis medium-g g-cell (20-50g)

X-axis high-g g-cell (100-250g)

BWGCELL

—

1.58

—

kHz

(3)

155

156

Gain at Package Resonance

Z-axis

X-axis Q

Q—

—10

12 —

—kHz

kHz (3)

(3)

157

158

Package Resonance

Z-axis

X-axis f

f—

—45

9.5 —

—kHz

kHz (3)

(3)

MMA81XXEG

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Freescale Semiconductor 39

Figure 5-4. A-to-D Conversion Timing

Figure 5-5. DSI Bus Interframe Timing

Figure 5-6. Serial Interface Timing

BUSIN

STABILIZATION S/H CONVERSION

tDELAY

tSAMPLE tCONVERT

BUSIN

tIFS

DSI BUS

COMMAND

tCLK

tDC tCDIN

CLK

DIN/VGND

DOUT

tCDOUT

DATA

VALID

MMA81XXEG

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40 Freescale Semiconductor

APPENDIX A TEST MODE OPERATION

Test mode is entered when certain conditions are satisfied after power is applied to the device. Commun ication with the device

is conducted using the SPI when in test mode. Two test mode operations are of interest to the customer. These operations are

described below. Test mode communication is conducted using the serial peripheral interface (SPI).

A.1 SPI DATA TRANSFER

A 16-bit SPI is available for data transfer when the voltage at VPP/TEST is raised above VTEST. Test mode is entered when the

sequence of data values shown above are transferred following reset. See Figure A-4 for details of 16-bit SPI packet.

The state of DIN is latched on the rising edge of CLK. DOUT changes on the falling edge of CLK. The interface conforms to

CPHA = 0, CPOL = 0 operation for conventional SPI devices.

A.2 ADC TEST MODE

A special device configuration useful for evaluating the performance of the analog-to-digital convertor block is available. When

selected, internal buffers which drive the CFIL pin and ADC input are disabled, and the input of the ADC is connected to the CFIL

pin, as illustrated in Figure A-1. The following sequence of operations must be performed to enter ADC Test Mode. Refer to

Appendix A.4 for details regarding register read and write operations.

1. Apply VHCAP to the HCAP pin. This may be accomplished through BUSIN if desired.

2. Apply VTEST to the VPP/TEST pin.

3. Transfer the data value $AA to device register address $30 via the SPI.

4. Transfer the data value $55 to device register address $30 via the SPI.

5. Transfer the data value $1D to device register address $30 via the SPI.

Remove power or lower the voltage at VPP/TEST to exit ADC Test Mode.

MMA81XXEG

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Freescale Semiconductor 41

Figure A-1. ADC Test Mode Configuration

BUSOUTBUSIN

BUSRTN

LOGIC

COMMAND DECODE

STATE MACHINE

RESPONSE GENERATION

BANDGAP

REFERENCE

OSCILLATOR

g-CELL C-TO-V

CONVERTER LOW-PASS

FILTER

OFFSET

TRIM

GAIN

TRIM TCS

TRIM

SELFTEST

TRIM OSC

TRIM

SELFTEST

VOLTAGE SELF-TEST ENABLE

VOLTAGE

REGULATOR CREG

HCAP

INTERNAL

SUPPLY

VOLTAGE

OTP

PROGRAMMING

INTERFACE

VPP/TEST

DOUT

CLK

CFIL

VSS

CREG

VSS

N/C

A-TO-D

CONVERTER

REGULATOR

TRIM

VSS 10

N/C 2

VGND/DIN

GROUND

LOSS

DETECTOR 7

MMA81XXEG

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42 Freescale Semiconductor

A.3 OTP PROGRAMMING OPERATIONS

The ten customer-programmed OTP locations (DEVCFG0, DE VCFG1 and REG-8 through REG-F) may be programmed when

the device is in test mode if the following sequence of operations is performed. Register access operations required for OTP pro-

gramming are described in Appendix A.4.

1. Apply VHCAP to the HCAP pin. This may be accomplished through BUSIN if desired.

2. Apply VTEST to the VPP/TEST pin.

3. Write the desired data values to the two registers via the SPI.

4. Transfer the data value $AA to device register address $30 via the SPI.

5. Transfer the data value $55 to device register address $30 via the SPI.

6. Transfer the data value $C6 to device register address $30 via the SPI.

7. Write the data value $00 to address $20 via the SPI. This will enable write access to the fuse mirror registers.

8. Write register data to be programmed into fuse array.

9. Write the data value $05 to address $20 via the SPI. The automatic programming sequence is initiated by this write

operation.

10. Delay a minimum of 32 μs to allow the programming sequence to begin.

11. Read data value from address $29 until bit 5 is set.

12. If bit 4 of value read from address $29 is set, the programming operation did not complete successfully.

Bits which are unprogrammed may be programmed to a logic ‘1’ state. The device may be incrementally programmed if desired,

however once a bit is programmed to a logic ‘1’ state, it may not be reset to logic ‘0’ in the OTP array. Once the LOCK2 bit has

been set, no further changes to the OTP array are possible. Setting LOCK2 also enables parity detection when the device oper-

ates in normal mode.

A.4 INTERNAL REGISTER ACCESS

Using the DIN /VGND, CLK, and DOUT pins, each address location of MMA81XXEG/MMA82XXEG/MMA82XXTEG can be read

and written from an external SPI interface shown in Figure A-2. The corresponding registers may be used to:

• Program the OTP memory

• Read the OTP memory

• Access various internal signals of the MMA81XXEG/MMA82XXEG/MMA82XXTEG in Test mode

Figure A-2. OTP Interface Overview

CLK

DOUT

DIN/VGND

SERIAL

PERIPHERAL

INTERFACE REGISTER

ARRAY

OTP

ARRAY

TO DIGITAL

INTERFACE

MMA81XXEG

Sensors

Freescale Semiconductor 43

A.4.1 Interface Data Bit Stream

The 16-bit SPI serial data consists of 6 bits for a data address, 1 bit for a data direction, and 8 bits for the data to be transferred

as shown below.

Figure A-3. Serial Data Stream

A[5:0]

D[7:0]

Register array data. This is the data to be transferred to the register array during write operations, or the data contained in the

array at the associated address during read operations.

Control of data direction during the clocking of D[7:0] data bits as follows:

RW = 1

RW = 0

A.4.2 Register Array Read Operation

Read operations are completed through 16-bit transfers using the SPI as shown below. Data contained in the array at the asso-

ciated address are presented at the DOUT pin during the 8th through 15th falling edges at the CLK input.

Figure A-4. Serial Data Timing, Register Array Rea d Op eration

Should the data transfer be corrupted by e.g., noise on the clock line, a device reset is required to restore the state of internal

logic.

A[5]

BIT

FUNCTION A[4]

A[3]

A[2]

A[1]

A[0]

⎯

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[5] A[4] A[3] A[2] A[1] A[0] RW

D[6] D[5] D[4] D[3] D[2] D[1] D[0]D[7]

12345678 910111213141516

CLK

DIN/VP2

DOUT

MMA81XXEG

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44 Freescale Semiconductor

A.4.3 Register Array Write Operation

A write operation is completed through the transfer of a 16-bit value using the SPI as shown in the diagram below . Data present

at the DIN pin are transferred to the register at the associated address during the 9th through 16th rising edges at the CLK input.

Contents of the register at the time the write operation is initiated are presented at the DOUT pin during the 8th through 15th falling

edges of the CLK input.

Figure A-5. Serial Data Timing, Register Array Write Opera tion

A.4.4 Internal Address Map Overview

OTP data is transferred to internal registers during the first sixteen clock cycles following oscillator startup and negation of internal

reset. When the de vi ce op erates in test mode, OTP data in the mirror registers may be overwritten. Mirror re gi st er w rites must

be enabled by setting the SPI_WRITE_ENABLE bit (address $29[5]). This bit may be set by writing the value $0 to address $20.

Internal register read and write operations are described in Section 3.

A[5] A[4] A[3] A[2] A[1] A[0] RW D[6 D[5] D[4] D[3] D[2] D[1] D[0]D[7]

12345678 910111213141516

CLK

DIN/VP2

D[6] D[5] D[4] D[3] D[2] D[1] D[0]D[7]DOUT

MMA81XXEG

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Freescale Semiconductor 45

PACKAGE DIMENSIONS

MMA81XXEG

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46 Freescale Semiconductor

PACKAGE DIMENSIONS

MMA81XXEG

Rev 5

04/2010

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