POWER MANAGEMENT
1www.semtech.com
SC1188
Programmable Synchronous DC/DC Converter,
Dual Low Dropout Regulator Controller
Features
Applications
Revision 11/3/2000
Typical Application Circuit
Description
The SC1188 combines a synchronous voltage mode con-
troller with two low-dropout linear regulators providing
most of the circuitry necessary to implement three DC/
DC converters for powering advanced, low cost
microprocessors.
The SC1188 switching section features an integrated 4
bit D/A converter, latched drive output for enhanced noise
immunity and pulse by pulse current limiting. The SC1188
switching section operates at a fixed frequency of
200kHz, providing an optimum compromise between
size, efficiency and cost in the intended application ar-
eas. The integrated D/A converter provides program-
mability of output voltage from 1.30V to 2.05V in 50mV
increments with no external components.
The SC1188 linear sections are low dropout regulators
with short circuit protection, supplying 1.8V for Bridge
and 2.5V for non-GTL I/O.
u Synchronous design, enables no heatsink solution
u 95% efficiency (switching section)
u 4 bit DAC for output programmability
u 1.8V, 2.5V short circuit protected linear controllers
u VRM8.4 Compliant
u Low Cost Motherboards
u 1.3V to 2.05V microprocessor supplies
u Programmable triple power supplies
IRLR024N
3.3V IN
0.1uF
1.8V OUT
5V IN
12V IN
2.5V OUT
+
330uF
0.1uF
VID0
VID3
U5 SC1188CS
13
5
6
7
8
10
11
12
14
15
16
9
1 2
34
VID3
LDOEN
CS-
CS+
GND
DH
BST
VOSENSE
VID2
VID1
VID0
DL
GATE2 GATE1
LDOS1LDOS2
+
Cin
1500uF
x4
VCC_CORE
1.9uH
2R2
VID2
IRLR024N
IRLR3103N
R15 R11
R8 5mOhm
+
C8
1500uF
x6
C10
0.1uF
+
330uF
VID1
IRLR3103N
2R2
+
330uF
0.1uF
R4 1.00k
R12
1k
R5 2.32k
+
47uF
2 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Absolute Maximum Ratings
retemaraPlobmySmumixaMstinU
DNGotTSB 51+ot3.0-V
DNGotNEODLdnaESNESOV 7+ot3.0-V
DNGotxDIV 5.5+ot3.0-V
xSODL 3.0+TSBot3.0-V
egnaRerutarepmeTgnitarepOT
A
07+ot0C°
egnaRerutarepmeTnoitcnuJT
J
521+ot0C°
egnaRerutarepmeTegarotST
GTS
051+ot56-C°
.ceS01)gniredloS(erutarepmeTdaeLT
DAEL
003C°
tneibmAotnoitcnuJecnatsiseRlamrehT θ
AJ
031W/C°
esaCotnoitcnuJecnadepmIlamrehT θ
CJ
03W/C°
Electrical Characteristics
Unless otherwise specified: LDOEN = 3.3V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; BST = 11.4V to 12.6V; TA = 0 to 70°C
retemaraPsnoitidnoCniMpyTxaMstinU
noitceSgnihctiwS
egatloVtuptuOtiucriCnoitacilppAniA2=OI elbaTegatloVtuptuOeeS
noitalugeRdaoLA51otA8.0=OI1%
noitalugeReniL 51.0±%
egatloVtimiLtnerruC 060758Vm
ycneuqerFrotallicsO 571002522zHk
elcyCytuDxaMrotallicsO 0959%
tnerruCecruoS/kniSHDkaeP V1.3=HDNGP-HD,V5.4=HD-HTSB V5.1=HDNGP-HD 005 001 AmAm
tnerruCecruoS/kniSLDkaeP V1.3=LDNGP-LD,V5.4=LD-LTSB V5.1=HDNGP-LD 005 001 AmAm
)LOA(niaGOVotESNESOV53Bd
tnerruCecruoSDIVV4.2<xDIV101Aµ
egakaeLDIVV3.3=xDIV01Aµ
emitdaeD 04001sn
NOTE:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
3
2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Electrical Characteristics (Cont.)
Unless specified: LDOEN = 3.3V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV ; BST = 11.4V to 12.6V; TA = 0 to 70°C
retemaraPsnoitidnoCniMpyTxaMstinU
snoitceSraeniL
tnerruCtnecseiuQV21=TSB5Am
1ODLegatloVtuptuO 394.2525.2655.2V
2ODLegatloVtuptuO 597.1818.1148.1V
)LOA(niaG)2,1(ETAGot)2,1(SODL09Bd
noitalugeRdaoLI
O
A8ot0=3.0%
noitalugeReniL 3.0%
ecnadepmItuptuOV
ETAG
V5.6=15.1kΩ
tuokcoLegatlovrednUTSB 0.8V
dlohserhTNEODL 3.19.1V
tnerruCkniSNEODLV3.3=NEODL 10.0 002- 0.1 003- µA
µA
egatloVpirTtnerrucrevOVfo%
O
tniopteS020406%
ytinummItiucriCtrohStuptuOpU-rewoP 15 06sm
ytinummIhctilGtiucriCtrohStuptuO 5.046 sm
ecnadepmInwodlluPetaG V0=TSB=CCV;DNG-)2,1(ETAG08003057kΩ
ecnadepmItupnIESNESOV 01kΩ
4 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Pin Configuration Ordering Information
Pin Descriptions
Note:
(1) Add suffix TR for tape and reel.
eciveD
)1(
egakcaP raeniL egatloV pmeT T(egnaR
J
)
SC8811CS61-OSV5.2/V8.1C°521ot°0
1
2
3
4
5
6
7
8
VID0
VID1
VID2
VID3
VOSENSE
BST
DH
DL
GATE2
GATE1
LDOS1
LDOS2
LDOEN
CS-
CS+
GND
TOP VIEW
(
SO-16
)
13
12
14
15
16
11
10
9
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
#niPemaNniPnoitcnuFniP
12ETAG2ODLtuptuOevirDetaG
21ETAG1ODLtuptuOevirDetaG
31SODL1ODLroftupnIesneS
42SODL2ODLroftupnIesneS
5NEODL2&1ODLrofnoitacifilauQV3.3
6-SC)evitagen(tupnIesneStnerruC
7+SC)evitisop(tupnIesneStnerruC
8DNGdnuorGgolanAdnarewoP
9LDtuptuOrevirDediSwoL
01HDtuptuOrevirDediShgiH
11TSBstiucricCIllarofylppuS
21ESNESOVniahCkcabdeeFlanretnIfodnepoT
313DIV
)1(
)BSM(tupnIgnimmargorP
412DIV
)1(
tupnIgnimmargorP
511DIV
)1(
tupnIgnimmargorP
610DIV
)1(
)BSL(tupnIgnimmargorP
5
2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Block Diagram
Unless specified: VCC = 3.13V to 3.47V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; BST = 11.4V to 12.6V; TA = 0 to 70°C
Applications Information - Output Voltage Table
retemaraPsnoitidnoC DIV 0123 .niM.pyT.xaMstinU
egatloVtuptuOI
O
draoBnoitaulavEniA2= 1111782.1003.1313.1 V
0111633.1053.1463.1
1011683.1004.1414.1
0011534.1054.1564.1
1101584.1005.1515.1
0101435.1055.1665.1
1001485.1006.1616.1
0001336.1056.1766.1
1110386.1007.1717.1
0110237.1057.1687.1
1010287.1008.1818.1
0010138.1058.1968.1
1100188.1009.1919.1
0100039.1059.1079.1
1000089.1000.2020.2
0000920.2050.2170.2
R
S
Q
OSCILLATOR
+
-
+
-
ERROR AMP
+
-
CURRENT LIMIT
70mV
VOSENSE
BST
VID0
GND
DL
DH
VID2
VID1
LDOS1
GATE1
VID3
LDOS2
GATE2
SHOOT-THRU
CONTROL
1.265V
REFERENCE
REFERENCE
LEVEL SHIFT
AND HIGH SIDE
MOSFET DRIVE
SYNCHRONOUS
MOSFET DRIVE
FET
CONTROLLER
2.5V
D/A
FET
CONTROLLER
1.8V
CS- CS+
LDOEN
REGULATOR
INTERNAL
BIAS
COMPARATOR
6 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Layout Guidelines
Careful attention to layout requirements are necessary for
successful implementation of the SC1188 PWM control-
ler. High currents switching at 200kHz are present in the
application and their effect on ground plane voltage differ-
entials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bot-
tom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Mini-
mizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically cleaner grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper re-
gion. It should be as short as practical. Since this connec-
tion has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the out-
put inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transi-
tions in this connection and length is not so important,
however adding unnecessary impedance will reduce effi-
ciency.
Vout
12V IN
3.3V Vo Lin1
Vo Lin2
5V
L
5mOhm
+
Cout
+
Cin
Q2
Q3
+
Cout Lin1
2.32k
Q4
+
Cout Lin2
1.00k
+
Cin Lin
SC1188
LDOEN
5
CS-
6
CS+
7
DH
10
BST
11
VOSENSE
12
VID2
14
VID1
15
VID0
16
GND
8
DL
9
GATE2
1
GATE1
2
LDOS1
3
LDOS2
4Q1
0.1uF
0.1uF
Heavy lines indicate
high current paths.
3.3V IN
VID3
13
La
y
out Dia
g
ram
SC1188
7
2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Layout Guidelines (Cont.)
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents
are supplied by Cout only, and connections between Cout
and the load must be short, wide copper areas to mini-
mize inductance and resistance.
5) The SC1188 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of (one
of) the output capacitor(s). If this is not possible, the GND
pin may be connected to the ground path between the
Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no
circumstances should GND be returned to a ground inside
the Cin, Q1, Q2 loop.
6) BST for the SC1188 should be supplied from the 12V
supply, the BST pin should be decoupled directly to GND
by a 0.1mF ceramic capacitor, trace lengths should be as
short as possible. The SC1188 Internal circuits are pow-
ered from this pin.
7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces run-
ning back to CS+ and CS- on the SC1188 should run par-
allel and close to each other. The 0.1µF capacitor should
be mounted as close to the CS+ and CS- pins as possible.
8) Ideally, the grounds for the two LDO sections should be
returned to the ground side of (one of) the output
capacitor(s).
Vout
5V
+
+
Currents in Power Section
8 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Component Selection
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
step current Transient I excursion voltage transient MaximumV
Where I
V
R
t
t
t
t
ESR
==
≤
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mW. To meet this kind of ESR level, there are three
available capacitor technologies.
ygolonhceT .paChcaE .ytQ .dqR
latoT
C
(µ)F RSE
m( Ω)C
(µ)F RSE
m( Ω)
mulatnaTRSEwoL033066000201
NOC-SO0335230993.8
munimulARSEwoL005144500573.8
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
The maximum inductor value may be calculated from:
()
OINOA
A
t
ESR
VV or V of lesser the is V where
V
ICR
L
−
⋅≤
The calculated maximum inductor value assumes 100%
and 0% duty cycle capability, so some allowance must be
made. Choosing an inductor value of 50 to 75% of the
calculated maximum will guarantee that the inductor cur-
rent will ramp fast enough to reduce the voltage dropped
across the ESR at a faster rate than the capacitor sags,
hence ensuring a good recovery from transient with no
additional excursions.
We must also be concerned with ripple current in the out-
put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
OSC
IN
LfL4 V
IRIPPLE ⋅⋅
=
Ripple current allowance will define the minimum permit-
ted inductor value.
POWER FETS - The FETs are chosen based on several
criteria, with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a combi-
nation of conduction losses, switching losses and bottom
FET body diode recovery losses.
a) Conduction losses are simply calculated as:
IN
O
)on(DS
2
OCOND
V
V
c
y
cle dut
y
=
where RIP
≈δ
δ⋅⋅=
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
2
INOSW 10VIP −
⋅⋅=
or more generally,
4f)tt(VI
POSCfrINO
SW ⋅+⋅⋅
=
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
OSCINRRRR fVQP ⋅⋅=
To a first order approximation, it is convenient to only con-
sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
9
2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra
output capacitance or, more usually, additional input ca-
pacitors. Choosing low ESR input capacitors will help maxi-
mize ripple rating for a given size.
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on the linear controllers is imple-
mented by using the Rds(on) of the FETs. As output cur-
rent increases, the regulation loop maintains the output
voltage by turning the FET on more and more. Eventually,
as the Rds(on) limit is reached, the FET will be unably to
turn on more fully, and output voltage will start to fall.
When the output voltage falls to approximately 50% of
nominal, the LDO controller is latched off, setting output
voltage to 0. Power must be cycled to reset the latch.
To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially dis-
abled. It is enabled at a preset time (nominally 2ms) after
both the VCC and BST rails rise above their lockout points.
To be most effective, the linear FET Rds(on) should not be
selected artificially low, the FET should be chosen so that,
at maximum required current, it is almost fully turned on.
If, for example, a linear supply of 1.5V at 4A is required
from a 3.3V ± 5% rail, max allowable Rds(on) would be.
Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ
To allow for temperature effects 200mΩ would be a suit-
able room temperature maximum, allowing a peak short
circuit current of approximately 15A for a short time be-
fore shutdown.
Component Selection (Cont.)
Using 1.5X Room temp RDS(ON) to allow for temperature rise.
epytTEFR
)no(SD
m( Ω)P
D
)W(egakcaP
52043LRI5196.1D
2
kaP
3022LRI5.0191.1D
2
kaP
0144iS0262.28-0S
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
)1(RIP )on(DS
2
OCOND δ−⋅⋅=
For the example above:
epytTEFR
)no(SD
m( Ω)P
D
)W(egakcaP
52043LRI5133.1D
2
kaP
3022LRI5.0139.0D
2
kaP
0144iS0277.18-0S
Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40oC/W for the D2PAK and 80oC/W for the
SO-8 are readily achievable. The corresponding tempera-
ture rise is detailed below:
(esiRerutarepmeT
O
)C
epytTEFTEFpoTTEFmottoB
52043LRI6.762.35
3022LRI6.742.73
0144iS8.0816.141
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
10 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Typical Characteristics
Transient Response Vo=2.0V , Io=300mA to 15A
75%
80%
85%
90%
0.0 5.0 10.0 15.0
Io (A)
Efficiency (%)
Vo=2.0V
Vo=1.6V
Vo=1.3V
-1.5%
-1.0%
-0.5%
0.0%
0.00 5.00 10.00 15.00
Io (A)
Regulation (%)
Ripple V oltage, V o=1.6V; Io=15A
Transient Response Vo=2.0V , Io=300mA to 15A
11
2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Evaluation Board Schematic
R4 1.00kR6 2R2
L1 1.9uH
Q5
IRLR024N
OFFSET
mV/V
0
2
2
2
5
5
5
10
10
10
+
C9
1500uF
C1
0.1uF
+
C15
330uF
+
C3
1500uF
R8 5mOhm
R15
See Table 2
J18
SCOPE TP
VOUT
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
VID3
SW1
SW DIP-4
1234
8765
Q3
IRLR3103N
+
C21
1500uF
+
C8
1500uF
R15
(
Ohm
)
EMPTY
10
5
2
25
12.5
5
50
25
10
VID2
J23
Q1
IRLR3103N
+
C2
1500uF
12V
Q2
IRLR3103N
R7 2R2
R12
1k
+
C24
47uF
J21
C5
0.1uF
C4
1uF
J24
+
C22
1500uF
+
C17
330uF
VINLIN
J22
R11
See Table 2
1.5V
DROOP
mV/A
0
1
2
5
1
2
5
1
2
5
VID0
J12
C10
0.1uF
+
C14
330uF
TABLE VALID FOR 1x5mOhm SENSE
RESISTOR
+
C19
1500uF
U5
SC1188CS
13
5
6
7
8
10
11
12
14
15
16
9
1 2
34
VID3
LDOEN
CS-
CS+
GND
DH
BST
VOSENSE
VID2
VID1
VID0
DL
GATE2 GATE1
LDOS1LDOS2
+
C6
1500uF
VCC_CORE
VID
3210
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
+
C23
1500uF
+
C12
330uF
Q4
IRLR3103N
VLIN2
J17
CON4
1
2
3
4
J16
CON4
1
2
3
4
R5 2.32k
R11
(
Ohm
)
0
2.5
3.3
EMPTY
6.3
8.3
EMPTY
12.5
16.7
EMPTY
Q6
IRLR024N
+
C16
330uF
5V
J14
VID1
+
C18
1500uF
J13
J1
VLIN1
+
C20
1500uF
R10 2R2
+
C11
330uF
+
C7
1500uF
R9 2R2
2.5V
12 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Evaluation Board Bill of Materials
.ytQecnerefeReulaVsetoN
14 01C,5C,1CFµ1.0
221,12C,02C,91C,81C,9C,8C,7C,6C,3C,2C 32C,22C Fµ0051 roXG-VMoynaSRSEwoL tnelaviuqe
14CFµ1cimareC
36 71C,61C,51C,41C,21C,11CFµ033
142CFµ74
41 1LHµ9.1
54 4Q,3Q,2Q,1QN3013RLRI
62 6Q,5QN420RLRI
71 4Rk00.1%1
81 5Rk23.2%1
94 01R9R,7R,6R2R2
011 8RmhOm51RAOCRI
112 11R,51RelbaTeeS
211 21Rk1
311 1WS4-PIDWS
411 4USC8811CSHCETMES
13
2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Evaluation Board Gerber Plots
14 2000 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1188
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
Outline Drawing - SO-16
Contact Information
Land Pattern - SO-16
