This is information on a product in full production.
February 2016 DocID022694 Rev 4 1/33
VND5T050AK-E
Double channel high-side driver with analog current sense for 24 V
automotive applications
Datasheet
−
production data
Features
•General
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliant with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
•Diagnostic Functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Off-state open load detection
– Output short to V
CC
detection
– Overload and short to ground latch off
– Therm al sh utdown latc h-off
– Very low current sense leakage
•Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Therm al sh utdow n
– Electros tatic disc harge protection
Application
•All types of resistive, inductive and capacitive
loads
Description
The VND5T050AK-E is a monolithic device made
using STMicroelectronics
®
VIPowe r
®
technology,
intended for driving resistive or inductive loads
with one side connected to ground. Active V
CC
pin voltage clamp protects the device against low
energy spi k es .
This device integrates an analog current sense
which delivers a current proportional to the load
current.
Fault conditions such as overload,
overtemperature or short to V
CC
are reported via
the current sense pin.
Output current limitation protects the device in
overload condition. The device will latch off in
case of overload or thermal shutdown.
The device is reset by a low level pass on the fault
reset standby pin.
A permanent low level on the inputs and fault
reset standby pin disable all outputs and set the
device in standby m ode .
Max transient supply voltage V
CC
58 V
Operati ng vol tage range V
CC
8 to 36V
Typ On-St ate resis t an ce (per ch .) R
ON
50 mΩ
Current lim itation (typ) I
LIM
34 A
Off state supply current I
S
2 µA
PowerSSO-24
www.st.com
Contents VND5T050AK-E
2/33 DocID022694 Rev 4
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Elect rical char acteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Maximum demagneti zation energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . 23
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 PowerSSO-24 mechanical da ta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 PowerSSO-24 packing informati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID022694 Rev 4 3/33
VND5T050AK-E List of tables
3
List of tables
Table 1. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (V
CC
=24V; T
j
= 25 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current sense (8 V < V
CC
< 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Open-load detection (V
FR_STBY
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
List of figures VND5T050AK-E
4/33 DocID022694 Rev 4
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram PowerSSO-24 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. T
reset
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. T
stby
definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Open-load off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Output stuck to V
CC
detection delay time at FR
STBY
activation . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Delay response time between rising edge of output current and rising edge of
current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input high level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. On-state resistance vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. On-state resistance vs V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. I
LIMH
vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. R
thj-amb
vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 24
Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 25
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 25
Figure 30. PowerSSO-24 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 32. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID022694 Rev 4 5/33
VND5T050AK-E Block diagram and pin description
32
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
V
CC
Battery connec ti on
OUT
1,2
Power output
GND Ground connection
IN
1,2
Voltage c ontrol led in put p ins wi th hy ster esis, CMOS comp ati ble. They c ontrol outpu t
switch state
CS
1,2
Analog current sense pins, they deliver a current proportional to the load current
FR_Stby In case of latch-off for overtemperature/overcurrent conditions, a low pulse on the
FR_Stby pin is needed to reset the channel.
The device enters in standby mode if all inputs and the FR_Stby pin are low.
Control & Diagnostic 2
VCC
CH1
LOGIC
DRIVER
Current
Limitation
Power
Clamp
Over
Temperature
Undervoltage
CH2
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
IN1
IN2
CS1
CS2
FR_Stby
GND
OUT2
OUT1
Signal Clamp
GAPGCFT00643
Current
Sense
VSENSEH
Control & Diagnostic 1
OFF-state
Open-load
VON
Limitation
Block diagram and pin description VND5T050AK-E
6/33 DocID022694 Rev 4
Figure 2. Configuration diagram PowerSSO-24 (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current Sense N.C. Output Input FR_Stby
Floating Not allowed X
(1)
1. X: do not care.
XX X
To ground Through 10 kΩ
resistor X Not allowed Through 10 kΩ
resistor T hrou gh 10 kΩ
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&&
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1&
9
&&
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&&
1&
,1
1&
1&
287
287
287
287
287
287
287
287
287
287
287
287
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DocID022694 Rev 4 7/33
VND5T050AK-E Electrical specifications
32
2 Electrical specifications
Fig ure 3. Cu rrent and voltage conventions
Note: V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not
implied. Exposure to the conditions reported in this section for extended periods may affect
device reliability.
I
S
I
GND
V
CC
V
CC
OUTn I
OUTn
CSn I
SENSEn
INn
I
INn
GND
FR_Stby
V
FR_Stby
V
INn
V
SENSEn
V
OUTn
V
Fn
I
FR_Stby
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 58 V
-V
CC
Reverse DC supply voltage 0.3 V
-I
GND
DC reverse ground pin current 200 mA
I
OUT
DC output current Internally limited A
-I
OUT
Reverse D C output current 30 A
I
IN
DC input current -1 to 10 mA
I
FR_Stby
Fault reset standby DC input current -1 to 1.5 mA
-I
CSENSE
DC reverse CS pin current 200 mA
V
CSENSE
Current sense maximum voltage V
CC
- 58 to
+V
CC
V
E
MAX
Maximum switching energy
L = 50 mH; V
bat
=32V; T
jstart
=150°C; I
OUT
=2A 210 mJ
Electrical specifications VND5T050AK-E
8/33 DocID022694 Rev 4
2.2 Thermal data
L
smax
Maximum strain inductance in short circuit condition
R
L
=300mΩ, V
batt
=32V, T
jstart
= 150°C, l
out
=I
LMHmax
40 µH
V
ESD
Electrostatic discharge
(Human Body Model: R = 1.5 kΩ; C = 100 pF)
–IN
1,2
–CS
1,2
–FR_Stby
–OUT
1,2
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
V
ESD
Charge device model (CDM-AEC-Q100-011) 750 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Value Unit
R
thj-case
Thermal resistance junction-case (max.) (with one channel ON) 2.4 °C/W
R
thj-amb
Thermal resistance junction-ambient (max.) See
Figure 27 °C/W
DocID022694 Rev 4 9/33
VND5T050AK-E Electrical specifications
32
2.3 Electrical characteristics
8V<V
CC
<36V; -40°C<T
j
< 150°C, unless otherwise specified.
Table 5.
Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operati ng supply voltage 8 24 36 V
V
USD
Undervoltage shutdown 3.5 5 V
V
USDhyst
Undervoltage shutdown
hysteresis 0.5 V
R
ON
On-state resistance
(1)
1. For each channel
I
OUT
= 2 A; T
j
= 25°C 50 mΩ
I
OUT
= 2 A; T
j
= 150°C 100
V
clamp
Clamp voltage I
S
=20mA 586470 V
I
S
Supply current
Off-state; V
CC
=24V; T
j
=25°C;
V
IN
=V
OUT
=V
SENSE
=0V 2
(2)
2. PowerMOS leakage included
5
(2)
µA
On-state; V
CC
=24V; V
IN
=5V;
I
OUT
=0A 4.2 6 mA
I
L(off)
Of f-state output current
V
IN
=V
OUT
=0V; V
CC
=24V;
T
j
=25°C 00.013 µA
V
IN
=V
OUT
=0V; V
CC
=24V;
T
j
=125°C 05
V
F
Output - V
CC
diode
voltage -I
OUT
= 2 A; T
j
=150°C 0.7 V
Table 6. Switching (V
CC
=24V; T
j
=25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
Turn-on delay time R
L
= 12 Ω30 µs
t
d(off)
Turn-off delay time R
L
= 12 Ω40 µs
dV
OUT
/dt
(on)
Turn-on voltage slope R
L
= 12 Ω0.7 V/us V/µs
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
= 12 Ω0.8 V/us V/µs
W
ON
Switching energy losses
during t
won
R
L
= 12 Ω0.5 mJ
W
OFF
Switching energy losses
during t
woff
R
L
= 12 Ω0.3 mJ
Electrical specifications VND5T050AK-E
10/33 DocID022694 Rev 4
Figure 4. T
reset
definition
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low lev el vo lt ag e 0.9 V
I
IL
Low level input current V
IN
= 0.9 V 1 µA
V
IH
Input high level voltage 2.1 V
I
IH
High level input current V
IN
= 2.1 V 10 µA
V
I(hyst)
Input hyste r es is vo lt age 0.25 V
V
ICL
Input clamp volt age I
IN
= 1 mA 5.5 7 V
I
IN
= -1 mA -0.7 V
V
FR_Stby_L
Fault reset standby low level
voltage 0.9 V
I
FR_Stby_L
Low level fault reset standby
current V
FR_Stby
= 0.9 V 1 µA
V
FR_Stby_H
Fault reset s tandby hi gh lev el
voltage 2.1 V
I
FR_Stby_H
High lev el fault reset s tandby
current V
FR_Stby
= 2.1 V 10 µA
V
FR_Stby
(hyst) Fault reset standby hysteresis
voltage 0.25 V
V
FR_Stby_CL
Fault reset standby clamp
voltage I
FR_Stby
= 15 mA (t < 10 m s) 11 15 V
I
FR_Stby
= -1 mA -0.7 V
t
reset
Overload latch-off reset time See Figure 4 224µs
t
stby
Standby delay See Figure 5 120 1200 µs
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DocID022694 Rev 4 11/33
VND5T050AK-E Electrical specifications
32
Figure 5. T
stby
definition
Table 8. Protections and diagnostics
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit current V
CC
= 24 V 24 34 46 A
5V<V
CC
<36V 46 A
I
limL
Short circuit current
during ther mal cyclin g V
CC
= 24 V;
T
R
<T
j
<T
TSD
8.5 A
T
TSD
Shut down tem pe rature 150 175 200 °C
T
R
Reset temperature T
RS
+ 1 T
RS
+ 5 °C
T
RS
Thermal reset of status 135 °C
T
HYST
Thermal hysteresis
(T
TSD
-T
R
)7°C
V
DEMAG
Turn-of f outp ut vol t ag e
clamp I
OUT
= 2 A; V
IN
= 0;
L=6mH V
CC
- 58 V
CC
- 64 V
CC
- 70 V
V
ON
Output voltage drop
limitation I
OUT
= 100 mA 25 mV
Table 9. Current sense (8 V < V
CC
<36V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
_ol
I
OUT
= 10 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C
T
j
= 25°C to 150°C 564
972 2800 5563
4895
K
led
I
OUT
= 50 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C
T
j
= 25°C to 150°C 1193
1416 2650 4268
3958
dK/K
totled
Current se nse rati o drif t I
OUT
= 12 mA to 60 mA;
V
SENSE
= 0.5 V; I
cal
=35mA -35 35 %
K
0
I
OUT
/I
SENSE
I
OUT
= 100 mA; V
SENSE
=0.5V;
T
j
= -40°C to 150°C 1409 2540 3726
dK
0
/K
0(1)
Current se nse rati o drif t I
OUT
=100mA; V
SENSE
=0.5V;
T
j
= -40°C to 150°C -20 20 %
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Electrical specifications VND5T050AK-E
12/33 DocID022694 Rev 4
K
1
I
OUT
/I
SENSE
I
OUT
= 0.7 A; V
SENSE
= 2 V;
T
j
= -40°C to 150°C 1597 2190 2764
dK
1
/K
1(1)
Current se nse rati o drif t I
OUT
= 0.7 A; V
SENSE
=2V;
T
j
= -40°C to 150°C -15 15 %
K
2
I
OUT
/I
SENSE
I
OUT
= 2 A; V
SENSE
=2V;
T
j
= -40 °C...150 °C 1850 2190 2550
dK
2
/K
2(1)
Current se nse rati o drif t I
OUT
= 2 A; V
SENSE
= 2 V;
T
j
= -40°C to 150°C -10 +10 %
K
3
I
OUT
/I
SENSE
I
OUT
= 8 A; V
SENSE
= 4 V;
T
j
= -40°C to 150°C 2050 2190 2280
dK
3
/K
3(1)
Current se nse rati o drif t I
OUT
= 8 A; V
SENSE
= 4 V;
T
j
= -40°C to 150°C -3 3 %
I
SENSE0
Analog sense leakage
current
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
=0V; T
j
= -40°C to 150°C 01µA
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
=5V; T
j
= -40°C to 150°C 02µA
V
SENSE
Max analog sense
output vo lt ag e I
OUT
= 8 A; R
SENSE
=3.9kΩ5V
V
SENSEH
Analog sense output
voltage in fault
condition
(2)
V
CC
=24V; R
SENSE
=3.9kΩ7.5 8.5 9.5 V
I
SENSEH
Analog sense output
current in fault
condition
(2)
V
CC
=24V; V
SENSE
=5V 4.9 7 12 mA
t
DSENSE2H
Delay response time
from rising edge of
INPUT pins
V
SENSE
<4V;
0.15 A < I
OUT
< 8 A;
I
SENSE
=90% of I
SENSE
max
(see Figure 6)
150 300 µs
Δt
DSEN
SE
2H
Delay response time
between rising edge of
output cu rrent and
rising edge of current
sense
V
SENSE
<4V;
I
SENSE
= 90% of I
SENSEMAX,
I
OUT
= 90% of I
OUTMAX
I
OUTMAX
= 2 A (see Figure 10)
250 µs
t
DSENSE2L
Delay response time
from falling edge of
INPUT pins
V
SENSE
<4V, 0.15A<I
OUT
<8A
I
SENSE
=10% of I
SENSE
max
(see Figure 6)520µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load in off-state condition.
Table 9. Current sense (8 V < V
CC
< 36 V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID022694 Rev 4 13/33
VND5T050AK-E Electrical specifications
32
Figure 6. Current sense delay characteristics
Figure 7. Open-load off-state dela y timing
1. V
fr_stby
= high.
Table 10.
Open-load detection
(V
FR_STBY
=5V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
OL
Open-load off-state voltage
detecti on thre sho ld V
IN
=0V; 8V<V
CC
<36V 2 — 4 V
t
DSTKON
Output short circuit to V
CC
detection delay at turn off See Figure 7 180 — 1800 µs
I
L(off2)
Of f-state output current at
V
OUT
=4V V
IN
=0V; V
SENSE
=0V;
V
OUT
rising from 0 V to 4 V -120 — 0 µA
td_vol Delay response fr om output
rising edge to V
SENSE
rising
edge in openload
V
OUT
=4V; V
IN
=0V;
V
SENSE
=90% of V
SENSEH
Rsense=3.9K —20µs
t
DFRSTK_ON
Output short circuit to V
CC
detection delay at FRSTBY
activation
See Figure 10;
Input
1,2
=low —50µs
SENSE CURRENT
INPUT
LOAD CURRENT
t
DSENSE2H
t
DSENSE2L
V
IN
V
CS
t
DSTKON
OUTPUT STUCK TO V
CC
V
OUT
> V
OL
V
SENSEH
DocID022694 Rev 4 15/33
VND5T050AK-E Electrical specifications
32
Figure 10. Delay response time between rising edge of output c urrent and rising edge
of current sense
Figure 11. Output voltage drop limitation
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
Δ
t
DSENSE2H
t
t
t
V
on
I
out
V
cc
-V
out
T
j
=150
o
CT
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
Electrical specifications VND5T050AK-E
16/33 DocID022694 Rev 4
Figure 12. Device behavior in overload condition
overload reset
VsenseH
overload diag reset
IN
n
OUTPUT
n
t reset
CS
n
OVERLOAD
(*)
CHANNEL
n
123 4 5
overload
67
t reset
8
FAULT_RESET
overload reset
VsenseH
overload diag reset
IN
n
OUTPUT
n
t reset
CS
n
OVERLOAD
(*)
CHANNEL
n
123 4 5
overload
67
t reset
8
FAULT_RESET
IN
n
OUTPUT
n
t reset
CS
n
OVERLOAD
(*)
CHANNEL
n
123 4 5
overload
67
t reset
8
FAULT_RESET
FAULT_RESET
1: OUTPUT
n
and CS
n
controlled by IN
n
.
2: FAULT_RESET from ‘0’ to ‘1’ no action on CS
n
pin
3: Overload latch-off. INn high CS
n
high
4: FAULT_RESET low AND Temp channeln < overload_reset Overload latch reset after t_reset
4 to 5: FAULT_RESET low AND IN
n
high thermal cycling, CS
n
high
5: FAULT_RESET high latch-off reset disabled
6 to 7: Overload event and FAULT_RESET high latch-off, no thermal cycling
7 to 8: Overload diagnostic disabled/enabled by the input
8: Overload latch-off reset by FAULT_RESET
(*) OVERLOAD = Thermal shutdown OR Power Limitation
DocID022694 Rev 4 17/33
VND5T050AK-E Electrical specifications
32
Table 11. Truth table
Conditions Fault reset standby Input Output Sense
Standby L L L 0
Normal operati on X
XL
HL
H0
Nominal
Overload X
XL
HL
H0
> Nominal
Overtemperature / short to ground X
L
H
L
H
H
L
Cycling
Latched
0
V
SENSEH
V
SENSEH
Undervoltage X X L 0
Short to V
BAT
L
H
X
L
L
H
H
H
H
0
V
SENSEH
< Nominal
Open load off- state ( with pull-up) L
H
X
L
L
H
H
H
H
0
V
SENSEH
0
Negative output voltage clamp X L Negative 0
Electrical specifications VND5T050AK-E
18/33 DocID022694 Rev 4
Table 12. Electrical transient requirements (p art 1)
ISO 7637-2:
2004(E)
Test pulse
Test levels
(1)
Number of
pulses or
test times
Burst cycle/p ulse
repetition time Delays and
impedance
III IV
1 - 450 V - 600 V 5000
pulses 0.5 s 5 s 1 ms, 50 Ω
2a + 37 V + 50 V 5000
pulses 0.2 s 5 s 50 µs, 2 Ω
3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 - 12 V - 16 V 1 pulse 100 ms, 0.01
Ω
5b
(1)
1. Valid in case of external load dump clamp: 58 V maximum referred to ground.
+ 123 V + 174 V 1 pulse 350 ms, 1
Ω
Table 13. Electrical transient requirements (p art 2)
ISO 7637-2:
2004(E)
Test pulse
Test level result s
(1)
1. In order to guarantee the ISO transient classes a minimum 10 kΩ protection resistors are needed an logic
pins.
III IV
1C C
2a C C
3a C C
3b
(2)
2. Without capacitor between V
CC
and GND.
EE
3b
(3)
3. With 10 nF between V
CC
and GND.
CC
4C C
5b
(4)
4. External load dump clamp, 58 V maximum, referred to ground.
CC
Table 14. Electrical transient requirements (p art 3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
device.
DocID022694 Rev 4 19/33
VND5T050AK-E Electrical specifications
32
2.4 Electrical characteristics curves
Figure 13. Off-state output current
Figure 14. High level input current
Figure 15. Input clamp voltage
Figure 16. Input low level volt age
Figure 17. Input high level voltage
Figure 18. Input hysteresis voltage
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Electrical specifications VND5T050AK-E
20/33 DocID022694 Rev 4
Figure 19. On-state resistance vs T
case
Figure 20. On-state resistance vs V
CC
Figure 21. I
LIMH
vs T
case
Figure 22. Turn-on voltage slope
Figure 23. Turn-off voltage slope
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DocID022694 Rev 4 21/33
VND5T050AK-E Application information
32
3 Application information
Figure 24. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R
GND
only)
This solution can be used with any type of load.
The following equations are an indication on how to size the R
GND
resistor.
1. R
GND
≤ 600 mV / (I
S(on)max
).
2. R
GND
≥ (−V
CC
) / (-I
GND
)
where -I
GND
is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND
will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
GND
.
V
CC
GND
OUT
D
GND
R
GND
D
ld
MCU
+5V
V
GND
FR_Stby
IN
R
prot
R
prot
R
prot
R
SENSE
CS
C
ext
Application information VND5T050AK-E
22/33 DocID022694 Rev 4
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).
3.1.2 Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND
=4.7kΩ) should be inserted in parallel to D
GND
if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values, if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
D
ld
is necessary (V oltage Transient Suppressor) if the load dump peak voltage exceeds to
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line
that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3 MCU I/Os pro te c tion
If a ground protection network is used and negative transients are present on the V
CC
line,
the control pins will be pulled negative. ST suggests that a resistor (R
prot
) be i ns er t ed i n li ne
to prevent the microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -600 V and I
latchup
≥ 20 mA; V
OHμC
≥ 4.5 V
30 kΩ ≤ R
prot
≤ 180 kΩ.
Recommended R
prot
value is 60 kΩ.
DocID022694 Rev 4 23/33
VND5T050AK-E Application information
32
3.4 Maximum demagnetization energy (V
CC
= 24 V)
Figure 25. Maximum turn-off current versus inductance
1. Values are generated with R
L
=0 Ω.
In case of repetitive pulses, T
jstart
(at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.
C: T
jstart
= 125°C repetitive pulse
A: T
jstart
= 150°C single pulse
B: T
jstart
= 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
V
IN
, I
L
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Package and PCB thermal data VND5T050AK-E
24/33 DocID022694 Rev 4
4 Package and PCB thermal data
4.1 PowerSSO-24 thermal data
Figure 26. PowerSSO-24 PC board
1. Layout condition of R
th
and Z
th
measurements (board finish thickness 1.6 mm +/- 10%; board double layer;
board dimension 77x86; board Material FR4; Cu thickness 0.070mm (front and back side); thermal vias
separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; footprint
dimension 4.1 mm x 6.5 mm).
Figure 27. R
thj-amb
vs PCB copper area in open box free air condition (one channel
ON)
GAPGCFT00418
57+MDPE
57+MDPE
3&%&XKHDWVLQNDUHDFPA
("1($'5
DocID022694 Rev 4 25/33
VND5T050AK-E Package and PCB thermal data
32
Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel ON)
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered
Equation 1: Pulse calculation formula
1
10
100
0.01 0.1 1 10 100 1000
ZTH (°C/W)
Time (s)
Cu=8 cm2
Cu=2 cm2
Cu=foot print
GAPGCFT00634
Z
THδ
R
TH
δZ
THtp
1δ–()+⋅=
where
δt
p
T⁄=
Package and PCB thermal data VND5T050AK-E
26/33 DocID022694 Rev 4
Table 15. Thermal parameters
Area/island (cm
2
)Footprint28
R1 = R7 (°C/W) 0.6
R2 = R8 (°C/W) 0.75
R3 (°C/W) 1
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1 = C7 (W.s/°C) 0.005
C2 = C8 (W.s/°C) 0.01
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.3
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
DocID022694 Rev 4 27/33
VND5T050AK-E Package and packing information
32
5 Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.1 PowerSSO-24 mechanical data
Figure 30. PowerSSO-24 package dimensions
("1($'5
Package and packing information VND5T050AK-E
28/33 DocID022694 Rev 4
Table 16. PowerSSO-24 mechanical data
Symbol Millimeters
Min. Typ. Max.
Θ0º 8º
Θ1 5º 10º
Θ20º
A2.45
A1 0.00 0.10
A2 2.15 2.35
b 0.33 0.51
b1 0.28 0.40 0.48
c 0.23 0.32
c1 0.20 0.20 0.30
D 10.30 BSC
D1 6.50 7.10
D2 3.65
D3 4.30
e 0.80 BSC
E 10.30 BSC
E1 7.50 BSC
E2 4.10 4.70
E3 2.30
E4 2.90
G1 1.20
G2 1.00
G3 0.80
h 0.30 0.40
L 0.55 0.70 0.85
L1 1.40
L2 0.25 BSC
N24
R0.30
R1 0.20
S0.25
Tolerance of form and position
aaa 0.20
Package and packing information VND5T050AK-E
30/33 DocID022694 Rev 4
5.2 PowerSSO-24 packing infor mation
Figure 31. PowerSSO-24 tube shipment (no suffix)
Figure 32. PowerSSO-24 tape and reel shipment (suffix “TR”)
A
CB
All dimensions are in mm.
Base Q.ty 49
Bulk Q.ty 1225
Tube length ( ± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max ) 30.4
Reel dimensions
Tape dimensions
According to Electr onic Indu stries Associatio n
(EIA) Standard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compar tm en t Dep th K (max) 2.85
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Revision history VND5T050AK-E
32/33 DocID022694 Rev 4
7 Revision history
Table 18. Document revision history
Date Revision Changes
07-Feb-2012 1 Initial release.
30-Mar-2012 2
Updated Table 2: Suggested connections for unused and not
co nnected pins
Table 9: Current sense (8 V < V
CC
<36V):
–dK
0
/K
0
: updated tes t cond ition fro m I
OUT
= 100 A to I
OUT
= 100 mA
Table 13: Electrical transient requirements (part 2):
– added not e
18-Sep-20 13 3 Updated disclaime r.
24-Feb-2016 4 Table 4: Thermal data:
–R
thj-case
: updated value
Updated Section 5.1: PowerSSO-24 mechanical data
DocID022694 Rev 4 33/33
VND5T050AK-E
33
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