MC14052BCP - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATA 1

MC14051B MC14052B MC14053B

Analog

Multiplexers/Demultiplexers

The MC14051B, MC14052B, and MC14053B analog multiplexers are

digitally–controlled analog switches. The MC14051B effectively implements

an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a

Triple SPDT. All three devices feature low ON impedance and very low OFF

leakage current. Control of analog signals up to the complete supply voltage

range can be achieved.

•Triple Diode Protection on Control Inputs

•Switch Function is Break Before Make

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Analog Voltage Range (VDD – VEE) = 3.0 to 18 V

Note: VEE must be

VSS

•Linearized Transfer Characteristics

•Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical

•Pin–for–Pin Replacement for CD4051, CD4052, and CD4053

•For 4PDT Switch, See MC14551B

•For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed

CMOS Devices

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VDD

ÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to VEE,

VSS ≥ VEE)

ÎÎÎÎÎÎ

– 0.5 to + 18.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Voltage (DC or Transient)

(Referenced to VSS for Control Inputs and

VEE for Switch I/O)

ÎÎÎÎÎÎ

– 0.5 to VDD + 0.5

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎ

Input Current (DC or Transient),

per Control Pin

ÎÎÎÎÎÎ

± 10

ÎÎÎ

ÎÎÎÎ

Isw

ÎÎÎÎÎÎÎÎÎÎÎ

Switch Through Current

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation. per Package†

ÎÎÎÎÎÎ

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature (8–Second Soldering)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:“P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

MC14051B

8–Channel Analog

Multiplexer/Demultiplexer

MC14052B

Dual 4–Channel Analog

Multiplexer/Demultiplexer

MC14053B

Triple 2–Channel Analog

Multiplexer/Demultiplexer

VDD = PIN 16

VSS = PIN 8

VEE = PIN 7

Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

INHIBIT

CONTROLS

SWITCHES

IN/OUT

COMMON

OUT/IN

CONTROLS

SWITCHES

IN/OUT

COMMONS

OUT/IN

VDD = PIN 16

VSS = PIN 8

VEE = PIN 7

CONTROLS

SWITCHES

IN/OUT

COMMONS

OUT/IN

VDD = PIN 16

VSS = PIN 8

VEE = PIN 7

INHIBIT

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94

MC14051B

MC14052B

MC14053B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎ

VDD

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎ

– 55

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎ

VDD

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ

Power Supply Voltage

Range

ÎÎÎÎ

VDD

ÎÎ

—

ÎÎÎÎÎÎÎ

VDD – 3.0 ≥ VSS ≥ VEE

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎÎ

—

ÎÎÎ

3.0

ÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Quiescent Current Per

Package

ÎÎÎÎ

IDD

ÎÎ

5.0

ÎÎÎÎÎÎÎ

Control Inputs:

Vin = VSS or VDD,

Switch I/O: VEE

VI/O

VDD, and

∆Vswitch

500 mV**

ÎÎÎ

—

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

0.005

0.010

0.015

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎ

150

300

600

ÎÎÎ

µA

ÎÎÎÎÎÎÎÎ

Total Supply Current

(Dynamic Plus

Quiescent, Per Package

ÎÎÎÎ

ID(AV)

ÎÎ

5.0

ÎÎÎÎÎÎÎ

TA = 25

C only (The

channel component,

(Vin – Vout)/Ron, is

not included.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

(0.07 µA/kHz) f + IDD

Typical (0.20 µA/kHz) f + IDD

(0.36 µA/kHz) f + IDD

ÎÎÎ

µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ

Low–Level Input Voltage

ÎÎÎÎ

VIL

ÎÎ

5.0

ÎÎÎÎÎÎÎ

Ron = per spec,

Ioff = per spec

ÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎ

1.5

3.0

4.0

ÎÎÎ

ÎÎÎÎÎÎÎÎ

High–Level Input Voltage

ÎÎÎÎ

VIH

ÎÎ

5.0

ÎÎÎÎÎÎÎ

Ron = per spec,

Ioff = per spec

ÎÎÎ

3.5

7.0

ÎÎÎ

—

ÎÎÎ

3.5

7.0

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

—

ÎÎÎ

3.5

7.0

ÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Input Leakage Current

ÎÎÎÎ

Iin

ÎÎ

ÎÎÎÎÎÎÎ

Vin = 0 or VDD

ÎÎÎ

—

ÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎ

1.0

ÎÎÎ

µA

ÎÎÎÎÎÎÎÎ

Input Capacitance

ÎÎÎÎ

Cin

ÎÎ

—

ÎÎÎÎÎÎÎ

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎ

—

ÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ

Recommended

Peak–to–Peak Voltage

Into or Out of the Switch

ÎÎÎÎ

VI/O

ÎÎ

—

ÎÎÎÎÎÎÎ

Channel On or Off

ÎÎÎ

VDD

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎ

VDD

ÎÎÎ

ÎÎ

VDD

ÎÎÎ

VPP

ÎÎÎÎÎÎÎÎ

Recommended Static or

Dynamic Voltage Across

the Switch** (Figure 5)

ÎÎÎÎ

∆Vswitch

ÎÎ

—

ÎÎÎÎÎÎÎ

Channel On

ÎÎÎ

600

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎ

600

ÎÎÎ

ÎÎ

300

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Output Offset Voltage

ÎÎÎÎ

VOO

ÎÎ

—

ÎÎÎÎÎÎÎ

Vin = 0 V, No Load

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

—

ÎÎÎ

—

ÎÎ

—

ÎÎÎ

µV

ÎÎÎÎÎÎÎÎ

ON Resistance

ÎÎÎÎ

Ron

ÎÎ

5.0

ÎÎÎÎÎÎÎ

∆Vswitch

500 mV**,

Vin = VIL or VIH

(Control), and Vin =

0 to VDD (Switch)

ÎÎÎ

—

ÎÎÎ

800

400

220

ÎÎÎ

—

ÎÎÎÎ

250

120

ÎÎÎ

1050

500

280

ÎÎÎ

—

ÎÎ

1200

520

300

ÎÎÎ

Ω

ÎÎÎÎÎÎÎÎ

∆ON Resistance Between

Any Two Channels in the

Same Package

ÎÎÎÎ

∆Ron

ÎÎ

5.0

ÎÎÎÎÎÎÎ

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

—

ÎÎ

135

ÎÎÎ

Ω

ÎÎÎÎÎÎÎÎ

Off–Channel Leakage

Current (Figure 10)

ÎÎÎÎ

Ioff

ÎÎ

ÎÎÎÎÎÎÎ

Vin = VIL or VIH

(Control) Channel to

Channel or Any One

Channel

ÎÎÎ

—

ÎÎÎ

± 100

ÎÎÎ

—

ÎÎÎÎ

± 0.05

ÎÎÎ

± 100

ÎÎÎ

—

ÎÎ

±1000

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Capacitance, Switch I/O

ÎÎÎÎ

CI/O

ÎÎ

—

ÎÎÎÎÎÎÎ

Inhibit = VDD

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

—

ÎÎÎ

—

ÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Capacitance, Common O/I

ÎÎÎÎ

CO/I

ÎÎ

—

ÎÎÎÎÎÎÎ

Inhibit = VDD

(MC14051B)

(MC14052B)

(MC14053B)

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

—

ÎÎÎ

—

ÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Capacitance, Feedthrough

(Channel Off)

ÎÎÎÎ

CI/O

ÎÎ

—

ÎÎÎÎÎÎÎ

Pins Not Adjacent

Pins Adjacent

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

0.15

0.47

ÎÎÎ

—

ÎÎÎ

—

ÎÎ

—

ÎÎÎ

#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

*For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the

current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum

Ratings are exceeded. (See first page of this data sheet.)

MOTOROLA CMOS LOGIC DATA 3

MC14051B MC14052B MC14053B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25

C) (VEE

VSS unless otherwise indicated)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎÎ

VDD – VEE

Vdc

ÎÎÎÎÎ

Typ #

All Types

ÎÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Times (Figure 6)

Switch Input to Switch Output (RL = 10 kΩ)

MC14051

tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns

tPLH, tPHL = (0.08 ns/pF) CL + 11 ns

tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns

ÎÎÎÎÎ

tPLH, tPHL

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14052

tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns

tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns

tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14053

tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns

tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns

tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

8.0

6.0

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Inhibit to Output (RL = 10 kΩ, VEE = VSS)

Output “1” or “0” to High Impedance, or

High Impedance to “1” or “0” Level

MC14051B

ÎÎÎÎÎ

tPHZ, tPLZ,

tPZH, tPZL

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

350

170

140

ÎÎÎÎÎ

700

340

280

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14052B

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

300

155

125

ÎÎÎÎÎ

600

310

250

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14053B

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

275

140

110

ÎÎÎÎÎ

550

280

220

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Control Input to Output (RL = 10 kΩ, VEE = VSS)

MC14051B

ÎÎÎÎÎ

tPLH, tPHL

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

360

160

120

ÎÎÎÎÎ

720

320

240

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14052B

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

325

130

ÎÎÎÎÎ

650

260

180

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14053B

ÎÎÎÎÎ

5.0

ÎÎÎÎÎ

300

120

ÎÎÎÎÎ

600

240

160

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Second Harmonic Distortion

(RL = 10KΩ, f = 1 kHz) Vin = 5 VPP

ÎÎÎÎÎ

—

ÎÎÎÎÎ

0.07

ÎÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Bandwidth (Figure 7)

(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF

20 Log (Vout/Vin) = – 3 dB)

ÎÎÎÎÎ

—

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Off Channel Feedthrough Attenuation (Figure 7)

RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p

fin = 4.5 MHz — MC14051B

fin = 30 MHz — MC14052B

fin = 55 MHz — MC14053B

ÎÎÎÎÎ

—

ÎÎÎÎÎ

– 50

ÎÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Channel Separation (Figure 8)

(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,

fin = 3.0 MHz

ÎÎÎÎÎ

—

ÎÎÎÎÎ

– 50

ÎÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Crosstalk, Control Input to Common O/I (Figure 9)

(R1 = 1 kΩ, RL = 10 kΩ

Control tTLH = tTHL = 20 ns, Inhibit = VSS)

ÎÎÎÎÎ

—

ÎÎÎÎÎ

—

ÎÎÎ

*The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However ,

precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance

circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs

must be left open.

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

Figure 1. Switch Circuit Schematic

IN/OUT

LEVEL

CONVERTED

CONTROL

VDD

VEE

VDD VDD

VDD OUT/IN

VEE

IN/OUT OUT/IN

CONTROL

TRUTH TABLE

Control Inputs

ON Switches

Inhibit

Select

ON Switches

Inhibit

C* B A MC14051B MC14052B MC14053B

0 0 0 0 X0 Y0 X0 Z0 Y0 X0

0 0 0 1 X1 Y1 X1 Z0 Y0 X1

0 0 1 0 X2 Y2 X2 Z0 Y1 X0

0 0 1 1 X3 Y3 X3 Z0 Y1 X1

0 1 0 0 X4 Z1 Y0 X0

0 1 0 1 X5 Z1 Y0 X1

0 1 1 0 X6 Z1 Y1 X0

0 1 1 1 X7 Z1 Y1 X1

1 x x x None None None

*Not applicable for MC14052

x = Don’t Care

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

16 VDD

8 VSS 7 VEE

13 X

3 Y

BINARY TO 1–OF–4

DECODER WITH

INHIBIT

LEVEL

CONVERTER

INH 6

A 10

B 9

X0 12

X1 14

X2 15

X3 11

Y0 1

Y1 5

Y2 2

Y3 4

BINARY TO 1–OF–2

DECODER WITH

INHIBIT

LEVEL

CONVERTER

16 VDD

8 VSS 7 VEE

14 X

15 Y

4 Z

INH 6

A 11

B 10

C 9

X0 12

X1 13

Y0 2

Y1 1

Z0 5

Z1 3

Figure 2. MC14051B Functional Diagram

INH 6

A 11

B 10

C 9

X0 13

X1 14

X2 15

X3 12

X4 1

X5 5

X6 2

X7 4

8 VSS 7 VEE

16 VDD

3 X

BINARY TO 1–OF–8

DECODER WITH

INHIBIT

LEVEL

CONVERTER

MOTOROLA CMOS LOGIC DATA 5

MC14051B MC14052B MC14053B

TEST CIRCUITS

Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output

Figure 7. Bandwidth and Off–Channel

Feedthrough Attenuation Figure 8. Channel Separation

(Adjacent Channels Used For Setup)

Figure 9. Crosstalk, Control Input to

Common O/I Figure 10. Off Channel Leakage

CONTROL

SECTION

OF IC

SOURCE

ON SWITCH

PULSE

GENERATOR

INH

RLCL

Vout

VDD VEE VEE VDD

INH

VSS

Vin

RLCL = 50 pF

Vout

VDD – VEE

INH

OFF

RLCL = 50 pF

Vout

Vin

VDD – VEE

INH

RLCL = 50 pF

Vout

CONTROL

SECTION

OF IC

OFF CHANNEL UNDER TEST

OTHER

CHANNEL(S)

COMMON

VDD

VEE

VDD

VEE

VDD

NOTE: See also Figures 7 and 8 on Page 6–51.

A, B, and C inputs used to turn ON or OFF

the switch under test.

LOAD

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

Figure 11. Channel Resistance (RON) Test Circuit

VDD

VEE = VSS

10 k

VDD

KEITHLEY 160

DIGITAL

MULTIMETER

1 k

Ω

RANGE X–Y

PLOTTER

TYPICAL RESISTANCE CHARACTERISTICS

Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V

RON, “ON” RESISTANCE (OHMS)

350

300

250

200

150

100

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125

–55

RON, “ON” RESISTANCE (OHMS)

350

300

250

200

150

100

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125

–55

Figure 14. VDD = 2.5 V, VEE = – 2.5 V

RON, “ON” RESISTANCE (OHMS)

700

600

500

400

300

200

100

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125

–55

Figure 15. Comparison at 25°C, VDD = –VEE

RON, “ON” RESISTANCE (OHMS)

350

300

250

200

150

100

–8.0–10 –6.0 –4.0 –2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 25

VDD = 2.5 V

5.0 V 7.5 V

PIN ASSIGMENT

MC14051B MC14052B MC14053B

125

VDD

VSS

VEE

INH

125

VDD

VSS

VEE

INH

125

VDD

VSS

VEE

INH

MOTOROLA CMOS LOGIC DATA 7

MC14051B MC14052B MC14053B

APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter de-

tailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control sig-

nal is used to directly control a 9 Vp–p analog signal.

The digital control logic levels are determined by VDD and

VSS. The VDD voltage is the logic high voltage; the VSS volt-

age is logic low. For the example, VDD = + 5 V = logic high at

the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by VDD

and VEE. The VDD voltage determines the maximum recom-

mended peak above VSS. The VEE voltage determines the

maximum swing below VSS. For the example, VDD – VSS =

5 V maximum swing above VSS; VSS – VEE = 5 V maximum

swing below VSS. The example shows a ± 4.5 V signal which

allows a 1/2 volt margin at each peak. If voltage transients

above VDD and/or below VEE are anticipated on the analog

channels, external diodes (Dx) are recommended as shown

in Figure B. These diodes should be small signal types able

to absorb the maximum anticipated current surges during

clipping.

The

absolute

maximum potential difference between VDD

and VEE is 18.0 V. Most parameters are specified up to 15 V

which is the

recommended

maximum difference between

VDD and VEE.

Balanced supplies are not required. However, VSS must

be greater than or equal to VEE. For example, VDD = + 10 V,

VSS = + 5 V, and VEE – 3 V is acceptable. See the Table

below.

Figure A. Application Example

+5 V –5 V

VDD VSS VEE

9 Vp–p

ANALOG SIGNAL

0–TO–5 V DIGITAL

CONTROL SIGNALS

SWITCH

I/O

INHIBIT,

A, B, C

COMMON

O/I 9 Vp–p

ANALOG SIGNAL

4.5 V

–

4.5 V

GND

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

MC14051B

MC14052B

MC14053B

Figure B. External Germanium or Schottky Clipping Diodes

VDD VDD

VEE VEE

DXDX

ANALOG

I/O COMMON

O/I

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

POSSIBLE SUPPLY CONNECTIONS

ÎÎÎÎ

VDD

In Volts

ÎÎÎÎ

VSS

In Volts

ÎÎÎÎ

VEE

In Volts

ÎÎÎÎÎÎÎ

Control Inputs

Logic High/Logic Low

In Volts

ÎÎÎÎÎÎÎÎÎÎ

Maximum Analog Signal Range

In Volts

ÎÎÎÎ

+ 8

ÎÎÎÎ

– 8

ÎÎÎÎÎÎÎ

+ 8/0

ÎÎÎÎÎÎÎÎÎÎ

+ 8 to – 8 = 16 Vp–p

ÎÎÎÎ

+ 5

ÎÎÎÎ

– 12

ÎÎÎÎÎÎÎ

+ 5/0

ÎÎÎÎÎÎÎÎÎÎ

+ 5 to – 12 = 17 Vp–p

ÎÎÎÎ

+ 5

ÎÎÎÎ

ÎÎÎÎÎÎÎ

+ 5/0

ÎÎÎÎÎÎÎÎÎÎ

+ 5 to 0 = 5 Vp–p

ÎÎÎÎ

+ 5

ÎÎÎÎ

– 5

ÎÎÎÎÎÎÎ

+ 5/0

ÎÎÎÎÎÎÎÎÎÎ

+ 5 to – 5 = 10 Vp–p

ÎÎÎÎ

+ 10

ÎÎÎÎ

+ 5

ÎÎÎÎ

– 5

ÎÎÎÎÎÎÎ

+ 10/ + 5

ÎÎÎÎÎÎÎÎÎÎ

+ 10 to – 5 = 15 Vp–p

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

1 8

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

–T–

SEATING

PLANE

16 PLD

0.25 (0.010) T

16 PLJ

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.93

B0.240 0.295 6.10 7.49

C––– 0.200 ––– 5.08

D0.015 0.020 0.39 0.50

E0.050 BSC 1.27 BSC

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

H0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA 9

MC14051B MC14052B MC14053B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

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MC14051B/D

*MC14051B/D*

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