RF1K49154 Data Sheet October 1999 2A, 60V, 0.130 Ohm, Dual N-Channel, LittleFETTM Power MOSFET 4143.3 Features * 2A, 60V Title This Dual N-Channel power MOSFET is manufactured using F1K the latest manufacturing process technology. This process, 154) which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, bresulting in outstanding performance. It is designed for use t in applications such as switching regulators, switching A, converters, motor drivers, relay drivers, and low voltage bus V, switches. These devices can be operated directly from 30 integrated circuits. m, Formerly developmental type TA49154. al Chan- Ordering Information , LitPART NUMBER PACKAGE BRAND FET RF1K49154 MS-012AA RF1K49154 wer OST) uthor File Number * rDS(ON) = 0.130 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol D1(8) D1(7) S1(1) G1(2) NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4915496. D2(6) D2(5) eyrds terCorratio Dual Packaging Chan, LitFET S2(3) G2(4) JEDEC MS-012AA BRANDING DASH 5 wer OST, S2AA 1 2 3 4 er () OCI O (c)2001 Fairchild Semiconductor Corporation RF1K49154 Rev. A RF1K49154 Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20k, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Drain Current Continuous (Pulse width = 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RF1K49154 60 60 20 UNITS V V V 2 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V, (Figure 12) 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A, (Figure 11) 2 - 4 V VDS = 55V, VGS = 0V - - 1 A Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time - - 250 A VGS = 20V - - 10 A ID = 2A, VGS = 10V, (Figures 9, 10) - - 0.130 VDD = 30V, ID 2A, RL = 15, VGS = 10V, RGS = 25 (Figure 14) - - 50 ns - 10 - ns - 25 - ns td(OFF) - 70 - ns tf - 35 - ns tOFF - - 155 ns - 26 32 nC Fall Time Turn-Off Time Total Gate Charge VDS = 50V, VGS = 0V, TC = 150oC Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Ambient RJA VDD = 48V, ID = 2A, RL = 24 (Figure 14) VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) - 14 17 nC - 0.8 1.0 nC - 340 - pF - 140 - pF - 40 - pF - - 62.5 oC/W MIN TYP MAX UNITS ISD = 2A - - 1.5 V ISD = 2A, dISD/dt = 100A/s - - 62 ns Pulse Width = 1s Device Mounted on FR-4 Material Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time (c)2001 Fairchild Semiconductor Corporation SYMBOL VSD trr TEST CONDITIONS RF1K49154 Rev. A RF1K49154 Typical Performance Curves TA = 25oC, Unless Otherwise Specified 2.5 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 0 2 1.5 1 0.5 0 0 25 50 75 100 125 150 25 50 TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE 5 ZJA, NORMALIZED 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE DUTY CYCLE DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1 THERMAL IMPEDANCE 75 100 125 TA, AMBIENT TEMPERATURE (oC) 0.1 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE ID, DRAIN CURRENT (A) 10 5ms 10ms 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 0.1 1 VDSS (MAX) = 60V 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation 200 IDM, PEAK CURRENT CAPABILITY (A) 100 TJ = MAX RATED TA = 25oC 20 VGS = 20V VGS = 10V TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I 10 1 = I25 150 - TA 125 THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 5. PEAK CURRENT CAPABILITY RF1K49154 Rev. A RF1K49154 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 20 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] VGS = 20V VGS = 9V VGS = 7V VGS = 10V ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 10 5 STARTING TJ = 25oC 15 VGS = 8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 10 VGS = 6V 5 STARTING TJ = 150oC VGS = 5V 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 0 100 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 16 25oC -55oC rDS(ON), ON-STATE RESISTANCE (m) ID(ON), ON-STATE DRAIN CURRENT (A) 20 FIGURE 7. SATURATION CHARACTERISTICS 150oC 12 8 4 500 400 ID = 2A 300 200 100 0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 4 2 10 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 2A VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED ON RESISTANCE ID = 4A ID = 1A 0 2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID = 0.5A 1.5 1 0.5 0 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation 160 1.25 1 0.75 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE RF1K49154 Rev. A RF1K49154 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 500 ID = 250A 400 1.25 C, CAPACITANCE (pF) 1 0.75 CISS 300 COSS 200 100 0.5 -80 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD CRSS 0 -40 0 40 80 160 120 0 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 25 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 60 VDS , DRAIN TO SOURCE VOLTAGE (V) 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 45 7.5 VDD = BVDSS RL = 30 IG(REF) = 0.26mA VGS = 10V 30 5 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 15 2.5 VGS , GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.5 0 0 I G ( REF ) 20 ---------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 ---------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 16. UNCLAMPED ENERGY WAVEFORMS RF1K49154 Rev. A RF1K49154 Test Circuits and Waveforms (Continued) tON tOFF td(ON) VDS td(OFF) tr VDS tf 90% 90% RL VGS + - DUT 10% 10% 0 VDD 90% RGS VGS VGS 0 10% FIGURE 17. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS Qg(10) OR Qg(5) VGS + VDD VGS DUT Ig(REF) VGS = 2V 0 VGS = 1V FOR L2 DEVICES Qg(TH) VGS = 20V VGS = 10V FOR L2 DEVICES VGS = 10V VGS = 5V FOR L2 DEVICES Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 20. GATE CHARGE WAVEFORMS RF1K49154 Rev. A RF1K49154 PSPICE Electrical Model SUBCKT RF1K49154 2 1 3 ; rev 2/2/96 CA 12 8 3.5e-10 CB 15 14 3.7e-10 CIN 6 8 2.26e-10 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - EBREAK 11 7 17 18 63 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 RLDRAIN RSLC1 51 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.4e-9 LSOURCE 3 7 3.1e-10 K1 LGATE LSOURCE 0.131 + 17 EBREAK 18 50 - EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 7.0e-3 RGATE 9 20 1.9 RLDRAIN 2 5 10 RLGATE 1 9 14 RLSOURCE 3 7 3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.6e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B S2A 13 8 14 13 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))} .MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46 + XTI = 5.5) .MODEL DBREAKMOD D (RS = 0.5 IKF = 0.1 N = 1 TRS1 = 3e-3 TRS2 = -5e-5) .MODEL DPLCAPMOD D (CJO = 5.6e-10 IS = 1e-30 N = 10 M = 0.92) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9) .MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 5e-7) .MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4) .MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4) .MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9) .MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6) .MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 2.2e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.1 VOFF= -4) VON = -4 VOFF= -7.1) VON = 0.01 VOFF= 1.9) VON = 1.9 VOFF= 0.01) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. (c)2001 Fairchild Semiconductor Corporation RF1K49154 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM Star* PowerTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM UltraFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H