TMXF33625 - Agere Systems, Inc.

Product Descri ption

February 21, 2003

TMXF33625 Hypermap per

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

1 Introduction

The documentation package for the TMXF33625 Hypermapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 system

chip consists of the following documents:

■The Register Description. This document is available on a password protected website.

■The Hypermapper Product Description (this do cument), the System Design Guide, and the Hypermapper Hardware

Design Guide. These documents are available on the public website shown below.

To contact Agere, please see the last page of this document. To access related documents, please contact your Agere rep-

resentative, or click on the following address: http://www.agere.com/enterprise_metro_access/mappers_muxes.html

Figure 1. Block Diagram and High-Level Interface Definition

(x12)

M13

MUX

FRM (X12)

x28/x21

DS1/J1/E1

(x12)

x28/x21

VTMPR

MRXC

A,B,C,D

DS1/J1/E1

VT/TU

DS3/E3

TPGM

(X4)

X12

x28/x21

DS1/E1

DJA

SPEMPR

(x12)

(0-2)

MCDR

A,B,C,D

MPU

JTAG

LOPOH

DS3/E3

DJA

(x12)

E13

MUX

SPEMPR

x12

(3-5)

System Interfaces

(x24) DS3/E3

(x12) STS-1

(x12) NSMI

(x12) STS-1

(Total of 3 STS-1 Max/

group)

LOPOH

622/ 15 5 Mbi ts/ s SONE T/ SDH

ADM Front End DS3/E3/DS1/E1/DS0 PDH

Tributary Termination

TOAC

POAC

MPU IF

CHI/PSB

Rx/Tx Clocks and Sync

JTAG IF

FRM PLL IF

24 24

DS3XCLK,

E3XCLK

DS1XCLK,

E1XCLK

Power a nd GND pi ns not shown

Mate Interconnect

622/155Mb/s

High-Speed IF

(x12)

092302

Miscellaneous

CDR

CDR STSPP

Clock and Data

Clock/Sync TMUX-A

CDR

CDR STSPP

Clock and Data

Clock/Sync TMUX-B

CDR

CDR STSPP

Clock and Data

Clock/Sync TMUX-C

CDR

CDR STSPP

Clock and Data

Clock/Sync TMUX-D

STS1LT

(x12)

A,B,C,D

From/To

TMUX A,B,C,D

168

144 CHI/PSB

ABCD

TMXF33625 Hypermapper Product Description
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 February 21, 2003
Agere Systems Inc.
Table of Contents
Contents Page
Introduction ........................................................................................................................................................................1
Features  ............ ............. ............. ............. ............. ............. ............. ............ ............. ..........................................................4
1 TMUX and CDR Features (x4)  ....................................................................................................................................4
2 CDR .............................................................................................................................................................................4
3 STS-12 Pointer Processor (STSPP) Features (x4)  .....................................................................................................4
4 STS Cross Connect (STSXC) Features (x4) ...............................................................................................................5
5 Mate Clock and Data Recovery (MCDR) Features (x4)  ..............................................................................................5
6 STS-1 Line Terminating (STS1LT) Features (x12) ......................................................................................................5
7 Synchronous Payload Envelope Mapper (SPEMPR) Features (x24) ..........................................................................5
8 Test Pattern Generator/Monitor (TPG/TPM) Features (x4) .........................................................................................6
9 Virtual Tributary Mapper (VTMPR) Features (x12) ......................................................................................................6
10 M13/E13 MUX Features (x12) ...................................................................................................................................6
10.1 M13 Featu re s .... ....... ...... ....... ...... ....... ................... ....... ...... ................... ....... ...... .............................................6
10.2 E13  Features  ........... ...... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...................................................7
11 DS1/J1/E1 Framing Features (FRM) (12x28/21) .......................................................................................................7
12 STS-1/DS3/E3/DS1/E1/VT/TU Multirate Cross Connect (MRXC) Features (x4)  ......................................................8
13 DS1/E1 Digital Jitter Attenuation (DJA) Features (12x28/21) ....................................................................................8
14 DS3/E3 Digital Jitter Attenuation (DJA) Features (x4) ...............................................................................................8
15 Microprocessor Unit (MPU) Features (x1) .................................................................................................................9
16 JTAG  .........................................................................................................................................................................9
Overview ............................................................................................................................................................................9
Applicati on Dia gr ams .................. ...... ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ... ..............................................10
1 Bidirectional STS-12 Portless TransMUX Application ...............................................................................................10
2 24 Clear Channel DS3/E3 to Dual STS-12/STM-4 Application  .................................................................................11
3 STS-12/STM-4 To/From DS0/E0 Application ............................................................................................................12
4 DS3/E3 TransMUX Application  .................................................................................................................................13
5 Single-Chip OC-12 with MSP 1 + 1 Protection Application  .......................................................................................13
6 Single-Chip Dual OC-3 with MSP 1 + 1 Protection Application .................................................................................14
7 Two Chip Quad OC-3 with MSP 1 + 1 Protection Application ...................................................................................15
Block Description .............................................................................................................................................................16
1 TMUX/Clock and Data Recovery (CDR) Blocks ........................................................................................................16
1.1 Transmit Path Section/Line Overhead ............................................................................................................16
1.2 Receive Path Section/Line Overhead .............................................................................................................16
1.3 Pointer Interpreter ...........................................................................................................................................17
1.4 Path Termination Function ..............................................................................................................................17
2 STS-12/STM-4 Pointer Processor (STSPP) Block ....................................................................................................17
3 STS-1 Line Terminating (STS1LT) Block  ..................................................................................................................17
4 STS Cross Connect (STSXC) Block ..........................................................................................................................17
5 Mate Interconnect and Clock Data Recovery (MCDR) Block ....................................................................................17
6 SPE/AU-3 Mapper (SPEMPR) Block .........................................................................................................................18
7 VT/TU Mapper (VTMPR) Block  .................................................................................................................................18
7.1 Receive Direction ............................................................................................................................................18
7.2 Transmit Direction ...........................................................................................................................................18
8 M13/E13 Multiplexer (M13/E13 MUX) Blocks  ...........................................................................................................19
8.1 M13 MUX ........................................................................................................................................................19
8.2 E13 MUX  ........................................................................................................................................................20
9 Multirate Cross Connect (MRXC) Block  ....................................................................................................................20
10 DS1 Digital Jitter Attenuator (DS1/E1 DJA) Block ...................................................................................................21
11 DS3 Digital Jitter Attenuator (DS3/E3 DJA) Block ...................................................................................................21
12 Test Pattern Generator/Monitor (TPG/TPM) Block ..................................................................................................21
13 Low-Order Path Over Head .....................................................................................................................................21

3Agere Systems Inc. 3
Table of Contents
Product Description TMXF33625 Hypermapper
February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0
5.14 Clock Generator (CG) Block ....................................................................................................................................21
5.15 Framer Block  ...........................................................................................................................................................22
5.15.1 Receive Frame Aligner/Transmit Frame Formatter  ......................................................................................22
5.15.2 Receive Performance Monitor  ......................................................................................................................22
5.15.3 Si gnalin g Proce ssor  ....... ....... ...... ....... ................... ....... ...... ................... ....... .................................................22
5.15.4 Facility Data Link (FDL) Processor ...............................................................................................................23
5.15.5 HD LC Unit ... ...... .................... ...... ....... ................... ....... ...... ................... ....... .................................................23
6 Glossary  ..........................................................................................................................................................................24
Figure Page
Figure  1 . Blo ck Diagr a m and  Hig h - L e ve l  In te r face Defi n iti o n ...... ....... .............. ............. ............. ............... ................................. 1
Figure 2. Translates x12 Bidirectional M13/E13 Mapped STS-1s to/from x12 Bidirectional 
VT-1.5/TU-11/TU-12 Mapped STS-1s....................................................................................................................... 10
Figure 3. 24 Clear Channel DS3/E3 to Dual STS-12/STM-4 Application.................................................................................. 11
Figure 4. STS-12/STM-4 to/from 8064 DS0s/E0s Configuration .............................................................................................. 12
Figure 5. x12 Channelized DS3s/E3s from/to x12 VT-Mapped STS-1s ................................................................................... 13
Figure 6. Single-Chip OC-12 with MSP 1 + 1 Protection Application........................................................................................ 13
Figure  7 . Sin g l e - Ch i p  Du a l  OC - 3  wit h  MSP 1  + 1 Prot e ction Application.. ............. .............. ............. .............. ......................... 14
Figure 8. Two Chip Quad OC-3 with MSP 1 + 1 Protection Application ................................................................................... 15

44 Agere Systems Inc.

Product Description

February 21, 2003

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

2 Feat ures

■Versatile IC supports SONET/SDH 622.08/

155.52 Mbits/s interface solutions for DS3/E3 and DS0/

J0/E0 applications.

■Terminates up to 336 DS1/J1 or 252 E1 using the NSMI

or as DS0/J0/E0 using the CHI or PSB system interface.

■Terminates up to 24 DS3/E3 channelized or

unchannelized signals with grooming for channelized

DS3/E3.

■Terminated DS3/E3 and DS1/J1/E1 signals may be flexi-

bly mapped into the SONET/SDH interface using all

allowed MUXing structures.

■Supports 1:1 and 1 + 1 protection schemes with dedi-

cated interfaces.

■3.3 V I/O, 1.5 V CORE, and –40 °C to +85 °C tempera-

ture range allows for uncontrolled or convection cooled

environments. Maximum power estimated to be 6 W.

■Built-in clock and data recovery circuits with optional

input for forward clocking of STS-3 input.

■Full SONET/SDH compliant alarm reporting.

■Supports full processing for all line/section/path over-

head with inhibitable automatic generation of AIS, RDI,

REI, and N times filtering on critical overhead.

■Allows extraction/insertion of DCC-L, DCC-S, or up to

20 Mbits/s using specified overhead bytes for the data

communications channel.

■Provides full high-speed pointer processing and synchro-

nization of the 8 kHz frame/2 kHz superframe to the sys-

tem timing.

■Loopbacks, manual error insertion, internal pattern

generator/monitor, and internal cross connects simplify

debugging and diagnostics.

■Standard 1152-pin ball grid array (PBGA).

■Complies with all appropriate Telcordia®, ITU, ANSI ®,

ETSI, and Japanese TTC standards as noted.

2.1 TMUX and CDR Features (x4)

■Multiplexes/demultiplexes twelve STS-1 signals or four

STS-3c signals to/from a SONET STS-12 signal.

■Multiplexes three STS-1 signals into a SONET

STS-3 signal.

■Multiplexes/demultiplexes four STM-1 (AU-4 or 3xAU-3)

signals to/from an SDH STM-4 signal.

■Multiplexes/demultiplexes three VC-3 signals to/from an

SDH STM-1 (3xA U-3) signal.

■Multiplexes/demultiplexes three VC -3 signals to/from an

SDH STM-1 (AU-4) signal via a TUG-3 construction.

■Provides STS-1-only mode for receive and transmit

directions.

■Provides separate protection input for support of 1:1

and 1 + 1.

■Provides SONET/SDH loss-of-signal (LOS), out-of-frame

(OOF), loss-of-frame (LOF), and loss-of-clock (LOC)

detection.

■Provides STS-12/STM-4/STS-3/STM-1/STS-1 selectable

scrambler/descrambler functions.

■Provides B1/B2/B3 generation/detection for STS-12/

STM-4/STS-3/STM-1/STS-1.

■Provides STS-12/STM-4/STS-3/STM-1/STS-1 pointer

interpretation.

■Complies with GR-253-CORE, T1.105, G.707, G.783,

G.806, G.821, and ETSI 417-1-1.

2.2 CDR

■Receives data at STS-12/STM-4 (622.08 Mbits/s) or

STS-3/ST M -1 (155.52 MHz ) data rate.

■155.52 MHz/622.08 MHz ± 20 ppm input reference clock

for on-chip PLL.

■On-chip PLL for clock synthesis, that requires only one

external resistor , generates 16 phases, and provides res-

olution of approximately 200 ps.

■PLL bypass mode for functional test.

■Meets type B jitter tolerance specification of ITU-T

recommendation G.783.

■No output clock drift in absence of data transitions once

lock is acquired.

2.3 STS-12 Pointer Processor (STSPP)

Feature s (x4)

■SONET and SDH compliant.

■Configurable STS-3/STM-1 or STS-12/STM-4 mode.

■Supports an arbitrary mix of STS-1 and STS-3c

tributaries, and SDH equivalents for passthrough from

receiver to transmitter.

■Supports STS-n add/drop capability.

■Complies with GR-253-CORE, T1.105, G.707, G.783,

G.806, G.821, and ETSI 417-1-1.

Agere Systems Inc. 5

Product Description

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

2 Feat ures (continued)

2.4 STS Cross Connect (STSXC) Features (x4)

■Internal clocks and controls are user transparent.

■30 x 30 STS-1 strictly nonblocking cross connect.

■The following STSXC outputs may be sourced from the

subsequent list of inputs without restriction per

STS-1/STM-0. (Must be between blocks of the same par-

tition, i.e., A, B, C, or D.)

2.5 Mate Clock and Dat a Recovery (MCDR)

Features (x4)

■Provides glueless capability to connect partitions (A, B,

C, D) of the Hypermapper device.

■Loss-of-clock detection from the three external

155.52 MHz clock inputs.

■Loss- of -frame (LOF ), out-of-frame (OOF), and B2 error

detection on the three 155.52 Mbits/s interfaces. Also

RDI and REI monitoring and generation is available.

■Manual B2 error insertion for debugging.

2.6 STS-1 Line Terminating (STS1LT)

Features (x12)

■Supports standard SPE mappings for sub-STS-1 pay-

loads (VT-mapped: 28 DS1, 28 J1, or 21 E1 signals).

■Supports standard SPE mappings for STS-1 payloads

(DS3/E3).

■Detects STS-1 loss-of-signal (LOS), out-of-frame (OOF),

loss-of-frame (LOF), AIS-P, and LOP conditions.

■Provides STS-1 selectable scrambler/descrambler func-

tions and B1/B2/B3 generation/detection.

■Provides STS-1 pointer interpretation/processing.

■Complies with GR-253-CORE, T1.105, G.707, G.783,

G.826, G.821, and ETSI 417-1-1.

2.7 Synchrono us Paylo ad Enve lo pe Map per

(SPEMPR) Features (x24)

■The SPE mapper accepts/delivers TUG-2 data from/to

the VT mapper. The TUG-2 data is mapped/demapped

either to/from an AU-3/STS-1 signal for the North Ameri-

can digital systems or to/from a TUG-3 signal for the ITU-

based systems. Only available for SPEMPR 0—2.

■The SPE mapper accepts/delivers channelized DS3 data

from/to the M13 MUX/deMUX. The DS3 data is mapped/

demapped either to/from an AU-3/STS-1 signal for the

North American digital systems or to/from a TUG-3 signal

for the ITU-based systems. Only available for SPEMPR

3—5.

■The SPE mapper accepts/delivers channelized or

unchannelized DS3 signals at a 44.736 Mbits/s rate from

external I/O. The DS3 signals are mapped/demapped

the same way as the M13 signal described above.

■The SPE mapper accepts/delivers channelized E3 data

from/to the E13 MUX/deMUX. The E3 data is mapped/

demapped either to/from an AU-3/STS-1 signal for the

North American digital systems or to/from a TUG-3 signal

for the ITU-based systems. Only available for SPEMPR

3—5.

■The SPE mapper accepts/delivers channelized or

unchannelized E3 signals at a 34.368 Mbits/s rate from

external I/O. These E3 signals are mapped/demapped

the same way as the E13 signal described above.

■The SPE mapper has a DS3/E3 loopback circuit placed

to demap and remap a DS3/E3 signal. It is particularly

useful in cases where a DS3/E3 signal, mapped as an

AU-3/STS-1 signal, requires remapping as a TUG-3 sig-

nal or vice versa.

■The SPE mapper supports a path overhead access

channel (POAC). Seven path overhead bytes (J1, C2,

F2, H4, F3, K3, and N1) can be inserted/dropped through

this channel. This channel works as the master , meaning

it provides a clock in both the transmit and receive direc-

tions and POH data can be inserted on the transmit side

or dropped on the receive side.

■Path overhead byte B3 (BIP error) generation/detection

and programmable BIP-8 bit error rate insertion.

■Signal fail and signal degrade indicators available to

report bit error rates above standard provisionable

thresholds.

Number of STS-1s Output Block

12 TMUX

6SPEMPR

3 STS1LT or STS1LT PP

9 Mate CDR (from TMUX only)

Number of STS-1s Input Block

12 TMUX or STS-12PP

6SPEMPR

3STS1LT

9 Mate CDR (to TMUX only)

66 Agere Systems Inc.

Product Description

February 21, 2003

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

2 Feat ures (continued)

■Capable of detecting/inserting AIS, RDI, and REI.

■Monitori ng is prov id ed on all the TU G-3 path overhea d

bytes.

■N1 tandem connection support is provided.

■TUG-3 pointer processor supports add/drop multiplexing.

■Complies with GR-253-CORE, T1.105, ITU-T G.707,

ITU-T G.831, G.7 83, and ETS 300 417- 1-1.

2.8 Test Pattern Generator/Monitor (TPG/TPM)

Features (x4)

■Configurable test pattern generator: DS1, E1 and DS3,

E3, or STS-1 formats.

■Provisionable test pattern data from the following

options: quasirandom signal source (QRSS), pseudoran-

dom bit stream length of 215 –1 (PRBS15 ), PRBS20,

PRBS23, alternating 1 and 0 (AL T_01), ALL_ONES, user

pattern (16 bits, repeating).

■The DS1 and E1 test patterns can be transmitted either

unframed or as the payload of a framed signal as defined

in ITU-T (DS3, E3, or STS-1 unframed only).

■Under register control, single bit or framing (DS1/E1

only) errors can be injected into any test pattern.

■Any sink or receiving channel can be replaced by a test

pattern monitor, which can detect and count bit errors or

misconfigurations, and/or detect idle conditions or AIS.

■Datalink (DS1-ESF DL) and SSM (E1 multiframe Sa)

fields read/writable.

■Supports all Hypermapper modes of operation.

■Complies with T1.107, T1.231, T1.403, G.703, G.704,

and O.150.

2.9 Virtual Tributary Mapper (VTMPR)

Features (x12)

■Maps DS1/J1/E1 into VT/TU structures:

—DS1 into VT1.5/TU-11/TU-12.

—J1 into VT1.5/TU-11/TU-12.

—E1 into VT2/TU-12.

■Maps VC-11/VC-12 into VTG/TUG-2 structures:

—V C-11 into VT1.5/TU-11/TU-12/VTG/TUG-2.

—VC-12 into VT2/TU-12/VTG/TUG-2.

■Synchronizes VT/TU SPE to system-shelf-timing

reference by setting the transmit VT/TU pointers to fixed

values for asynchronous mapping or by dynamically

changing the transmit VT/TU pointers for byte

synchronous mapping.

■Supports asynchronous, byte synchronous, and bit

synchronous mappings.

■Supports automatic generation or microprocessor

overwrite of one bit RDI-V or enhanced RDI-V, and one

bit RFI-V.

■Supports ADM applications with tributary loopback and

tributary pointer processing.

■Provides a low-order path overhead access channel.

■Supports TIM-V generation and termination for all 28/21

VT/TU signals.

■Supports BIP-V BER insertion and detection.

■Supports fast AIS generation for downstream devices.

■Supports a one second error counter for BIP-V and

REI-V.

■Allows grooming of VTs/TUs in granularity of TUG-2s

within the STS-3/STM-1 signal.

■Configurable VT/TU slot selection for DS1, E1, and J1

insertion and drop.

■Automatic receive monitor functions include VT/TU

RDI-V, REI-V, BIP-2 errors, AIS-V, and LOP-V.

■Supports all Hypermapper modes of operation.

■Complies with O.150, T1.105, T1.107, T1.231, T1.403,

G.703, G.704, G.707, G.783, GR-253-CORE, GR-499,

JT-G707, and ETS 300 417-1-1.

2.10 M13/E13 MUX Features (x12)

2.10.1 M13 Features

■Configurable multiplexer/demultiplexer for 28 DS1 sig-

nals or 21 E1 signals to/from a DS3 signal.

■Operates in either M23 or C-bit parity mode.

■Provisionable time-slot selection for DS1 and E1

insertion or drop.

■Full alarm monitoring and generation (LOS, BPV, EXZ,

OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit parity errors,

and FEBE).

Agere Systems Inc. 7

Product Description TMXF33625 Hypermapper

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

2 Feat ures (continued)

■DS3 forced loopback and DS1 and E1 forced loopback

and loopback request generation.

■Complies with T1.102, T1.107, T1.231, T1.403, T1.404,

GR 499, G.747, and G.775.

2.10.2 E13 Features

■Configurable multiplexer/demultiplexer for up to 16 E1

signals to/from an E3 signal.

■Provisionable time-slot selection for E1 insertion or drop

via the multirate cross connect functional block.

■E13 multiplexers capable of generating alarm indication

signal (AIS) and remote alarm indicator (RAI) signals.

■Configurable HDB3 encoder/decoder for E3 output/input.

■E1 transmit path monitors that detect loss-of-clock (LOC)

and AIS.

■E3 receive monitor that detects loss-of-signal (LOS),

LOC, bipolar violation (BPV), AIS, and RAI.

■E3 and E2 loopback modes.

■Complies with ITU G.703, G.742, G.751, and G.775.

2.11 DS1/J1/E1 Framing Features (FRM)

(12x28/21)

■28/21 DS1/J1/E1 channels.

■DS1 framing modes: ESF, D4, SLC ®-96, T1 DM DDS,

and SF (Ft only).

■E1 framing modes: G.704 basic and CRC-4 multiframe

consistent with G.706.

■J1 framing modes: JESF (Japan).

■DS1 signaling modes: transparent; register and system

access for ESF 2-state, 4-state, and 16-state; D4 2-state,

4-state, and 16-state; SLC-96 2-state, 4-state, and

16-state; J-ESF handling groups maintenance and

signaling; VT 1.5 SPE 2-state, 4-state, 16-state.

■E1 signaling modes: transparent; register and system

access for entire TS16 multiframe structure as per ITU

G.732.

■Signaling debounce and change of state interrupt.

■V5 .2 Sa7 processing.

■Alarm reporting and performance monitoring per AT&T ®,

ANSI, ITU-T, and ETSI standards.

■Facility data link features:

—HDLC or transparent access for either ESF or

DDS + FDL frame formats.

—Register/st ack access for SLC-96 transmit and receive

data.

—Extended superframe (ESF): automatic transmission

of the ESF performance report messages (PRM).

Automatic transmission of the ANSI T1.403 ESF per-

formance report messages. Automatic detection and

transmission of the ANSI T1.403 ESF FDL bit-oriented

codes.

—Register/stack access for all CEPT Sa bits transmit

and receive data.

■HDLC features:

—HDLC or transparent mode.

—Programmable logical channel assignment: any time-

slot, any bit for ISDN D channel, also inserts/extracts

C-channels for V5.1, V5.2 interfaces.

—64 logical channels in both transmit and receive direc-

tion (any framing format).

—Maximum channel data rate is 64 kbits/s.

—Minimum channel data rate is 4 kbits/s (DS1/FDL or

E1 Sa bit).

—128-byte FIFO per channel in both transmit and

receive directions.

—Tx to Rx loopback supported.

■System inte r faces :

—Concentration hig hway interfa ce :

! Single clock and frame synchronizing signals;

programmable clock and data rates at 8.192 MHz

and 16.384 MHz; programmable clock edges and

bit/byte offsets.

—Parallel system bus interface at 19.44 MHz for data

and signal ing : sing le cl oc k and frame sync hr on iz in g

signals.

—Network serial multiplexed interface (NSMI) minimal

pin count serial inte rface at 51.84 MHz optimized for

data and IMA applications.

TMXF33625 Hypermapper Product Description

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 February 21, 2003

88 Agere Systems Inc.

2 Feat ures (continued)

2.12 STS-1/DS3/E3/DS1/E1/VT/TU Multirate

Cross Connec t (MRXC)

Features (x4)

■Configurable cross point interconnect for up to 84/63

DS1/E1 signals to/from the FRM, VTMPR, M13/E13,

TPG/TPM, and DS1/E1 DJA.

■Connects three DS3/E3 signals from the external pins to

the M13/E13 MUX. Connects six DS3/E3 signals

between the external pins and DS3/E3 DJA, SPEMPR,

and three STS-1 signals from external pins to the

STS1LT.

■Also connects three external NSMI interfaces to the

SPEMPR, M13/E13, or FRM functional blocks.

■Three NSMI ports are shared with three STS-1 line termi-

nations.

■Provides grooming capability for up to 168 (84 receive

plus 84 transmit) DS1/E1 connections between the FRM,

VTMPR, M13/E13, and DS1/E1 DJA. This allows for

cross connect grooming of any block signal port n to any

other signa l por t m on a different block, or on the same

block in the case of a groomed loopback.

■Multicast operation (one to many) is supported for 168

sources and destinations.

■Multirate cross connect allows 16 x 3 E1 signals to/from

E13 modules from/to the framer, VT mapper, and

TPG/TPM.

■There are three E3 signals from/to the E13 functional

block to/from external pins and the SPE mapper.

■Jitter attenuation can also be inserted in-line on any

DS3/E3 or DS1/E1 channel. (Note that cascading of jitter

attenuators is not allowed.)

■Standard network loopback or straight-away facility

testing is supported for DS1/E1 and DS3/E3. A test-

pattern generator capable of injecting idle standards-

based, pseudorandom bit sequence test patterns, or AIS

(blue) alarm can replace any source or transmitter. A

test-pattern monitor that can detect/count bit errors in a

pseudorandom test sequence, or loss of frame or

synchronization, can replace any sink or receiver.

■One to any number of loopbacks are supported for up to

84/63 channels in DS1/E1 channels from the VT mapper ,

M13/E13, and framer functional blocks. One-to-one

loopback is supported in all DS1/E1 channels. One-to-

one loopback is supported for DS3/E3 channels from the

M13/E13, and SPE mapper functional blocks.

■Loopbacks can be configured to sectionalize a circuit for

identifying faults or misconfiguration during out of service

maintenance.

■Fast alarm channels are supported for VT mapper, E13,

and M13 to framer interconnects for alarm indication

signal (AIS or blue alarm) and VT mapper only for remote

alarm indicator (RAI or yellow alarm). This feature

reduces the propagation delay of the alarms by

eliminating multiple integration of alarm conditions.

2.13 DS1/E1 Digital Jitter Attenuation (DJA)

Features (12x28/21)

■The PLL bandwidth, damping factor, and sampling rates

are programmable.

■Configurable to meet jitter and MTIE requirements.

■Supports one DJA per each DS1/E1. (Note that the DJA

may not be cascaded.) 28/21 DJAs per block.

2.14 DS3/E3 Digital Jitter Attenuation (DJA)

Features (x4)

■The PLL bandwidth, damping factor, and sampling rates

are programmable.

■The DJA functional block accepts/delivers DS3/E3 clock

and data from/to the multirate cross connect functional

block.

■Supports one DJA per each DS3/E3. (Note that the DJA

may not be cascaded.) Six DJAs per block.

Agere Systems Inc. 9

Product Description

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

2 Feat ures (continued)

2.15 Microproc essor Unit (MPU) Features (x1)

■21-bit address/16-bit data bus microprocessor interface

(little end ian ).

■Synchronous (16 MHz to 66 MHz)/asynchronous

microprocessor interface modes.

■Microprocessor data bus parity monitoring.

■Summary of two level priority interrupts from major

functional blocks (maskable).

■Separate device interrupt outputs for automatic

protection switch and the Hypermapper global interrupts.

■Global configuration of network performance monitoring

counters operation.

■Global software resets.

■Global enabling and powerdown of major functional

blocks.

■Registers provisionable for clear on read/clear on write.

■Compatible with most industry-standard processors.

2.16 JTAG

■IEEE ® 1149.1 JTAG boundary scan.

3 Overvi ew

The SONET/SDH Hypermapper device integrates the

SONET/SDH section, line, path, and tributary termination

functions with M13/E13 multiplex functions and the primary

rate framing function. It interfaces to multiple OC-3/STM-1

optical signals or to an OC-12/STM-4 for terminal or add/

drop applications.

The SONET/SDH Hypermapper device provides a versatile

interface for STS-12/STM-4, STS-3/STM-1, and STS-1/

STM-0 termination applications for point-to-point scenarios

and ring applications.

Mapping flexibility allows for software upgrades from M13/

E13 mapped connections to VT/TU mapped connections.

A single Hypermapper is capable of processing the

aggregate bandwidth of one STS-12/STM-4 to 12

transMUXed DS3/E3s. Further, a single device can

process the aggregate bandwidth of two STS-12/STSM-4s

terminated to 24 clear-channel DS3/E3s. Additionally, a

single Hyp ermapper can functi on as an STS-12/STS- 3/

STM-4/STM-1 add/drop MUX by terminating up to 12

STS-1/STM-0 channels or four AU-4 channels and by

using the internal pointer processors to forward any

nonterminating channels. Hypermapper can terminate all

8064 DS0/E0s from an STS-12/STM-4 and is ideal for

other applications including dual STS-12/STM-4 portless

transMUX, dual STS-3/STM-1 with MSP 1 + 1 protection,

and single-chip STS-12/STM-4 MSP 1 + 1 applications,

among others .

TMXF33625 Hypermapper Product Description

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 February 21, 2003

1010 Agere Systems Inc.

4 Application Diagrams

This section shows several typical Hypermapper applications. Figure 2 through Figure 8 depict system-level diagrams.

4.1 Bidirectional STS-12 Portless TransMUX App lication

■Each of two STS-12s consist of x6 VT/TU-mapped STS-1s, and x6 M13/E13-mapped STS-1s.

■Hypermapper will bidirectionally transMUX between DS1-mapped DS3s and VT -mapped STS-1s.

■STS-12 interface to backplane is 622 Mbits/s LVDS with integrated CDR.

■Eight local glueless board-level signal connections required as shown in Figure 2.

■Provides PMON and FDL to all 336/252 bidirectional DS1s/E1s.

■Provides DS3 PMON and FEAC for all 12 bidirectional DS3s.

■Provides high-order section/line/path overhead termination and insertion for 24 STS-1s.

Figure 2. Translates x12 Bidirectional M13/E13 Mapped STS-1s to/from

x12 Bidirectional VT-1.5/TU-11/TU-12 Mapped STS-1s

CLK GEN

TSWC01622

REF CLK

HYPERMAPPER

CROSS CONNECT

x6 VT-1.5 /TU-11/TU-1 2

MAPPED STS- 1

STS-12 INTERFACE

x3 STS-1

BACKPLANE

WITH STS -1

x6 M13/E13

MAPPED ST S-1

STS-12/STM-4

x6 VT-1.5 /TU-11/TU-1 2

MAPPED STS- 1

x6 M13/E13

MAPPED ST S-1

STS-12/STM-4

INTERFACE

STS-3 INTERFACE

STS-12 INTERFACE

STS-3 INTERFACE x3 STS-1

Agere Systems Inc. 11

Product Description TMXF33625 Hypermapper

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

4 Application Diagrams (continued)

4.2 24 Clear Channel DS3/E3 to Dual STS-12/STM-4 Application

■Two STS-12/STM-4 signals will be input to the high-speed interfaces of the device and deMUXed to 24 DS3s/E3s.

■Similarly, 24 DS3s/E3s are input from LIUs and MUXed to two STS-12s/STM-4s.

■STS-12 interface to backplane is 622 Mbits/s LVDS with integrated CDR.

■Eight local glueless board-level signal connections required.

■Provides DS3 PMON and FEAC for all 24 bidirectional DS3s.

■Provides high-order section/line/path overhead termination and insertion for 24 STS-1s.

Figure 3. 24 Clear Channel DS3/E3 to Dual STS-12/STM-4 Application

HYPERMAPPER

STS-12 INTERFACE

OC-12/STM-4o STS-12/STM-4e

STS-12 INTERFACE

DS3/E3

OC-12/STM-4o STS-12/STM-4e

CLK GEN

TSWC01622

REF CLK

DS3/E3 LIU

OC-12

TRANSCEIVER

OC-12

TRANSCEIVER

TMXF33625 Hypermapper Product Description

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 February 21, 2003

1212 Agere Systems Inc.

4 Application Diagrams (continued)

4.3 STS-12/STM-4 To/From DS0/E0 Application

■8064 DS0s/E0s are input from a switch and MUXed to STS-12/STM-4 level.

■Similarly, an STS-12/STM-4 is input to the high-speed interface of the device and deMUXed to 8064 DS0s/E0s.

■STS-12 interface to backplane is 622 Mbits/s LVDS with integrated CDR.

■Six local glueless board-level signal connections required.

■The system interface can be CHI (concentrated highway interface) or PSB (parallel system bus):

—CHI can be programmed to operate at 8.192 MHz, or 16.384 MHz clock and data rates.

—The PSB interface consists of a 16-bit wide parallel bus operating at 19.44 Mbits/s.

■Provides high-order section/line/path overhead termination and insertion for 24 STS-1s.

■The internal block diagram for this application assumes the STS-12/STM-4 is mapped with the VT/TU signal structure

(though DS3/E3 mapping is also possible).

Figure 4. STS-12/STM-4 to/from 8064 DS0s/E0s Configuration

HYPERMAPPER

STS-12/STM-4e

SYSTEM INTERFACE

(CHI OR PSB)

STSI-144

DS0/E0

SWITCH

(xN)

CLK GEN

TSWC01622

REF CLK

OC-12/STM-4o

OC-12

TRANSCEIVER

Agere Systems Inc. 13

Product Description TMXF33625 Hypermapper

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

4 Application Diagrams (continued)

4.4 DS3/E3 TransMUX Application

■12 DS3s/E3s are input from LIUs and MUXed to an STS-12/STM-4 level.

■Similarly, an STS-12/STM-4 is input to the high-speed interface of the master device and deMUXed to 12 DS3s/E3s.

■Hypermapper will bidirectionally transMUX between DS1-mapped DS3s and VT -mapped STS-1s.

■STS-12 interface to backplane is 622 Mbits/s LVDS with integrated CDR.

■Six local glueless board-level signal connections required.

■Optional connection to internal framer blocks to provide PMON for all 336/252/144 bidirectional DS1s/E1s.

■Provides high-order section/line/path overhead termination and insertion for 24 STS-1s.

Figure 5. x12 Channelized DS3s/E3s from/to x12 VT-Mapped STS-1s

4.5 Single-Chip OC-12 with MSP 1 + 1 Protection Application

■An STS-12/STM-4 signal is input to the high-speed interface of the device and deMUXed to DS3s/E3s and/or

STS-1/EC-1 and/or DS0/E0 level.

■Similarly, multiple STS-1s/EC-1s and/or DS3s/E3s and/or DS0s/E0s can be input to the device and MUXed to an

STS-12/STM-4 signal.

■One TMUX sub-block (A, B, C, or D) provides the interface to the working line while another provides the interface to the

protection line. MSP 1 + 1 achieved via external connection between these two TMUX subblocks.

■STS-12 (working and protect) interfaces to backplane are 622 Mbits/s LVDS with integrated CDR.

■Eight local glueless board-level signal connections required.

■Number of possible DS0s/E0s, DS3s/E3s, and STS-1s/EC-1s dependent on application (mapping type and signal path

through the device).

Figure 6. Single-Chip OC-12 with MSP 1 + 1 Protection Application

HYPERMAPPER

STS-12 INTERFACE

OC-12/STM-4o STS-12/STM-4e DS3/E3

CLK GEN

TSWC01622

REF CLK

OC-12

TRANSCEIVER

DS3/E3 LIU

HYPERMAPPER

STS-12 INTERFACE

OC-12/STM-4o STS-12/STM-4e

WORKING

STS-12 INTERFACE

STS-1/EC-1

OC-12/STM-4o STS-12/STM-4e

PROTECTION

DS3/E3

DS0/E0

(VIA CHI OR PSB)

CLK GEN

TSWC01622

REF CLK

OC-12

TRANSCEIVER

OC-12

TRANSCEIVER

TMXF33625 Hypermapper Product Description

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 February 21, 2003

1414 Agere Systems Inc.

4 Application Diagrams (continued)

4.6 Single-Chip Dual OC-3 with MSP 1 + 1 Protection Application

■Two STS-3/STM-1 signals are input to the high-speed interfaces of the device. Both signals are replicated and sent into

the two other dedicated high-speed interfaces as protection lines.

■The dual STS-3s/STM-1s can be deMUXed to STS-1s/STM-0s, DS3s/E3s, and/or DS0s/E0s. Termination dependent on

application desired.

■Similarly, a mix of STS-1s/STM-0s, DS3s/E3s, and/or DS0s/E0s can be MUXed to STS-3/STM-1 level (to two separate

STS-3s/STM-1s).

■Two internal TMUX blocks provide the interface to the receive/transmit protection links.

■The device is effectively split in half: one half is dedicated to working/protect STS-3/STM-1 #1, while the other is

dedicated to STS-3/STM-1 #2.

Figure 7. Single-Chip Dual OC-3 with MSP 1 + 1 Protection Application

HYPERMAPPER

STS-3 INTERFACE

OC-3/STM-1o STS-3/STM-1e

WORKING 1

STS-3 INTERFACE

STS-1/STM-0

OC-3/STM-1o STS-3/STM-1e

PROTECTION 1

DS3/E3

DS0/E0

(VIA CHI OR PSB)

STS-3 INTERFACE

OC-3/STM-1o STS-3/STM-1e

WORKING 2

STS-3 INTERFACE

STS-1/STM-0

OC-3/STM-1o STS-3/STM-1e

PROTECTION 2

DS3/E3

DS0/E0

(VIA CHI OR PSB)

CLK GEN

TSWC01622

REF CLK

OC-3

TRANSCEIVER

OC-3

TRANSCEIVER

OC-3

TRANSCEIVER

OC-3

TRANSCEIVER

Agere Systems Inc. 15

Product Description TMXF33625 Hypermapper

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

4 Application Diagrams (continued)

4.7 Two Chip Quad OC-3 with M SP 1 + 1 Protection Application

■Two Hypermappers can be interconnected for a quad STS-3/STM-1 MSP 1 + 1 protection solution.

■One device is used to interface with x4 STS-3/STM-1 working lines while the other is used as an interface for the

protection lines associated with the four working STS-3s/STM-1s.

■A mixture of STS-1s/STM-0s, DS3s/E3s, and/or DS0s/E0s can be terminated from each STS-3/STM-1.

■Similarly, a mixture of STS-1s/STM-0s, DS3s/E3s, and/or DS0s/E0s can be MUXed to STS-3/STM-1 level (four separate

STS-3s/STM-1s).

■Half of the CHI interfaces (for DS0/E0 applications) are used to provide redundant I/O to a protection switch fabric. Side

select for the switch fabric and multicast to the redundant CHI interfaces is done in the Hypermapper’s multirate cross

connect (MRXC) blocks.

■CHI interfaces (for DS0/E0 applications) will run at either 8.192 Mbits/s or 16.384 Mbits/s depending on exact application.

■External selector switches will serve to broadcast the transmit direction STS-1s/STM-0 and/or DS3s/E3s to both devices

while also serving to choose between STS-1s/STM-0s and/or DS3s/E3s from either the working or protect device.

Figure 8. Two Chip Quad OC-3 with MSP 1 + 1 Protection Application

HYPERMAPPER

WORKING

STS-1/EC-1

DS3/E3

DS0/E0 VIA CHI

(WORKING)

DEVICE 1

STS-3/STM-1

HYPERMAPPER

PROTECTION (PROTECTION)

DEVICE 2

STS-3/STM-1

SWITCH FABRIC

(SIDE 1)

STSI-144 (x3)

SWITCH FABRIC

(SIDE 2)

STSI-144 (x3)

DS0/E0 VIA CHI

x4 STS-3/S T M-1

CLK GEN

TSWC01622

REF CLK

TMXF33625 Hypermapper Product Description

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 February 21, 2003

1616 Agere Systems Inc.

5 Block Description

5.1 TMUX/Clock and Data Recovery (CDR)

Blocks

The TMUX and CDR blocks (four per device) provide the

high-speed interfaces to the SONET/SDH line and

terminate the section and line signals. Several features are

incorporated in these blocks to allow for a variety of system

applications. First, a redundant interface is provided with

the appropriate selectors and bridges to allow easy

implementation of 1:1, 1 + 1, or ring protection schemes.

Second, a separate interface is provided for access to

selected overhead bytes. In SONET applications, the

section DCC-S may be added/dropped at 192 kbits/s, while

SDH applications may use the same I/O for adding/

dropping the DCC-L at 576 kbits/s. Alternately, any bytes in

the entire overhead may be added/dropped. A third feature

of these blocks is that they can operate at both

622.08 Mbits/s or 155.52 Mbits/s, where the 155.52 Mbits/s

mode may use a clock forwarded from the external PHY

device. In this mode, both the receive and transmit

directions of the device may operate asynchronously . In the

622 Mbits/s mode, a CDR is provided for ease of retiming

the data signal. The fourth and final function of these blocks

is to terminate/generate the section, line, and path

overhead (only for the SONET/SDH STS-12/3 or STM-4/1

signals). Automatic generation of AIS/RDI/REI is possible

since the protection path is available on the device.

Additionally, N times filtering is provided for critical bytes

such as K1/K2. All variations in overhead processing

between SONET and SDH are also accommodated. A

summary of the overhead processing follows and includes

the pointer interpretation function necessary for AIS

detection.

5.1.1 Transmit Path Section/Line Overhead

Transmit path section/line overhead is as follows:

■Synchronizing status byte (S1) insertion

■M0/M1 REI-L insertion; automatic insertion may be

inhibited

■K1 and K2 insertion, AIS-L insertion

■B2 calculation and insertion

■F1 byte insertion

■B1 generation and error insertion

■Scrambler

■J0 insert control

■A2 erro r in s er t i on

The entire APS value or K2[2:0] can be inserted via

microprocessor control. Automatic RDI insertion is

supported with individual inhibits for each contributor. A

protection switch selects the RDI-L value for insertion from

the protection board rather than from the working side.

B1 and B2 BIP-8 values are calculated and inserted. Both

values can be inverted.

5.1.2 Receive Path Section/Line Overhead

Receive path section/line overhead is as follows:

■Frame alignment (STS-12/STM-4 or STS-3)

■B1 BIP-8 check

■J0 monitoring

■Descrambling

■F1 monitoring

■B2 BIP-8 check

■APS and K2 monito ri ng

■AIS-L and RDI-L detection

■M1 REI-L detection

■S1 synchronization status monitoring

Framer states and all other state changes are reported.

These cause an interrupt if not masked.

The B1 and B2 parity check supp orts both bit and bloc k

modes. The counters count up to one second’s worth of

BIP errors. These stay at their maximum value in case of

overflow or rollover and should be read (and cleared) at

least once per second.

The J0 monitor supports nonframed, SONET-framed, and

SDH-framed 16-byte sequences, as well as single J0 byte

monitoring modes.

APS monito ring is perform ed on K1[7 :0] and K2[ 7:3] . The

value is stored, and changes are reported. Bits [2:0] of the

K2 byte are monitored independently.

The alarm indication sign al (AIS -L /MS-A IS ) and remote

defect indication (RDI-L/MS-RDI) are monitored separately ,

and changes are reported. This information is also sent to

the protection device for ADM applications.

The M1 monitor operates either in bit or block mode and

allows access to the remote error indication

(REI-L/MS-REI) errored bit count.

The S1 by te c an be m oni tored eith er as an entir e 8- bit w ord

or as one 4-bit nibble (bits 7:4).

Agere Systems Inc. 17

Product Description TMXF33625 Hypermapper

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

5 Block Description (continued)

5.1.3 Pointer Interpreter

The TMUX pointer interpreter conforms to ETS 300

417-1-1: January 1996—Annex B.

The pointer interpreter evaluates the current pointer state

for the normal state, path AIS state, or LOP (loss of pointer)

conditions, as well as pointer increments and decrements.

The current pointer state and any changes in pointer

condition are reported to the control system. The number of

consecutive frames for invalid pointer and invalid

concatenation indication is fixed at nine.

5.1.4 Path Termination Function

In STS-3/STM-1 mode, path termination is performed on

either all three STS-1s or on the VC-4. In the

STS-12/STM-4 mode, path termination is performed either

on all twelve STS-1s/four STS-3cs, or on the four VC-4

POH. On the receive side, it includes the following:

■J1 monitoring

■B3 BIP-8 check ing

■C2 signal label monitoring

■REI-P and RDI-P detection

■H4 multiframe monitoring

■F2, F3, and K3 automatic protection switch monitoring

■N1 tandem connection monitoring

■Signal degrade BER and signal fail BER detection

■Path overhead access channel (RPOAC) drop

■AIS-P/HO-AIS insertion

■Automatic AIS generation (with individual inhibit)

The J1 monitor (as found in the TMUX block) provides the

following four modes of operation (16 byte or 64 byte):

■SONET mode

■SDH mode

■User mode

■Single byte mode

Note: For additional J1 functionality, please refer to the

STS1-LT and SPEMPR sections of the Register

Description document.

B3 is monitored either in bit or block mode. Provisionable

N-times detection counters are implemented for C2, F2,

F3, N1, and K3 bytes. The K3 APS byte and N1 TCM byte

can be monitored as an entire 8-bit word or as two 4-bit nib-

bles.

5.2 STS-12/STM-4 Pointer Processor (STSPP)

Block

A pointer processor (four per device) is used to move a

SONET/SDH payload from the line clock domain to the

system clock domain. The Hypermapper STS-12 pointer

processors are SONET and SDH compliant and offer a

configurable STS-3/STM-1 or STS-12/STM-4 mode. They

support an arbitrary mix of STS-1/STS-3c tributaries and

SDH equivalents, and comply with GR-253-CORE, T1.105,

G.707, G.783, G.826, G.821, and ETSI 417-1-1.

5.3 STS-1 Line Terminating (STS1LT) Block

The STS-1 line terminating block (12 per device) allows

termination of an STS-1 line signal routed from the

multirate cross connect. It provides access to the section/

line and path overhead similarly to the TMUX. It can also

source an SPE to the STS cross connect for transport on

the high-speed line interface.

5.4 STS Cross Connect (STSXC) Block

The high-order cross connect block (four per device)

connects the SONET/SDH interfaces to the PDH portion of

the device. It will permit connections that support a variety

of applications. The data paths, clocks, and syncs are

internally configured as appropriate for the different signal

rates and interconnects. A significant portion of the STSXC

block is the mate interconnect described in Section 5.5.

5.5 Mate Interconnect and Clock Data Recovery

(MCDR) Block

The Hypermapper can be configured to terminate an

STS-12/STM-4 signal by connecting the device partitions

(A, B, C, D) together via the mate interconnect. Each

interconnect operates at 155 Mbits/s and is connected

between a single Hypermapper partition configured as

master and up to thre e Hyperm appe r partition s with high-

speed TMUX input configured as slaves. The mate

interconnect uses SONET/SDH framing and overhead so

there is performance monitoring of the link between

partitions.

Note: Not all applications require all four partitions to fully

terminate an STS-12/STM-4.

1818 Agere Systems Inc.

Product Description

February 21, 2003

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

5 Block Description (continued)

5.6 SPE/AU-3 Mapper (SPEMPR) Block

The SPE mapper functional block (24 per device) operates

either as an AU-3/STS-1 mapper or as a TUG-3 mapper . In

either mode, it maps/demaps data from/to either the VT

mapper, the M13/E13 MUX/deMUX, the DS3/E3 clear

channel, or the DS3/E3 loopback channel. The SPE

mapper supports numerous automatic monitoring functions

and provides interrupts to the control system, or it can be

operated in a polled mode.

In DS3 mapping mode, the SPE mapper functional block

accepts/delivers structured DS3 data from/to the M13

functional block or a clear channel DS3 signal at

44.736 Mbits/s rate and maps/demaps it asynchronously

to/from the STS-1 SPE or a TU-3. The DS3 mapper

generates a fixed pointer value of 522.

On the receive side, pointer interpretation is performed,

detecting LOP, AIS, NDF, NORM, INC, and DEC. A DS3

loopback mode allows demapping and remapping of a DS3

signal. It is particularly useful in cases where a DS3 signal

mapped as AU-3/STS-1 needs to be remapped as a TU-3

signal or vice versa. B3ZS encoding/decoding is included.

The E3 mapping mode is similar in functionality to that of

the DS3 mapping mode just described.

This functional block also connects to the path overhead

access channel (POAC) to insert/drop path overhead bytes

J1, C2, F2, H4, F3, K3, and N1 into/from the STS-1 SPE or

VC-3.

The SPE mapper functional block complies with GR-253-

CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, and ETS

300 417-1-1.

5.7 VT/TU Mapper (VTMPR) Block

The VT/TU mapper (12 per device) maps any valid combi-

nation of DS1 and E1 signals into a stream at a rate of

51.84 Mbits/s (STS-1 or AU-3). The mapping methods

(VT1.5, VT2, and VT group in ANSI nomenclature; TU-11,

TU-12, and TUG-2 in ITU nomenclature) are analogous.

The VT/VC mapper supports the following mappings:

■28 asynchronous, byte-, or bit-synchronous DS1 signals

are mapped into seven VT groups or TUG-2s.

■28 asynchronous, byte-, or bit-synchronous J1 signals

are mapped into seven VT groups or TUG-2s.

■21 asynchronous, byte-, or bit-synchronous E1 signals

are mapped into seven VT groups or TUG-2s.

■Maps DS1 into VT1.5/TU-11/TU-12, J1 into VT1.5/TU-11/

TU-12, and E1 into VT2/TU-12.

ADM applications are supported via tributary loopback,

tributary pointer processing, and a low-order path overhead

access channel.

The VT/TU mapper supports automatic generation or

microprocessor overwrite of 1-bit RDI-V, enhanced RDI-V,

1-bit RFI-V, automatic downstream AIS generation, and five

J2 trace identifier modes.

The VT/TU mapper complies with GR-253-CORE, G.707,

T1.105, G.704, G.783, JT-G707, GR-499, and ETS 300

417-1-1.

5.7.1 Receive Direction

In the receive direction, the VT mapper terminates the data

stream it receives from the SPE mapper. It demultiplexes

the AU-3/TUG-3 into the VTs/TUs and checks the H4

multiframe alignment. A pointer interpreter for up to

28 VTs/TUs detects LOP, AIS, NDF, NORM, INC, and DEC

on each channe l.

The low-order path termination includes V5 byt e

termination, J2 path trace, Z6/N2 tandem connection,

Z7/K4 enhanced RDI-V and low-order APS monitoring, and

the payload termination for asynchronous, byte- or bit-

synchronous signals. The V5 byte termination performs

BIP-2 check (bit or block mode), REI-V count, RFI-V, and

RDI-V detection, signal label monitoring, and automatic

AIS-V insertion (which can be inhibited).

The J2 monitor supports the following modes:

■Cyclic check

■SONET framing mode

■SDH framing mode

■Single byte check

In byte-synchronous mode, the receive demapper

generates a frame synchronization signal to indicate the

DS1 frame bit or the MSB of the E1 time slot 0. Additionally,

it provides the framer access to the received signaling bits.

Output of the VT mapper is a DS1/J1/E1 signal with a

gapped clock. It can be overwritten with AIS automatically

or upon microprocessor request.

5.7.2 Transmit Direction

In the transmit direction, the VT mapper gets a clock, data,

and frame synchronization signal from the multirate cross

connect. The input is retimed and is checked for a digital

loss of clock (LOC), an AIS condition, and low zeros

density. In byte-synchronous mode, the input signal is

additionally checked for loss-of-frame (LOF).

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Product Description

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TMXF33625 Hypermapper

5 Block Description (continued)

A transmit elastic store synchronizes the incoming

DS1/J1/E1 signals to the local STS-1 clock. In

asynchronous and bit-synchronous mode, it works as a bit-

oriented (64-bit) FIFO, and in byte-synchronous mode, as a

byte- wide (8-byte) buffer using a V5 byte marker bit (8-bit).

Overflow or underflow conditions are monitored and

reported.

In asynchronous and bit-synchronous mode, a fixed VT

pointer of 78 (VT1.5/TU-11) or 105 (VT2/TU-12) is

generated and the payload is mapped into the container

using a positive/null/negative bit stuffing mechanism

(C-bits and S-bits). In bit-synchronous mode, the bit stuffing

mechanism is disabled. In byte-synchronous mode, a

dynamic VT pointer value is generated using the V5

marker, implementing NORM, NDF, INC, and DEC

pointers.

The VT POH generation comprises V5 byte with BIP-2

generation, AIS-V, UNEQ-V insertion, automatic REI-V,

RFI-V, RDI-V, and enhanced RDI-V generation (Telcordia,

ITU-T), J2 path trace insertion via the microprocessor, Z6/

N2 byte insertion, and Z7/K4 byte insertion via the

microprocessor or low-order path overhead (LOPOH)

access channel.

The data stream is synchronized to the received internal

2 kHz synchronization pulse and is multiplexed to form the

STS-1/AU-3 signal, which is then output to the SPE

mapper.

When operating in byte-synchronous mode, the phase and

signaling bits from the framer are stored and inserted into

the mapped frame.

5.8 M13/E13 Multiplexer (M13/E13 MUX) Blocks

The M13/E13 block (12 blocks per device) is a highly

configurable multiplexer/demultiplexer for which each block

can be configured for M13 or E13 operation. The features

are as described below.

5.8.1 M13 MUX

The M13 may operate in the C-bit parity or M23 mode. In

the C-bit parity mode, the M13 provides a far-end alarm

and control (FEAC) code generator and receiver , an HDLC

transmitter and receiver, and an automatic far-end block

error (FEBE) generator.

28 DS1 inputs (in groups of four) or 21 E1 input signals (in

groups of three) can feed into individual M13 MUXs.

The M13 supports numerous automatic monitoring

functions. It can provide an interrupt to the control system,

or it can operate in a polled mode.

The M13 complies with T1.102, T1.107, T1.231, T1.403,

T1.404, GR-499, G.747, and G.775.

5.8.1.1 Receive Direction

The receive DS3 is monitored for loss of clock and loss of

signal (LOS) according to T1.231. The B3ZS decoder

accepts either the unipolar clock and data, or unipolar clock

and positive and negative data. It also checks for bipolar

coding violations. The transmit DS3 can be looped back

into the receive side after B3ZS decoding. The M23

demultiplexer checks for valid DS3 framing by finding the

frame alignment pattern (F-bits) and then locating the

multiframe alignment signal (M-bits). During each M frame,

the data stream is checked for the presence of the AIS

(1010) or idle (1100) pattern.

Within the M13 demultiplexer, there are four performance

monitoring counters for F- or M-bit, P-bit, E-bit parity, and

FEB E e r ro rs.

5.8.1.2 Transmit Direction

The incoming DS1/E1 clocks are first checked for activity or

loss-of-clock (LOC). The data signals are retimed and

checked for AIS and activity. DS1/E1 loopback selectors

allow the individual DS1/E1 signals within the received DS3

to be looped back toward the DS3 input. This loopback can

be performed automatically, or the user can force a DS1 or

E1 loopback.

The four DS1 or three E1 signals for each M12 MUX are

fed into single-bit, 16-word-deep FIFOs to synchronize the

signals to the DS2 frame generation clock. The fill level of

each FIFO determines the need for bit stuffing its DS1/E1

input. The M13 can handle DS1/E1 signals with nominal

frequency offsets of ±130 ppm and up to five unit intervals

peak jitter. The DS3 transmit clock is used to derive the

clock source for DS2 frame generation.

The transmit DS3 output can either be in the form of

unipolar clock and data, or unipolar clock and positive and

negative data. The DS3 data is B3ZS-encoded and can be

looped back from the receive DS3 input.

2020 Agere Systems Inc.

Product Description

February 21, 2003

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

5 Block Description (continued)

5.8.2 E13 MUX

The E13 is a functional block that performs MUX/deMUX

from/to 16 E1s and one E3 signal compliant with ITU G.742

and ITU G.751. The E13 functional block is a highly

configurable multiplexer/demultip lexer. Each internal E12

MUX/deMUX and E23 MUX/deMUX is independently

configurable. The E3 inputs to the receive path can be

HDB3-encoded dual-rail (bipolar) signals or already

decoded single-rail signals with or without a BPV indication

input. The E1 inputs are expected to be decoded prior to

the E13 functional block. E3 transmit direction output can

be configured as HDB3-encoded dual rail (bipolar) or as

single rail. The E13 provides status and two-level priority

maskable interrupt outputs to the microprocessor.

E1 transmit path monitors detect loss of clock (LOC) and

AIS. The E3 receive monitor detects loss of signal (LOS),

loss of clock (LOC), bipolar violations (BPV), AIS, and RAI.

E3 and E2 loopback modes are also available.

5.9 Multirate Cross Connect (MRXC) Block

The multirate cross connect (MRXC) functional block (four

per device) is a crosspoint switch for DS1/J1/E1, DS3/E3,

and path overhead I/O. The multirate cross connect routes

signals to/from the major functional blocks and external I/O

pins as necessary for each application. The MRXC can

multicast, route test patterns, idles, or alarm conditions to

any channel, and provide system loopbacks.

For DS1/E1 applications, the multirate cross connect can

interconnect up to 84 individual DS1/E1 channels between

the framer, M13/E13 multiplexer, VT mapper, or jitter

attenuator. The external I/O pins support one of four

availab le sys tem inte r fac es .

Independent signal paths for remote alarm indication (RAI),

alarm indication signal (AIS), and byte-synchronous frame

synchronizing signals on channels between the VT mapper

or M13/E13 and the framer are supported. Receive pointer

adjustment information is routed to the jitter attenuator

functional block for each channel originating in the VT

mapper.

For DS3/E3 signals, the multirate cross connect supports

configuration of interconnects between the following:

■The M13/E13 and the SPEMPR

■External I/O interconnection to the M13/E13 or SPEMPR

■Insertion/monitoring of unframed test patterns from the

test-pattern generator/monitor functional block

The test-pattern generator/monitor functional block (TPG/

TPM) provides test signals and monitors inputs for signals

to/from the multirate cross connect. The TPG can generate

a set of test signals at DS1, E1, and DS3, E3, or

STS-1 rates. There is only one test pattern generator and

monitor per signal rate.

For overhead, the MRXC provides an access channel

connection (TOAC and POAC) to the SPEMPR or to the

TMUX functional blocks.

The MRXC also provides the interface to the external pins.

The external pins may be configured to work in four modes:

a transport mode, a concentration highway interface (CHI)

mode, a parallel system bus (PSB) mode, and a network

serial multiplexed interface (NSMI) mode. The first mode is

used to provide dedicated access to the device for DS3/E3

signals, and the last three modes are described below.

■Concentration highway interface (serial time-division

multiplex interface) CHI:

—Global frame synchronization.

—Global clock: 8.192 MHz, or 16.384 MHz.

—18 transmit and 18 receive data ports (per device

partition); data rates: 8.192 Mbits/s, or 16.384 Mbits/s.

■Parallel system bus (parallel time-division multiplex

interface/transmit and receive) PSB:

—Global frame synchronization.

—Global clock: 19.44 MHz.

—Data rate: 19.44 Mbits/s.

—8 bits of data + associated parity bit.

—4 bits of signaling + 2 bits of signaling control + 1 bit of

parity.

■Network serial multiplexed bus (NSMI):

—6- or 8-pin serial interface.

—Transmit and receive clock and data at 51.84 MHz (or

44.736/34.368 MHz for M13/E13).

—Accommodates one STS-1 SPE.

—Provides a minimal pin count interface for data and

inverse multiplexing for ATM (IMA) applications

without slip buffers.

—Three modes of operation:

! Framer—NSMI payload assembled/disassembled

into DS1/E1s.

! M13/E13—proprietary transport format with DS3/

E3 framing.

! SPE—proprietary transport format mapped into an

STS-1/AU-3.

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Product Description

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TMXF33625 Hypermapper

5 Block Description (continued)

5.10 DS1 Digital Jitter Attenuator (DS1/E1 DJA)

Block

The DS1/E1 digital jitter attenuator (DS1/E1 DJA) block (12

per device), contains 28 copies of the digital jitter

attenuator for a total of 336/252 DS1/E1 DJAs. These

digital jitter attenuator functional blocks can operate in two

different modes: as a DS1 or as an E1 jitter attenuator.

In both modes, the digital jitter attenuator can be

provisioned to always operate as a second-order PLL, or it

can switch to act as a first-order PLL during VT pointer

adjustments to help meet MTIE requirements. The period

of time in the first-order mode is provisionable. The PLL

bandwidth is provisionable between 0.1 Hz and 0.5 Hz, and

the damping factor for these bandwidths varies between 2

and 0.5 to accommodate a number of different system

constraints.

The DS1/E1 DJA allows automatic pass-through of an AIS

from both the VTMPR and M13/E13 blocks.

5.11 DS3 Digital Jitter Attenuator (DS3/E3 DJA)

Block

The Hypermapper device contains four DS3/E3 digital jitter

attenuator blocks containing six DS3/E3 digital jitter

attenuators each. These digital jitter attenuators can

operate in two different modes: as a DS3 or as an E3 jitter

attenuator. The PLL bandwidth and the sampling ratio can

be set over a wide range to accommodate a number of

different system constraints.

The DJA functional block accepts/delivers DS3/E3 clock

and data from/to the multirate cross connect functional

block. The PLL bandwidth, damping factor, and sampling

rates are programmable. Output is programmable as data

only, as B3ZS-coded, or as HDB3-coded.

5.12 Test Pattern Generator/Monitor (TPG/TPM)

Block

The test pattern generator/test pattern monitor functional

block (TPG/TPM) consists of a set of configurable test

pattern generators and monitors for local self-test,

maintenance, and troubleshooting operations.

The TPG feeds one or more DS1/E1 test signals (via data,

clock, and FS or AIS signal paths) to the multirate cross

connect, which can redistribute or broadcast these signals

to any valid channel in the framer, M13/E13 MUX, or VT

mapper functional blocks. The TPG can also generate

DS3, E3, or STS-1 test signals.

Any channel arriving at the multirate cross connect can be

routed to the test monitor. The test monitor can

automatically detect/count bit errors in a pseudorandom

test sequence, loss of frame (DS1/E1 only), or loss of

synchronization situation. The TPM can provide an

interrupt to the control system, or it can be operated in a

polled mode.

Simultaneous testing of DS1, E1, and DS3, E3, or STS-1

signals is supported with one channel for each (one

channel shared between DS3, E3, and STS-1).

Supported test patterns are a quasirandom signal (QRSS),

a pseudorandom bit sequence (PRBS23, PRBS20,

PRBS15), alternating zeros/ones, an all-ones pattern, and

a 16-bit user-provisionable pattern.

The DS1 and E1 test patterns can be transmitted as either

unframed or as the payload of a framed signal, as defined

in ITU-T Recommendation O.150. DS3, E3, or STS-1

patterns are unframed only.

Under register control, single bit-errors can be injected into

any test pattern.

5.13 Low-Orde r Pa th Over Head

This block is shown in Figure 1, but it cannot be addressed

by the MPU. It is shown as a virtual block to highlight that

the LOPOH bytes from the TMUX, SPEMPR, and VTMPR

can be provisioned to appear at the LOPOH device pins.

Provisioning is accomplished by setting registers in the

device via the MPU.

5.14 Clock Generator (CG) Block

The clock generator block may optionally be used to

override the device configuration specified by the

MODE[2:0]_PLL device pins. If the block is not provisioned,

the default mode will generate all the necessary FRM block

PDH clocks, based upon the logic states on the

MODE[2:0]_PLL pins (see the Hypermapper Hardware

Design Guide).

2222 Agere Systems Inc.

Product Description

February 21, 2003

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

5 Block Description (continued)

5.15 Framer Block

Functionalities present in each subcomponent of the DS1/

J1/E1 fr amers are shown below.

5.15.1 Receive Frame Aligner/Transmit

Frame Formatter

The receive frame aligner and transmit frame formatter

support the following frame formats:

■D4 superframe

■SF D4 superframe: FT framing only

■J-D4 superframe with Japanese remote alarm

■DDS

■SLC-96

■ESF

■J-ESF (J1 standard with different CRC-6 algorithm)

■Nonalign DS1 (193 bits—clear channel)

■CEPT basic frame (ITU G.706)

■CEPT CRC-4 multiframe with 100 ms timer (ITU G.706)

■CEPT CRC-4 multiframe with 400 ms timer (automatic

CRC-4/non-CRC-4 equipment interworking) (ITU G.706

Annex B)

■Nonalign E1 (256 bits—clear channel)

■2.048 coded mark inversion (CMI) coded interface (TTC

standards JJ-20.11)

5.15.2 Receive Performance Monitor

The receive performance monitor detects the following

alarms:

■Loss of receive clock

■Loss-of-frame

■Alarm indication signal (AIS)

■Remote frame alarms

■Remote multiframe alarms

These alarms are detected as defined by the appropriate

ANSI, AT&T, ITU, and ETSI standards.

Performance monitoring, as specified by AT&T, ANSI, and

ITU, is provided through counters monitoring the following:

■Frame bit errors

■CRC errors

■Errored eve n ts

■Errored seconds

■Bursty errored seconds

■Severely errored seconds

In-band loopback activation and deactivation codes can be

transmitted to the line via the payload or the facility data

link. In-band loopback activation and deactivation codes in

the payload or the facility data link are detected.

5.15.3 Signaling Processor

The signaling processor supports the following modes:

■Superframe (D4, SLC-96): 2-state, 4-state, and 16-state

■VT 1.5 SPE: 2-state, 4-state, and 16-state

■Extended superframe: 2-state, 4-state, and 16-state

■CEPT: common channel signaling (CCS) (TS-16)

■Transparent (pass thro ugh ) signa li ng

■J-ESF handling groups

Signaling features supported per channel are as follows:

■Signaling debounce

■Signaling freeze

■Signaling interrupt upon change of state

■Associated signaling mode (ASM)

■Signaling inhibit

■Signaling stomp

Voice and data channels are programmable in the DS1

robbed-bit signaling modes. The entire payload can be

forced into a data-only (no signaling channels) mode

(i.e., transparent mode, achieved by programming one

control bit).

Signaling access occurs through the on-chip signaling

registers or the system interface. Data and its associated

signaling information can be accessed through the system

in either DS1 or CEPT-E1 modes.

Agere Systems Inc. 23

Product Description

February 21, 2003 622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

5 Block Description (continued)

5.15.4 Facility Data Link (FDL) Processor

The receive facility data link processor monitors the bit-

oriented ESF data-link messages defined in ANSI T1.403.

The transmit facility data link unit overrides the FDL-FIFO

for the transmission of the bit-oriented ESF data-link

messages defined in ANSI T1.403-1995.

The FDL processor extracts and stores data link bits from

three different frame types as follows:

■D-bits and delineator bits from the SLC-96 multi-

superframe.

■Data link bits from DDS frames (bit 6 of time slot 24).

■Two multiframes of Sa[4:8] bits from timeslot 0 in CEPT

basic and CRC-4 multiframes.

The respective bits are always extracted from frame-

aligned frames and are stored in a stack. The processor

controls notification of stack updates through the interrupt

(maskable) registers.

The transmit FDL functional block performs the

transmission of D-bits into SLC-96 Superframes, Sa-bits in

CEPT frames, and D-bits in DDS frames.

■In SLC-96 frames, the D and delineator bits are always

sourced from this functional block when the block is

enabled for insertion.

■In DDS frames, the data link bits are always sourced

from this functional block when this block is enabled for

insertion. This functional block also provides the

capability to transmit BOMs (bit-oriented messages) in

the data link channel of ESF links.

■In CEPT frames, the Sa bits are sourced from either the

Sa stack within this functional block or from the system

interface. The data link functional block only responds

with valid data when selected by the Sa source control

bits.

5.15.5 HDLC Unit

The HDLC processor formats the HDLC packets for

insertion into the programmable channels. A channel can

be any number of bits (1 to 8) from a time slot.

The maximum number of channels is 64. The maximum

channel bit rate is 64 kbits/s. The minimum channel bit rate

is 4 kbits/s. Each channel is allocated 128 bytes of storage.

HDLC processing of data on the facility data link (PRMs,

Sa-bits, or otherwise) is implemented by assigning the FDL

bit position to a logical HDLC channel.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems and the Agere logo are trademarks of Agere Systems Inc.

February 21, 2003

DS03-077BBAC (Replaces DS03-005B BAC)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo ), KOREA: (82) 2-767- 1850 (Seoul), SINGAPORE: (65) 778- 8833, T AIWAN: (886) 2-27 25-5858 (Taipei)

EUROPE: Tel. (44) 134 4 296 400

Product Description

February 21, 2003

622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0

TMXF33625 Hypermapper

6 Glossar y

AIS Alarm indication signal

AMI Alternate mark inversion

APS Automatic protection switch

ASM Associated signaling mode

BER Bit error rate

BLSR Bidirectional line switching ring

BOM Bit-oriented me ssage

BPV Bipolar violation

B8ZS Bipolar 8 zero substitution

CCI Common channel signaling

CDR Clock and data recovery

CHI Concentrated highway interface

CMI Coded mark inversion

CRC Cyclic redundancy check

CRV Coding rule violation

DACS Digital acc es s cr os s co nne cts

DJA Digital jitter attenuation

ESF Extended superframe

EXZ Excessive zeros

FCS Frame ch eck seq uenc e

FDL Facility data link

FEAC Far-end alarm and control

FEBE Far-end block error

HDB3 High-density bipolar of order three

HDLC High-level data link control

LIU Line inter fac e unit

LOC Loss-of-clock

LOF Loss-of-frame

LOS Loss of signal

LOPOH Low-order path overhead

OOF Out of frame

MCDR Mate clock and data recovery

MRXC Multirate cross connect

NSMI Network serial multiplexed interface

PBGA Plastic ball grid array

POAC Path overhead access channel

PRBS Pseudorandom bit sequence

PRM Performance report message

QRSS Quasirandom signal source

RAI Remote alarm indicator

RDI Remote defect indication

REI Remote error indication

SDH Synchronous digital hierarchy

SEF Severely errored frame

TCM Tandem connection monitoring

TOAC Transport overhead access channels

UPSR Unidirectional path s witch ring

Telcordia and Telcordia Technologies are registered trademarks of Telcordia Technologies, Inc.

ANSI is a registered trademark of American National S tandards Institute, Inc.

SLC is a registered trademark of Lucent Technologies Inc.

AT&T is a registered trademark of A T&T in the USA and other countries.

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.